Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 7 0 7 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 7419 1 T1 60 T3 2 T5 1
all_levels[1] 5299 1 T38 2 T15 1 T19 8
all_levels[2] 5070 1 T1 23 T3 19 T5 18
all_levels[3] 4839 1 T1 33 T2 15 T6 2
all_levels[4] 6390 1 T1 68 T2 22 T3 75
all_levels[5] 9769 1 T3 234 T4 5 T5 7
all_levels[6] 9351 1 T1 27 T3 73 T5 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%