Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	557	1			T1	4		T9	18		T75	7
all_values[1]	557	1			T1	4		T9	18		T75	7
all_values[2]	557	1			T1	4		T9	18		T75	7
all_values[3]	557	1			T1	4		T9	18		T75	7
all_values[4]	557	1			T1	4		T9	18		T75	7
all_values[5]	557	1			T1	4		T9	18		T75	7
all_values[6]	557	1			T1	4		T9	18		T75	7
all_values[7]	557	1			T1	4		T9	18		T75	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2368

1

T1

22

T9

71

T75

35

auto[1]

2088

1

T1

10

T9

73

T75

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1679

1

T1

18

T9

47

T75

14

auto[1]

2777

1

T1

14

T9

97

T75

42

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2641

1

T1

22

T9

73

T75

28

auto[1]

1815

1

T1

10

T9

71

T75

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	190	1			T1	2		T9	3		T75	1
all_values[0]	auto[0]	auto[1]	auto[1]	136	1			T9	4		T75	2		T76	1
all_values[0]	auto[1]	auto[0]	auto[1]	121	1			T9	4		T75	3		T109	2
all_values[0]	auto[1]	auto[1]	auto[1]	110	1			T1	2		T9	7		T75	1
all_values[1]	auto[0]	auto[0]	auto[0]	172	1			T1	1		T9	6		T75	2
all_values[1]	auto[0]	auto[1]	auto[0]	154	1			T1	1		T9	7		T75	2
all_values[1]	auto[1]	auto[0]	auto[1]	120	1			T1	1		T9	2		T75	3
all_values[1]	auto[1]	auto[1]	auto[1]	111	1			T1	1		T9	3		T109	1
all_values[2]	auto[0]	auto[0]	auto[0]	132	1			T1	4		T9	7		T75	2
all_values[2]	auto[0]	auto[0]	auto[1]	48	1			T75	1		T31	1		T32	2
all_values[2]	auto[0]	auto[1]	auto[0]	101	1			T75	1		T109	5		T391	4
all_values[2]	auto[0]	auto[1]	auto[1]	52	1			T9	2		T75	1		T76	1
all_values[2]	auto[1]	auto[0]	auto[1]	118	1			T9	3		T75	2		T76	2
all_values[2]	auto[1]	auto[1]	auto[1]	106	1			T9	6		T76	1		T391	5
all_values[3]	auto[0]	auto[0]	auto[0]	128	1			T1	2		T9	4		T75	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1			T9	1		T75	2		T76	2
all_values[3]	auto[0]	auto[1]	auto[0]	98	1			T1	2		T9	2		T391	5
all_values[3]	auto[0]	auto[1]	auto[1]	45	1			T9	3		T75	1		T105	1
all_values[3]	auto[1]	auto[0]	auto[1]	122	1			T9	3		T75	2		T76	1
all_values[3]	auto[1]	auto[1]	auto[1]	105	1			T9	5		T75	1		T76	1
all_values[4]	auto[0]	auto[0]	auto[0]	100	1			T9	4		T75	1		T76	2
all_values[4]	auto[0]	auto[0]	auto[1]	62	1			T1	1		T9	2		T76	1
all_values[4]	auto[0]	auto[1]	auto[0]	118	1			T9	1		T76	1		T109	2
all_values[4]	auto[0]	auto[1]	auto[1]	57	1			T9	2		T75	2		T76	1
all_values[4]	auto[1]	auto[0]	auto[1]	118	1			T1	1		T9	5		T75	3
all_values[4]	auto[1]	auto[1]	auto[1]	102	1			T1	2		T9	4		T75	1
all_values[5]	auto[0]	auto[0]	auto[0]	131	1			T1	2		T9	2		T75	3
all_values[5]	auto[0]	auto[0]	auto[1]	48	1			T9	1		T76	1		T109	2
all_values[5]	auto[0]	auto[1]	auto[0]	93	1			T1	2		T9	1		T391	2
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T9	2		T75	2		T76	1
all_values[5]	auto[1]	auto[0]	auto[1]	111	1			T9	5		T76	2		T109	2
all_values[5]	auto[1]	auto[1]	auto[1]	116	1			T9	7		T75	2		T76	1
all_values[6]	auto[0]	auto[0]	auto[0]	113	1			T1	2		T9	1		T76	2
all_values[6]	auto[0]	auto[0]	auto[1]	48	1			T1	1		T9	2		T75	1
all_values[6]	auto[0]	auto[1]	auto[0]	109	1			T9	6		T76	2		T109	3
all_values[6]	auto[0]	auto[1]	auto[1]	60	1			T9	1		T75	1		T391	2
all_values[6]	auto[1]	auto[0]	auto[1]	121	1			T1	1		T9	4		T75	4
all_values[6]	auto[1]	auto[1]	auto[1]	106	1			T9	4		T75	1		T76	2
all_values[7]	auto[0]	auto[0]	auto[0]	136	1			T1	2		T9	5		T75	2
all_values[7]	auto[0]	auto[0]	auto[1]	51	1			T9	1		T76	1		T109	1
all_values[7]	auto[0]	auto[1]	auto[0]	94	1			T9	1		T391	1		T31	5
all_values[7]	auto[0]	auto[1]	auto[1]	48	1			T9	2		T76	1		T391	1
all_values[7]	auto[1]	auto[0]	auto[1]	119	1			T1	2		T9	6		T75	2
all_values[7]	auto[1]	auto[1]	auto[1]	109	1			T9	3		T75	3		T76	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal