Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.93 99.38 97.89 100.00 98.83 100.00 97.48


Total test records in report: 1240
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T1045 /workspace/coverage/default/43.uart_rx_start_bit_filter.2933552115 Mar 07 01:46:17 PM PST 24 Mar 07 01:47:24 PM PST 24 37873603540 ps
T360 /workspace/coverage/default/12.uart_fifo_full.2542980989 Mar 07 01:44:44 PM PST 24 Mar 07 01:45:18 PM PST 24 20939054159 ps
T1046 /workspace/coverage/default/12.uart_alert_test.1620372662 Mar 07 01:44:45 PM PST 24 Mar 07 01:44:46 PM PST 24 29480922 ps
T1047 /workspace/coverage/default/3.uart_rx_parity_err.3366976362 Mar 07 01:43:49 PM PST 24 Mar 07 01:44:22 PM PST 24 23584109589 ps
T1048 /workspace/coverage/default/7.uart_noise_filter.3380624407 Mar 07 01:44:37 PM PST 24 Mar 07 01:47:27 PM PST 24 134596724153 ps
T1049 /workspace/coverage/default/34.uart_smoke.3552870816 Mar 07 01:45:43 PM PST 24 Mar 07 01:45:45 PM PST 24 490303702 ps
T1050 /workspace/coverage/default/41.uart_tx_rx.2022110860 Mar 07 01:46:05 PM PST 24 Mar 07 01:49:38 PM PST 24 111247437113 ps
T1051 /workspace/coverage/default/23.uart_rx_oversample.518357532 Mar 07 01:45:03 PM PST 24 Mar 07 01:45:16 PM PST 24 3922508806 ps
T1052 /workspace/coverage/default/30.uart_fifo_reset.2775932549 Mar 07 01:45:31 PM PST 24 Mar 07 01:46:09 PM PST 24 102382296383 ps
T1053 /workspace/coverage/default/36.uart_loopback.2383305741 Mar 07 01:45:56 PM PST 24 Mar 07 01:46:07 PM PST 24 5738144919 ps
T264 /workspace/coverage/default/144.uart_fifo_reset.779557224 Mar 07 01:47:26 PM PST 24 Mar 07 01:48:27 PM PST 24 151550279915 ps
T1054 /workspace/coverage/default/27.uart_fifo_full.2058031560 Mar 07 01:45:17 PM PST 24 Mar 07 01:45:41 PM PST 24 129523055726 ps
T1055 /workspace/coverage/default/24.uart_noise_filter.3098678880 Mar 07 01:45:10 PM PST 24 Mar 07 01:47:25 PM PST 24 77027140614 ps
T1056 /workspace/coverage/default/18.uart_rx_parity_err.1836926193 Mar 07 01:44:51 PM PST 24 Mar 07 01:45:29 PM PST 24 37400883467 ps
T1057 /workspace/coverage/default/3.uart_perf.3290519075 Mar 07 01:43:59 PM PST 24 Mar 07 01:48:19 PM PST 24 19011679568 ps
T1058 /workspace/coverage/default/32.uart_fifo_overflow.2077308848 Mar 07 01:45:39 PM PST 24 Mar 07 01:48:40 PM PST 24 127843827775 ps
T1059 /workspace/coverage/default/35.uart_alert_test.2460035608 Mar 07 01:45:48 PM PST 24 Mar 07 01:45:48 PM PST 24 13836947 ps
T1060 /workspace/coverage/default/230.uart_fifo_reset.2413540635 Mar 07 01:47:52 PM PST 24 Mar 07 01:48:28 PM PST 24 21995277711 ps
T323 /workspace/coverage/default/64.uart_fifo_reset.3729625109 Mar 07 01:46:52 PM PST 24 Mar 07 01:47:40 PM PST 24 117230679522 ps
T1061 /workspace/coverage/default/9.uart_smoke.4174527391 Mar 07 01:44:36 PM PST 24 Mar 07 01:44:38 PM PST 24 481820864 ps
T378 /workspace/coverage/default/106.uart_fifo_reset.2135176389 Mar 07 01:47:18 PM PST 24 Mar 07 01:47:37 PM PST 24 115361606386 ps
T370 /workspace/coverage/default/22.uart_rx_parity_err.2397163598 Mar 07 01:45:01 PM PST 24 Mar 07 01:45:11 PM PST 24 33421114089 ps
T1062 /workspace/coverage/default/247.uart_fifo_reset.653618733 Mar 07 01:48:01 PM PST 24 Mar 07 01:48:42 PM PST 24 98693121115 ps
T1063 /workspace/coverage/default/20.uart_fifo_full.2725105883 Mar 07 01:44:45 PM PST 24 Mar 07 01:45:57 PM PST 24 87906050113 ps
T1064 /workspace/coverage/default/14.uart_smoke.1558822992 Mar 07 01:44:40 PM PST 24 Mar 07 01:44:43 PM PST 24 689914798 ps
T1065 /workspace/coverage/default/4.uart_rx_parity_err.3979601991 Mar 07 01:43:59 PM PST 24 Mar 07 01:44:30 PM PST 24 18649895643 ps
T1066 /workspace/coverage/default/29.uart_alert_test.2266865878 Mar 07 01:45:31 PM PST 24 Mar 07 01:45:32 PM PST 24 13726691 ps
T1067 /workspace/coverage/default/37.uart_rx_oversample.1680941935 Mar 07 01:45:48 PM PST 24 Mar 07 01:46:00 PM PST 24 5813007249 ps
T1068 /workspace/coverage/default/9.uart_loopback.1901668022 Mar 07 01:44:35 PM PST 24 Mar 07 01:44:36 PM PST 24 3184744695 ps
T1069 /workspace/coverage/default/45.uart_perf.3018961430 Mar 07 01:46:23 PM PST 24 Mar 07 02:14:06 PM PST 24 30639249650 ps
T1070 /workspace/coverage/default/238.uart_fifo_reset.3622087522 Mar 07 01:47:53 PM PST 24 Mar 07 01:48:09 PM PST 24 59651432149 ps
T1071 /workspace/coverage/default/5.uart_rx_start_bit_filter.312618612 Mar 07 01:43:55 PM PST 24 Mar 07 01:43:58 PM PST 24 3443360893 ps
T247 /workspace/coverage/default/217.uart_fifo_reset.771716914 Mar 07 01:47:51 PM PST 24 Mar 07 01:48:17 PM PST 24 25302116259 ps
T1072 /workspace/coverage/default/8.uart_long_xfer_wo_dly.3932270853 Mar 07 01:44:35 PM PST 24 Mar 07 01:52:13 PM PST 24 53668945413 ps
T1073 /workspace/coverage/default/5.uart_intr.2113853099 Mar 07 01:43:57 PM PST 24 Mar 07 01:44:32 PM PST 24 58933480388 ps
T228 /workspace/coverage/default/123.uart_fifo_reset.4250156956 Mar 07 01:47:16 PM PST 24 Mar 07 01:47:35 PM PST 24 20671830871 ps
T330 /workspace/coverage/default/235.uart_fifo_reset.2130576797 Mar 07 01:47:52 PM PST 24 Mar 07 01:48:36 PM PST 24 49647109334 ps
T1074 /workspace/coverage/default/294.uart_fifo_reset.2099436372 Mar 07 01:48:06 PM PST 24 Mar 07 01:49:08 PM PST 24 38897310724 ps
T1075 /workspace/coverage/default/49.uart_rx_start_bit_filter.2125652145 Mar 07 01:46:42 PM PST 24 Mar 07 01:47:00 PM PST 24 41489894137 ps
T1076 /workspace/coverage/default/39.uart_loopback.260666946 Mar 07 01:45:57 PM PST 24 Mar 07 01:46:14 PM PST 24 6020241657 ps
T1077 /workspace/coverage/default/15.uart_smoke.736848215 Mar 07 01:44:46 PM PST 24 Mar 07 01:44:49 PM PST 24 686333174 ps
T1078 /workspace/coverage/default/37.uart_rx_parity_err.1829077382 Mar 07 01:45:50 PM PST 24 Mar 07 01:50:09 PM PST 24 174749514291 ps
T1079 /workspace/coverage/default/298.uart_fifo_reset.2508394040 Mar 07 01:48:16 PM PST 24 Mar 07 01:48:57 PM PST 24 58922734450 ps
T1080 /workspace/coverage/default/188.uart_fifo_reset.3396081850 Mar 07 01:47:36 PM PST 24 Mar 07 01:48:51 PM PST 24 87553756267 ps
T1081 /workspace/coverage/default/40.uart_perf.3175992984 Mar 07 01:46:07 PM PST 24 Mar 07 01:55:15 PM PST 24 15837044628 ps
T1082 /workspace/coverage/default/19.uart_rx_start_bit_filter.1807275281 Mar 07 01:44:55 PM PST 24 Mar 07 01:45:00 PM PST 24 3853305159 ps
T1083 /workspace/coverage/default/7.uart_fifo_full.3183895073 Mar 07 01:44:00 PM PST 24 Mar 07 01:46:02 PM PST 24 78591941234 ps
T1084 /workspace/coverage/default/29.uart_smoke.1520607889 Mar 07 01:45:20 PM PST 24 Mar 07 01:45:23 PM PST 24 660705943 ps
T1085 /workspace/coverage/default/120.uart_fifo_reset.3056134935 Mar 07 01:47:17 PM PST 24 Mar 07 01:49:42 PM PST 24 91901808098 ps
T1086 /workspace/coverage/default/15.uart_loopback.348058237 Mar 07 01:44:47 PM PST 24 Mar 07 01:44:50 PM PST 24 1618592999 ps
T377 /workspace/coverage/default/88.uart_fifo_reset.1984157528 Mar 07 01:47:01 PM PST 24 Mar 07 01:47:37 PM PST 24 284076249603 ps
T1087 /workspace/coverage/default/127.uart_fifo_reset.192971655 Mar 07 01:47:24 PM PST 24 Mar 07 01:47:42 PM PST 24 44541716726 ps
T1088 /workspace/coverage/default/48.uart_rx_parity_err.2099326655 Mar 07 01:46:41 PM PST 24 Mar 07 01:47:05 PM PST 24 59850908225 ps
T1089 /workspace/coverage/default/197.uart_fifo_reset.4178748335 Mar 07 01:47:45 PM PST 24 Mar 07 01:48:38 PM PST 24 34150532857 ps
T1090 /workspace/coverage/default/5.uart_tx_rx.1744704288 Mar 07 01:43:58 PM PST 24 Mar 07 01:45:41 PM PST 24 62531813321 ps
T232 /workspace/coverage/default/128.uart_fifo_reset.3668528920 Mar 07 01:47:21 PM PST 24 Mar 07 01:52:58 PM PST 24 213076370219 ps
T1091 /workspace/coverage/default/37.uart_intr.1802973523 Mar 07 01:45:49 PM PST 24 Mar 07 01:51:54 PM PST 24 244983779413 ps
T1092 /workspace/coverage/default/11.uart_perf.317266388 Mar 07 01:44:41 PM PST 24 Mar 07 01:57:58 PM PST 24 34553767816 ps
T1093 /workspace/coverage/default/253.uart_fifo_reset.4234740564 Mar 07 01:48:04 PM PST 24 Mar 07 01:48:31 PM PST 24 17041133620 ps
T372 /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2327513439 Mar 07 01:46:06 PM PST 24 Mar 07 01:50:15 PM PST 24 82508216058 ps
T1094 /workspace/coverage/default/48.uart_fifo_overflow.7478719 Mar 07 01:46:34 PM PST 24 Mar 07 01:47:09 PM PST 24 27171602084 ps
T1095 /workspace/coverage/default/43.uart_perf.3211018573 Mar 07 01:46:20 PM PST 24 Mar 07 01:49:32 PM PST 24 31121837142 ps
T1096 /workspace/coverage/default/46.uart_fifo_reset.2541386799 Mar 07 01:46:27 PM PST 24 Mar 07 01:46:48 PM PST 24 39832964940 ps
T1097 /workspace/coverage/default/68.uart_fifo_reset.2457435470 Mar 07 01:46:54 PM PST 24 Mar 07 01:47:27 PM PST 24 107514549454 ps
T373 /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2420632523 Mar 07 01:46:50 PM PST 24 Mar 07 01:56:32 PM PST 24 77058480428 ps
T1098 /workspace/coverage/default/13.uart_rx_oversample.658406710 Mar 07 01:44:43 PM PST 24 Mar 07 01:44:53 PM PST 24 4445589185 ps
T1099 /workspace/coverage/default/25.uart_intr.2213226055 Mar 07 01:45:10 PM PST 24 Mar 07 01:45:30 PM PST 24 34871915132 ps
T1100 /workspace/coverage/default/41.uart_perf.4028865276 Mar 07 01:46:06 PM PST 24 Mar 07 01:55:28 PM PST 24 20013672361 ps
T1101 /workspace/coverage/default/24.uart_loopback.3895496481 Mar 07 01:45:09 PM PST 24 Mar 07 01:45:12 PM PST 24 4612106280 ps
T1102 /workspace/coverage/default/2.uart_rx_start_bit_filter.2836102239 Mar 07 01:43:50 PM PST 24 Mar 07 01:43:52 PM PST 24 1994720666 ps
T1103 /workspace/coverage/default/234.uart_fifo_reset.1380908245 Mar 07 01:47:53 PM PST 24 Mar 07 01:48:05 PM PST 24 25563242669 ps
T1104 /workspace/coverage/default/3.uart_tx_ovrd.583803533 Mar 07 01:43:45 PM PST 24 Mar 07 01:43:48 PM PST 24 1221868119 ps
T1105 /workspace/coverage/default/265.uart_fifo_reset.2694697991 Mar 07 01:48:03 PM PST 24 Mar 07 01:48:32 PM PST 24 26337514947 ps
T1106 /workspace/coverage/default/264.uart_fifo_reset.3028537853 Mar 07 01:48:01 PM PST 24 Mar 07 01:48:17 PM PST 24 63159529318 ps
T1107 /workspace/coverage/default/33.uart_perf.2576307463 Mar 07 01:45:43 PM PST 24 Mar 07 01:51:35 PM PST 24 13692601111 ps
T78 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1006544688 Mar 07 12:54:26 PM PST 24 Mar 07 12:54:27 PM PST 24 1503781972 ps
T1108 /workspace/coverage/cover_reg_top/2.uart_intr_test.3066122854 Mar 07 12:54:28 PM PST 24 Mar 07 12:54:29 PM PST 24 13093588 ps
T1109 /workspace/coverage/cover_reg_top/8.uart_csr_rw.4016175 Mar 07 12:54:35 PM PST 24 Mar 07 12:54:36 PM PST 24 51145948 ps
T1110 /workspace/coverage/cover_reg_top/44.uart_intr_test.3332365108 Mar 07 12:55:11 PM PST 24 Mar 07 12:55:12 PM PST 24 108805357 ps
T1111 /workspace/coverage/cover_reg_top/40.uart_intr_test.396640516 Mar 07 12:54:31 PM PST 24 Mar 07 12:54:31 PM PST 24 130369329 ps
T54 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1245387716 Mar 07 12:54:44 PM PST 24 Mar 07 12:54:45 PM PST 24 11961389 ps
T67 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1224296462 Mar 07 12:54:37 PM PST 24 Mar 07 12:54:38 PM PST 24 58819828 ps
T68 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.942351947 Mar 07 12:54:27 PM PST 24 Mar 07 12:54:28 PM PST 24 46735084 ps
T1112 /workspace/coverage/cover_reg_top/33.uart_intr_test.2023992071 Mar 07 12:54:37 PM PST 24 Mar 07 12:54:38 PM PST 24 12585322 ps
T1113 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1382384052 Mar 07 12:54:22 PM PST 24 Mar 07 12:54:23 PM PST 24 95139548 ps
T1114 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3750247030 Mar 07 12:54:39 PM PST 24 Mar 07 12:54:41 PM PST 24 967953263 ps
T1115 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.311253309 Mar 07 12:54:40 PM PST 24 Mar 07 12:54:41 PM PST 24 27431460 ps
T69 /workspace/coverage/cover_reg_top/5.uart_csr_rw.804837709 Mar 07 12:54:21 PM PST 24 Mar 07 12:54:21 PM PST 24 49372659 ps
T1116 /workspace/coverage/cover_reg_top/4.uart_intr_test.1288157509 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:10 PM PST 24 42748773 ps
T1117 /workspace/coverage/cover_reg_top/42.uart_intr_test.2004508313 Mar 07 12:54:30 PM PST 24 Mar 07 12:54:31 PM PST 24 40108911 ps
T1118 /workspace/coverage/cover_reg_top/5.uart_intr_test.2071859746 Mar 07 12:54:26 PM PST 24 Mar 07 12:54:27 PM PST 24 21895237 ps
T1119 /workspace/coverage/cover_reg_top/23.uart_intr_test.1449067163 Mar 07 12:54:47 PM PST 24 Mar 07 12:54:48 PM PST 24 13937543 ps
T1120 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2912119629 Mar 07 12:54:39 PM PST 24 Mar 07 12:54:40 PM PST 24 28614606 ps
T1121 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3504211210 Mar 07 12:54:35 PM PST 24 Mar 07 12:54:37 PM PST 24 110248121 ps
T1122 /workspace/coverage/cover_reg_top/6.uart_intr_test.2441294477 Mar 07 12:54:23 PM PST 24 Mar 07 12:54:24 PM PST 24 34656317 ps
T55 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.829771191 Mar 07 12:54:30 PM PST 24 Mar 07 12:54:31 PM PST 24 50825347 ps
T1123 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3123068133 Mar 07 12:54:28 PM PST 24 Mar 07 12:54:29 PM PST 24 25880587 ps
T1124 /workspace/coverage/cover_reg_top/7.uart_intr_test.3957178595 Mar 07 12:54:25 PM PST 24 Mar 07 12:54:26 PM PST 24 32349413 ps
T1125 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3950286888 Mar 07 12:54:41 PM PST 24 Mar 07 12:54:43 PM PST 24 108226036 ps
T79 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1295929846 Mar 07 12:54:25 PM PST 24 Mar 07 12:54:26 PM PST 24 521648890 ps
T1126 /workspace/coverage/cover_reg_top/12.uart_intr_test.3843394488 Mar 07 12:54:27 PM PST 24 Mar 07 12:54:28 PM PST 24 25337452 ps
T1127 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3618461173 Mar 07 12:54:14 PM PST 24 Mar 07 12:54:15 PM PST 24 15243705 ps
T1128 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3239065367 Mar 07 12:54:13 PM PST 24 Mar 07 12:54:14 PM PST 24 63273233 ps
T1129 /workspace/coverage/cover_reg_top/1.uart_intr_test.2583991259 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:10 PM PST 24 11819239 ps
T1130 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2771924673 Mar 07 12:54:27 PM PST 24 Mar 07 12:54:28 PM PST 24 28458843 ps
T56 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1996182677 Mar 07 12:54:37 PM PST 24 Mar 07 12:54:38 PM PST 24 17568197 ps
T80 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.55850034 Mar 07 12:54:19 PM PST 24 Mar 07 12:54:20 PM PST 24 97245154 ps
T1131 /workspace/coverage/cover_reg_top/8.uart_intr_test.2574684394 Mar 07 12:54:23 PM PST 24 Mar 07 12:54:24 PM PST 24 22523193 ps
T1132 /workspace/coverage/cover_reg_top/24.uart_intr_test.60433295 Mar 07 12:54:59 PM PST 24 Mar 07 12:55:01 PM PST 24 89842963 ps
T1133 /workspace/coverage/cover_reg_top/14.uart_intr_test.972665480 Mar 07 12:54:40 PM PST 24 Mar 07 12:54:41 PM PST 24 202892687 ps
T1134 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3730442831 Mar 07 12:54:36 PM PST 24 Mar 07 12:54:37 PM PST 24 126454609 ps
T84 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3210843082 Mar 07 12:54:33 PM PST 24 Mar 07 12:54:34 PM PST 24 109942833 ps
T1135 /workspace/coverage/cover_reg_top/39.uart_intr_test.3106181027 Mar 07 12:54:44 PM PST 24 Mar 07 12:54:45 PM PST 24 32543120 ps
T70 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1913683528 Mar 07 12:54:35 PM PST 24 Mar 07 12:54:35 PM PST 24 327962185 ps
T81 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1051970199 Mar 07 12:54:28 PM PST 24 Mar 07 12:54:29 PM PST 24 42888436 ps
T71 /workspace/coverage/cover_reg_top/7.uart_csr_rw.4141743493 Mar 07 12:54:14 PM PST 24 Mar 07 12:54:15 PM PST 24 61878420 ps
T72 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2950423240 Mar 07 12:54:18 PM PST 24 Mar 07 12:54:19 PM PST 24 16449250 ps
T1136 /workspace/coverage/cover_reg_top/27.uart_intr_test.4025013027 Mar 07 12:54:47 PM PST 24 Mar 07 12:54:47 PM PST 24 41719663 ps
T390 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3164353077 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:30 PM PST 24 94869402 ps
T73 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.696942748 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:30 PM PST 24 29039550 ps
T1137 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3365492894 Mar 07 12:54:31 PM PST 24 Mar 07 12:54:32 PM PST 24 160744741 ps
T1138 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1883975379 Mar 07 12:54:23 PM PST 24 Mar 07 12:54:24 PM PST 24 34248490 ps
T1139 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3289850348 Mar 07 12:54:33 PM PST 24 Mar 07 12:54:34 PM PST 24 143888031 ps
T57 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1280227116 Mar 07 12:54:11 PM PST 24 Mar 07 12:54:12 PM PST 24 31344658 ps
T85 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.696221689 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:30 PM PST 24 53740059 ps
T74 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.122210753 Mar 07 12:54:30 PM PST 24 Mar 07 12:54:31 PM PST 24 99390798 ps
T86 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.510483332 Mar 07 12:54:47 PM PST 24 Mar 07 12:54:48 PM PST 24 43294179 ps
T1140 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2561293951 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:03 PM PST 24 38707158 ps
T58 /workspace/coverage/cover_reg_top/0.uart_csr_rw.876374488 Mar 07 12:53:58 PM PST 24 Mar 07 12:53:59 PM PST 24 14468127 ps
T1141 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2138310333 Mar 07 12:54:28 PM PST 24 Mar 07 12:54:29 PM PST 24 33522267 ps
T59 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3269178481 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:33 PM PST 24 16342926 ps
T1142 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1304782095 Mar 07 12:54:03 PM PST 24 Mar 07 12:54:05 PM PST 24 95691650 ps
T1143 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1654512192 Mar 07 12:54:16 PM PST 24 Mar 07 12:54:18 PM PST 24 174646380 ps
T1144 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2096049845 Mar 07 12:54:22 PM PST 24 Mar 07 12:54:24 PM PST 24 135049976 ps
T1145 /workspace/coverage/cover_reg_top/10.uart_intr_test.409392822 Mar 07 12:54:25 PM PST 24 Mar 07 12:54:26 PM PST 24 48802824 ps
T1146 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3661497 Mar 07 12:54:44 PM PST 24 Mar 07 12:54:45 PM PST 24 23761817 ps
T1147 /workspace/coverage/cover_reg_top/17.uart_intr_test.1753225856 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:33 PM PST 24 13736712 ps
T1148 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1593559410 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:31 PM PST 24 22292966 ps
T1149 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3245906701 Mar 07 12:54:24 PM PST 24 Mar 07 12:54:25 PM PST 24 77166531 ps
T1150 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3574893064 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:32 PM PST 24 66624840 ps
T1151 /workspace/coverage/cover_reg_top/21.uart_intr_test.2864649105 Mar 07 12:54:39 PM PST 24 Mar 07 12:54:40 PM PST 24 33790447 ps
T1152 /workspace/coverage/cover_reg_top/29.uart_intr_test.486038433 Mar 07 12:54:39 PM PST 24 Mar 07 12:54:40 PM PST 24 17407924 ps
T1153 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2809458664 Mar 07 12:54:18 PM PST 24 Mar 07 12:54:19 PM PST 24 51331040 ps
T1154 /workspace/coverage/cover_reg_top/25.uart_intr_test.972775948 Mar 07 12:54:48 PM PST 24 Mar 07 12:54:49 PM PST 24 146840790 ps
T1155 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1121527462 Mar 07 12:54:33 PM PST 24 Mar 07 12:54:34 PM PST 24 30922168 ps
T1156 /workspace/coverage/cover_reg_top/18.uart_intr_test.1498109902 Mar 07 12:54:46 PM PST 24 Mar 07 12:54:46 PM PST 24 13959068 ps
T1157 /workspace/coverage/cover_reg_top/34.uart_intr_test.2160453142 Mar 07 12:54:40 PM PST 24 Mar 07 12:54:41 PM PST 24 41409519 ps
T1158 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2442817953 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:18 PM PST 24 121144634 ps
T1159 /workspace/coverage/cover_reg_top/32.uart_intr_test.1759959315 Mar 07 12:54:36 PM PST 24 Mar 07 12:54:37 PM PST 24 38075648 ps
T1160 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3499082887 Mar 07 12:54:50 PM PST 24 Mar 07 12:54:51 PM PST 24 18930474 ps
T1161 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3231678567 Mar 07 12:54:26 PM PST 24 Mar 07 12:54:28 PM PST 24 469120583 ps
T1162 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1907677124 Mar 07 12:54:39 PM PST 24 Mar 07 12:54:41 PM PST 24 274977316 ps
T60 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3687808905 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:30 PM PST 24 16895738 ps
T1163 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2784106271 Mar 07 12:54:38 PM PST 24 Mar 07 12:54:39 PM PST 24 40716834 ps
T1164 /workspace/coverage/cover_reg_top/3.uart_intr_test.319990554 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:18 PM PST 24 121018105 ps
T1165 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2329786925 Mar 07 12:54:03 PM PST 24 Mar 07 12:54:04 PM PST 24 15645157 ps
T1166 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2581713759 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:31 PM PST 24 371161609 ps
T1167 /workspace/coverage/cover_reg_top/31.uart_intr_test.2434876824 Mar 07 12:54:47 PM PST 24 Mar 07 12:54:48 PM PST 24 117867126 ps
T1168 /workspace/coverage/cover_reg_top/38.uart_intr_test.3809976814 Mar 07 12:54:46 PM PST 24 Mar 07 12:54:47 PM PST 24 12011740 ps
T1169 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3932003546 Mar 07 12:54:21 PM PST 24 Mar 07 12:54:22 PM PST 24 21394808 ps
T1170 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4004621102 Mar 07 12:54:13 PM PST 24 Mar 07 12:54:15 PM PST 24 1031979845 ps
T82 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.983778010 Mar 07 12:54:34 PM PST 24 Mar 07 12:54:35 PM PST 24 342547505 ps
T1171 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.4057218310 Mar 07 12:54:28 PM PST 24 Mar 07 12:54:29 PM PST 24 184244088 ps
T1172 /workspace/coverage/cover_reg_top/41.uart_intr_test.3240851276 Mar 07 12:54:31 PM PST 24 Mar 07 12:54:31 PM PST 24 128321252 ps
T1173 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.761279921 Mar 07 12:54:33 PM PST 24 Mar 07 12:54:39 PM PST 24 196174242 ps
T1174 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3530337544 Mar 07 12:54:28 PM PST 24 Mar 07 12:54:29 PM PST 24 28641386 ps
T1175 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.39349622 Mar 07 12:54:26 PM PST 24 Mar 07 12:54:27 PM PST 24 35153287 ps
T1176 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3618048475 Mar 07 12:54:35 PM PST 24 Mar 07 12:54:36 PM PST 24 159164801 ps
T1177 /workspace/coverage/cover_reg_top/35.uart_intr_test.1940478584 Mar 07 12:54:40 PM PST 24 Mar 07 12:54:41 PM PST 24 14254892 ps
T1178 /workspace/coverage/cover_reg_top/37.uart_intr_test.2392488847 Mar 07 12:54:41 PM PST 24 Mar 07 12:54:42 PM PST 24 41312394 ps
T1179 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.122988989 Mar 07 12:54:24 PM PST 24 Mar 07 12:54:25 PM PST 24 221137941 ps
T1180 /workspace/coverage/cover_reg_top/28.uart_intr_test.134463757 Mar 07 12:54:46 PM PST 24 Mar 07 12:54:47 PM PST 24 13414050 ps
T1181 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.4237875615 Mar 07 12:54:45 PM PST 24 Mar 07 12:54:46 PM PST 24 47905188 ps
T1182 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3496318942 Mar 07 12:54:08 PM PST 24 Mar 07 12:54:09 PM PST 24 27033190 ps
T61 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3469887267 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:18 PM PST 24 255749024 ps
T87 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1377888135 Mar 07 12:54:31 PM PST 24 Mar 07 12:54:32 PM PST 24 943054082 ps
T1183 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2767084550 Mar 07 12:54:30 PM PST 24 Mar 07 12:54:31 PM PST 24 25619126 ps
T1184 /workspace/coverage/cover_reg_top/16.uart_intr_test.443058684 Mar 07 12:54:38 PM PST 24 Mar 07 12:54:38 PM PST 24 15009822 ps
T1185 /workspace/coverage/cover_reg_top/45.uart_intr_test.986084151 Mar 07 12:54:47 PM PST 24 Mar 07 12:54:48 PM PST 24 13131841 ps
T1186 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1561320438 Mar 07 12:54:23 PM PST 24 Mar 07 12:54:24 PM PST 24 18186228 ps
T62 /workspace/coverage/cover_reg_top/10.uart_csr_rw.67067943 Mar 07 12:54:24 PM PST 24 Mar 07 12:54:24 PM PST 24 45161592 ps
T1187 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1545235619 Mar 07 12:54:34 PM PST 24 Mar 07 12:54:35 PM PST 24 16381267 ps
T1188 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2716130671 Mar 07 12:54:38 PM PST 24 Mar 07 12:54:39 PM PST 24 22011199 ps
T1189 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.245980841 Mar 07 12:54:50 PM PST 24 Mar 07 12:54:51 PM PST 24 16248927 ps
T1190 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2814734710 Mar 07 12:54:26 PM PST 24 Mar 07 12:54:27 PM PST 24 36135663 ps
T1191 /workspace/coverage/cover_reg_top/19.uart_intr_test.2929367776 Mar 07 12:54:44 PM PST 24 Mar 07 12:54:45 PM PST 24 19782419 ps
T1192 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.620934611 Mar 07 12:54:33 PM PST 24 Mar 07 12:54:35 PM PST 24 412055107 ps
T1193 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.514116215 Mar 07 12:54:22 PM PST 24 Mar 07 12:54:23 PM PST 24 17159366 ps
T1194 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1598764191 Mar 07 12:54:30 PM PST 24 Mar 07 12:54:31 PM PST 24 19216986 ps
T1195 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2671569257 Mar 07 12:54:33 PM PST 24 Mar 07 12:54:33 PM PST 24 17568765 ps
T1196 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2028640074 Mar 07 12:54:11 PM PST 24 Mar 07 12:54:14 PM PST 24 251779920 ps
T1197 /workspace/coverage/cover_reg_top/26.uart_intr_test.3630179256 Mar 07 12:54:39 PM PST 24 Mar 07 12:54:40 PM PST 24 11458264 ps
T1198 /workspace/coverage/cover_reg_top/20.uart_intr_test.2002364586 Mar 07 12:54:45 PM PST 24 Mar 07 12:54:46 PM PST 24 101893507 ps
T1199 /workspace/coverage/cover_reg_top/9.uart_intr_test.863236447 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:18 PM PST 24 41538616 ps
T1200 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3817873462 Mar 07 12:54:40 PM PST 24 Mar 07 12:54:42 PM PST 24 132354180 ps
T1201 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1696152450 Mar 07 12:54:34 PM PST 24 Mar 07 12:54:35 PM PST 24 18222587 ps
T1202 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2735057362 Mar 07 12:54:27 PM PST 24 Mar 07 12:54:29 PM PST 24 558015212 ps
T1203 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3534299148 Mar 07 12:54:16 PM PST 24 Mar 07 12:54:17 PM PST 24 14539331 ps
T1204 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1771868783 Mar 07 12:54:31 PM PST 24 Mar 07 12:54:32 PM PST 24 42127305 ps
T63 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1839702711 Mar 07 12:54:38 PM PST 24 Mar 07 12:54:39 PM PST 24 49425796 ps
T1205 /workspace/coverage/cover_reg_top/5.uart_tl_errors.33193065 Mar 07 12:54:19 PM PST 24 Mar 07 12:54:21 PM PST 24 57784758 ps
T1206 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2346087339 Mar 07 12:54:27 PM PST 24 Mar 07 12:54:28 PM PST 24 16227200 ps
T1207 /workspace/coverage/cover_reg_top/30.uart_intr_test.1680384267 Mar 07 12:54:34 PM PST 24 Mar 07 12:54:35 PM PST 24 15093711 ps
T1208 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3194524707 Mar 07 12:54:42 PM PST 24 Mar 07 12:54:43 PM PST 24 57587181 ps
T1209 /workspace/coverage/cover_reg_top/47.uart_intr_test.292101778 Mar 07 12:54:43 PM PST 24 Mar 07 12:54:44 PM PST 24 38328955 ps
T1210 /workspace/coverage/cover_reg_top/0.uart_intr_test.2967738638 Mar 07 12:54:13 PM PST 24 Mar 07 12:54:14 PM PST 24 35224197 ps
T1211 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3363735724 Mar 07 12:54:22 PM PST 24 Mar 07 12:54:24 PM PST 24 167561792 ps
T1212 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1698706935 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:30 PM PST 24 41901961 ps
T1213 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.334594412 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:33 PM PST 24 45657613 ps
T1214 /workspace/coverage/cover_reg_top/46.uart_intr_test.3610259631 Mar 07 12:54:37 PM PST 24 Mar 07 12:54:38 PM PST 24 13152660 ps
T1215 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1597054075 Mar 07 12:54:21 PM PST 24 Mar 07 12:54:22 PM PST 24 502945822 ps
T64 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2769018954 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:18 PM PST 24 14121490 ps
T1216 /workspace/coverage/cover_reg_top/48.uart_intr_test.3902973173 Mar 07 12:54:50 PM PST 24 Mar 07 12:54:51 PM PST 24 52137900 ps
T1217 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3317323121 Mar 07 12:54:24 PM PST 24 Mar 07 12:54:25 PM PST 24 19375345 ps
T1218 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3417441535 Mar 07 12:54:08 PM PST 24 Mar 07 12:54:10 PM PST 24 53825092 ps
T1219 /workspace/coverage/cover_reg_top/13.uart_intr_test.2243320375 Mar 07 12:54:34 PM PST 24 Mar 07 12:54:35 PM PST 24 33843306 ps
T1220 /workspace/coverage/cover_reg_top/13.uart_csr_rw.550691764 Mar 07 12:54:34 PM PST 24 Mar 07 12:54:35 PM PST 24 14348247 ps
T1221 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4010346539 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:11 PM PST 24 97511433 ps
T1222 /workspace/coverage/cover_reg_top/43.uart_intr_test.1543547990 Mar 07 12:54:42 PM PST 24 Mar 07 12:54:43 PM PST 24 23386603 ps
T1223 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3715787937 Mar 07 12:54:20 PM PST 24 Mar 07 12:54:20 PM PST 24 49413280 ps
T1224 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2052060788 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:31 PM PST 24 309586618 ps
T1225 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1848308127 Mar 07 12:54:31 PM PST 24 Mar 07 12:54:33 PM PST 24 324334754 ps
T1226 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.254934341 Mar 07 12:54:30 PM PST 24 Mar 07 12:54:31 PM PST 24 41009672 ps
T1227 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2588224723 Mar 07 12:54:19 PM PST 24 Mar 07 12:54:20 PM PST 24 50261572 ps
T1228 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3765202182 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:34 PM PST 24 423811037 ps
T1229 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.307150368 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:29 PM PST 24 15467475 ps
T65 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2903086928 Mar 07 12:54:34 PM PST 24 Mar 07 12:54:34 PM PST 24 47599614 ps
T1230 /workspace/coverage/cover_reg_top/11.uart_intr_test.2777304407 Mar 07 12:54:27 PM PST 24 Mar 07 12:54:27 PM PST 24 38351185 ps
T83 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2978842724 Mar 07 12:54:27 PM PST 24 Mar 07 12:54:28 PM PST 24 41261875 ps
T1231 /workspace/coverage/cover_reg_top/36.uart_intr_test.3265793069 Mar 07 12:54:44 PM PST 24 Mar 07 12:54:45 PM PST 24 11430808 ps
T1232 /workspace/coverage/cover_reg_top/22.uart_intr_test.1642407620 Mar 07 12:54:59 PM PST 24 Mar 07 12:55:00 PM PST 24 221862575 ps
T66 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3565598886 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:29 PM PST 24 23179509 ps
T1233 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2140036403 Mar 07 12:54:21 PM PST 24 Mar 07 12:54:22 PM PST 24 323581942 ps
T1234 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.45150972 Mar 07 12:54:06 PM PST 24 Mar 07 12:54:12 PM PST 24 63851293 ps
T1235 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4032801128 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:38 PM PST 24 18821177 ps
T1236 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.877770861 Mar 07 12:54:39 PM PST 24 Mar 07 12:54:40 PM PST 24 63704767 ps
T1237 /workspace/coverage/cover_reg_top/4.uart_csr_rw.488270629 Mar 07 12:54:30 PM PST 24 Mar 07 12:54:31 PM PST 24 13677745 ps
T1238 /workspace/coverage/cover_reg_top/15.uart_intr_test.2553699289 Mar 07 12:54:34 PM PST 24 Mar 07 12:54:35 PM PST 24 11602995 ps
T1239 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2031548491 Mar 07 12:54:26 PM PST 24 Mar 07 12:54:28 PM PST 24 80139685 ps
T1240 /workspace/coverage/cover_reg_top/49.uart_intr_test.861267250 Mar 07 12:54:42 PM PST 24 Mar 07 12:54:42 PM PST 24 12620753 ps

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4139714341
Short name T9
Test name
Test status
Simulation time 87776819572 ps
CPU time 335.7 seconds
Started Mar 07 01:43:44 PM PST 24
Finished Mar 07 01:49:20 PM PST 24
Peak memory 216300 kb
Host smart-65fb4231-b598-4b47-9836-c5bacc3b5b9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139714341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4139714341
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.268203881
Short name T19
Test name
Test status
Simulation time 71036632053 ps
CPU time 408.67 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:52:23 PM PST 24
Peak memory 200488 kb
Host smart-96125ebd-3ea4-41f9-b09d-b319dad9cd1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268203881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.268203881
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all.3298887881
Short name T18
Test name
Test status
Simulation time 1795713026675 ps
CPU time 3163.75 seconds
Started Mar 07 01:45:47 PM PST 24
Finished Mar 07 02:38:31 PM PST 24
Peak memory 200468 kb
Host smart-7b6c6c0f-9e4d-402a-a4d8-5642d7015f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298887881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3298887881
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all.2246791275
Short name T151
Test name
Test status
Simulation time 402744564349 ps
CPU time 484.05 seconds
Started Mar 07 01:45:04 PM PST 24
Finished Mar 07 01:53:08 PM PST 24
Peak memory 200508 kb
Host smart-c5bf4518-6d7d-43c5-810c-c3186c0fdaf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246791275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2246791275
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all.1875316068
Short name T1
Test name
Test status
Simulation time 332971666573 ps
CPU time 307.2 seconds
Started Mar 07 01:44:44 PM PST 24
Finished Mar 07 01:49:52 PM PST 24
Peak memory 200600 kb
Host smart-d21825b8-2db4-4eaf-841d-58e406401829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875316068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1875316068
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2602943359
Short name T466
Test name
Test status
Simulation time 132097170469 ps
CPU time 235.19 seconds
Started Mar 07 01:46:33 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 200520 kb
Host smart-b3754303-c6e5-4305-8ae1-49fffd4b73b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602943359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2602943359
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_stress_all.430872282
Short name T76
Test name
Test status
Simulation time 791449520864 ps
CPU time 96.98 seconds
Started Mar 07 01:43:56 PM PST 24
Finished Mar 07 01:45:34 PM PST 24
Peak memory 200556 kb
Host smart-786b9778-15b3-4f98-8789-a55380ac0b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430872282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.430872282
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2810508358
Short name T28
Test name
Test status
Simulation time 577594302 ps
CPU time 0.86 seconds
Started Mar 07 01:43:46 PM PST 24
Finished Mar 07 01:43:47 PM PST 24
Peak memory 217972 kb
Host smart-cbbc63f2-9c80-4494-a912-408be892373b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810508358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2810508358
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/44.uart_stress_all.1635325798
Short name T153
Test name
Test status
Simulation time 203862767056 ps
CPU time 110.35 seconds
Started Mar 07 01:46:22 PM PST 24
Finished Mar 07 01:48:13 PM PST 24
Peak memory 200572 kb
Host smart-029a541b-abde-45f6-8010-8aed410895b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635325798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1635325798
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2535382807
Short name T23
Test name
Test status
Simulation time 86357753295 ps
CPU time 662.05 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:57:19 PM PST 24
Peak memory 217368 kb
Host smart-f4a98454-81b3-4f79-a8fc-d8edfe64f33a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535382807 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2535382807
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.2089617969
Short name T391
Test name
Test status
Simulation time 1816432149710 ps
CPU time 380.43 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:51:17 PM PST 24
Peak memory 200532 kb
Host smart-be0b600c-32da-4669-bb62-73931d6ed000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089617969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2089617969
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3060475300
Short name T33
Test name
Test status
Simulation time 43711510883 ps
CPU time 209.73 seconds
Started Mar 07 01:45:08 PM PST 24
Finished Mar 07 01:48:38 PM PST 24
Peak memory 208944 kb
Host smart-b7b7b010-5f13-4d77-a8a3-bfc39d3c702c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060475300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3060475300
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_perf.1268322246
Short name T3
Test name
Test status
Simulation time 13686019948 ps
CPU time 788.69 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:58:25 PM PST 24
Peak memory 200516 kb
Host smart-0ac5278a-9ca9-48aa-94a8-f41af2edb5fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268322246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1268322246
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.62098520
Short name T133
Test name
Test status
Simulation time 169940652445 ps
CPU time 73.84 seconds
Started Mar 07 01:47:59 PM PST 24
Finished Mar 07 01:49:13 PM PST 24
Peak memory 200592 kb
Host smart-b2fcb540-227a-47f0-b918-b9110ddcae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62098520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.62098520
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.3348670390
Short name T342
Test name
Test status
Simulation time 580373052477 ps
CPU time 226.77 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:47:35 PM PST 24
Peak memory 200456 kb
Host smart-967a0cb7-6ae5-4e7a-b0f2-0f104c34756b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348670390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3348670390
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.55850034
Short name T80
Test name
Test status
Simulation time 97245154 ps
CPU time 1.3 seconds
Started Mar 07 12:54:19 PM PST 24
Finished Mar 07 12:54:20 PM PST 24
Peak memory 199428 kb
Host smart-4b95cec0-727d-4353-b9ad-5f08f26237fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55850034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.55850034
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/2.uart_intr.3311451587
Short name T419
Test name
Test status
Simulation time 183365291309 ps
CPU time 216.99 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:47:25 PM PST 24
Peak memory 200544 kb
Host smart-8accf402-0ca8-447f-a8c9-57f1114e471b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311451587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3311451587
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/10.uart_alert_test.931492815
Short name T468
Test name
Test status
Simulation time 56213797 ps
CPU time 0.55 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:44:35 PM PST 24
Peak memory 196000 kb
Host smart-fcf33d00-4f75-4bdb-a324-5cd2cc4fe4b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931492815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.931492815
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.729950617
Short name T121
Test name
Test status
Simulation time 84653226765 ps
CPU time 54.19 seconds
Started Mar 07 01:46:59 PM PST 24
Finished Mar 07 01:47:54 PM PST 24
Peak memory 200600 kb
Host smart-ce104e6a-52ee-41b3-951e-8971158a26a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729950617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.729950617
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1996182677
Short name T56
Test name
Test status
Simulation time 17568197 ps
CPU time 0.6 seconds
Started Mar 07 12:54:37 PM PST 24
Finished Mar 07 12:54:38 PM PST 24
Peak memory 195496 kb
Host smart-38dbcff6-b5e3-48cc-b87a-dde6c6969759
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996182677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1996182677
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3150787014
Short name T322
Test name
Test status
Simulation time 138077638706 ps
CPU time 218.51 seconds
Started Mar 07 01:45:35 PM PST 24
Finished Mar 07 01:49:14 PM PST 24
Peak memory 200564 kb
Host smart-5cb4bb1f-6c07-4c0e-a7a7-2ffd02d7b6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150787014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3150787014
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.381715088
Short name T43
Test name
Test status
Simulation time 149620565164 ps
CPU time 164.94 seconds
Started Mar 07 01:46:33 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 200368 kb
Host smart-0244df1a-12db-41d5-8803-c2ea3ce86b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381715088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.381715088
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3495539540
Short name T168
Test name
Test status
Simulation time 140584770580 ps
CPU time 121.22 seconds
Started Mar 07 01:47:40 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 200568 kb
Host smart-93da7adc-5631-48c1-8674-c3cca8f0d700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495539540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3495539540
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.841567095
Short name T39
Test name
Test status
Simulation time 96741767644 ps
CPU time 55.83 seconds
Started Mar 07 01:47:16 PM PST 24
Finished Mar 07 01:48:13 PM PST 24
Peak memory 200596 kb
Host smart-51fda734-2ed0-48b1-b7f1-9f56d3859d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841567095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.841567095
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1893891209
Short name T107
Test name
Test status
Simulation time 128238227967 ps
CPU time 733.03 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:57:47 PM PST 24
Peak memory 200456 kb
Host smart-e703edf8-c17a-40b6-99f8-c1796dc3bbf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893891209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1893891209
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1403335393
Short name T141
Test name
Test status
Simulation time 95658336647 ps
CPU time 362.79 seconds
Started Mar 07 01:47:16 PM PST 24
Finished Mar 07 01:53:20 PM PST 24
Peak memory 200600 kb
Host smart-29754923-fc35-48e4-bb66-47be1bc8bca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403335393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1403335393
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.4282000002
Short name T161
Test name
Test status
Simulation time 214522929610 ps
CPU time 1048.81 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 02:01:14 PM PST 24
Peak memory 200552 kb
Host smart-62d32e97-0536-4cd8-9c45-421611fe94bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282000002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.4282000002
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2314962812
Short name T122
Test name
Test status
Simulation time 26155329187 ps
CPU time 43.79 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:45 PM PST 24
Peak memory 200580 kb
Host smart-cbfabc87-e243-409f-87d0-488c6f41fda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314962812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2314962812
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2753558240
Short name T163
Test name
Test status
Simulation time 124448921347 ps
CPU time 190.21 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:50:32 PM PST 24
Peak memory 200512 kb
Host smart-d4325616-e8f2-41f4-9cc8-59abbb8da2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753558240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2753558240
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.983778010
Short name T82
Test name
Test status
Simulation time 342547505 ps
CPU time 1.32 seconds
Started Mar 07 12:54:34 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 199112 kb
Host smart-fb0887cb-a7d1-4dd6-a94d-b8639a09e87d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983778010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.983778010
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.4064567065
Short name T94
Test name
Test status
Simulation time 11587508593 ps
CPU time 19.23 seconds
Started Mar 07 01:47:15 PM PST 24
Finished Mar 07 01:47:34 PM PST 24
Peak memory 200480 kb
Host smart-c26e9e73-383b-4c82-a3be-e89ec832374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064567065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.4064567065
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3307540104
Short name T147
Test name
Test status
Simulation time 118548741405 ps
CPU time 28.27 seconds
Started Mar 07 01:47:23 PM PST 24
Finished Mar 07 01:47:51 PM PST 24
Peak memory 200580 kb
Host smart-61125183-ae55-4e72-b62a-22dba80d5646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307540104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3307540104
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1581177714
Short name T200
Test name
Test status
Simulation time 362326205147 ps
CPU time 845.04 seconds
Started Mar 07 01:46:47 PM PST 24
Finished Mar 07 02:00:53 PM PST 24
Peak memory 217380 kb
Host smart-44e4cf0b-3305-4ff5-a087-9e83b053b3aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581177714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1581177714
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2921017192
Short name T166
Test name
Test status
Simulation time 14811567649 ps
CPU time 25.9 seconds
Started Mar 07 01:46:47 PM PST 24
Finished Mar 07 01:47:14 PM PST 24
Peak memory 200344 kb
Host smart-3c07a6bb-f5d7-4ce1-8e12-91eab2610cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921017192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2921017192
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2026503910
Short name T191
Test name
Test status
Simulation time 184629097578 ps
CPU time 28.86 seconds
Started Mar 07 01:46:18 PM PST 24
Finished Mar 07 01:46:47 PM PST 24
Peak memory 200548 kb
Host smart-df8a4667-8322-4e7c-8682-979645e31a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026503910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2026503910
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.106127799
Short name T253
Test name
Test status
Simulation time 91122436134 ps
CPU time 43.11 seconds
Started Mar 07 01:47:17 PM PST 24
Finished Mar 07 01:48:01 PM PST 24
Peak memory 200408 kb
Host smart-929448e7-a574-4270-b91d-5491b73ac5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106127799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.106127799
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.531522175
Short name T17
Test name
Test status
Simulation time 29699831861 ps
CPU time 44.52 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:45:27 PM PST 24
Peak memory 200500 kb
Host smart-2602d540-85d5-4ef1-bf7e-1932d54705e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531522175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.531522175
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3462665911
Short name T42
Test name
Test status
Simulation time 30911335167 ps
CPU time 22.98 seconds
Started Mar 07 01:46:53 PM PST 24
Finished Mar 07 01:47:17 PM PST 24
Peak memory 200440 kb
Host smart-cf028cf1-8973-43ac-b01c-a6de9ada2ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462665911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3462665911
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2603121079
Short name T276
Test name
Test status
Simulation time 243168031428 ps
CPU time 162.4 seconds
Started Mar 07 01:47:25 PM PST 24
Finished Mar 07 01:50:08 PM PST 24
Peak memory 200536 kb
Host smart-ebfb4a2c-6f6e-4b68-9554-38272e1d11e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603121079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2603121079
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.185971292
Short name T46
Test name
Test status
Simulation time 57277009763 ps
CPU time 23.88 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:45:12 PM PST 24
Peak memory 200460 kb
Host smart-298a026b-cd19-477e-9368-df1195061402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185971292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.185971292
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1795730008
Short name T221
Test name
Test status
Simulation time 72540173682 ps
CPU time 14.9 seconds
Started Mar 07 01:45:30 PM PST 24
Finished Mar 07 01:45:45 PM PST 24
Peak memory 200528 kb
Host smart-efd6513b-48dd-41b5-9ac9-72cebfe6d537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795730008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1795730008
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1136672346
Short name T132
Test name
Test status
Simulation time 19175593096 ps
CPU time 35.01 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:51 PM PST 24
Peak memory 200560 kb
Host smart-5f7047fe-de16-4764-a7fe-953d4ffc3726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136672346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1136672346
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.207241437
Short name T389
Test name
Test status
Simulation time 1071919379966 ps
CPU time 322.97 seconds
Started Mar 07 01:46:28 PM PST 24
Finished Mar 07 01:51:51 PM PST 24
Peak memory 200792 kb
Host smart-9e253d73-2f92-449d-97dd-8dcb0c819e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207241437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.207241437
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1439660119
Short name T210
Test name
Test status
Simulation time 189275541434 ps
CPU time 73.04 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:45:14 PM PST 24
Peak memory 200468 kb
Host smart-066de1d7-7102-41ae-a15d-520c269c595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439660119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1439660119
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2286942799
Short name T155
Test name
Test status
Simulation time 115238560767 ps
CPU time 109.8 seconds
Started Mar 07 01:47:29 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 200612 kb
Host smart-cd6e21d4-eb70-4d6b-af30-45e07b79a518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286942799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2286942799
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2380628152
Short name T222
Test name
Test status
Simulation time 6307449616 ps
CPU time 21.64 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:45:13 PM PST 24
Peak memory 200528 kb
Host smart-dc82576f-a647-4e80-becc-37f482cece07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380628152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2380628152
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2500800740
Short name T184
Test name
Test status
Simulation time 9197801782 ps
CPU time 18.57 seconds
Started Mar 07 01:47:29 PM PST 24
Finished Mar 07 01:47:48 PM PST 24
Peak memory 200488 kb
Host smart-c14c5073-d0e9-4073-83e4-22972e83f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500800740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2500800740
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3196924501
Short name T139
Test name
Test status
Simulation time 97424589690 ps
CPU time 119.39 seconds
Started Mar 07 01:47:54 PM PST 24
Finished Mar 07 01:49:54 PM PST 24
Peak memory 200448 kb
Host smart-75fa9231-0e73-47a9-9037-0b5dd9daf27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196924501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3196924501
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3143299751
Short name T325
Test name
Test status
Simulation time 29006522238 ps
CPU time 20.2 seconds
Started Mar 07 01:45:12 PM PST 24
Finished Mar 07 01:45:32 PM PST 24
Peak memory 200516 kb
Host smart-be0d1122-2be3-4deb-ade4-cd3eb03672f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143299751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3143299751
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2135176389
Short name T378
Test name
Test status
Simulation time 115361606386 ps
CPU time 19.19 seconds
Started Mar 07 01:47:18 PM PST 24
Finished Mar 07 01:47:37 PM PST 24
Peak memory 199604 kb
Host smart-bbcf6890-782a-4610-bc12-465e641d13a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135176389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2135176389
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.826773766
Short name T204
Test name
Test status
Simulation time 61578418198 ps
CPU time 30.99 seconds
Started Mar 07 01:47:16 PM PST 24
Finished Mar 07 01:47:47 PM PST 24
Peak memory 200248 kb
Host smart-a168124a-7504-424c-95ae-146f3b80e49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826773766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.826773766
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.4250156956
Short name T228
Test name
Test status
Simulation time 20671830871 ps
CPU time 18.66 seconds
Started Mar 07 01:47:16 PM PST 24
Finished Mar 07 01:47:35 PM PST 24
Peak memory 200500 kb
Host smart-b9b10a34-149f-45ac-8402-ccdb6dee0305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250156956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.4250156956
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2628289437
Short name T368
Test name
Test status
Simulation time 45920303037 ps
CPU time 19.87 seconds
Started Mar 07 01:47:10 PM PST 24
Finished Mar 07 01:47:30 PM PST 24
Peak memory 200188 kb
Host smart-254214d3-1fa2-49ff-ba41-e83c64f4ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628289437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2628289437
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1904996289
Short name T285
Test name
Test status
Simulation time 50553189899 ps
CPU time 40.92 seconds
Started Mar 07 01:47:30 PM PST 24
Finished Mar 07 01:48:11 PM PST 24
Peak memory 200472 kb
Host smart-b720861b-51e1-4ebc-82e3-95987a6a68e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904996289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1904996289
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3678411112
Short name T384
Test name
Test status
Simulation time 207651017158 ps
CPU time 41.08 seconds
Started Mar 07 01:47:28 PM PST 24
Finished Mar 07 01:48:09 PM PST 24
Peak memory 200520 kb
Host smart-55f27ddd-35ea-4bfe-aa91-dbcbe021af99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678411112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3678411112
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2800705935
Short name T350
Test name
Test status
Simulation time 18556380672 ps
CPU time 9.32 seconds
Started Mar 07 01:47:28 PM PST 24
Finished Mar 07 01:47:38 PM PST 24
Peak memory 200428 kb
Host smart-6368f9ce-0257-4704-86d7-b467e26fbc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800705935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2800705935
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.2303764932
Short name T329
Test name
Test status
Simulation time 298392066282 ps
CPU time 235.65 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:47:45 PM PST 24
Peak memory 200524 kb
Host smart-d42fdd1e-b35d-434f-9a00-82c52aafd0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303764932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2303764932
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1871038701
Short name T328
Test name
Test status
Simulation time 147048166253 ps
CPU time 62.37 seconds
Started Mar 07 01:45:07 PM PST 24
Finished Mar 07 01:46:10 PM PST 24
Peak memory 200580 kb
Host smart-91fa97f5-74fb-43c2-92ae-60f307701c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871038701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1871038701
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2486208299
Short name T288
Test name
Test status
Simulation time 273845114219 ps
CPU time 874.36 seconds
Started Mar 07 01:46:05 PM PST 24
Finished Mar 07 02:00:40 PM PST 24
Peak memory 225488 kb
Host smart-c72091e1-8fcd-4f0a-8869-7178a3b01c39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486208299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2486208299
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.574807497
Short name T257
Test name
Test status
Simulation time 20738307001 ps
CPU time 42.25 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:47:26 PM PST 24
Peak memory 200592 kb
Host smart-b07fe761-6766-4e49-a1f9-73730102c4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574807497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.574807497
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2891446861
Short name T281
Test name
Test status
Simulation time 105382430126 ps
CPU time 44.8 seconds
Started Mar 07 01:47:17 PM PST 24
Finished Mar 07 01:48:02 PM PST 24
Peak memory 200484 kb
Host smart-fed6da63-8eb3-4ee9-8d6d-e809dc838736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891446861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2891446861
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.684644444
Short name T223
Test name
Test status
Simulation time 99619613140 ps
CPU time 82.28 seconds
Started Mar 07 01:47:16 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 200296 kb
Host smart-c0f9bbf7-5f41-444e-a9fd-39eee9a61d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684644444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.684644444
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.540409887
Short name T282
Test name
Test status
Simulation time 40647791936 ps
CPU time 34.14 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:45:12 PM PST 24
Peak memory 200276 kb
Host smart-4b7eb494-7619-43e8-b5b5-c6b032043c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540409887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.540409887
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_stress_all.2133700907
Short name T291
Test name
Test status
Simulation time 533537031433 ps
CPU time 193.07 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:47:56 PM PST 24
Peak memory 200604 kb
Host smart-2bd6e96b-7a2e-4dcd-b56c-fba64c4d46ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133700907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2133700907
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2771770937
Short name T177
Test name
Test status
Simulation time 29896231707 ps
CPU time 26.88 seconds
Started Mar 07 01:47:24 PM PST 24
Finished Mar 07 01:47:51 PM PST 24
Peak memory 200504 kb
Host smart-db120a41-8b27-4ebe-a02d-1a94f5832716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771770937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2771770937
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3289642533
Short name T335
Test name
Test status
Simulation time 103029408539 ps
CPU time 46.39 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:45:34 PM PST 24
Peak memory 199700 kb
Host smart-840861da-4f4f-410a-9c98-9bc0e7dd3b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289642533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3289642533
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_stress_all.1895857017
Short name T312
Test name
Test status
Simulation time 115047373014 ps
CPU time 209.2 seconds
Started Mar 07 01:44:52 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 216056 kb
Host smart-82639085-c2c9-4e5c-ae78-bc788f27667a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895857017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1895857017
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2821126122
Short name T175
Test name
Test status
Simulation time 59005807673 ps
CPU time 38.38 seconds
Started Mar 07 01:47:40 PM PST 24
Finished Mar 07 01:48:18 PM PST 24
Peak memory 200524 kb
Host smart-514dfc45-c86b-4bdc-ac97-aed0ccc9c9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821126122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2821126122
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2005126304
Short name T246
Test name
Test status
Simulation time 114508692177 ps
CPU time 71.81 seconds
Started Mar 07 01:47:41 PM PST 24
Finished Mar 07 01:48:53 PM PST 24
Peak memory 200600 kb
Host smart-4eca1c61-8a12-437b-8809-6529fdff9848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005126304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2005126304
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1880670067
Short name T340
Test name
Test status
Simulation time 193895806374 ps
CPU time 267.1 seconds
Started Mar 07 01:47:50 PM PST 24
Finished Mar 07 01:52:17 PM PST 24
Peak memory 200448 kb
Host smart-36b4ce7b-c3c7-41e7-8ee7-88a8a41ab2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880670067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1880670067
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.35891314
Short name T188
Test name
Test status
Simulation time 72748198685 ps
CPU time 31.04 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:48:24 PM PST 24
Peak memory 200512 kb
Host smart-1545fb78-79a0-489b-9de5-f30e77a06cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35891314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.35891314
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3142141988
Short name T332
Test name
Test status
Simulation time 232424754990 ps
CPU time 84.73 seconds
Started Mar 07 01:45:05 PM PST 24
Finished Mar 07 01:46:29 PM PST 24
Peak memory 200524 kb
Host smart-1ea95718-634e-40eb-a110-f92e0f02ea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142141988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3142141988
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2871961892
Short name T336
Test name
Test status
Simulation time 163249722392 ps
CPU time 73.4 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:49:07 PM PST 24
Peak memory 200120 kb
Host smart-fb4c435b-60f6-4a65-aea3-cfddcce6574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871961892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2871961892
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1652385291
Short name T136
Test name
Test status
Simulation time 67693791928 ps
CPU time 30.39 seconds
Started Mar 07 01:47:57 PM PST 24
Finished Mar 07 01:48:28 PM PST 24
Peak memory 200516 kb
Host smart-f2446502-fe80-4b47-a30f-0fd65d601e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652385291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1652385291
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.4157114674
Short name T858
Test name
Test status
Simulation time 47795793656 ps
CPU time 66.56 seconds
Started Mar 07 01:48:08 PM PST 24
Finished Mar 07 01:49:15 PM PST 24
Peak memory 200644 kb
Host smart-cfcb0dbc-006f-4f83-92c7-b8c976c85c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157114674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4157114674
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2591507706
Short name T261
Test name
Test status
Simulation time 51611992080 ps
CPU time 88.12 seconds
Started Mar 07 01:45:20 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 200500 kb
Host smart-e05ed0cb-65c5-4fa9-8487-a7131a18d490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591507706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2591507706
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2567728869
Short name T338
Test name
Test status
Simulation time 45951646474 ps
CPU time 25.03 seconds
Started Mar 07 01:48:07 PM PST 24
Finished Mar 07 01:48:32 PM PST 24
Peak memory 200636 kb
Host smart-13e17c26-7aa2-482a-a7d8-b68a40158256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567728869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2567728869
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2460247071
Short name T230
Test name
Test status
Simulation time 26088718547 ps
CPU time 8.71 seconds
Started Mar 07 01:46:19 PM PST 24
Finished Mar 07 01:46:28 PM PST 24
Peak memory 200608 kb
Host smart-d21448f3-2c9b-4488-991b-977f5828b870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460247071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2460247071
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3185554196
Short name T346
Test name
Test status
Simulation time 27551301211 ps
CPU time 14.9 seconds
Started Mar 07 01:46:21 PM PST 24
Finished Mar 07 01:46:36 PM PST 24
Peak memory 200256 kb
Host smart-ee610441-f01d-4f8c-bba5-548793fd2864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185554196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3185554196
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.254312126
Short name T374
Test name
Test status
Simulation time 467072730861 ps
CPU time 735.94 seconds
Started Mar 07 01:46:52 PM PST 24
Finished Mar 07 01:59:09 PM PST 24
Peak memory 217128 kb
Host smart-cceaeeb1-8aed-4400-9c89-9cf09d7d8f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254312126 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.254312126
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.4094364781
Short name T235
Test name
Test status
Simulation time 19131132565 ps
CPU time 32.09 seconds
Started Mar 07 01:47:05 PM PST 24
Finished Mar 07 01:47:38 PM PST 24
Peak memory 200460 kb
Host smart-c7697d79-e7bb-403b-a349-bae59aa52129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094364781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.4094364781
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.510483332
Short name T86
Test name
Test status
Simulation time 43294179 ps
CPU time 1 seconds
Started Mar 07 12:54:47 PM PST 24
Finished Mar 07 12:54:48 PM PST 24
Peak memory 198932 kb
Host smart-927bcb67-9841-46d3-8e0c-646da86c3d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510483332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.510483332
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_fifo_full.830711779
Short name T376
Test name
Test status
Simulation time 158065238348 ps
CPU time 25.19 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:44:10 PM PST 24
Peak memory 200288 kb
Host smart-2d663fc2-6ed6-46ec-931e-955f2ad58754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830711779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.830711779
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_perf.3317428234
Short name T295
Test name
Test status
Simulation time 9515619861 ps
CPU time 581.08 seconds
Started Mar 07 01:43:44 PM PST 24
Finished Mar 07 01:53:25 PM PST 24
Peak memory 200540 kb
Host smart-441249a4-aa40-49d2-bd61-cf3d15235cb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3317428234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3317428234
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1809323100
Short name T292
Test name
Test status
Simulation time 40658505226 ps
CPU time 35.16 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:45:10 PM PST 24
Peak memory 200644 kb
Host smart-320268fc-4239-456d-ac92-5e3077d3224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809323100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1809323100
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3119796727
Short name T179
Test name
Test status
Simulation time 230791989952 ps
CPU time 40.76 seconds
Started Mar 07 01:47:10 PM PST 24
Finished Mar 07 01:47:51 PM PST 24
Peak memory 200528 kb
Host smart-75f3a803-0d40-4cec-b64f-ca778b5b5407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119796727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3119796727
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3201823228
Short name T265
Test name
Test status
Simulation time 74201435644 ps
CPU time 30.62 seconds
Started Mar 07 01:47:16 PM PST 24
Finished Mar 07 01:47:47 PM PST 24
Peak memory 200480 kb
Host smart-e385adcb-37a3-4308-8c8f-2dfda69d4016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201823228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3201823228
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1242267859
Short name T196
Test name
Test status
Simulation time 79860263859 ps
CPU time 61.6 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:45:39 PM PST 24
Peak memory 200412 kb
Host smart-6c5c829c-3223-4550-b98d-b56387e0eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242267859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1242267859
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2542980989
Short name T360
Test name
Test status
Simulation time 20939054159 ps
CPU time 33.66 seconds
Started Mar 07 01:44:44 PM PST 24
Finished Mar 07 01:45:18 PM PST 24
Peak memory 200512 kb
Host smart-9aa0155f-c59a-4437-bcac-bf85121db307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542980989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2542980989
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3056134935
Short name T1085
Test name
Test status
Simulation time 91901808098 ps
CPU time 144.9 seconds
Started Mar 07 01:47:17 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 200504 kb
Host smart-9e35af6a-a7c8-4e4e-85c6-e3fd99ee5bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056134935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3056134935
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3520031681
Short name T145
Test name
Test status
Simulation time 14313643728 ps
CPU time 24.28 seconds
Started Mar 07 01:44:45 PM PST 24
Finished Mar 07 01:45:10 PM PST 24
Peak memory 200572 kb
Host smart-21654190-7129-4d64-b122-2d4b9de1133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520031681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3520031681
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_perf.902519870
Short name T289
Test name
Test status
Simulation time 18987407612 ps
CPU time 1029.54 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 02:01:52 PM PST 24
Peak memory 200584 kb
Host smart-04bd963a-df31-46c0-86d2-53f0986890f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902519870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.902519870
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_stress_all.1910151867
Short name T239
Test name
Test status
Simulation time 187995881766 ps
CPU time 497.9 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 01:53:05 PM PST 24
Peak memory 208936 kb
Host smart-0ad24406-974f-495c-9862-2feea5ff9498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910151867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1910151867
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2332744366
Short name T349
Test name
Test status
Simulation time 29134133591 ps
CPU time 13.64 seconds
Started Mar 07 01:47:22 PM PST 24
Finished Mar 07 01:47:36 PM PST 24
Peak memory 200352 kb
Host smart-5a6ac726-169b-41f6-af08-e1f8375d606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332744366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2332744366
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2984742176
Short name T284
Test name
Test status
Simulation time 85478935991 ps
CPU time 35.55 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:45:30 PM PST 24
Peak memory 200532 kb
Host smart-f4c1c494-a0e3-4599-8ebf-d0f22f3daf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984742176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2984742176
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1851029942
Short name T320
Test name
Test status
Simulation time 27425341908 ps
CPU time 48.16 seconds
Started Mar 07 01:47:27 PM PST 24
Finished Mar 07 01:48:15 PM PST 24
Peak memory 200492 kb
Host smart-9abdb9dd-79c3-4ba0-a1f4-a7b2d7a73715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851029942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1851029942
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2448934210
Short name T386
Test name
Test status
Simulation time 27807801190 ps
CPU time 12.65 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:45:00 PM PST 24
Peak memory 200316 kb
Host smart-08094f44-7369-455d-8a61-233a83ce5a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448934210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2448934210
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3875116265
Short name T258
Test name
Test status
Simulation time 42958433577 ps
CPU time 71.23 seconds
Started Mar 07 01:47:27 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 200396 kb
Host smart-b3af54fe-5435-4adf-a7fd-cd688341b13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875116265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3875116265
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2026802253
Short name T220
Test name
Test status
Simulation time 17366280213 ps
CPU time 9.37 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:43:54 PM PST 24
Peak memory 200568 kb
Host smart-1e02007b-e528-4b6a-a710-ebcc2a820e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026802253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2026802253
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.4267110230
Short name T356
Test name
Test status
Simulation time 26705358964 ps
CPU time 4.55 seconds
Started Mar 07 01:47:43 PM PST 24
Finished Mar 07 01:47:48 PM PST 24
Peak memory 200544 kb
Host smart-09e5f579-7f45-4f43-a604-71474f356779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267110230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.4267110230
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1124110309
Short name T293
Test name
Test status
Simulation time 41990731320 ps
CPU time 21.8 seconds
Started Mar 07 01:47:51 PM PST 24
Finished Mar 07 01:48:13 PM PST 24
Peak memory 200540 kb
Host smart-d21d287d-b35a-4c85-8eb7-d2296d2f2315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124110309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1124110309
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1751135599
Short name T195
Test name
Test status
Simulation time 74180342193 ps
CPU time 109.09 seconds
Started Mar 07 01:47:52 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 200512 kb
Host smart-1f0a74e1-3eca-4846-9865-a64d21c7e36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751135599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1751135599
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4066644845
Short name T243
Test name
Test status
Simulation time 87832431816 ps
CPU time 59.61 seconds
Started Mar 07 01:47:49 PM PST 24
Finished Mar 07 01:48:49 PM PST 24
Peak memory 200436 kb
Host smart-63970ce0-e381-4f46-9e66-f730d4f1086b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066644845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4066644845
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1526950391
Short name T171
Test name
Test status
Simulation time 20671987476 ps
CPU time 32.33 seconds
Started Mar 07 01:48:07 PM PST 24
Finished Mar 07 01:48:40 PM PST 24
Peak memory 200524 kb
Host smart-e985e308-797c-4922-9113-23664379a3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526950391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1526950391
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.820501348
Short name T205
Test name
Test status
Simulation time 32396750239 ps
CPU time 17.31 seconds
Started Mar 07 01:48:20 PM PST 24
Finished Mar 07 01:48:38 PM PST 24
Peak memory 200372 kb
Host smart-cabf7fc6-e0d8-4909-b0aa-31dde7dbdf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820501348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.820501348
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.948013697
Short name T385
Test name
Test status
Simulation time 196599623229 ps
CPU time 54.91 seconds
Started Mar 07 01:45:32 PM PST 24
Finished Mar 07 01:46:27 PM PST 24
Peak memory 200520 kb
Host smart-73d01300-64df-47b8-a113-f5f60c1d4f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948013697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.948013697
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.50818907
Short name T290
Test name
Test status
Simulation time 20933841733 ps
CPU time 8.86 seconds
Started Mar 07 01:45:35 PM PST 24
Finished Mar 07 01:45:44 PM PST 24
Peak memory 198216 kb
Host smart-4bb6c696-9011-490d-bb0f-b696d61078a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50818907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.50818907
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1789585172
Short name T366
Test name
Test status
Simulation time 44402966053 ps
CPU time 14.43 seconds
Started Mar 07 01:45:38 PM PST 24
Finished Mar 07 01:45:52 PM PST 24
Peak memory 200576 kb
Host smart-3701463f-e867-413a-bff4-339ea83dbe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789585172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1789585172
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.2357369053
Short name T354
Test name
Test status
Simulation time 76948416447 ps
CPU time 144.92 seconds
Started Mar 07 01:45:53 PM PST 24
Finished Mar 07 01:48:18 PM PST 24
Peak memory 200588 kb
Host smart-83f46822-0786-4624-94d7-e34f5681f0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357369053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2357369053
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3465126537
Short name T267
Test name
Test status
Simulation time 162994081229 ps
CPU time 564.88 seconds
Started Mar 07 01:45:54 PM PST 24
Finished Mar 07 01:55:20 PM PST 24
Peak memory 217356 kb
Host smart-2c4e4b68-d9b0-480c-97df-50993fe42a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465126537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3465126537
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.523419696
Short name T382
Test name
Test status
Simulation time 49902917484 ps
CPU time 71.02 seconds
Started Mar 07 01:46:07 PM PST 24
Finished Mar 07 01:47:19 PM PST 24
Peak memory 200556 kb
Host smart-6cef6723-51da-4670-81c3-039654e2cddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523419696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.523419696
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2327513439
Short name T372
Test name
Test status
Simulation time 82508216058 ps
CPU time 248.65 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:50:15 PM PST 24
Peak memory 215780 kb
Host smart-0e136892-1df5-4fb1-9280-370bf4af5254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327513439 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2327513439
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2938165307
Short name T207
Test name
Test status
Simulation time 95931321870 ps
CPU time 36.36 seconds
Started Mar 07 01:46:18 PM PST 24
Finished Mar 07 01:46:55 PM PST 24
Peak memory 200088 kb
Host smart-60a4173f-a52f-4d9d-acb2-7c19ec9e0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938165307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2938165307
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2306621267
Short name T383
Test name
Test status
Simulation time 39669265266 ps
CPU time 30.06 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:47:09 PM PST 24
Peak memory 200308 kb
Host smart-33b65d90-2800-45b1-a0b4-9764b0faa964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306621267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2306621267
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3303120509
Short name T296
Test name
Test status
Simulation time 71372582424 ps
CPU time 32.85 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:47:16 PM PST 24
Peak memory 200528 kb
Host smart-6cba7d5e-331c-411e-a3ae-0a21a5d7ec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303120509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3303120509
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2853282879
Short name T211
Test name
Test status
Simulation time 41217790108 ps
CPU time 59.8 seconds
Started Mar 07 01:46:44 PM PST 24
Finished Mar 07 01:47:44 PM PST 24
Peak memory 200524 kb
Host smart-d31882f3-a00f-4463-813b-5559402403e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853282879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2853282879
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.897305328
Short name T341
Test name
Test status
Simulation time 8539515816 ps
CPU time 15.05 seconds
Started Mar 07 01:46:51 PM PST 24
Finished Mar 07 01:47:06 PM PST 24
Peak memory 199396 kb
Host smart-22c895f4-7f13-4a42-a1ed-a3b879d7f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897305328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.897305328
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.254934341
Short name T1226
Test name
Test status
Simulation time 41009672 ps
CPU time 0.67 seconds
Started Mar 07 12:54:30 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 194628 kb
Host smart-012d43a8-aa16-4647-b350-e3214e5ead93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254934341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.254934341
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2028640074
Short name T1196
Test name
Test status
Simulation time 251779920 ps
CPU time 2.4 seconds
Started Mar 07 12:54:11 PM PST 24
Finished Mar 07 12:54:14 PM PST 24
Peak memory 197888 kb
Host smart-e301122b-d080-4c8d-95aa-24a112176758
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028640074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2028640074
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4004621102
Short name T1170
Test name
Test status
Simulation time 1031979845 ps
CPU time 2.06 seconds
Started Mar 07 12:54:13 PM PST 24
Finished Mar 07 12:54:15 PM PST 24
Peak memory 195376 kb
Host smart-be86b7d7-5a2a-4abb-9947-c0af01b4ccf5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004621102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4004621102
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3317323121
Short name T1217
Test name
Test status
Simulation time 19375345 ps
CPU time 0.76 seconds
Started Mar 07 12:54:24 PM PST 24
Finished Mar 07 12:54:25 PM PST 24
Peak memory 199896 kb
Host smart-b6a2ab15-2e97-4bda-8d2b-bf60b2cfbf90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317323121 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3317323121
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.876374488
Short name T58
Test name
Test status
Simulation time 14468127 ps
CPU time 0.6 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:53:59 PM PST 24
Peak memory 195396 kb
Host smart-0295bb74-e2c5-4884-b9d5-23fa8c245526
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876374488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.876374488
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2967738638
Short name T1210
Test name
Test status
Simulation time 35224197 ps
CPU time 0.57 seconds
Started Mar 07 12:54:13 PM PST 24
Finished Mar 07 12:54:14 PM PST 24
Peak memory 194400 kb
Host smart-09c64cca-6966-40f2-9355-e44837ef5f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967738638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2967738638
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2767084550
Short name T1183
Test name
Test status
Simulation time 25619126 ps
CPU time 0.63 seconds
Started Mar 07 12:54:30 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 195700 kb
Host smart-67763f4f-3402-491a-b9bf-c61838ad8eda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767084550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2767084550
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2052060788
Short name T1224
Test name
Test status
Simulation time 309586618 ps
CPU time 1.7 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 200100 kb
Host smart-1960b66d-32cd-476b-b663-072d9cd14ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052060788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2052060788
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1295929846
Short name T79
Test name
Test status
Simulation time 521648890 ps
CPU time 0.99 seconds
Started Mar 07 12:54:25 PM PST 24
Finished Mar 07 12:54:26 PM PST 24
Peak memory 198980 kb
Host smart-b98a22ec-f530-4ee6-a4bd-cebccb7dd21c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295929846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1295929846
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3687808905
Short name T60
Test name
Test status
Simulation time 16895738 ps
CPU time 0.82 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 196284 kb
Host smart-6c6eea4b-0412-43e5-9783-7ee1a96e1fd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687808905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3687808905
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.4057218310
Short name T1171
Test name
Test status
Simulation time 184244088 ps
CPU time 1.49 seconds
Started Mar 07 12:54:28 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 197116 kb
Host smart-b56a9c59-2a62-4832-b66b-bdbcc510de84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057218310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.4057218310
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.514116215
Short name T1193
Test name
Test status
Simulation time 17159366 ps
CPU time 0.62 seconds
Started Mar 07 12:54:22 PM PST 24
Finished Mar 07 12:54:23 PM PST 24
Peak memory 195432 kb
Host smart-cbe8a931-b079-4a5d-84a9-32af220cbba2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514116215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.514116215
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.307150368
Short name T1229
Test name
Test status
Simulation time 15467475 ps
CPU time 0.67 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 197564 kb
Host smart-216ef8a6-60a6-4aec-85e1-a08eb9964541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307150368 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.307150368
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2769018954
Short name T64
Test name
Test status
Simulation time 14121490 ps
CPU time 0.62 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:18 PM PST 24
Peak memory 195460 kb
Host smart-a40b48cd-4326-4339-810e-cbe34c515c86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769018954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2769018954
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2583991259
Short name T1129
Test name
Test status
Simulation time 11819239 ps
CPU time 0.55 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 194456 kb
Host smart-6bca4c69-c332-43b9-8d5f-7a77d4eb35ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583991259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2583991259
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1545235619
Short name T1187
Test name
Test status
Simulation time 16381267 ps
CPU time 0.63 seconds
Started Mar 07 12:54:34 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 195572 kb
Host smart-91a407d6-d005-43b5-b47d-513e4d8b0dbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545235619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1545235619
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1304782095
Short name T1142
Test name
Test status
Simulation time 95691650 ps
CPU time 2.09 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:54:05 PM PST 24
Peak memory 200016 kb
Host smart-5ad4c29f-2cf5-45f0-85b0-aca7b01ae774
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304782095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1304782095
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1006544688
Short name T78
Test name
Test status
Simulation time 1503781972 ps
CPU time 1.32 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 199068 kb
Host smart-167b3c48-3b23-47fc-9626-3cc361e660fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006544688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1006544688
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3245906701
Short name T1149
Test name
Test status
Simulation time 77166531 ps
CPU time 0.78 seconds
Started Mar 07 12:54:24 PM PST 24
Finished Mar 07 12:54:25 PM PST 24
Peak memory 198924 kb
Host smart-6e580efd-ebd9-43b4-890c-37f5bb63f4fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245906701 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3245906701
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.67067943
Short name T62
Test name
Test status
Simulation time 45161592 ps
CPU time 0.6 seconds
Started Mar 07 12:54:24 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 195452 kb
Host smart-e3d42a7e-a788-479c-8dca-8a98a39e789e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67067943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.67067943
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.409392822
Short name T1145
Test name
Test status
Simulation time 48802824 ps
CPU time 0.58 seconds
Started Mar 07 12:54:25 PM PST 24
Finished Mar 07 12:54:26 PM PST 24
Peak memory 194340 kb
Host smart-496d6e46-980e-482e-8e74-ba5d9d2718e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409392822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.409392822
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3530337544
Short name T1174
Test name
Test status
Simulation time 28641386 ps
CPU time 0.77 seconds
Started Mar 07 12:54:28 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 197992 kb
Host smart-b3a27fb3-fa06-4335-a36a-6956d2ab1b99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530337544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3530337544
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2735057362
Short name T1202
Test name
Test status
Simulation time 558015212 ps
CPU time 2.51 seconds
Started Mar 07 12:54:27 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 199972 kb
Host smart-df3d456e-8a8f-4cdb-b7c3-74eb983748d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735057362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2735057362
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2809458664
Short name T1153
Test name
Test status
Simulation time 51331040 ps
CPU time 0.91 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:54:19 PM PST 24
Peak memory 198456 kb
Host smart-ae0e2e50-5767-411e-be7b-01cf6b2e9152
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809458664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2809458664
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3715787937
Short name T1223
Test name
Test status
Simulation time 49413280 ps
CPU time 0.71 seconds
Started Mar 07 12:54:20 PM PST 24
Finished Mar 07 12:54:20 PM PST 24
Peak memory 197628 kb
Host smart-29d756c4-a873-4461-8d05-d11eec75d399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715787937 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3715787937
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1771868783
Short name T1204
Test name
Test status
Simulation time 42127305 ps
CPU time 0.6 seconds
Started Mar 07 12:54:31 PM PST 24
Finished Mar 07 12:54:32 PM PST 24
Peak memory 195568 kb
Host smart-7784bee6-6c06-4b63-9172-ac4d7cf202ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771868783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1771868783
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2777304407
Short name T1230
Test name
Test status
Simulation time 38351185 ps
CPU time 0.55 seconds
Started Mar 07 12:54:27 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 194420 kb
Host smart-fc10f1fb-8f9b-4580-a065-1e98f320edc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777304407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2777304407
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2346087339
Short name T1206
Test name
Test status
Simulation time 16227200 ps
CPU time 0.69 seconds
Started Mar 07 12:54:27 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 196812 kb
Host smart-d36fb33d-4d38-4a07-9b42-7112ec6ea132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346087339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2346087339
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1593559410
Short name T1148
Test name
Test status
Simulation time 22292966 ps
CPU time 1.03 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 199772 kb
Host smart-c9c72b50-9895-4df8-a43a-19e8ae7d6da8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593559410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1593559410
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.311253309
Short name T1115
Test name
Test status
Simulation time 27431460 ps
CPU time 1.24 seconds
Started Mar 07 12:54:40 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 200052 kb
Host smart-f293c8e0-4bc3-4773-bb48-24a18895de2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311253309 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.311253309
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2671569257
Short name T1195
Test name
Test status
Simulation time 17568765 ps
CPU time 0.63 seconds
Started Mar 07 12:54:33 PM PST 24
Finished Mar 07 12:54:33 PM PST 24
Peak memory 195448 kb
Host smart-05e72cf1-2e40-41d4-8c8c-700128e62f37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671569257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2671569257
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3843394488
Short name T1126
Test name
Test status
Simulation time 25337452 ps
CPU time 0.58 seconds
Started Mar 07 12:54:27 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 194532 kb
Host smart-c59ba4a3-44a3-43a6-8473-f6418d4b0d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843394488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3843394488
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3661497
Short name T1146
Test name
Test status
Simulation time 23761817 ps
CPU time 0.66 seconds
Started Mar 07 12:54:44 PM PST 24
Finished Mar 07 12:54:45 PM PST 24
Peak memory 195500 kb
Host smart-73d4771f-2125-4672-aa36-4ff16a0c7441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_o
utstanding.3661497
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1848308127
Short name T1225
Test name
Test status
Simulation time 324334754 ps
CPU time 1.44 seconds
Started Mar 07 12:54:31 PM PST 24
Finished Mar 07 12:54:33 PM PST 24
Peak memory 200008 kb
Host smart-a3dfcdec-7707-4454-aaf9-5ec85b75a997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848308127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1848308127
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.620934611
Short name T1192
Test name
Test status
Simulation time 412055107 ps
CPU time 1.18 seconds
Started Mar 07 12:54:33 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 199160 kb
Host smart-22ce0668-055f-4bbd-8555-78efd8ce6e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620934611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.620934611
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3730442831
Short name T1134
Test name
Test status
Simulation time 126454609 ps
CPU time 1.24 seconds
Started Mar 07 12:54:36 PM PST 24
Finished Mar 07 12:54:37 PM PST 24
Peak memory 200048 kb
Host smart-6012dda1-e3f4-4909-a9ac-5ba01f5f5e69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730442831 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3730442831
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.550691764
Short name T1220
Test name
Test status
Simulation time 14348247 ps
CPU time 0.57 seconds
Started Mar 07 12:54:34 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 195436 kb
Host smart-f5e8c841-a5a5-49e9-9f6a-2d8e3931a2f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550691764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.550691764
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2243320375
Short name T1219
Test name
Test status
Simulation time 33843306 ps
CPU time 0.56 seconds
Started Mar 07 12:54:34 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 194484 kb
Host smart-604c885f-b63f-4c0d-8d21-582dd0fe49f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243320375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2243320375
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1224296462
Short name T67
Test name
Test status
Simulation time 58819828 ps
CPU time 0.63 seconds
Started Mar 07 12:54:37 PM PST 24
Finished Mar 07 12:54:38 PM PST 24
Peak memory 195540 kb
Host smart-f828ba8e-cdf3-4adf-9e96-892415c614d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224296462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1224296462
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1907677124
Short name T1162
Test name
Test status
Simulation time 274977316 ps
CPU time 1.37 seconds
Started Mar 07 12:54:39 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 200092 kb
Host smart-47cb6b55-bf2b-4cfd-ba8c-1c2f958c26c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907677124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1907677124
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3365492894
Short name T1137
Test name
Test status
Simulation time 160744741 ps
CPU time 0.97 seconds
Started Mar 07 12:54:31 PM PST 24
Finished Mar 07 12:54:32 PM PST 24
Peak memory 198808 kb
Host smart-b4ea1f5e-bbc3-42ea-a1d9-02e7611368b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365492894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3365492894
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.334594412
Short name T1213
Test name
Test status
Simulation time 45657613 ps
CPU time 0.98 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:33 PM PST 24
Peak memory 199844 kb
Host smart-a8d2880b-54a5-4284-86d3-6cac357e7ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334594412 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.334594412
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2903086928
Short name T65
Test name
Test status
Simulation time 47599614 ps
CPU time 0.61 seconds
Started Mar 07 12:54:34 PM PST 24
Finished Mar 07 12:54:34 PM PST 24
Peak memory 195544 kb
Host smart-029b2478-c479-4f8c-8a64-56364ef12f32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903086928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2903086928
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.972665480
Short name T1133
Test name
Test status
Simulation time 202892687 ps
CPU time 0.58 seconds
Started Mar 07 12:54:40 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 194456 kb
Host smart-636f6e7c-8b71-492d-8e89-4153715221b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972665480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.972665480
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1696152450
Short name T1201
Test name
Test status
Simulation time 18222587 ps
CPU time 0.69 seconds
Started Mar 07 12:54:34 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 195472 kb
Host smart-d311e13a-7f79-4735-bbfe-d8e0c63c07f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696152450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1696152450
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3950286888
Short name T1125
Test name
Test status
Simulation time 108226036 ps
CPU time 1.4 seconds
Started Mar 07 12:54:41 PM PST 24
Finished Mar 07 12:54:43 PM PST 24
Peak memory 199944 kb
Host smart-075c63bb-b84e-4de0-81b7-6a3e7d948167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950286888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3950286888
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2138310333
Short name T1141
Test name
Test status
Simulation time 33522267 ps
CPU time 0.68 seconds
Started Mar 07 12:54:28 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 197548 kb
Host smart-eef8393c-4ddc-4303-b8df-4e9830b5c5a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138310333 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2138310333
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2912119629
Short name T1120
Test name
Test status
Simulation time 28614606 ps
CPU time 0.59 seconds
Started Mar 07 12:54:39 PM PST 24
Finished Mar 07 12:54:40 PM PST 24
Peak memory 195528 kb
Host smart-05f4d5cb-7390-4062-81b7-7113de3fbbbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912119629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2912119629
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2553699289
Short name T1238
Test name
Test status
Simulation time 11602995 ps
CPU time 0.55 seconds
Started Mar 07 12:54:34 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 194372 kb
Host smart-12877e7f-655f-465f-8519-ba12ce520a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553699289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2553699289
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4032801128
Short name T1235
Test name
Test status
Simulation time 18821177 ps
CPU time 0.62 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:38 PM PST 24
Peak memory 195488 kb
Host smart-b1dba068-3cbc-47f2-ba49-31fb53fd96be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032801128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.4032801128
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2096049845
Short name T1144
Test name
Test status
Simulation time 135049976 ps
CPU time 1.73 seconds
Started Mar 07 12:54:22 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 200076 kb
Host smart-78ba22be-935a-4928-9c11-0f59d7666c19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096049845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2096049845
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2978842724
Short name T83
Test name
Test status
Simulation time 41261875 ps
CPU time 0.93 seconds
Started Mar 07 12:54:27 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 198760 kb
Host smart-da9dff9c-598f-4b27-8991-836cdc274342
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978842724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2978842724
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2716130671
Short name T1188
Test name
Test status
Simulation time 22011199 ps
CPU time 0.7 seconds
Started Mar 07 12:54:38 PM PST 24
Finished Mar 07 12:54:39 PM PST 24
Peak memory 198256 kb
Host smart-2cc414a7-a3bd-43b9-8770-3ea1cdc94e49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716130671 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2716130671
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.443058684
Short name T1184
Test name
Test status
Simulation time 15009822 ps
CPU time 0.59 seconds
Started Mar 07 12:54:38 PM PST 24
Finished Mar 07 12:54:38 PM PST 24
Peak memory 194420 kb
Host smart-dc98e636-a4e4-4a53-8298-530d0270a052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443058684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.443058684
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1598764191
Short name T1194
Test name
Test status
Simulation time 19216986 ps
CPU time 0.65 seconds
Started Mar 07 12:54:30 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 195564 kb
Host smart-91fd8139-aec1-4805-badd-4ccf4aaa6736
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598764191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1598764191
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3765202182
Short name T1228
Test name
Test status
Simulation time 423811037 ps
CPU time 2.26 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:34 PM PST 24
Peak memory 200032 kb
Host smart-b18e8677-aede-4f9e-ac83-94dbeac73371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765202182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3765202182
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3210843082
Short name T84
Test name
Test status
Simulation time 109942833 ps
CPU time 0.96 seconds
Started Mar 07 12:54:33 PM PST 24
Finished Mar 07 12:54:34 PM PST 24
Peak memory 198644 kb
Host smart-1c296427-80bf-4a31-bea7-7bc9640efbff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210843082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3210843082
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2771924673
Short name T1130
Test name
Test status
Simulation time 28458843 ps
CPU time 0.83 seconds
Started Mar 07 12:54:27 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 199768 kb
Host smart-3de837b3-5eff-4378-b514-80aba6e44207
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771924673 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2771924673
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1839702711
Short name T63
Test name
Test status
Simulation time 49425796 ps
CPU time 0.59 seconds
Started Mar 07 12:54:38 PM PST 24
Finished Mar 07 12:54:39 PM PST 24
Peak memory 195552 kb
Host smart-eff2e714-a906-45ae-ae30-beb5de3ed26f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839702711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1839702711
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1753225856
Short name T1147
Test name
Test status
Simulation time 13736712 ps
CPU time 0.58 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:33 PM PST 24
Peak memory 194536 kb
Host smart-0a87013f-c5da-470e-a3c5-01eaf742b233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753225856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1753225856
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3932003546
Short name T1169
Test name
Test status
Simulation time 21394808 ps
CPU time 0.6 seconds
Started Mar 07 12:54:21 PM PST 24
Finished Mar 07 12:54:22 PM PST 24
Peak memory 195632 kb
Host smart-6c6e8b57-48f1-4cda-8598-5dc121d99abb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932003546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3932003546
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3750247030
Short name T1114
Test name
Test status
Simulation time 967953263 ps
CPU time 2.02 seconds
Started Mar 07 12:54:39 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 200032 kb
Host smart-8f9aa2e2-8358-4a88-9552-1070f58df82a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750247030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3750247030
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3499082887
Short name T1160
Test name
Test status
Simulation time 18930474 ps
CPU time 0.98 seconds
Started Mar 07 12:54:50 PM PST 24
Finished Mar 07 12:54:51 PM PST 24
Peak memory 199896 kb
Host smart-a222c3e8-f2b1-4ac1-a027-fb51e86ba049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499082887 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3499082887
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3269178481
Short name T59
Test name
Test status
Simulation time 16342926 ps
CPU time 0.57 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:33 PM PST 24
Peak memory 195392 kb
Host smart-a9143ae2-56d3-48fe-8d0a-4e0648994ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269178481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3269178481
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1498109902
Short name T1156
Test name
Test status
Simulation time 13959068 ps
CPU time 0.56 seconds
Started Mar 07 12:54:46 PM PST 24
Finished Mar 07 12:54:46 PM PST 24
Peak memory 194488 kb
Host smart-66964753-e98b-4b9c-8747-25e3ee6ed7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498109902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1498109902
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.245980841
Short name T1189
Test name
Test status
Simulation time 16248927 ps
CPU time 0.63 seconds
Started Mar 07 12:54:50 PM PST 24
Finished Mar 07 12:54:51 PM PST 24
Peak memory 195644 kb
Host smart-e70bab7f-b2de-41a7-93a1-d2d893bdc00e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245980841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.245980841
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3194524707
Short name T1208
Test name
Test status
Simulation time 57587181 ps
CPU time 0.88 seconds
Started Mar 07 12:54:42 PM PST 24
Finished Mar 07 12:54:43 PM PST 24
Peak memory 199840 kb
Host smart-208750bf-1f14-4cec-89d9-61165db7d0e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194524707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3194524707
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.4237875615
Short name T1181
Test name
Test status
Simulation time 47905188 ps
CPU time 0.93 seconds
Started Mar 07 12:54:45 PM PST 24
Finished Mar 07 12:54:46 PM PST 24
Peak memory 198820 kb
Host smart-b63b222a-3e40-4121-8be2-a052f13c4a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237875615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.4237875615
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.877770861
Short name T1236
Test name
Test status
Simulation time 63704767 ps
CPU time 0.72 seconds
Started Mar 07 12:54:39 PM PST 24
Finished Mar 07 12:54:40 PM PST 24
Peak memory 198476 kb
Host smart-4732f6ee-ca8e-498a-802a-e66440197cdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877770861 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.877770861
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1245387716
Short name T54
Test name
Test status
Simulation time 11961389 ps
CPU time 0.59 seconds
Started Mar 07 12:54:44 PM PST 24
Finished Mar 07 12:54:45 PM PST 24
Peak memory 195516 kb
Host smart-9b8bc71b-9982-4212-8675-ce70c6adbbd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245387716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1245387716
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2929367776
Short name T1191
Test name
Test status
Simulation time 19782419 ps
CPU time 0.59 seconds
Started Mar 07 12:54:44 PM PST 24
Finished Mar 07 12:54:45 PM PST 24
Peak memory 194404 kb
Host smart-8c19cc1e-8617-4049-b362-3ac79c11d015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929367776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2929367776
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1913683528
Short name T70
Test name
Test status
Simulation time 327962185 ps
CPU time 0.75 seconds
Started Mar 07 12:54:35 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 197008 kb
Host smart-40f4f5cc-5aba-48b4-bcc6-df4ef80c7548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913683528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1913683528
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2784106271
Short name T1163
Test name
Test status
Simulation time 40716834 ps
CPU time 1.09 seconds
Started Mar 07 12:54:38 PM PST 24
Finished Mar 07 12:54:39 PM PST 24
Peak memory 199920 kb
Host smart-f769f49d-4108-47e5-8c8b-c8d08f3ae4cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784106271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2784106271
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3817873462
Short name T1200
Test name
Test status
Simulation time 132354180 ps
CPU time 1.35 seconds
Started Mar 07 12:54:40 PM PST 24
Finished Mar 07 12:54:42 PM PST 24
Peak memory 199188 kb
Host smart-8c4aeba0-e5f2-4fc3-968e-d3834c1869a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817873462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3817873462
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3239065367
Short name T1128
Test name
Test status
Simulation time 63273233 ps
CPU time 0.62 seconds
Started Mar 07 12:54:13 PM PST 24
Finished Mar 07 12:54:14 PM PST 24
Peak memory 195464 kb
Host smart-4c9a2339-58cd-45c6-ad53-ba1914b8a555
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239065367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3239065367
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3469887267
Short name T61
Test name
Test status
Simulation time 255749024 ps
CPU time 2.54 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:18 PM PST 24
Peak memory 197832 kb
Host smart-0498efaa-9ac2-4b82-a441-a8b1d829d8e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469887267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3469887267
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3618461173
Short name T1127
Test name
Test status
Simulation time 15243705 ps
CPU time 0.58 seconds
Started Mar 07 12:54:14 PM PST 24
Finished Mar 07 12:54:15 PM PST 24
Peak memory 195384 kb
Host smart-3b86461e-a702-4e80-b81a-f14ba7b4a94b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618461173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3618461173
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3289850348
Short name T1139
Test name
Test status
Simulation time 143888031 ps
CPU time 0.8 seconds
Started Mar 07 12:54:33 PM PST 24
Finished Mar 07 12:54:34 PM PST 24
Peak memory 199788 kb
Host smart-645bb06c-94d2-4827-ba6c-58427450560f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289850348 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3289850348
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2329786925
Short name T1165
Test name
Test status
Simulation time 15645157 ps
CPU time 0.62 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:54:04 PM PST 24
Peak memory 195440 kb
Host smart-d74b4ae6-490a-4e2e-9da1-1a316aa36e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329786925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2329786925
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3066122854
Short name T1108
Test name
Test status
Simulation time 13093588 ps
CPU time 0.54 seconds
Started Mar 07 12:54:28 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 194404 kb
Host smart-cc8206c6-c2e6-4ce8-8629-0bddeb3bfe5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066122854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3066122854
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2442817953
Short name T1158
Test name
Test status
Simulation time 121144634 ps
CPU time 0.82 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:18 PM PST 24
Peak memory 197012 kb
Host smart-bcf6785c-84a4-4186-a2ea-1186a0f61073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442817953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2442817953
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3123068133
Short name T1123
Test name
Test status
Simulation time 25880587 ps
CPU time 1.29 seconds
Started Mar 07 12:54:28 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 200044 kb
Host smart-b207dc55-b824-4b38-8479-14faed2d7e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123068133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3123068133
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3417441535
Short name T1218
Test name
Test status
Simulation time 53825092 ps
CPU time 1.02 seconds
Started Mar 07 12:54:08 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 198952 kb
Host smart-cdcdd135-a7c8-4996-8059-74130efe82be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417441535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3417441535
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2002364586
Short name T1198
Test name
Test status
Simulation time 101893507 ps
CPU time 0.55 seconds
Started Mar 07 12:54:45 PM PST 24
Finished Mar 07 12:54:46 PM PST 24
Peak memory 194332 kb
Host smart-3130231a-28db-4993-b32b-68810f4160bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002364586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2002364586
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2864649105
Short name T1151
Test name
Test status
Simulation time 33790447 ps
CPU time 0.56 seconds
Started Mar 07 12:54:39 PM PST 24
Finished Mar 07 12:54:40 PM PST 24
Peak memory 194416 kb
Host smart-cc849678-75ea-4629-a413-ac377141a055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864649105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2864649105
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1642407620
Short name T1232
Test name
Test status
Simulation time 221862575 ps
CPU time 0.55 seconds
Started Mar 07 12:54:59 PM PST 24
Finished Mar 07 12:55:00 PM PST 24
Peak memory 194332 kb
Host smart-0474524a-8c4a-4110-8a7b-55dbab6cc861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642407620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1642407620
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1449067163
Short name T1119
Test name
Test status
Simulation time 13937543 ps
CPU time 0.56 seconds
Started Mar 07 12:54:47 PM PST 24
Finished Mar 07 12:54:48 PM PST 24
Peak memory 194416 kb
Host smart-0f316dfa-1a79-4859-b0c3-34d5eed9710c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449067163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1449067163
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.60433295
Short name T1132
Test name
Test status
Simulation time 89842963 ps
CPU time 0.57 seconds
Started Mar 07 12:54:59 PM PST 24
Finished Mar 07 12:55:01 PM PST 24
Peak memory 194448 kb
Host smart-6c384f78-3f01-4821-b9c1-b92438017d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60433295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.60433295
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.972775948
Short name T1154
Test name
Test status
Simulation time 146840790 ps
CPU time 0.55 seconds
Started Mar 07 12:54:48 PM PST 24
Finished Mar 07 12:54:49 PM PST 24
Peak memory 194468 kb
Host smart-7391b31b-1064-4fed-a82d-fa7616a49260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972775948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.972775948
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3630179256
Short name T1197
Test name
Test status
Simulation time 11458264 ps
CPU time 0.55 seconds
Started Mar 07 12:54:39 PM PST 24
Finished Mar 07 12:54:40 PM PST 24
Peak memory 194408 kb
Host smart-76cd7193-2f7d-4cb2-8554-cd7b73c8a9ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630179256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3630179256
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4025013027
Short name T1136
Test name
Test status
Simulation time 41719663 ps
CPU time 0.54 seconds
Started Mar 07 12:54:47 PM PST 24
Finished Mar 07 12:54:47 PM PST 24
Peak memory 194448 kb
Host smart-9e64d365-d88d-476a-a846-8a3289fc9638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025013027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4025013027
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.134463757
Short name T1180
Test name
Test status
Simulation time 13414050 ps
CPU time 0.61 seconds
Started Mar 07 12:54:46 PM PST 24
Finished Mar 07 12:54:47 PM PST 24
Peak memory 194456 kb
Host smart-6b9e5fc8-c824-436c-97dc-dca45c64e87e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134463757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.134463757
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.486038433
Short name T1152
Test name
Test status
Simulation time 17407924 ps
CPU time 0.58 seconds
Started Mar 07 12:54:39 PM PST 24
Finished Mar 07 12:54:40 PM PST 24
Peak memory 194424 kb
Host smart-f78a8c84-a6e4-46e4-aa22-6e79694887ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486038433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.486038433
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2588224723
Short name T1227
Test name
Test status
Simulation time 50261572 ps
CPU time 0.76 seconds
Started Mar 07 12:54:19 PM PST 24
Finished Mar 07 12:54:20 PM PST 24
Peak memory 196632 kb
Host smart-faa6723f-24db-408b-ace2-fdb7b0bff4f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588224723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2588224723
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1883975379
Short name T1138
Test name
Test status
Simulation time 34248490 ps
CPU time 1.34 seconds
Started Mar 07 12:54:23 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 197596 kb
Host smart-8c718703-1377-444d-8398-3721f83cefe5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883975379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1883975379
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1280227116
Short name T57
Test name
Test status
Simulation time 31344658 ps
CPU time 0.62 seconds
Started Mar 07 12:54:11 PM PST 24
Finished Mar 07 12:54:12 PM PST 24
Peak memory 195560 kb
Host smart-a0399a9d-024f-4789-aeff-78134c363906
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280227116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1280227116
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.45150972
Short name T1234
Test name
Test status
Simulation time 63851293 ps
CPU time 0.68 seconds
Started Mar 07 12:54:06 PM PST 24
Finished Mar 07 12:54:12 PM PST 24
Peak memory 198336 kb
Host smart-4e97d7f1-76ec-485f-84b2-17ac7ce236f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45150972 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.45150972
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3534299148
Short name T1203
Test name
Test status
Simulation time 14539331 ps
CPU time 0.61 seconds
Started Mar 07 12:54:16 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 195528 kb
Host smart-b32de2ef-a527-47c6-aea8-ef51efa08662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534299148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3534299148
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.319990554
Short name T1164
Test name
Test status
Simulation time 121018105 ps
CPU time 0.56 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:18 PM PST 24
Peak memory 194460 kb
Host smart-daa32d83-4712-4997-8db7-fb6052c8a128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319990554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.319990554
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2561293951
Short name T1140
Test name
Test status
Simulation time 38707158 ps
CPU time 0.61 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:03 PM PST 24
Peak memory 195384 kb
Host smart-7cad9d26-5497-414c-87e2-09a902fb3dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561293951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2561293951
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3231678567
Short name T1161
Test name
Test status
Simulation time 469120583 ps
CPU time 2.1 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 199976 kb
Host smart-194a99b9-ad20-4cda-80c6-7f04ecb5d7b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231678567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3231678567
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3164353077
Short name T390
Test name
Test status
Simulation time 94869402 ps
CPU time 1.33 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 199240 kb
Host smart-506f27e4-ee5a-4f21-829c-66fd0f74fb3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164353077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3164353077
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1680384267
Short name T1207
Test name
Test status
Simulation time 15093711 ps
CPU time 0.56 seconds
Started Mar 07 12:54:34 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 194488 kb
Host smart-f5abe523-5dc1-4bd0-b66c-3cf1679ae976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680384267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1680384267
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2434876824
Short name T1167
Test name
Test status
Simulation time 117867126 ps
CPU time 0.57 seconds
Started Mar 07 12:54:47 PM PST 24
Finished Mar 07 12:54:48 PM PST 24
Peak memory 194440 kb
Host smart-0b21e436-a018-4cd9-85b8-7ac690016329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434876824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2434876824
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1759959315
Short name T1159
Test name
Test status
Simulation time 38075648 ps
CPU time 0.63 seconds
Started Mar 07 12:54:36 PM PST 24
Finished Mar 07 12:54:37 PM PST 24
Peak memory 194488 kb
Host smart-621785dc-1fc5-4ce1-b106-28551a7b60a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759959315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1759959315
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2023992071
Short name T1112
Test name
Test status
Simulation time 12585322 ps
CPU time 0.56 seconds
Started Mar 07 12:54:37 PM PST 24
Finished Mar 07 12:54:38 PM PST 24
Peak memory 194360 kb
Host smart-e8f655ab-aa55-4825-9dc1-a484b9b7412d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023992071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2023992071
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2160453142
Short name T1157
Test name
Test status
Simulation time 41409519 ps
CPU time 0.62 seconds
Started Mar 07 12:54:40 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 194420 kb
Host smart-4a0caa69-cb70-4c30-b7fe-a6946a9eea9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160453142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2160453142
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1940478584
Short name T1177
Test name
Test status
Simulation time 14254892 ps
CPU time 0.62 seconds
Started Mar 07 12:54:40 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 194524 kb
Host smart-f40668e6-fdae-4058-ab70-b74688268b45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940478584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1940478584
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3265793069
Short name T1231
Test name
Test status
Simulation time 11430808 ps
CPU time 0.58 seconds
Started Mar 07 12:54:44 PM PST 24
Finished Mar 07 12:54:45 PM PST 24
Peak memory 194412 kb
Host smart-98fb93f2-0fd3-4b50-baa9-9eec33e64390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265793069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3265793069
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2392488847
Short name T1178
Test name
Test status
Simulation time 41312394 ps
CPU time 0.55 seconds
Started Mar 07 12:54:41 PM PST 24
Finished Mar 07 12:54:42 PM PST 24
Peak memory 194420 kb
Host smart-a58b5bc4-464e-4959-aed6-08ed6b1c17fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392488847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2392488847
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3809976814
Short name T1168
Test name
Test status
Simulation time 12011740 ps
CPU time 0.58 seconds
Started Mar 07 12:54:46 PM PST 24
Finished Mar 07 12:54:47 PM PST 24
Peak memory 194408 kb
Host smart-6309822b-af92-47a9-b465-7dc49c0c97b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809976814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3809976814
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3106181027
Short name T1135
Test name
Test status
Simulation time 32543120 ps
CPU time 0.58 seconds
Started Mar 07 12:54:44 PM PST 24
Finished Mar 07 12:54:45 PM PST 24
Peak memory 194484 kb
Host smart-9c3f3f7b-b18e-4d0f-8c7c-c28e1d994926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106181027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3106181027
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3574893064
Short name T1150
Test name
Test status
Simulation time 66624840 ps
CPU time 0.65 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:32 PM PST 24
Peak memory 195464 kb
Host smart-46dec3ee-72ee-4bff-84fb-e57d8e0543ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574893064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3574893064
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4010346539
Short name T1221
Test name
Test status
Simulation time 97511433 ps
CPU time 1.5 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:11 PM PST 24
Peak memory 197920 kb
Host smart-d7e456e4-73db-44c7-a459-015fc833d28f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010346539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4010346539
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.829771191
Short name T55
Test name
Test status
Simulation time 50825347 ps
CPU time 0.6 seconds
Started Mar 07 12:54:30 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 195148 kb
Host smart-9fd9839d-a9f9-4f16-ad45-926db9734a0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829771191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.829771191
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1561320438
Short name T1186
Test name
Test status
Simulation time 18186228 ps
CPU time 0.67 seconds
Started Mar 07 12:54:23 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 197696 kb
Host smart-9421b88a-21f1-4a67-912a-67b466bc1007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561320438 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1561320438
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.488270629
Short name T1237
Test name
Test status
Simulation time 13677745 ps
CPU time 0.59 seconds
Started Mar 07 12:54:30 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 195468 kb
Host smart-67772776-fb7a-4538-a46a-5e4a2609041b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488270629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.488270629
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1288157509
Short name T1116
Test name
Test status
Simulation time 42748773 ps
CPU time 0.57 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 194448 kb
Host smart-9ea6080c-1adf-421f-a2a5-bb4c901056fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288157509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1288157509
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.122210753
Short name T74
Test name
Test status
Simulation time 99390798 ps
CPU time 0.74 seconds
Started Mar 07 12:54:30 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 197000 kb
Host smart-6c73c382-cfe5-4836-a9ac-1face427e026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122210753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.122210753
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3363735724
Short name T1211
Test name
Test status
Simulation time 167561792 ps
CPU time 2 seconds
Started Mar 07 12:54:22 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 200048 kb
Host smart-8a07b567-1765-4a99-9efd-0bd569d1b625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363735724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3363735724
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1377888135
Short name T87
Test name
Test status
Simulation time 943054082 ps
CPU time 1.29 seconds
Started Mar 07 12:54:31 PM PST 24
Finished Mar 07 12:54:32 PM PST 24
Peak memory 199212 kb
Host smart-d8bfd91d-ae56-4877-aa5c-ed7233bc3aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377888135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1377888135
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.396640516
Short name T1111
Test name
Test status
Simulation time 130369329 ps
CPU time 0.53 seconds
Started Mar 07 12:54:31 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 194368 kb
Host smart-94350be4-3226-407e-9c6e-98d1d43b8dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396640516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.396640516
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3240851276
Short name T1172
Test name
Test status
Simulation time 128321252 ps
CPU time 0.58 seconds
Started Mar 07 12:54:31 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 194480 kb
Host smart-d9e19268-7d79-4056-8234-89d41c596809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240851276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3240851276
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2004508313
Short name T1117
Test name
Test status
Simulation time 40108911 ps
CPU time 0.55 seconds
Started Mar 07 12:54:30 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 194464 kb
Host smart-3a950cd1-f716-4bbe-8987-0c9c3411c22c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004508313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2004508313
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1543547990
Short name T1222
Test name
Test status
Simulation time 23386603 ps
CPU time 0.57 seconds
Started Mar 07 12:54:42 PM PST 24
Finished Mar 07 12:54:43 PM PST 24
Peak memory 194524 kb
Host smart-ce0ddd65-fc20-4eb1-987e-09d81f8c508c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543547990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1543547990
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3332365108
Short name T1110
Test name
Test status
Simulation time 108805357 ps
CPU time 0.57 seconds
Started Mar 07 12:55:11 PM PST 24
Finished Mar 07 12:55:12 PM PST 24
Peak memory 194408 kb
Host smart-7bd75b0d-1b06-43f0-a6d6-16533769ad35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332365108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3332365108
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.986084151
Short name T1185
Test name
Test status
Simulation time 13131841 ps
CPU time 0.58 seconds
Started Mar 07 12:54:47 PM PST 24
Finished Mar 07 12:54:48 PM PST 24
Peak memory 194432 kb
Host smart-18dba6a5-38f2-4f7b-afa1-24b2d3787821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986084151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.986084151
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3610259631
Short name T1214
Test name
Test status
Simulation time 13152660 ps
CPU time 0.57 seconds
Started Mar 07 12:54:37 PM PST 24
Finished Mar 07 12:54:38 PM PST 24
Peak memory 194432 kb
Host smart-d6219f4a-ddb9-4798-abc2-b5c8bf163c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610259631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3610259631
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.292101778
Short name T1209
Test name
Test status
Simulation time 38328955 ps
CPU time 0.6 seconds
Started Mar 07 12:54:43 PM PST 24
Finished Mar 07 12:54:44 PM PST 24
Peak memory 194432 kb
Host smart-4496af9d-fd51-4962-abdb-c2609e903afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292101778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.292101778
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3902973173
Short name T1216
Test name
Test status
Simulation time 52137900 ps
CPU time 0.58 seconds
Started Mar 07 12:54:50 PM PST 24
Finished Mar 07 12:54:51 PM PST 24
Peak memory 194416 kb
Host smart-35408e75-ebe6-46f4-b79f-15f21f4990c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902973173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3902973173
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.861267250
Short name T1240
Test name
Test status
Simulation time 12620753 ps
CPU time 0.57 seconds
Started Mar 07 12:54:42 PM PST 24
Finished Mar 07 12:54:42 PM PST 24
Peak memory 194460 kb
Host smart-186b1bf7-8cce-4298-9b90-a4bb5a4d2634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861267250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.861267250
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1121527462
Short name T1155
Test name
Test status
Simulation time 30922168 ps
CPU time 0.84 seconds
Started Mar 07 12:54:33 PM PST 24
Finished Mar 07 12:54:34 PM PST 24
Peak memory 199872 kb
Host smart-997cf543-86dc-4bf5-a79b-2ae825491500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121527462 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1121527462
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.804837709
Short name T69
Test name
Test status
Simulation time 49372659 ps
CPU time 0.65 seconds
Started Mar 07 12:54:21 PM PST 24
Finished Mar 07 12:54:21 PM PST 24
Peak memory 195484 kb
Host smart-8125fdd0-e8f4-4381-a42d-b115071dc174
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804837709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.804837709
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2071859746
Short name T1118
Test name
Test status
Simulation time 21895237 ps
CPU time 0.6 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 194456 kb
Host smart-b9c0de00-4332-4e6b-a074-0d756c4855b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071859746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2071859746
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.696942748
Short name T73
Test name
Test status
Simulation time 29039550 ps
CPU time 0.65 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 195436 kb
Host smart-a9815bc8-5171-4364-9737-1a1dbe088916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696942748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.696942748
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.33193065
Short name T1205
Test name
Test status
Simulation time 57784758 ps
CPU time 1.31 seconds
Started Mar 07 12:54:19 PM PST 24
Finished Mar 07 12:54:21 PM PST 24
Peak memory 200120 kb
Host smart-e7c52cf1-4044-4ddd-81ed-69eaa3eb6d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.33193065
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.761279921
Short name T1173
Test name
Test status
Simulation time 196174242 ps
CPU time 1.27 seconds
Started Mar 07 12:54:33 PM PST 24
Finished Mar 07 12:54:39 PM PST 24
Peak memory 199232 kb
Host smart-df6f46a5-50d6-4ddd-836c-8d8ca179ea74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761279921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.761279921
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.122988989
Short name T1179
Test name
Test status
Simulation time 221137941 ps
CPU time 0.95 seconds
Started Mar 07 12:54:24 PM PST 24
Finished Mar 07 12:54:25 PM PST 24
Peak memory 199896 kb
Host smart-e709f74f-067b-4b8b-8b56-9c7ea75ce28e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122988989 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.122988989
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3618048475
Short name T1176
Test name
Test status
Simulation time 159164801 ps
CPU time 0.61 seconds
Started Mar 07 12:54:35 PM PST 24
Finished Mar 07 12:54:36 PM PST 24
Peak memory 195492 kb
Host smart-fc9ad2fc-e11a-4e9e-a158-139e566475e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618048475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3618048475
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2441294477
Short name T1122
Test name
Test status
Simulation time 34656317 ps
CPU time 0.55 seconds
Started Mar 07 12:54:23 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 194348 kb
Host smart-3960a80c-70f2-4371-a0b3-a5a82b149774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441294477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2441294477
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.942351947
Short name T68
Test name
Test status
Simulation time 46735084 ps
CPU time 0.64 seconds
Started Mar 07 12:54:27 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 195576 kb
Host smart-87487497-add5-4819-8376-f1c80c25005a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942351947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.942351947
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3504211210
Short name T1121
Test name
Test status
Simulation time 110248121 ps
CPU time 1.46 seconds
Started Mar 07 12:54:35 PM PST 24
Finished Mar 07 12:54:37 PM PST 24
Peak memory 200040 kb
Host smart-ad2c0dd3-17e5-4279-946f-5a2bd7990911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504211210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3504211210
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1597054075
Short name T1215
Test name
Test status
Simulation time 502945822 ps
CPU time 1.06 seconds
Started Mar 07 12:54:21 PM PST 24
Finished Mar 07 12:54:22 PM PST 24
Peak memory 198804 kb
Host smart-3eaf3f12-e805-4e6c-bfb2-d5b34c548cac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597054075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1597054075
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1698706935
Short name T1212
Test name
Test status
Simulation time 41901961 ps
CPU time 0.68 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 198056 kb
Host smart-3702c206-bd6b-4e4b-ae0d-191b0eef8cae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698706935 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1698706935
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4141743493
Short name T71
Test name
Test status
Simulation time 61878420 ps
CPU time 0.62 seconds
Started Mar 07 12:54:14 PM PST 24
Finished Mar 07 12:54:15 PM PST 24
Peak memory 195512 kb
Host smart-1c1a51f6-0a26-4629-a6a6-d0a62c2c29a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141743493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4141743493
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3957178595
Short name T1124
Test name
Test status
Simulation time 32349413 ps
CPU time 0.58 seconds
Started Mar 07 12:54:25 PM PST 24
Finished Mar 07 12:54:26 PM PST 24
Peak memory 194420 kb
Host smart-4b23fd35-2e01-4f67-8ec6-fa87464997cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957178595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3957178595
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.39349622
Short name T1175
Test name
Test status
Simulation time 35153287 ps
CPU time 0.66 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 195480 kb
Host smart-6ac64b1d-b15e-4027-acf1-9a51aad997e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39349622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_o
utstanding.39349622
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2031548491
Short name T1239
Test name
Test status
Simulation time 80139685 ps
CPU time 1.72 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 200040 kb
Host smart-2de87eb3-0d24-4aea-ba47-47869e093455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031548491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2031548491
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2140036403
Short name T1233
Test name
Test status
Simulation time 323581942 ps
CPU time 1.31 seconds
Started Mar 07 12:54:21 PM PST 24
Finished Mar 07 12:54:22 PM PST 24
Peak memory 199008 kb
Host smart-d29b8b6e-93e7-4563-8ecf-aa03bc76ce10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140036403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2140036403
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2814734710
Short name T1190
Test name
Test status
Simulation time 36135663 ps
CPU time 0.64 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 197116 kb
Host smart-af2e1b68-45ae-4582-bbbc-dbbe227aa016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814734710 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2814734710
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.4016175
Short name T1109
Test name
Test status
Simulation time 51145948 ps
CPU time 0.6 seconds
Started Mar 07 12:54:35 PM PST 24
Finished Mar 07 12:54:36 PM PST 24
Peak memory 195444 kb
Host smart-6b2306ed-6f66-4144-aa93-a6c8fc5a7716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.4016175
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2574684394
Short name T1131
Test name
Test status
Simulation time 22523193 ps
CPU time 0.62 seconds
Started Mar 07 12:54:23 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 194428 kb
Host smart-6597c32c-2cee-4a10-9a83-1a997f231401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574684394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2574684394
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3496318942
Short name T1182
Test name
Test status
Simulation time 27033190 ps
CPU time 0.72 seconds
Started Mar 07 12:54:08 PM PST 24
Finished Mar 07 12:54:09 PM PST 24
Peak memory 195856 kb
Host smart-6ab91f5d-b808-44b6-942b-e7720752b00c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496318942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3496318942
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1654512192
Short name T1143
Test name
Test status
Simulation time 174646380 ps
CPU time 1.14 seconds
Started Mar 07 12:54:16 PM PST 24
Finished Mar 07 12:54:18 PM PST 24
Peak memory 200068 kb
Host smart-3b099c9b-5175-4522-8f1a-44e9da1ff600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654512192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1654512192
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1051970199
Short name T81
Test name
Test status
Simulation time 42888436 ps
CPU time 0.91 seconds
Started Mar 07 12:54:28 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 198852 kb
Host smart-926f4374-bf16-4dbc-a48b-2f554f029502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051970199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1051970199
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1382384052
Short name T1113
Test name
Test status
Simulation time 95139548 ps
CPU time 1.29 seconds
Started Mar 07 12:54:22 PM PST 24
Finished Mar 07 12:54:23 PM PST 24
Peak memory 200072 kb
Host smart-a88c5540-1636-40ee-94d5-7df72e5f4f66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382384052 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1382384052
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3565598886
Short name T66
Test name
Test status
Simulation time 23179509 ps
CPU time 0.56 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 195392 kb
Host smart-39bde259-6fe8-483b-b925-1c5393796594
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565598886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3565598886
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.863236447
Short name T1199
Test name
Test status
Simulation time 41538616 ps
CPU time 0.55 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:18 PM PST 24
Peak memory 194432 kb
Host smart-0dfe95c3-53a8-445c-a9b1-61d43f61e2c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863236447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.863236447
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2950423240
Short name T72
Test name
Test status
Simulation time 16449250 ps
CPU time 0.74 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:54:19 PM PST 24
Peak memory 196988 kb
Host smart-5d96410c-2ebf-414e-b4ad-f13eaf366560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950423240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2950423240
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2581713759
Short name T1166
Test name
Test status
Simulation time 371161609 ps
CPU time 1.98 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 200060 kb
Host smart-b697212a-e88e-4a37-b1db-01ceb3efcf23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581713759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2581713759
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.696221689
Short name T85
Test name
Test status
Simulation time 53740059 ps
CPU time 1.09 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 198984 kb
Host smart-a0804482-e264-4924-8268-04a7c20a0ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696221689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.696221689
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2813303193
Short name T561
Test name
Test status
Simulation time 11535183 ps
CPU time 0.53 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:43:50 PM PST 24
Peak memory 195964 kb
Host smart-5ad421b2-bb26-42e9-a791-84299b1b9a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813303193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2813303193
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2031443632
Short name T617
Test name
Test status
Simulation time 148495916069 ps
CPU time 115.49 seconds
Started Mar 07 01:43:47 PM PST 24
Finished Mar 07 01:45:42 PM PST 24
Peak memory 200464 kb
Host smart-b3c50ccd-e6f0-4fd4-9a35-53e7448670a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031443632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2031443632
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1057960837
Short name T119
Test name
Test status
Simulation time 42328227487 ps
CPU time 51.53 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:44:36 PM PST 24
Peak memory 199976 kb
Host smart-4652bd84-dda0-4ea9-9d1a-dc0bd933668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057960837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1057960837
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3946810521
Short name T213
Test name
Test status
Simulation time 118628383490 ps
CPU time 30.36 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:44:15 PM PST 24
Peak memory 200584 kb
Host smart-9fe0783d-351c-4998-bc84-d482773f58a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946810521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3946810521
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2427816206
Short name T1025
Test name
Test status
Simulation time 73158565605 ps
CPU time 78.6 seconds
Started Mar 07 01:43:46 PM PST 24
Finished Mar 07 01:45:04 PM PST 24
Peak memory 200512 kb
Host smart-38f2351c-a471-4b57-902e-7b37c5fd6022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427816206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2427816206
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.196992523
Short name T704
Test name
Test status
Simulation time 3434568888 ps
CPU time 6.12 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:43:55 PM PST 24
Peak memory 199672 kb
Host smart-cbdaaf87-676b-4c2e-9667-9001e3207744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196992523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.196992523
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1544283463
Short name T687
Test name
Test status
Simulation time 18390991460 ps
CPU time 28.94 seconds
Started Mar 07 01:43:44 PM PST 24
Finished Mar 07 01:44:13 PM PST 24
Peak memory 198928 kb
Host smart-2c09ab74-2fef-402c-a261-835e6649499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544283463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1544283463
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2542280620
Short name T395
Test name
Test status
Simulation time 13006130317 ps
CPU time 164.36 seconds
Started Mar 07 01:43:46 PM PST 24
Finished Mar 07 01:46:30 PM PST 24
Peak memory 200640 kb
Host smart-fbf5a5a5-ba13-40b8-8c83-fe38f8e77893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542280620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2542280620
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2751409306
Short name T611
Test name
Test status
Simulation time 8217493666 ps
CPU time 35.04 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:44:24 PM PST 24
Peak memory 199164 kb
Host smart-47b382f0-a707-4e59-870d-dccad3edd697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751409306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2751409306
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3788524279
Short name T367
Test name
Test status
Simulation time 64571365410 ps
CPU time 54.27 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:44:40 PM PST 24
Peak memory 199840 kb
Host smart-6ff2fe50-f41c-4512-bee6-b9274c7b083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788524279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3788524279
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1075328467
Short name T655
Test name
Test status
Simulation time 35070469849 ps
CPU time 52.71 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:44:41 PM PST 24
Peak memory 196300 kb
Host smart-069a76b4-bba6-4387-b180-abfb3ccd4be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075328467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1075328467
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2602205825
Short name T89
Test name
Test status
Simulation time 144090845 ps
CPU time 0.77 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:43:49 PM PST 24
Peak memory 217844 kb
Host smart-1facc66a-0198-454f-b568-a87b820a8832
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602205825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2602205825
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.3866033696
Short name T652
Test name
Test status
Simulation time 713855391 ps
CPU time 3.49 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:43:49 PM PST 24
Peak memory 198384 kb
Host smart-5208e329-6a2f-4b88-8362-c7fdf847bcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866033696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3866033696
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.4082791729
Short name T1024
Test name
Test status
Simulation time 420165146 ps
CPU time 1.54 seconds
Started Mar 07 01:43:46 PM PST 24
Finished Mar 07 01:43:48 PM PST 24
Peak memory 198364 kb
Host smart-4c62d734-173d-4374-bfea-8abebeed09e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082791729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.4082791729
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2748671309
Short name T850
Test name
Test status
Simulation time 33719298170 ps
CPU time 54.87 seconds
Started Mar 07 01:43:47 PM PST 24
Finished Mar 07 01:44:42 PM PST 24
Peak memory 200628 kb
Host smart-4e71d42c-bc77-4b13-93d9-2168c4695875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748671309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2748671309
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3558743267
Short name T464
Test name
Test status
Simulation time 36023849 ps
CPU time 0.51 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:43:45 PM PST 24
Peak memory 194928 kb
Host smart-f786d0be-b2f2-4bfb-b192-fc6c41e5027c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558743267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3558743267
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1767064558
Short name T862
Test name
Test status
Simulation time 35042653492 ps
CPU time 63.92 seconds
Started Mar 07 01:43:47 PM PST 24
Finished Mar 07 01:44:51 PM PST 24
Peak memory 200472 kb
Host smart-eafe3863-a998-42ab-a8c2-774d364bf6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767064558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1767064558
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1141248213
Short name T846
Test name
Test status
Simulation time 23915227806 ps
CPU time 44.5 seconds
Started Mar 07 01:43:46 PM PST 24
Finished Mar 07 01:44:30 PM PST 24
Peak memory 200656 kb
Host smart-8f80f130-d83b-4331-899b-d23b25e3c09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141248213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1141248213
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.4025404846
Short name T601
Test name
Test status
Simulation time 258719600110 ps
CPU time 102.76 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:45:31 PM PST 24
Peak memory 200424 kb
Host smart-9e99ef0f-d04f-46b0-944b-71690d50c140
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025404846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.4025404846
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1052679444
Short name T15
Test name
Test status
Simulation time 68474641887 ps
CPU time 118.33 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:45:46 PM PST 24
Peak memory 200532 kb
Host smart-e356c33a-8ebc-4f1b-9b43-9224812bc246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052679444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1052679444
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3474744368
Short name T515
Test name
Test status
Simulation time 535501418 ps
CPU time 1.44 seconds
Started Mar 07 01:43:46 PM PST 24
Finished Mar 07 01:43:47 PM PST 24
Peak memory 196008 kb
Host smart-2eee9481-7774-4f15-9c1d-2b0b95b626fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474744368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3474744368
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.374619045
Short name T414
Test name
Test status
Simulation time 100283009796 ps
CPU time 157.78 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:46:23 PM PST 24
Peak memory 200388 kb
Host smart-c52bbeca-d56b-42ff-8d19-37f146fd120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374619045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.374619045
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2955500183
Short name T449
Test name
Test status
Simulation time 4010483250 ps
CPU time 31.72 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:44:21 PM PST 24
Peak memory 199048 kb
Host smart-a406a434-e4d5-4bb1-880c-cfc3c8b641fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955500183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2955500183
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4201626552
Short name T883
Test name
Test status
Simulation time 102861136318 ps
CPU time 74.91 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:45:04 PM PST 24
Peak memory 199508 kb
Host smart-495c6d20-d4f4-472f-8f53-615a90cbf523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201626552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4201626552
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.309174225
Short name T569
Test name
Test status
Simulation time 7211068574 ps
CPU time 3.73 seconds
Started Mar 07 01:43:47 PM PST 24
Finished Mar 07 01:43:51 PM PST 24
Peak memory 196432 kb
Host smart-ff3208a5-955d-4fa5-b6a0-24d0befff6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309174225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.309174225
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1103823928
Short name T29
Test name
Test status
Simulation time 59388754 ps
CPU time 0.88 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:43:49 PM PST 24
Peak memory 217924 kb
Host smart-059eec56-8352-4170-80bc-f2a7f2a310c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103823928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1103823928
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.733836358
Short name T1013
Test name
Test status
Simulation time 5794414495 ps
CPU time 23.01 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:44:08 PM PST 24
Peak memory 200076 kb
Host smart-39a03dea-7231-430f-afcd-ceddec4351a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733836358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.733836358
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2115857197
Short name T702
Test name
Test status
Simulation time 1501427771 ps
CPU time 3.15 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:43:51 PM PST 24
Peak memory 198848 kb
Host smart-6e037b65-1104-4542-96bf-cb2b022efdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115857197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2115857197
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1034327810
Short name T868
Test name
Test status
Simulation time 33750243670 ps
CPU time 15.08 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:44:01 PM PST 24
Peak memory 200524 kb
Host smart-c4ed4605-106d-431e-82b3-38fff99faed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034327810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1034327810
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3785224359
Short name T357
Test name
Test status
Simulation time 25901049033 ps
CPU time 44.56 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:45:23 PM PST 24
Peak memory 200560 kb
Host smart-69d923f9-585c-4f84-8762-77d7d0e06e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785224359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3785224359
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1562983274
Short name T896
Test name
Test status
Simulation time 36656062088 ps
CPU time 19.17 seconds
Started Mar 07 01:44:34 PM PST 24
Finished Mar 07 01:44:53 PM PST 24
Peak memory 200516 kb
Host smart-f44dfc03-d625-432f-91f4-4dedda990369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562983274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1562983274
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1736258855
Short name T418
Test name
Test status
Simulation time 83289318294 ps
CPU time 82.35 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:46:00 PM PST 24
Peak memory 200508 kb
Host smart-627ac405-6b78-4369-8419-c2358050fa1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736258855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1736258855
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1265910428
Short name T747
Test name
Test status
Simulation time 188453224792 ps
CPU time 494.9 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:52:50 PM PST 24
Peak memory 200496 kb
Host smart-5976b916-febd-41e7-b26f-f5d6d7ab9dcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265910428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1265910428
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3256915597
Short name T457
Test name
Test status
Simulation time 1401780675 ps
CPU time 5.22 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:44:40 PM PST 24
Peak memory 197424 kb
Host smart-ae6e84e2-952a-4121-859b-69bc13d39205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256915597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3256915597
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.153163586
Short name T610
Test name
Test status
Simulation time 102838274111 ps
CPU time 75 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:45:52 PM PST 24
Peak memory 199044 kb
Host smart-3983d100-c473-41ca-971f-ab189af54e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153163586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.153163586
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.4237876862
Short name T628
Test name
Test status
Simulation time 23273576339 ps
CPU time 291.77 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:49:29 PM PST 24
Peak memory 200540 kb
Host smart-249afc87-9b51-44aa-87c8-1c07603dc3b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237876862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4237876862
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.250093058
Short name T800
Test name
Test status
Simulation time 3183486430 ps
CPU time 6.24 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:44:44 PM PST 24
Peak memory 198420 kb
Host smart-8da5931f-4229-4ab9-95eb-b9ff19a1efb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250093058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.250093058
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2667148656
Short name T273
Test name
Test status
Simulation time 224796609643 ps
CPU time 33.89 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:45:09 PM PST 24
Peak memory 199692 kb
Host smart-042300ae-fa46-4538-a964-2ff39eead198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667148656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2667148656
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2710003910
Short name T91
Test name
Test status
Simulation time 3260815968 ps
CPU time 3.07 seconds
Started Mar 07 01:44:36 PM PST 24
Finished Mar 07 01:44:39 PM PST 24
Peak memory 196340 kb
Host smart-fcee315e-310c-46cf-bd25-e3cf24b9d9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710003910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2710003910
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2205725695
Short name T878
Test name
Test status
Simulation time 892996764 ps
CPU time 1.67 seconds
Started Mar 07 01:44:36 PM PST 24
Finished Mar 07 01:44:38 PM PST 24
Peak memory 198888 kb
Host smart-4aadbb14-eed7-480a-b24f-5de6db82d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205725695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2205725695
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3019661791
Short name T777
Test name
Test status
Simulation time 962489709226 ps
CPU time 661.49 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:55:43 PM PST 24
Peak memory 200524 kb
Host smart-e644aef9-245c-4ab8-9dac-2dd28076133e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019661791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3019661791
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.4117222281
Short name T993
Test name
Test status
Simulation time 49880968474 ps
CPU time 545.94 seconds
Started Mar 07 01:44:03 PM PST 24
Finished Mar 07 01:53:09 PM PST 24
Peak memory 217336 kb
Host smart-5970fbf2-2b60-4781-a353-b5ada6ee6044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117222281 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.4117222281
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4193855852
Short name T599
Test name
Test status
Simulation time 1692137883 ps
CPU time 1.92 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:44:37 PM PST 24
Peak memory 198604 kb
Host smart-0c39b297-ca45-490f-8bc8-3d9c682e0263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193855852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4193855852
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.280598201
Short name T799
Test name
Test status
Simulation time 66017521514 ps
CPU time 35.04 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:45:08 PM PST 24
Peak memory 200544 kb
Host smart-54bb7d92-b8cc-4757-aaa7-aeab10d169ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280598201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.280598201
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2680855666
Short name T215
Test name
Test status
Simulation time 54898040001 ps
CPU time 26.03 seconds
Started Mar 07 01:47:17 PM PST 24
Finished Mar 07 01:47:43 PM PST 24
Peak memory 200436 kb
Host smart-ce58375e-93f8-4822-8a5a-e085ced7b556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680855666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2680855666
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3536911557
Short name T730
Test name
Test status
Simulation time 40885333070 ps
CPU time 64.99 seconds
Started Mar 07 01:47:08 PM PST 24
Finished Mar 07 01:48:13 PM PST 24
Peak memory 200608 kb
Host smart-174375b7-43e7-4661-8159-a0b931ec38e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536911557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3536911557
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.601410160
Short name T811
Test name
Test status
Simulation time 180176129748 ps
CPU time 272.79 seconds
Started Mar 07 01:47:10 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 200464 kb
Host smart-b25ac815-0493-43a0-a00b-d8f190aa930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601410160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.601410160
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1991179157
Short name T1000
Test name
Test status
Simulation time 148261262462 ps
CPU time 106.39 seconds
Started Mar 07 01:47:16 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 200548 kb
Host smart-8feac4e0-45f1-41df-a0e8-fe47368b0fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991179157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1991179157
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3975549249
Short name T193
Test name
Test status
Simulation time 162483528967 ps
CPU time 63.09 seconds
Started Mar 07 01:47:12 PM PST 24
Finished Mar 07 01:48:15 PM PST 24
Peak memory 200532 kb
Host smart-a221f1a3-312f-45fe-ae91-67efab7ef15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975549249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3975549249
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.1019370378
Short name T959
Test name
Test status
Simulation time 22212803 ps
CPU time 0.55 seconds
Started Mar 07 01:44:36 PM PST 24
Finished Mar 07 01:44:36 PM PST 24
Peak memory 196000 kb
Host smart-b014741b-f4ad-4dea-ac58-42b6d0aeec57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019370378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1019370378
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2563856702
Short name T596
Test name
Test status
Simulation time 310490526127 ps
CPU time 850.68 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:58:52 PM PST 24
Peak memory 200540 kb
Host smart-405a45cf-5785-432e-abbc-2bc71592e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563856702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2563856702
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_intr.749986469
Short name T778
Test name
Test status
Simulation time 42749318950 ps
CPU time 69.11 seconds
Started Mar 07 01:44:36 PM PST 24
Finished Mar 07 01:45:46 PM PST 24
Peak memory 200568 kb
Host smart-777027a2-a9a1-418b-a0ec-5fc0cb9b6dba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749986469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.749986469
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3505613735
Short name T640
Test name
Test status
Simulation time 114919610103 ps
CPU time 285.38 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:49:25 PM PST 24
Peak memory 200532 kb
Host smart-4af00639-08d1-4cdc-bf09-7f0ea7329ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505613735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3505613735
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1376414734
Short name T475
Test name
Test status
Simulation time 53342875 ps
CPU time 0.74 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:44:40 PM PST 24
Peak memory 195904 kb
Host smart-b8d76e0f-a94e-4e23-90b4-49e1d664d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376414734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1376414734
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.889639595
Short name T1030
Test name
Test status
Simulation time 172573634077 ps
CPU time 76.87 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:45:55 PM PST 24
Peak memory 208900 kb
Host smart-5df11e74-1f26-4b3c-a96b-c07001da0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889639595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.889639595
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.317266388
Short name T1092
Test name
Test status
Simulation time 34553767816 ps
CPU time 797.23 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:57:58 PM PST 24
Peak memory 200584 kb
Host smart-595a07a0-d98e-4bba-891d-11f3fd6f4cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317266388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.317266388
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1064543876
Short name T510
Test name
Test status
Simulation time 5876840795 ps
CPU time 52.78 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:45:30 PM PST 24
Peak memory 199000 kb
Host smart-bdd5aaf9-59fb-4a39-a9d8-b7b68b7d5278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064543876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1064543876
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.4191462860
Short name T681
Test name
Test status
Simulation time 104173543999 ps
CPU time 46.33 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:45:28 PM PST 24
Peak memory 200536 kb
Host smart-d44eb978-fb73-4f85-bad0-8f944bbb3a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191462860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4191462860
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1052895150
Short name T848
Test name
Test status
Simulation time 4535150616 ps
CPU time 1.18 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:44:43 PM PST 24
Peak memory 196400 kb
Host smart-06ab923f-71a0-4667-a81c-e08e5702b043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052895150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1052895150
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3897452163
Short name T806
Test name
Test status
Simulation time 6044328171 ps
CPU time 8.62 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:44:46 PM PST 24
Peak memory 200572 kb
Host smart-0502d683-0cb9-4549-b82e-b268c8c85129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897452163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3897452163
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2651707391
Short name T352
Test name
Test status
Simulation time 992051468620 ps
CPU time 918.61 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:59:56 PM PST 24
Peak memory 200528 kb
Host smart-62496a53-9ccd-4f58-99f2-17caef2243d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651707391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2651707391
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1340604153
Short name T103
Test name
Test status
Simulation time 27782347703 ps
CPU time 239.48 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 217304 kb
Host smart-953e83d1-1130-4e26-8d8d-4df4e7cc059f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340604153 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1340604153
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.590902278
Short name T793
Test name
Test status
Simulation time 1212731060 ps
CPU time 5.74 seconds
Started Mar 07 01:44:44 PM PST 24
Finished Mar 07 01:44:50 PM PST 24
Peak memory 199612 kb
Host smart-c57bed98-250f-4f03-8028-1ae0bee22496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590902278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.590902278
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1601109795
Short name T651
Test name
Test status
Simulation time 5735656682 ps
CPU time 4.81 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:44:44 PM PST 24
Peak memory 199400 kb
Host smart-c1607cb7-93cc-4815-a5bd-e85c2dd35753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601109795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1601109795
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3351336570
Short name T744
Test name
Test status
Simulation time 72074082521 ps
CPU time 110.46 seconds
Started Mar 07 01:47:11 PM PST 24
Finished Mar 07 01:49:01 PM PST 24
Peak memory 200488 kb
Host smart-db6cee5f-6ddc-4f82-bb9b-92ddfa1282fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351336570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3351336570
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.770698810
Short name T262
Test name
Test status
Simulation time 64444882932 ps
CPU time 32.04 seconds
Started Mar 07 01:47:10 PM PST 24
Finished Mar 07 01:47:42 PM PST 24
Peak memory 200068 kb
Host smart-6fb0c97d-5789-4130-b88a-52794ae35a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770698810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.770698810
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.829890480
Short name T1001
Test name
Test status
Simulation time 16706363902 ps
CPU time 7.33 seconds
Started Mar 07 01:47:19 PM PST 24
Finished Mar 07 01:47:26 PM PST 24
Peak memory 200120 kb
Host smart-fe074794-7090-4991-a22d-289c9d83c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829890480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.829890480
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3151626623
Short name T173
Test name
Test status
Simulation time 34109082198 ps
CPU time 16.09 seconds
Started Mar 07 01:47:17 PM PST 24
Finished Mar 07 01:47:33 PM PST 24
Peak memory 200488 kb
Host smart-3ad50485-2ccf-4ec7-9fea-d085417da4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151626623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3151626623
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2046843471
Short name T926
Test name
Test status
Simulation time 97283792824 ps
CPU time 163.45 seconds
Started Mar 07 01:47:19 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 200516 kb
Host smart-4a705c27-a486-4532-b96d-25ae83b9ee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046843471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2046843471
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2269824062
Short name T127
Test name
Test status
Simulation time 142149517547 ps
CPU time 58.75 seconds
Started Mar 07 01:47:10 PM PST 24
Finished Mar 07 01:48:09 PM PST 24
Peak memory 200508 kb
Host smart-3c3dfc33-4eb1-4466-998e-c130383c9040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269824062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2269824062
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1620372662
Short name T1046
Test name
Test status
Simulation time 29480922 ps
CPU time 0.54 seconds
Started Mar 07 01:44:45 PM PST 24
Finished Mar 07 01:44:46 PM PST 24
Peak memory 194932 kb
Host smart-0345f09e-0b71-43f6-8add-8ab337056ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620372662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1620372662
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1689823780
Short name T879
Test name
Test status
Simulation time 100091454269 ps
CPU time 32.75 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:45:10 PM PST 24
Peak memory 199968 kb
Host smart-2f7a9828-79a0-4f13-a49d-60077c2454a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689823780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1689823780
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4123529496
Short name T686
Test name
Test status
Simulation time 10206005205 ps
CPU time 5.16 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:44:48 PM PST 24
Peak memory 200472 kb
Host smart-cce6d5db-9c17-403e-81b8-d18834b1c0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123529496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4123529496
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3280167522
Short name T902
Test name
Test status
Simulation time 126319994256 ps
CPU time 213.35 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:48:15 PM PST 24
Peak memory 200540 kb
Host smart-5691130f-3978-4fd0-bb7b-5780601339da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280167522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3280167522
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1478421048
Short name T712
Test name
Test status
Simulation time 82093471202 ps
CPU time 185.93 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:47:44 PM PST 24
Peak memory 200544 kb
Host smart-50705e62-3a5a-4266-981c-a3b46e38d950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478421048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1478421048
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2295034858
Short name T571
Test name
Test status
Simulation time 70927936011 ps
CPU time 51.15 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:45:33 PM PST 24
Peak memory 200400 kb
Host smart-e4ba8124-b43a-475c-aa3d-00f9f5d44d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295034858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2295034858
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1463673999
Short name T623
Test name
Test status
Simulation time 19227714818 ps
CPU time 206.75 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:48:09 PM PST 24
Peak memory 200528 kb
Host smart-27bb5ad4-a3ea-47eb-a15b-0e680a2c4722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463673999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1463673999
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3106031215
Short name T459
Test name
Test status
Simulation time 7456419426 ps
CPU time 66.34 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:45:49 PM PST 24
Peak memory 199392 kb
Host smart-9b34c013-ff22-4d1d-97dd-8a7a8333c601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106031215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3106031215
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1884774911
Short name T669
Test name
Test status
Simulation time 30146344237 ps
CPU time 40.4 seconds
Started Mar 07 01:44:44 PM PST 24
Finished Mar 07 01:45:24 PM PST 24
Peak memory 199356 kb
Host smart-cb10febb-5a94-467b-9ac4-233471292ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884774911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1884774911
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2629415309
Short name T706
Test name
Test status
Simulation time 37732768437 ps
CPU time 27.04 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:45:09 PM PST 24
Peak memory 196336 kb
Host smart-a4b867dd-96ac-4072-9fd2-95850c91da08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629415309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2629415309
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1782950024
Short name T508
Test name
Test status
Simulation time 268451278 ps
CPU time 1.39 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:44:44 PM PST 24
Peak memory 199460 kb
Host smart-b00feb40-450e-4d31-a71f-721806408187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782950024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1782950024
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3246873613
Short name T396
Test name
Test status
Simulation time 1774760259 ps
CPU time 1.84 seconds
Started Mar 07 01:44:44 PM PST 24
Finished Mar 07 01:44:46 PM PST 24
Peak memory 198452 kb
Host smart-625c714a-4593-422f-b2cf-67354eebb312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246873613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3246873613
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3835190647
Short name T700
Test name
Test status
Simulation time 16833322791 ps
CPU time 9.49 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:44:51 PM PST 24
Peak memory 200508 kb
Host smart-d56dfe89-2d52-44a2-879a-1da37b3149db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835190647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3835190647
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1423554746
Short name T897
Test name
Test status
Simulation time 96352499952 ps
CPU time 43.92 seconds
Started Mar 07 01:47:16 PM PST 24
Finished Mar 07 01:48:00 PM PST 24
Peak memory 200164 kb
Host smart-5c903f7e-756f-453e-a115-706fdd52db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423554746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1423554746
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.4040529739
Short name T708
Test name
Test status
Simulation time 118768422975 ps
CPU time 44.37 seconds
Started Mar 07 01:47:12 PM PST 24
Finished Mar 07 01:47:56 PM PST 24
Peak memory 200160 kb
Host smart-1ea168d6-18e1-4953-9a65-7665f95d92af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040529739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.4040529739
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3476451672
Short name T216
Test name
Test status
Simulation time 63100910789 ps
CPU time 106.77 seconds
Started Mar 07 01:47:19 PM PST 24
Finished Mar 07 01:49:06 PM PST 24
Peak memory 200500 kb
Host smart-d398275e-7d09-4e00-8550-ad1596b938db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476451672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3476451672
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3392413673
Short name T782
Test name
Test status
Simulation time 113159802041 ps
CPU time 47.04 seconds
Started Mar 07 01:47:20 PM PST 24
Finished Mar 07 01:48:07 PM PST 24
Peak memory 199840 kb
Host smart-ed70cb10-1e2b-46fc-8c14-e2cda05e3426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392413673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3392413673
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.192971655
Short name T1087
Test name
Test status
Simulation time 44541716726 ps
CPU time 17.66 seconds
Started Mar 07 01:47:24 PM PST 24
Finished Mar 07 01:47:42 PM PST 24
Peak memory 200528 kb
Host smart-2afda792-5a87-4765-9d00-5a6774dfd821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192971655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.192971655
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3668528920
Short name T232
Test name
Test status
Simulation time 213076370219 ps
CPU time 336.56 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:52:58 PM PST 24
Peak memory 200476 kb
Host smart-3f51e7cb-a68a-458f-803f-cf7ffc1f8890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668528920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3668528920
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3702560233
Short name T111
Test name
Test status
Simulation time 115428989843 ps
CPU time 113.06 seconds
Started Mar 07 01:47:27 PM PST 24
Finished Mar 07 01:49:20 PM PST 24
Peak memory 200564 kb
Host smart-3c303b89-aa9a-4547-881b-d940740cf1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702560233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3702560233
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1517497787
Short name T946
Test name
Test status
Simulation time 13544476 ps
CPU time 0.56 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 01:44:47 PM PST 24
Peak memory 195864 kb
Host smart-a40229f2-249b-4771-b942-b48492d287cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517497787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1517497787
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1833555200
Short name T256
Test name
Test status
Simulation time 123358066542 ps
CPU time 215.79 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 01:48:22 PM PST 24
Peak memory 200540 kb
Host smart-5bef2807-144b-4bbc-b568-600dda7132d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833555200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1833555200
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1360995594
Short name T756
Test name
Test status
Simulation time 213978102970 ps
CPU time 19.28 seconds
Started Mar 07 01:44:44 PM PST 24
Finished Mar 07 01:45:03 PM PST 24
Peak memory 198388 kb
Host smart-5e84a8f7-9a97-4787-8339-e4d54493cc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360995594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1360995594
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.3649615100
Short name T516
Test name
Test status
Simulation time 336453153002 ps
CPU time 535.64 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:53:38 PM PST 24
Peak memory 200512 kb
Host smart-76c24121-b9bb-43a7-851c-c084263a1e9a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649615100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3649615100
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.344593203
Short name T951
Test name
Test status
Simulation time 109926115985 ps
CPU time 190.35 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:47:52 PM PST 24
Peak memory 200476 kb
Host smart-bda57ea2-f85b-4404-a9a9-75b5dc6cd765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344593203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.344593203
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.327864801
Short name T622
Test name
Test status
Simulation time 6123960378 ps
CPU time 6.96 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:44:49 PM PST 24
Peak memory 198496 kb
Host smart-2513412a-7868-4d3b-9d1f-c0e9cf7c5a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327864801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.327864801
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2472103530
Short name T856
Test name
Test status
Simulation time 87748778674 ps
CPU time 86.26 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:46:06 PM PST 24
Peak memory 200840 kb
Host smart-e71be8ae-0277-43e2-9842-f34a9c9a3ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472103530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2472103530
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2254854663
Short name T398
Test name
Test status
Simulation time 25067848145 ps
CPU time 1044.06 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 02:02:06 PM PST 24
Peak memory 200552 kb
Host smart-125818c3-7014-4152-98eb-2c0917779164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254854663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2254854663
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.658406710
Short name T1098
Test name
Test status
Simulation time 4445589185 ps
CPU time 9.72 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:44:53 PM PST 24
Peak memory 199392 kb
Host smart-638da1bc-a01f-4fd1-839d-021f72192e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658406710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.658406710
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3336508871
Short name T630
Test name
Test status
Simulation time 232823033068 ps
CPU time 232.34 seconds
Started Mar 07 01:44:45 PM PST 24
Finished Mar 07 01:48:38 PM PST 24
Peak memory 200532 kb
Host smart-eeb4e84f-191b-404a-ae05-b798a1fc6428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336508871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3336508871
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3658009180
Short name T755
Test name
Test status
Simulation time 33195233890 ps
CPU time 45.13 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:45:25 PM PST 24
Peak memory 196316 kb
Host smart-435cc222-6d59-4509-b705-9fe5fb856a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658009180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3658009180
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3534845089
Short name T859
Test name
Test status
Simulation time 105155855 ps
CPU time 0.98 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:44:43 PM PST 24
Peak memory 198236 kb
Host smart-8bc3ed59-adc5-48df-9a01-b80f38f432d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534845089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3534845089
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2070075530
Short name T829
Test name
Test status
Simulation time 7379689561 ps
CPU time 9.08 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:44:48 PM PST 24
Peak memory 200472 kb
Host smart-b2c614ff-7d09-401d-926d-af7a3ee30b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070075530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2070075530
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2752560981
Short name T156
Test name
Test status
Simulation time 22926470871 ps
CPU time 37.6 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:45:19 PM PST 24
Peak memory 200444 kb
Host smart-0235ec0c-581f-4085-a4e9-1a5686e7fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752560981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2752560981
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3152695989
Short name T159
Test name
Test status
Simulation time 84352424679 ps
CPU time 208.14 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 200544 kb
Host smart-4d4d8de9-4af8-4c8e-a5aa-9a2104a028bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152695989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3152695989
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1546014531
Short name T95
Test name
Test status
Simulation time 44819561498 ps
CPU time 29.42 seconds
Started Mar 07 01:47:24 PM PST 24
Finished Mar 07 01:47:54 PM PST 24
Peak memory 200584 kb
Host smart-c51abb0f-03b4-4101-bd40-c9e1504ef5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546014531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1546014531
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1250011662
Short name T299
Test name
Test status
Simulation time 14400235015 ps
CPU time 18.36 seconds
Started Mar 07 01:47:20 PM PST 24
Finished Mar 07 01:47:38 PM PST 24
Peak memory 199720 kb
Host smart-1199f2d4-e246-47c7-9203-8373352e4499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250011662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1250011662
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1383950
Short name T250
Test name
Test status
Simulation time 68948007499 ps
CPU time 107.89 seconds
Started Mar 07 01:47:23 PM PST 24
Finished Mar 07 01:49:11 PM PST 24
Peak memory 200516 kb
Host smart-05a70b88-1d7e-4fcd-96b2-f1d1bd570b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1383950
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3220044626
Short name T501
Test name
Test status
Simulation time 7368842154 ps
CPU time 12.26 seconds
Started Mar 07 01:47:19 PM PST 24
Finished Mar 07 01:47:32 PM PST 24
Peak memory 198832 kb
Host smart-0b98e632-a3b8-469e-912c-61d40e9d66e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220044626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3220044626
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1271319798
Short name T821
Test name
Test status
Simulation time 205899991760 ps
CPU time 32.58 seconds
Started Mar 07 01:47:20 PM PST 24
Finished Mar 07 01:47:53 PM PST 24
Peak memory 200608 kb
Host smart-41f8f891-be7c-4436-9f74-7f8d74ba0a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271319798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1271319798
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1187961587
Short name T725
Test name
Test status
Simulation time 22297276786 ps
CPU time 8.2 seconds
Started Mar 07 01:47:20 PM PST 24
Finished Mar 07 01:47:29 PM PST 24
Peak memory 199076 kb
Host smart-b06207be-db69-4437-b6f6-bf1ecf1021a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187961587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1187961587
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.904983100
Short name T697
Test name
Test status
Simulation time 230585610893 ps
CPU time 253.91 seconds
Started Mar 07 01:47:20 PM PST 24
Finished Mar 07 01:51:34 PM PST 24
Peak memory 200580 kb
Host smart-fb448a65-b172-422c-a336-4c2979ca88d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904983100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.904983100
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2322032981
Short name T808
Test name
Test status
Simulation time 14569245 ps
CPU time 0.58 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 01:44:47 PM PST 24
Peak memory 195968 kb
Host smart-0343522a-d0dc-4f4c-b03b-9c63b6cc01e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322032981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2322032981
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.585210047
Short name T840
Test name
Test status
Simulation time 65193007720 ps
CPU time 19.95 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 01:45:07 PM PST 24
Peak memory 200412 kb
Host smart-c59ab2a0-08be-422e-ac4a-b778ba1341a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585210047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.585210047
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.14287617
Short name T331
Test name
Test status
Simulation time 35057407005 ps
CPU time 54.1 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:45:36 PM PST 24
Peak memory 200520 kb
Host smart-a6d13dad-3e48-4168-8ea4-c359c5b53fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14287617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.14287617
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1398548754
Short name T405
Test name
Test status
Simulation time 127158630012 ps
CPU time 667.41 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:55:50 PM PST 24
Peak memory 200532 kb
Host smart-620c11d8-af17-45c3-bc83-fcd45659e045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398548754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1398548754
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3061904885
Short name T739
Test name
Test status
Simulation time 196821644947 ps
CPU time 54.65 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:45:37 PM PST 24
Peak memory 200440 kb
Host smart-6d24508d-b4ab-4a75-a103-7e0a2e119b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061904885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3061904885
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.585797030
Short name T642
Test name
Test status
Simulation time 6029877186 ps
CPU time 53.84 seconds
Started Mar 07 01:44:45 PM PST 24
Finished Mar 07 01:45:39 PM PST 24
Peak memory 199300 kb
Host smart-5fe079e6-895e-4b1e-a32d-e98102b96d4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585797030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.585797030
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1388070383
Short name T318
Test name
Test status
Simulation time 218916815425 ps
CPU time 291.93 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:49:34 PM PST 24
Peak memory 200464 kb
Host smart-308ae17b-4c27-4ad0-b456-0edd42869fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388070383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1388070383
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4149192425
Short name T409
Test name
Test status
Simulation time 41716692148 ps
CPU time 66.28 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:45:48 PM PST 24
Peak memory 196332 kb
Host smart-6860a3bc-8252-44ef-8634-b9401e05b4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149192425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4149192425
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1558822992
Short name T1064
Test name
Test status
Simulation time 689914798 ps
CPU time 2.48 seconds
Started Mar 07 01:44:40 PM PST 24
Finished Mar 07 01:44:43 PM PST 24
Peak memory 198796 kb
Host smart-a8abc960-1b6c-47c4-b620-55db507cfe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558822992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1558822992
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.770754418
Short name T678
Test name
Test status
Simulation time 430546077 ps
CPU time 1.15 seconds
Started Mar 07 01:44:40 PM PST 24
Finished Mar 07 01:44:42 PM PST 24
Peak memory 198228 kb
Host smart-663e2966-23e5-44b0-81ca-efe209f03e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770754418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.770754418
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2090092655
Short name T985
Test name
Test status
Simulation time 411067507524 ps
CPU time 59.18 seconds
Started Mar 07 01:44:41 PM PST 24
Finished Mar 07 01:45:41 PM PST 24
Peak memory 200596 kb
Host smart-f70224c9-b381-481b-b50a-6cab1629c001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090092655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2090092655
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2855990998
Short name T619
Test name
Test status
Simulation time 55492243639 ps
CPU time 80.83 seconds
Started Mar 07 01:47:19 PM PST 24
Finished Mar 07 01:48:40 PM PST 24
Peak memory 200500 kb
Host smart-704bd702-f1a5-40e3-8948-991e70a3dcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855990998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2855990998
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1051558298
Short name T118
Test name
Test status
Simulation time 8589267997 ps
CPU time 13.16 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:47:34 PM PST 24
Peak memory 198476 kb
Host smart-4ba324c0-7aa7-4582-8a03-905ed94340fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051558298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1051558298
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3265120220
Short name T864
Test name
Test status
Simulation time 51930719592 ps
CPU time 23.44 seconds
Started Mar 07 01:47:29 PM PST 24
Finished Mar 07 01:47:53 PM PST 24
Peak memory 200556 kb
Host smart-6e881a5c-7220-4ade-894c-be1cfd17a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265120220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3265120220
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.779557224
Short name T264
Test name
Test status
Simulation time 151550279915 ps
CPU time 61.64 seconds
Started Mar 07 01:47:26 PM PST 24
Finished Mar 07 01:48:27 PM PST 24
Peak memory 200124 kb
Host smart-7b7cbe22-b41a-425b-9895-b04ff86c9083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779557224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.779557224
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2259559651
Short name T2
Test name
Test status
Simulation time 195307843491 ps
CPU time 197.32 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:50:39 PM PST 24
Peak memory 200320 kb
Host smart-5630fce4-bfcf-4fc6-ad72-88b7de53fa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259559651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2259559651
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2348072859
Short name T241
Test name
Test status
Simulation time 86586633263 ps
CPU time 193.31 seconds
Started Mar 07 01:47:19 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 200464 kb
Host smart-da05e6f1-c14c-4995-af99-a6bc141a881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348072859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2348072859
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1662710774
Short name T313
Test name
Test status
Simulation time 17889261059 ps
CPU time 17.26 seconds
Started Mar 07 01:47:26 PM PST 24
Finished Mar 07 01:47:43 PM PST 24
Peak memory 200148 kb
Host smart-9834c6db-56f5-45c2-95a6-c4892018b6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662710774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1662710774
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.584121914
Short name T750
Test name
Test status
Simulation time 14685064 ps
CPU time 0.57 seconds
Started Mar 07 01:44:45 PM PST 24
Finished Mar 07 01:44:45 PM PST 24
Peak memory 195972 kb
Host smart-c1d7f764-da73-4977-8c98-d0763e6d18f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584121914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.584121914
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4082584437
Short name T1016
Test name
Test status
Simulation time 76283558155 ps
CPU time 26.84 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:45:09 PM PST 24
Peak memory 200524 kb
Host smart-70fd1df1-6c4d-416e-83c4-fa19c8dc151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082584437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4082584437
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.919547530
Short name T355
Test name
Test status
Simulation time 257158781204 ps
CPU time 49.89 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:45:38 PM PST 24
Peak memory 200440 kb
Host smart-35e87115-d8f3-4909-bdd2-2a230e2ad282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919547530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.919547530
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3022255694
Short name T979
Test name
Test status
Simulation time 57394618297 ps
CPU time 26.31 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:45:09 PM PST 24
Peak memory 200444 kb
Host smart-0af712d5-97d1-466d-bfe8-e3e4edcf526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022255694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3022255694
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3868683511
Short name T600
Test name
Test status
Simulation time 160295662246 ps
CPU time 394.02 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 01:51:21 PM PST 24
Peak memory 200540 kb
Host smart-c5bd6938-9efe-4fbf-b279-1ff24148e906
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868683511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3868683511
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.348058237
Short name T1086
Test name
Test status
Simulation time 1618592999 ps
CPU time 2.02 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:44:50 PM PST 24
Peak memory 197160 kb
Host smart-aaff5e2c-91d0-4503-a202-a6b5be416f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348058237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.348058237
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2781006700
Short name T784
Test name
Test status
Simulation time 21381280033 ps
CPU time 2.5 seconds
Started Mar 07 01:44:49 PM PST 24
Finished Mar 07 01:44:52 PM PST 24
Peak memory 195196 kb
Host smart-38892813-69dc-469f-8ac4-8eba1da0bcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781006700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2781006700
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2172496099
Short name T761
Test name
Test status
Simulation time 14844122342 ps
CPU time 369.81 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:50:58 PM PST 24
Peak memory 200576 kb
Host smart-02646c9b-bbd4-43d0-b5c0-2e2fa9860efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172496099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2172496099
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.401021740
Short name T999
Test name
Test status
Simulation time 6884775003 ps
CPU time 16.99 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:45:05 PM PST 24
Peak memory 199336 kb
Host smart-57886bac-5d02-4402-9c6a-91740dc32247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401021740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.401021740
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.319513463
Short name T766
Test name
Test status
Simulation time 28362690999 ps
CPU time 23.23 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:45:11 PM PST 24
Peak memory 199752 kb
Host smart-c2e19501-c328-471d-b67f-985458f26e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319513463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.319513463
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1087911457
Short name T839
Test name
Test status
Simulation time 3809391147 ps
CPU time 6.84 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:44:54 PM PST 24
Peak memory 196372 kb
Host smart-af2faf64-9b87-4bc4-86d1-ebd2a9c362bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087911457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1087911457
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.736848215
Short name T1077
Test name
Test status
Simulation time 686333174 ps
CPU time 2.83 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 01:44:49 PM PST 24
Peak memory 198892 kb
Host smart-543afa80-d73f-4997-bcc2-a51ab6809d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736848215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.736848215
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1630371195
Short name T137
Test name
Test status
Simulation time 114890845495 ps
CPU time 594 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:54:41 PM PST 24
Peak memory 200556 kb
Host smart-275a4dd2-be72-4833-b0a0-8a84a25dc65d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630371195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1630371195
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3211823857
Short name T51
Test name
Test status
Simulation time 290884635172 ps
CPU time 375.25 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 01:51:02 PM PST 24
Peak memory 210856 kb
Host smart-bc3942b0-4b6a-417d-a07d-45232c451033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211823857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3211823857
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2716582339
Short name T7
Test name
Test status
Simulation time 3487733950 ps
CPU time 1.93 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:44:45 PM PST 24
Peak memory 199320 kb
Host smart-99d8eb7d-7fb6-4e80-9bc5-4be0a8abed61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716582339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2716582339
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3023897410
Short name T719
Test name
Test status
Simulation time 38227603121 ps
CPU time 18.33 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:45:06 PM PST 24
Peak memory 199108 kb
Host smart-ff97c3c5-62ae-4c3c-99ba-bfc24ff0a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023897410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3023897410
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1572336098
Short name T916
Test name
Test status
Simulation time 115332065563 ps
CPU time 34.87 seconds
Started Mar 07 01:47:24 PM PST 24
Finished Mar 07 01:47:59 PM PST 24
Peak memory 200596 kb
Host smart-47d6f9a6-b942-402b-8628-38374f192869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572336098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1572336098
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.186639012
Short name T197
Test name
Test status
Simulation time 38150899811 ps
CPU time 14.63 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:47:36 PM PST 24
Peak memory 200588 kb
Host smart-489e8c84-5f57-42d4-a529-82e3e67c431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186639012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.186639012
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.46876058
Short name T124
Test name
Test status
Simulation time 116042279059 ps
CPU time 51.18 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:48:12 PM PST 24
Peak memory 200516 kb
Host smart-811800b2-06f0-4fc2-a60f-1d77f03c5689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46876058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.46876058
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1562759466
Short name T162
Test name
Test status
Simulation time 106586825348 ps
CPU time 88.14 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:48:49 PM PST 24
Peak memory 199708 kb
Host smart-456197a5-58c6-46e7-bb98-947c5e876dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562759466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1562759466
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3735723755
Short name T580
Test name
Test status
Simulation time 22157334309 ps
CPU time 36.93 seconds
Started Mar 07 01:47:22 PM PST 24
Finished Mar 07 01:47:59 PM PST 24
Peak memory 200528 kb
Host smart-b7225bbb-1e22-41bf-b28c-d09fa7264500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735723755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3735723755
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1599790322
Short name T274
Test name
Test status
Simulation time 65572466712 ps
CPU time 25.57 seconds
Started Mar 07 01:47:25 PM PST 24
Finished Mar 07 01:47:51 PM PST 24
Peak memory 200588 kb
Host smart-3d9f58e2-2b03-4fa1-86a3-7e37d7d9b770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599790322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1599790322
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2882869674
Short name T275
Test name
Test status
Simulation time 108784520748 ps
CPU time 43.56 seconds
Started Mar 07 01:47:27 PM PST 24
Finished Mar 07 01:48:12 PM PST 24
Peak memory 200256 kb
Host smart-aba436da-bd87-4407-b4ef-aac56aaf5400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882869674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2882869674
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3817637091
Short name T237
Test name
Test status
Simulation time 82189394986 ps
CPU time 156.65 seconds
Started Mar 07 01:47:22 PM PST 24
Finished Mar 07 01:49:59 PM PST 24
Peak memory 200520 kb
Host smart-6b2d75a9-1354-4d9a-b3d6-6b26e8dd378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817637091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3817637091
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.4154740976
Short name T279
Test name
Test status
Simulation time 60479724172 ps
CPU time 30.31 seconds
Started Mar 07 01:47:20 PM PST 24
Finished Mar 07 01:47:50 PM PST 24
Peak memory 200520 kb
Host smart-d295574a-0c28-4fd1-a7f8-252c0b21a95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154740976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.4154740976
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1811600808
Short name T458
Test name
Test status
Simulation time 13266721 ps
CPU time 0.56 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:44:52 PM PST 24
Peak memory 195960 kb
Host smart-78b006f0-a35e-424f-9478-260d60e40c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811600808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1811600808
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2036048960
Short name T726
Test name
Test status
Simulation time 65336619989 ps
CPU time 26.29 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:45:20 PM PST 24
Peak memory 199644 kb
Host smart-ab745984-5482-4b17-bb0e-620c1518fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036048960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2036048960
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.1813550694
Short name T453
Test name
Test status
Simulation time 299231137233 ps
CPU time 465.82 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:52:40 PM PST 24
Peak memory 200540 kb
Host smart-d07252b3-69db-4c48-89b5-93568ccca186
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813550694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1813550694
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.7148086
Short name T866
Test name
Test status
Simulation time 100970464149 ps
CPU time 307.37 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 200544 kb
Host smart-ffa5d76e-7be9-47e9-aa48-cbc0ca620920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7148086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.7148086
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2415749008
Short name T503
Test name
Test status
Simulation time 6569013835 ps
CPU time 13.47 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:45:05 PM PST 24
Peak memory 198672 kb
Host smart-84e22835-ea46-4500-a5ca-cd5f8ccbf40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415749008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2415749008
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1012241401
Short name T732
Test name
Test status
Simulation time 50032515668 ps
CPU time 81.27 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:46:09 PM PST 24
Peak memory 200004 kb
Host smart-6c3b4300-b75e-4f78-ba0f-491e28e27201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012241401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1012241401
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1171023292
Short name T760
Test name
Test status
Simulation time 24268723627 ps
CPU time 1355.06 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 02:07:23 PM PST 24
Peak memory 200464 kb
Host smart-916bac49-5faa-4828-912d-af545ba0e66a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171023292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1171023292
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2616269256
Short name T463
Test name
Test status
Simulation time 3362531060 ps
CPU time 21.2 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:45:13 PM PST 24
Peak memory 198556 kb
Host smart-ef84c469-4b11-4056-b440-af5c51806977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2616269256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2616269256
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2674017572
Short name T245
Test name
Test status
Simulation time 44690321213 ps
CPU time 14.08 seconds
Started Mar 07 01:44:44 PM PST 24
Finished Mar 07 01:44:59 PM PST 24
Peak memory 200500 kb
Host smart-d8f9314d-5ba5-4c76-bd3e-2ea4155a0f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674017572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2674017572
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1457653591
Short name T590
Test name
Test status
Simulation time 4139442761 ps
CPU time 7.58 seconds
Started Mar 07 01:44:49 PM PST 24
Finished Mar 07 01:44:57 PM PST 24
Peak memory 196384 kb
Host smart-ae02de58-b49a-4736-8d6f-c3fd3e1e8b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457653591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1457653591
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1370792873
Short name T616
Test name
Test status
Simulation time 461506795 ps
CPU time 2.04 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:44:50 PM PST 24
Peak memory 198688 kb
Host smart-da5833e3-7fee-4fd8-87f3-97594f66053b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370792873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1370792873
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.20236121
Short name T699
Test name
Test status
Simulation time 395678008666 ps
CPU time 424.39 seconds
Started Mar 07 01:44:49 PM PST 24
Finished Mar 07 01:51:54 PM PST 24
Peak memory 200596 kb
Host smart-630b748c-9e32-4e6c-8953-2bae54225abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20236121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.20236121
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3659375628
Short name T99
Test name
Test status
Simulation time 65081154169 ps
CPU time 308.06 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:49:55 PM PST 24
Peak memory 209128 kb
Host smart-055c87bb-44a2-47a0-9ede-8376d0ea5d6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659375628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3659375628
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.368634091
Short name T621
Test name
Test status
Simulation time 7239286655 ps
CPU time 14.66 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:45:06 PM PST 24
Peak memory 200012 kb
Host smart-3a08234f-b12d-449e-ab4a-5708a4b4545a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368634091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.368634091
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2012965161
Short name T770
Test name
Test status
Simulation time 40764225433 ps
CPU time 69.65 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:45:57 PM PST 24
Peak memory 200584 kb
Host smart-12010ed0-729d-474d-89c4-693ffa689eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012965161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2012965161
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.158017709
Short name T658
Test name
Test status
Simulation time 123103312955 ps
CPU time 105.63 seconds
Started Mar 07 01:47:21 PM PST 24
Finished Mar 07 01:49:06 PM PST 24
Peak memory 200548 kb
Host smart-bb26b9bb-d26c-4765-a556-256a30427ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158017709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.158017709
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3377911324
Short name T260
Test name
Test status
Simulation time 52611776624 ps
CPU time 78.96 seconds
Started Mar 07 01:47:20 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 200596 kb
Host smart-cbf63a30-c230-44ad-881d-4b23e8f341a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377911324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3377911324
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.117822133
Short name T40
Test name
Test status
Simulation time 21597506926 ps
CPU time 37.25 seconds
Started Mar 07 01:47:26 PM PST 24
Finished Mar 07 01:48:04 PM PST 24
Peak memory 200316 kb
Host smart-0716af6d-7db1-4d84-b87a-94fbd895f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117822133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.117822133
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3086896268
Short name T117
Test name
Test status
Simulation time 39799649417 ps
CPU time 68.55 seconds
Started Mar 07 01:47:20 PM PST 24
Finished Mar 07 01:48:29 PM PST 24
Peak memory 200520 kb
Host smart-b61a5482-ee4e-454b-a6f6-acb64ef2a2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086896268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3086896268
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.397091520
Short name T865
Test name
Test status
Simulation time 116718996945 ps
CPU time 25.23 seconds
Started Mar 07 01:47:29 PM PST 24
Finished Mar 07 01:47:54 PM PST 24
Peak memory 200564 kb
Host smart-5c80cd47-61c6-44eb-af45-db7130bc307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397091520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.397091520
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.666261149
Short name T115
Test name
Test status
Simulation time 118135649215 ps
CPU time 213.11 seconds
Started Mar 07 01:47:28 PM PST 24
Finished Mar 07 01:51:02 PM PST 24
Peak memory 200608 kb
Host smart-8a4d6b3b-75c0-4aa3-8aa4-76d918134fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666261149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.666261149
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3855171967
Short name T904
Test name
Test status
Simulation time 19171107686 ps
CPU time 16.26 seconds
Started Mar 07 01:47:27 PM PST 24
Finished Mar 07 01:47:44 PM PST 24
Peak memory 200564 kb
Host smart-b48ab7ac-eb68-42f8-bd8d-620d8a608640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855171967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3855171967
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3237553434
Short name T319
Test name
Test status
Simulation time 17275901263 ps
CPU time 15.38 seconds
Started Mar 07 01:47:30 PM PST 24
Finished Mar 07 01:47:46 PM PST 24
Peak memory 200416 kb
Host smart-118d3bcf-80e2-4d81-bf25-4aa7b673512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237553434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3237553434
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2603433669
Short name T938
Test name
Test status
Simulation time 32647724 ps
CPU time 0.55 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:44:48 PM PST 24
Peak memory 196020 kb
Host smart-d9bdad40-43f8-4ff8-8f18-ae2edda38ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603433669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2603433669
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3522296621
Short name T647
Test name
Test status
Simulation time 51019938086 ps
CPU time 89.21 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:46:16 PM PST 24
Peak memory 200612 kb
Host smart-11a9fdc1-bf31-47c3-b1e4-0683bdc5257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522296621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3522296621
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3809470206
Short name T660
Test name
Test status
Simulation time 80162270062 ps
CPU time 29.94 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:45:25 PM PST 24
Peak memory 200528 kb
Host smart-5dff3925-e019-4534-8528-29b53aaf9a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809470206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3809470206
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1747105966
Short name T303
Test name
Test status
Simulation time 101180031406 ps
CPU time 188.51 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:47:56 PM PST 24
Peak memory 200588 kb
Host smart-acd6304f-164a-4c5d-b44a-a055328aa1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747105966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1747105966
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3429827622
Short name T1036
Test name
Test status
Simulation time 37881843014 ps
CPU time 11.84 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:45:06 PM PST 24
Peak memory 200500 kb
Host smart-80d452ec-df44-4217-b617-a0661bc4961f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429827622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3429827622
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.487717262
Short name T470
Test name
Test status
Simulation time 111899903124 ps
CPU time 694.62 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:56:18 PM PST 24
Peak memory 200520 kb
Host smart-efd45abb-27f1-48b3-af75-257344d7782a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487717262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.487717262
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2864626744
Short name T722
Test name
Test status
Simulation time 8031427514 ps
CPU time 18.09 seconds
Started Mar 07 01:44:49 PM PST 24
Finished Mar 07 01:45:08 PM PST 24
Peak memory 199520 kb
Host smart-082477cc-0929-4433-a0d1-a8678d5fe084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864626744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2864626744
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1446281605
Short name T422
Test name
Test status
Simulation time 32795964353 ps
CPU time 15.32 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:45:03 PM PST 24
Peak memory 198056 kb
Host smart-a39ee813-c409-40a4-8971-8011a43ea458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446281605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1446281605
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1270154142
Short name T178
Test name
Test status
Simulation time 18118997373 ps
CPU time 130.29 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:46:58 PM PST 24
Peak memory 200536 kb
Host smart-29888952-4ab8-4fab-9416-e1ca428c5f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270154142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1270154142
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3922974826
Short name T707
Test name
Test status
Simulation time 7057717916 ps
CPU time 61.01 seconds
Started Mar 07 01:44:54 PM PST 24
Finished Mar 07 01:45:56 PM PST 24
Peak memory 199344 kb
Host smart-2c6718fe-e42f-4c6a-88fe-3ead580214df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922974826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3922974826
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2156541166
Short name T609
Test name
Test status
Simulation time 4372977797 ps
CPU time 1.65 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:44:56 PM PST 24
Peak memory 196344 kb
Host smart-041e12bd-c4b5-41fd-bc1d-d9259af6526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156541166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2156541166
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.226917093
Short name T489
Test name
Test status
Simulation time 5992084078 ps
CPU time 24.37 seconds
Started Mar 07 01:44:40 PM PST 24
Finished Mar 07 01:45:05 PM PST 24
Peak memory 199956 kb
Host smart-53eed595-7ca1-4798-a9df-03089ecc08fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226917093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.226917093
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.252620605
Short name T208
Test name
Test status
Simulation time 273266908908 ps
CPU time 1426.43 seconds
Started Mar 07 01:44:46 PM PST 24
Finished Mar 07 02:08:33 PM PST 24
Peak memory 200600 kb
Host smart-6d97477d-448f-48fe-b2b3-2c3a7fc68a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252620605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.252620605
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1924393537
Short name T955
Test name
Test status
Simulation time 1108606555 ps
CPU time 3.06 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:44:50 PM PST 24
Peak memory 198844 kb
Host smart-6a37641e-b2cc-4b13-a6ee-e58619c5c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924393537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1924393537
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2449540198
Short name T746
Test name
Test status
Simulation time 145171655088 ps
CPU time 58.94 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:45:47 PM PST 24
Peak memory 200584 kb
Host smart-8f28a039-f9f4-47d6-a21a-3ea127602e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449540198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2449540198
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.865316595
Short name T369
Test name
Test status
Simulation time 131700980419 ps
CPU time 206.07 seconds
Started Mar 07 01:47:27 PM PST 24
Finished Mar 07 01:50:53 PM PST 24
Peak memory 200528 kb
Host smart-7ef76eba-f41e-4874-843e-d5522899ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865316595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.865316595
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2048671785
Short name T307
Test name
Test status
Simulation time 47551839134 ps
CPU time 20.59 seconds
Started Mar 07 01:47:28 PM PST 24
Finished Mar 07 01:47:49 PM PST 24
Peak memory 200396 kb
Host smart-1d6a39bb-d94a-40e3-b00e-7cfcf305c2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048671785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2048671785
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1101349557
Short name T271
Test name
Test status
Simulation time 50027737171 ps
CPU time 71.12 seconds
Started Mar 07 01:47:28 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 200556 kb
Host smart-f672e9c3-0212-4248-965e-f61d39ac6991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101349557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1101349557
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2871740673
Short name T254
Test name
Test status
Simulation time 14039791794 ps
CPU time 20.68 seconds
Started Mar 07 01:47:36 PM PST 24
Finished Mar 07 01:47:57 PM PST 24
Peak memory 198888 kb
Host smart-29cd0e0d-45a4-4312-8969-b757faa48f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871740673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2871740673
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1916561878
Short name T98
Test name
Test status
Simulation time 25806586873 ps
CPU time 22.62 seconds
Started Mar 07 01:47:29 PM PST 24
Finished Mar 07 01:47:52 PM PST 24
Peak memory 199960 kb
Host smart-ed0a675d-5423-4e7e-b11f-28865f6929fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916561878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1916561878
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.931085904
Short name T287
Test name
Test status
Simulation time 67350716428 ps
CPU time 104.75 seconds
Started Mar 07 01:47:30 PM PST 24
Finished Mar 07 01:49:15 PM PST 24
Peak memory 200564 kb
Host smart-36d5a4ec-5b54-467e-8af9-5015c42b7070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931085904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.931085904
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3023227995
Short name T269
Test name
Test status
Simulation time 136457683705 ps
CPU time 213.23 seconds
Started Mar 07 01:47:33 PM PST 24
Finished Mar 07 01:51:07 PM PST 24
Peak memory 200488 kb
Host smart-f7250321-d760-4dac-ad37-5e0635d8721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023227995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3023227995
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2575264796
Short name T443
Test name
Test status
Simulation time 161482765722 ps
CPU time 18.61 seconds
Started Mar 07 01:47:29 PM PST 24
Finished Mar 07 01:47:48 PM PST 24
Peak memory 198848 kb
Host smart-8133c4ce-06e6-45e1-a610-1711aff90a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575264796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2575264796
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.721936555
Short name T187
Test name
Test status
Simulation time 46526365871 ps
CPU time 73.74 seconds
Started Mar 07 01:47:30 PM PST 24
Finished Mar 07 01:48:44 PM PST 24
Peak memory 200496 kb
Host smart-124a80da-75eb-4cc4-b5eb-1fcd977bcc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721936555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.721936555
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1288790335
Short name T202
Test name
Test status
Simulation time 10961968496 ps
CPU time 20.41 seconds
Started Mar 07 01:47:27 PM PST 24
Finished Mar 07 01:47:48 PM PST 24
Peak memory 200596 kb
Host smart-34fbf1cb-d666-4397-8cca-61afb3b5ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288790335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1288790335
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3708217176
Short name T815
Test name
Test status
Simulation time 15079262 ps
CPU time 0.57 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:44:43 PM PST 24
Peak memory 195940 kb
Host smart-9e612cfe-9db9-4f8d-8126-7400ddded460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708217176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3708217176
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3269660525
Short name T748
Test name
Test status
Simulation time 30577046939 ps
CPU time 48.94 seconds
Started Mar 07 01:44:54 PM PST 24
Finished Mar 07 01:45:44 PM PST 24
Peak memory 200532 kb
Host smart-5b72ebd1-5f42-4b7e-94ed-a60d26276149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269660525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3269660525
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_intr.1374536559
Short name T408
Test name
Test status
Simulation time 477005343708 ps
CPU time 1050.61 seconds
Started Mar 07 01:44:52 PM PST 24
Finished Mar 07 02:02:24 PM PST 24
Peak memory 200344 kb
Host smart-02c60e7d-ef17-48ed-8519-8da4d7bc1dda
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374536559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1374536559
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.700805480
Short name T566
Test name
Test status
Simulation time 289951009527 ps
CPU time 465.16 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:52:38 PM PST 24
Peak memory 200600 kb
Host smart-19a7ec1c-24e6-412d-9219-2bf876473524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700805480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.700805480
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1960876293
Short name T546
Test name
Test status
Simulation time 9907770844 ps
CPU time 15.17 seconds
Started Mar 07 01:44:52 PM PST 24
Finished Mar 07 01:45:08 PM PST 24
Peak memory 199356 kb
Host smart-5ff6dffe-311c-4a58-98cf-9c8b06922872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960876293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1960876293
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2651164995
Short name T131
Test name
Test status
Simulation time 25044993868 ps
CPU time 40.65 seconds
Started Mar 07 01:44:54 PM PST 24
Finished Mar 07 01:45:36 PM PST 24
Peak memory 198668 kb
Host smart-77699f4f-eca7-467e-b190-0189d41c9ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651164995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2651164995
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1949838223
Short name T226
Test name
Test status
Simulation time 11381374461 ps
CPU time 148.22 seconds
Started Mar 07 01:44:50 PM PST 24
Finished Mar 07 01:47:19 PM PST 24
Peak memory 200476 kb
Host smart-c0bd1326-ba6b-480d-89c0-3c5af9ee48ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1949838223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1949838223
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3557573118
Short name T581
Test name
Test status
Simulation time 3655422794 ps
CPU time 16.15 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:45:04 PM PST 24
Peak memory 198992 kb
Host smart-4f993bda-5145-430d-9629-326f4983f072
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557573118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3557573118
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1836926193
Short name T1056
Test name
Test status
Simulation time 37400883467 ps
CPU time 37.64 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:45:29 PM PST 24
Peak memory 200332 kb
Host smart-d429d33c-e036-4bee-a356-248ab0242289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836926193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1836926193
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1241763753
Short name T437
Test name
Test status
Simulation time 34032439341 ps
CPU time 50.09 seconds
Started Mar 07 01:44:49 PM PST 24
Finished Mar 07 01:45:39 PM PST 24
Peak memory 196292 kb
Host smart-4be49043-a14f-4d84-97c7-8e7c61532cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241763753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1241763753
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3913459534
Short name T933
Test name
Test status
Simulation time 11067787117 ps
CPU time 17.1 seconds
Started Mar 07 01:44:54 PM PST 24
Finished Mar 07 01:45:12 PM PST 24
Peak memory 200164 kb
Host smart-8d7e8124-7031-46be-8341-c9e17364d72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913459534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3913459534
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1704483207
Short name T626
Test name
Test status
Simulation time 247589279 ps
CPU time 1.2 seconds
Started Mar 07 01:44:49 PM PST 24
Finished Mar 07 01:44:50 PM PST 24
Peak memory 197048 kb
Host smart-7e575931-e374-4607-bd92-4287c6f1c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704483207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1704483207
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.22027981
Short name T680
Test name
Test status
Simulation time 16794542903 ps
CPU time 7.99 seconds
Started Mar 07 01:44:54 PM PST 24
Finished Mar 07 01:45:04 PM PST 24
Peak memory 196984 kb
Host smart-9fe53f9f-75da-4144-add8-619bae788da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22027981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.22027981
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.195318087
Short name T935
Test name
Test status
Simulation time 85794583668 ps
CPU time 24.67 seconds
Started Mar 07 01:47:30 PM PST 24
Finished Mar 07 01:47:55 PM PST 24
Peak memory 199784 kb
Host smart-a821963f-5508-4488-9555-431153d35ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195318087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.195318087
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3568641294
Short name T911
Test name
Test status
Simulation time 32991374107 ps
CPU time 62.35 seconds
Started Mar 07 01:47:28 PM PST 24
Finished Mar 07 01:48:30 PM PST 24
Peak memory 200436 kb
Host smart-98f08363-656c-4ed3-82b2-f872029a1e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568641294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3568641294
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2804935295
Short name T180
Test name
Test status
Simulation time 154683700046 ps
CPU time 108.86 seconds
Started Mar 07 01:47:29 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 200400 kb
Host smart-09fa3216-473e-480a-b2f7-de78585d99dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804935295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2804935295
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.216773205
Short name T1031
Test name
Test status
Simulation time 26458723173 ps
CPU time 13.78 seconds
Started Mar 07 01:47:30 PM PST 24
Finished Mar 07 01:47:44 PM PST 24
Peak memory 200584 kb
Host smart-3460c540-3274-4a4d-8afb-242a9ddc7884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216773205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.216773205
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1315354481
Short name T298
Test name
Test status
Simulation time 99467566821 ps
CPU time 16.59 seconds
Started Mar 07 01:47:27 PM PST 24
Finished Mar 07 01:47:44 PM PST 24
Peak memory 200024 kb
Host smart-6ae03ca7-8f1f-44e7-b841-ad20e4cee4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315354481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1315354481
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1442411462
Short name T831
Test name
Test status
Simulation time 86491100093 ps
CPU time 36.72 seconds
Started Mar 07 01:47:29 PM PST 24
Finished Mar 07 01:48:05 PM PST 24
Peak memory 200072 kb
Host smart-85dc4a0b-4cd8-490c-be7d-b7daf4cf270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442411462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1442411462
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3396081850
Short name T1080
Test name
Test status
Simulation time 87553756267 ps
CPU time 74.3 seconds
Started Mar 07 01:47:36 PM PST 24
Finished Mar 07 01:48:51 PM PST 24
Peak memory 200588 kb
Host smart-e62243b1-065e-4b32-b1a0-ebd094c9a49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396081850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3396081850
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3126186043
Short name T472
Test name
Test status
Simulation time 12028219 ps
CPU time 0.55 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:44:47 PM PST 24
Peak memory 195968 kb
Host smart-cd7dd1fa-2567-4855-8ab1-cfd1576f81fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126186043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3126186043
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.518822444
Short name T337
Test name
Test status
Simulation time 33336170883 ps
CPU time 15.54 seconds
Started Mar 07 01:44:52 PM PST 24
Finished Mar 07 01:45:08 PM PST 24
Peak memory 200644 kb
Host smart-2b23ce27-448b-46d4-a7e5-d3e64a5aca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518822444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.518822444
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2479990871
Short name T577
Test name
Test status
Simulation time 51297501112 ps
CPU time 41.44 seconds
Started Mar 07 01:44:50 PM PST 24
Finished Mar 07 01:45:32 PM PST 24
Peak memory 199892 kb
Host smart-887df8a4-77e9-4654-87ff-676a9cd0da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479990871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2479990871
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2462215536
Short name T234
Test name
Test status
Simulation time 159989486502 ps
CPU time 34.7 seconds
Started Mar 07 01:44:50 PM PST 24
Finished Mar 07 01:45:25 PM PST 24
Peak memory 200468 kb
Host smart-2d33f9a9-520c-4fa9-957a-96eb17b149c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462215536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2462215536
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1221439848
Short name T578
Test name
Test status
Simulation time 131308195312 ps
CPU time 130.66 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:46:57 PM PST 24
Peak memory 200528 kb
Host smart-37adc008-8b32-4184-9e10-1337f1a3cc3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221439848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1221439848
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2754303358
Short name T768
Test name
Test status
Simulation time 105596476660 ps
CPU time 637.07 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:55:29 PM PST 24
Peak memory 200456 kb
Host smart-f580d136-3118-41dc-a451-2368ad8adadb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754303358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2754303358
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3751049994
Short name T721
Test name
Test status
Simulation time 4244516822 ps
CPU time 8.98 seconds
Started Mar 07 01:44:55 PM PST 24
Finished Mar 07 01:45:06 PM PST 24
Peak memory 198788 kb
Host smart-f1ba5df6-901c-4ee8-9e20-35d3fbcbaa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751049994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3751049994
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1202948512
Short name T867
Test name
Test status
Simulation time 209388686432 ps
CPU time 57.8 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:45:55 PM PST 24
Peak memory 198712 kb
Host smart-db5d32d2-7fe2-41aa-9391-7628fcb9a503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202948512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1202948512
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1939910671
Short name T774
Test name
Test status
Simulation time 10786149573 ps
CPU time 142.2 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:47:16 PM PST 24
Peak memory 200600 kb
Host smart-68a4e6da-52fd-40d1-879f-28d8c7306138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939910671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1939910671
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.87347247
Short name T705
Test name
Test status
Simulation time 6790199304 ps
CPU time 59.44 seconds
Started Mar 07 01:44:50 PM PST 24
Finished Mar 07 01:45:50 PM PST 24
Peak memory 198692 kb
Host smart-7268b99a-9c65-4437-8ce6-04249617b471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87347247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.87347247
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3831896753
Short name T268
Test name
Test status
Simulation time 95530189256 ps
CPU time 68.92 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:45:56 PM PST 24
Peak memory 200504 kb
Host smart-4c7ed2c8-607a-4865-acd3-8363b9481a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831896753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3831896753
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1807275281
Short name T1082
Test name
Test status
Simulation time 3853305159 ps
CPU time 3.65 seconds
Started Mar 07 01:44:55 PM PST 24
Finished Mar 07 01:45:00 PM PST 24
Peak memory 196360 kb
Host smart-54e2da85-f5dc-40ef-b46d-774412e115c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807275281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1807275281
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1359500783
Short name T1007
Test name
Test status
Simulation time 5767297248 ps
CPU time 7.76 seconds
Started Mar 07 01:44:42 PM PST 24
Finished Mar 07 01:44:50 PM PST 24
Peak memory 199724 kb
Host smart-7f7060f4-dadd-430a-b59b-8cf784fa7f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359500783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1359500783
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1298328377
Short name T104
Test name
Test status
Simulation time 498603063759 ps
CPU time 414.3 seconds
Started Mar 07 01:44:48 PM PST 24
Finished Mar 07 01:51:42 PM PST 24
Peak memory 208880 kb
Host smart-0690ce07-1cf4-4a35-b14f-ed63be67fc5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298328377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1298328377
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3711007479
Short name T41
Test name
Test status
Simulation time 7928437119 ps
CPU time 3.45 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:45:01 PM PST 24
Peak memory 199932 kb
Host smart-cbf41e91-f5a3-4956-8aaa-0dfbff284f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711007479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3711007479
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.315509103
Short name T947
Test name
Test status
Simulation time 94206458081 ps
CPU time 48.28 seconds
Started Mar 07 01:44:50 PM PST 24
Finished Mar 07 01:45:39 PM PST 24
Peak memory 200428 kb
Host smart-b74c3f74-2fcd-4cdb-b6f6-f3536fc6053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315509103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.315509103
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.970560318
Short name T665
Test name
Test status
Simulation time 154281836221 ps
CPU time 69.43 seconds
Started Mar 07 01:47:28 PM PST 24
Finished Mar 07 01:48:38 PM PST 24
Peak memory 200084 kb
Host smart-cbf30eee-fe5f-45bb-b114-b6baae77e49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970560318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.970560318
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3487661069
Short name T128
Test name
Test status
Simulation time 20817387531 ps
CPU time 15 seconds
Started Mar 07 01:47:30 PM PST 24
Finished Mar 07 01:47:46 PM PST 24
Peak memory 200272 kb
Host smart-fcacc39e-23a9-47e3-a22c-e06eeed3bb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487661069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3487661069
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3550486423
Short name T209
Test name
Test status
Simulation time 57392926860 ps
CPU time 45.54 seconds
Started Mar 07 01:47:34 PM PST 24
Finished Mar 07 01:48:20 PM PST 24
Peak memory 200036 kb
Host smart-f7b39252-76ac-4bd0-8d80-70678654bbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550486423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3550486423
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1889810218
Short name T483
Test name
Test status
Simulation time 79717451346 ps
CPU time 35.28 seconds
Started Mar 07 01:47:28 PM PST 24
Finished Mar 07 01:48:04 PM PST 24
Peak memory 200544 kb
Host smart-e7f53fc5-d87f-4b93-96c0-3f252a48520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889810218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1889810218
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2829289250
Short name T804
Test name
Test status
Simulation time 40427331205 ps
CPU time 55.44 seconds
Started Mar 07 01:47:36 PM PST 24
Finished Mar 07 01:48:32 PM PST 24
Peak memory 200552 kb
Host smart-2f0901da-3ee3-45f2-8dd7-a0bb8f7f7b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829289250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2829289250
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2802038532
Short name T817
Test name
Test status
Simulation time 199882138043 ps
CPU time 398.75 seconds
Started Mar 07 01:47:42 PM PST 24
Finished Mar 07 01:54:21 PM PST 24
Peak memory 200556 kb
Host smart-eb404562-db5f-4fe2-a3c3-7037ac64fccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802038532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2802038532
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4178748335
Short name T1089
Test name
Test status
Simulation time 34150532857 ps
CPU time 53.21 seconds
Started Mar 07 01:47:45 PM PST 24
Finished Mar 07 01:48:38 PM PST 24
Peak memory 200560 kb
Host smart-4be6276a-375a-47a1-b6e7-8bcb3b6f7929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178748335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4178748335
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1005947915
Short name T278
Test name
Test status
Simulation time 23666771266 ps
CPU time 39 seconds
Started Mar 07 01:47:41 PM PST 24
Finished Mar 07 01:48:20 PM PST 24
Peak memory 200584 kb
Host smart-de786adc-0182-4546-af6b-e905054a2d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005947915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1005947915
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.239437530
Short name T602
Test name
Test status
Simulation time 12694124 ps
CPU time 0.58 seconds
Started Mar 07 01:43:46 PM PST 24
Finished Mar 07 01:43:47 PM PST 24
Peak memory 195980 kb
Host smart-d8ece6c8-abf4-4085-ba71-0d646de8ec39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239437530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.239437530
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2450041499
Short name T308
Test name
Test status
Simulation time 156254881844 ps
CPU time 72.2 seconds
Started Mar 07 01:43:46 PM PST 24
Finished Mar 07 01:44:58 PM PST 24
Peak memory 200640 kb
Host smart-414aa476-335d-40e4-81bb-d426d4eaf7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450041499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2450041499
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.730869003
Short name T10
Test name
Test status
Simulation time 20694423412 ps
CPU time 18.48 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:44:08 PM PST 24
Peak memory 199480 kb
Host smart-4c64c444-61d5-4a1f-88f7-fb132b214576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730869003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.730869003
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1005751256
Short name T482
Test name
Test status
Simulation time 85731906652 ps
CPU time 744.61 seconds
Started Mar 07 01:43:50 PM PST 24
Finished Mar 07 01:56:14 PM PST 24
Peak memory 200436 kb
Host smart-94293475-88ac-4855-ae5a-de8abbeb3d1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1005751256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1005751256
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1760081916
Short name T1005
Test name
Test status
Simulation time 4550144548 ps
CPU time 6.63 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:43:56 PM PST 24
Peak memory 198920 kb
Host smart-89284135-6d5e-47b6-ad06-dd0eccef0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760081916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1760081916
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3051816437
Short name T925
Test name
Test status
Simulation time 35927399035 ps
CPU time 61.99 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:44:50 PM PST 24
Peak memory 198056 kb
Host smart-2f48ddde-8498-4508-9c1f-27c0c65e9087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051816437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3051816437
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2339934004
Short name T662
Test name
Test status
Simulation time 27987695594 ps
CPU time 1471.82 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 02:08:21 PM PST 24
Peak memory 200584 kb
Host smart-430c7cd4-da98-4a74-871d-5b88280bf6a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339934004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2339934004
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.4173216524
Short name T570
Test name
Test status
Simulation time 2039000285 ps
CPU time 2.82 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:43:51 PM PST 24
Peak memory 198736 kb
Host smart-e1a4e73f-1278-4f85-a19e-ee64e7b2297c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173216524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.4173216524
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1358826909
Short name T417
Test name
Test status
Simulation time 61343929500 ps
CPU time 24.62 seconds
Started Mar 07 01:43:47 PM PST 24
Finished Mar 07 01:44:12 PM PST 24
Peak memory 199676 kb
Host smart-2284fe2c-e7ba-41c3-9d99-f2485855495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358826909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1358826909
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2836102239
Short name T1102
Test name
Test status
Simulation time 1994720666 ps
CPU time 2.31 seconds
Started Mar 07 01:43:50 PM PST 24
Finished Mar 07 01:43:52 PM PST 24
Peak memory 195852 kb
Host smart-7e4d6e6f-b5ef-4f66-971b-f27aaa294707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836102239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2836102239
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.2871147448
Short name T847
Test name
Test status
Simulation time 116661626 ps
CPU time 0.96 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:43:46 PM PST 24
Peak memory 197252 kb
Host smart-d890d2ce-b780-497e-88d3-260ce1ffdf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871147448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2871147448
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2104601013
Short name T31
Test name
Test status
Simulation time 106920656047 ps
CPU time 254.16 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:47:59 PM PST 24
Peak memory 217428 kb
Host smart-0625f8df-4b47-48db-bc3e-f048d696a657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104601013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2104601013
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.4112991022
Short name T786
Test name
Test status
Simulation time 1305625889 ps
CPU time 2.75 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:43:51 PM PST 24
Peak memory 198940 kb
Host smart-1350b313-bde9-4263-ae8b-3811a26930a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112991022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.4112991022
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1161562908
Short name T659
Test name
Test status
Simulation time 36428770174 ps
CPU time 17.87 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:44:06 PM PST 24
Peak memory 198760 kb
Host smart-05c2e4ab-d0f6-41ea-810c-d9db51df01df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161562908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1161562908
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3834406053
Short name T27
Test name
Test status
Simulation time 13797552 ps
CPU time 0.6 seconds
Started Mar 07 01:44:54 PM PST 24
Finished Mar 07 01:44:56 PM PST 24
Peak memory 196004 kb
Host smart-6ab58ff6-f9a6-49ef-b158-ccb3eb255e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834406053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3834406053
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2725105883
Short name T1063
Test name
Test status
Simulation time 87906050113 ps
CPU time 71.9 seconds
Started Mar 07 01:44:45 PM PST 24
Finished Mar 07 01:45:57 PM PST 24
Peak memory 200572 kb
Host smart-c7b3768d-a42f-49c7-b4c4-9bdfe88e29fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725105883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2725105883
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3653970303
Short name T923
Test name
Test status
Simulation time 195785867619 ps
CPU time 157.24 seconds
Started Mar 07 01:44:52 PM PST 24
Finished Mar 07 01:47:31 PM PST 24
Peak memory 200616 kb
Host smart-452fc302-bd24-4fc8-bd9a-7e8b2a753858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653970303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3653970303
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.98968802
Short name T286
Test name
Test status
Simulation time 429489053043 ps
CPU time 90.98 seconds
Started Mar 07 01:44:57 PM PST 24
Finished Mar 07 01:46:28 PM PST 24
Peak memory 199916 kb
Host smart-70ac8c70-6102-4974-bca1-219bb31beb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98968802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.98968802
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3819977515
Short name T519
Test name
Test status
Simulation time 338098729056 ps
CPU time 133.34 seconds
Started Mar 07 01:44:55 PM PST 24
Finished Mar 07 01:47:10 PM PST 24
Peak memory 200560 kb
Host smart-36848ddb-d3a0-4f35-8cdd-704068fe5df6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819977515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3819977515
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2114953310
Short name T727
Test name
Test status
Simulation time 144568172282 ps
CPU time 740.79 seconds
Started Mar 07 01:44:51 PM PST 24
Finished Mar 07 01:57:13 PM PST 24
Peak memory 200304 kb
Host smart-c3ce93bb-9e12-407d-8978-59f89cbcb1f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114953310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2114953310
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1189730158
Short name T986
Test name
Test status
Simulation time 851630894 ps
CPU time 0.87 seconds
Started Mar 07 01:44:54 PM PST 24
Finished Mar 07 01:44:56 PM PST 24
Peak memory 195928 kb
Host smart-9b0e0ac8-9df6-4d31-a2ff-75e470216e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189730158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1189730158
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1833799759
Short name T890
Test name
Test status
Simulation time 40494760030 ps
CPU time 38.48 seconds
Started Mar 07 01:44:43 PM PST 24
Finished Mar 07 01:45:22 PM PST 24
Peak memory 200608 kb
Host smart-29c9a439-0fa8-4048-bd32-05674c1aa0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833799759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1833799759
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.658992099
Short name T691
Test name
Test status
Simulation time 21850573610 ps
CPU time 159.4 seconds
Started Mar 07 01:44:47 PM PST 24
Finished Mar 07 01:47:27 PM PST 24
Peak memory 200592 kb
Host smart-448e8cce-cb29-4e86-bda3-6d1d79944949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658992099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.658992099
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3123982593
Short name T930
Test name
Test status
Simulation time 7297361815 ps
CPU time 33.75 seconds
Started Mar 07 01:44:55 PM PST 24
Finished Mar 07 01:45:30 PM PST 24
Peak memory 199524 kb
Host smart-b36685a6-1dff-45a2-8e56-4cffdd2e0dd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123982593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3123982593
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1302903149
Short name T822
Test name
Test status
Simulation time 64925495345 ps
CPU time 27.3 seconds
Started Mar 07 01:44:44 PM PST 24
Finished Mar 07 01:45:12 PM PST 24
Peak memory 199376 kb
Host smart-49e860a3-bd99-4acc-acfa-79b4218a4723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302903149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1302903149
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.74535367
Short name T945
Test name
Test status
Simulation time 6305439142 ps
CPU time 3.01 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:45:00 PM PST 24
Peak memory 196376 kb
Host smart-75d563ab-e67f-4965-a0f7-c3e5dfd6e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74535367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.74535367
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.902155435
Short name T557
Test name
Test status
Simulation time 293721140 ps
CPU time 1.83 seconds
Started Mar 07 01:44:45 PM PST 24
Finished Mar 07 01:44:47 PM PST 24
Peak memory 199952 kb
Host smart-419d2a15-ec31-4f48-be45-8459a3675dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902155435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.902155435
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3459818203
Short name T361
Test name
Test status
Simulation time 506179141967 ps
CPU time 312.93 seconds
Started Mar 07 01:44:55 PM PST 24
Finished Mar 07 01:50:10 PM PST 24
Peak memory 200596 kb
Host smart-aa4c6a6f-9156-437a-b4df-a72fbe71a88f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459818203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3459818203
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3049942164
Short name T1002
Test name
Test status
Simulation time 1987078720 ps
CPU time 1.95 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:44:58 PM PST 24
Peak memory 198880 kb
Host smart-239cc25c-e9f9-48b1-b977-bf7390a50125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049942164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3049942164
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2581812396
Short name T439
Test name
Test status
Simulation time 68465109312 ps
CPU time 105.13 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:46:42 PM PST 24
Peak memory 200560 kb
Host smart-5562e90a-1533-45fb-a2d3-1be14e7e008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581812396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2581812396
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.344913458
Short name T825
Test name
Test status
Simulation time 120059306749 ps
CPU time 44.18 seconds
Started Mar 07 01:47:41 PM PST 24
Finished Mar 07 01:48:25 PM PST 24
Peak memory 200556 kb
Host smart-66ac756f-4254-4e12-b5d2-5835618aa60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344913458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.344913458
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2919570249
Short name T199
Test name
Test status
Simulation time 380226766513 ps
CPU time 37.15 seconds
Started Mar 07 01:47:39 PM PST 24
Finished Mar 07 01:48:17 PM PST 24
Peak memory 199796 kb
Host smart-94aeac85-1b48-4b51-b056-f4b5f49572a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919570249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2919570249
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1322118131
Short name T941
Test name
Test status
Simulation time 159546210653 ps
CPU time 27.44 seconds
Started Mar 07 01:47:41 PM PST 24
Finished Mar 07 01:48:08 PM PST 24
Peak memory 200432 kb
Host smart-4aa1baad-f520-40de-a2c8-06e7040a93f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322118131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1322118131
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.573944836
Short name T362
Test name
Test status
Simulation time 167248334867 ps
CPU time 83.14 seconds
Started Mar 07 01:47:40 PM PST 24
Finished Mar 07 01:49:04 PM PST 24
Peak memory 199976 kb
Host smart-ab32307a-2265-419d-8098-8870ec89832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573944836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.573944836
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.770279005
Short name T1043
Test name
Test status
Simulation time 37225046238 ps
CPU time 17.76 seconds
Started Mar 07 01:47:40 PM PST 24
Finished Mar 07 01:47:58 PM PST 24
Peak memory 200328 kb
Host smart-fd088455-77da-4199-b36b-f14efcd729d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770279005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.770279005
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3301445876
Short name T888
Test name
Test status
Simulation time 102262301461 ps
CPU time 76.49 seconds
Started Mar 07 01:47:48 PM PST 24
Finished Mar 07 01:49:05 PM PST 24
Peak memory 200464 kb
Host smart-620ca5c6-70b5-451e-a748-c9a6a282a1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301445876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3301445876
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1750133491
Short name T194
Test name
Test status
Simulation time 29477660593 ps
CPU time 13.41 seconds
Started Mar 07 01:47:45 PM PST 24
Finished Mar 07 01:48:00 PM PST 24
Peak memory 200076 kb
Host smart-da2002f5-6189-457c-ad4d-68b0fb381406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750133491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1750133491
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.757493151
Short name T238
Test name
Test status
Simulation time 62560722172 ps
CPU time 49.44 seconds
Started Mar 07 01:47:42 PM PST 24
Finished Mar 07 01:48:32 PM PST 24
Peak memory 200544 kb
Host smart-3f1b6545-89c2-440d-a5f8-c8421767a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757493151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.757493151
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1408435367
Short name T585
Test name
Test status
Simulation time 149517302191 ps
CPU time 31.52 seconds
Started Mar 07 01:47:49 PM PST 24
Finished Mar 07 01:48:21 PM PST 24
Peak memory 200576 kb
Host smart-233d0961-e0b2-4071-ba2b-32ea892c79ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408435367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1408435367
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4076956421
Short name T676
Test name
Test status
Simulation time 24955210 ps
CPU time 0.56 seconds
Started Mar 07 01:45:00 PM PST 24
Finished Mar 07 01:45:01 PM PST 24
Peak memory 195916 kb
Host smart-69e39d95-6336-44b4-8098-18e99022f915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076956421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4076956421
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3514279273
Short name T170
Test name
Test status
Simulation time 134485891770 ps
CPU time 199.85 seconds
Started Mar 07 01:44:57 PM PST 24
Finished Mar 07 01:48:17 PM PST 24
Peak memory 200528 kb
Host smart-d6fe98bf-ed3a-42d1-99cb-0d1901c2d4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514279273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3514279273
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3747973090
Short name T880
Test name
Test status
Simulation time 63776308201 ps
CPU time 94.83 seconds
Started Mar 07 01:44:54 PM PST 24
Finished Mar 07 01:46:30 PM PST 24
Peak memory 199980 kb
Host smart-31816911-284f-47ec-a570-64025c77b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747973090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3747973090
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.662863262
Short name T887
Test name
Test status
Simulation time 120038698214 ps
CPU time 32.92 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:45:30 PM PST 24
Peak memory 200600 kb
Host smart-5f514472-3f13-4845-9f3d-9f35816a4ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662863262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.662863262
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2895625020
Short name T789
Test name
Test status
Simulation time 122608885241 ps
CPU time 356.83 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:50:54 PM PST 24
Peak memory 200524 kb
Host smart-b4da4460-09b8-4839-ba3e-d338b925cb0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895625020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2895625020
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1448973774
Short name T554
Test name
Test status
Simulation time 3486771768 ps
CPU time 3.95 seconds
Started Mar 07 01:44:55 PM PST 24
Finished Mar 07 01:45:01 PM PST 24
Peak memory 199060 kb
Host smart-8df59851-0512-4981-adaa-f2bfda92ebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448973774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1448973774
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3778353406
Short name T932
Test name
Test status
Simulation time 131615044702 ps
CPU time 139.82 seconds
Started Mar 07 01:44:57 PM PST 24
Finished Mar 07 01:47:17 PM PST 24
Peak memory 208868 kb
Host smart-7052284e-1e7f-4a9d-a8ce-1fbd394ff485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778353406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3778353406
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.627505987
Short name T649
Test name
Test status
Simulation time 5656648679 ps
CPU time 324.96 seconds
Started Mar 07 01:44:52 PM PST 24
Finished Mar 07 01:50:18 PM PST 24
Peak memory 199920 kb
Host smart-4c237f93-5a2a-42f7-bfa6-26b2ac7669e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627505987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.627505987
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3382279450
Short name T672
Test name
Test status
Simulation time 4135969624 ps
CPU time 8.56 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:45:03 PM PST 24
Peak memory 199204 kb
Host smart-b9629613-bec1-49be-aa46-6b0776391902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382279450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3382279450
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1290991448
Short name T388
Test name
Test status
Simulation time 18776484413 ps
CPU time 16.24 seconds
Started Mar 07 01:44:55 PM PST 24
Finished Mar 07 01:45:13 PM PST 24
Peak memory 199320 kb
Host smart-72f8523c-be40-433e-9bf9-8586cd654bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290991448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1290991448
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1416406167
Short name T410
Test name
Test status
Simulation time 33241999563 ps
CPU time 11.08 seconds
Started Mar 07 01:44:53 PM PST 24
Finished Mar 07 01:45:05 PM PST 24
Peak memory 196340 kb
Host smart-d4d4cad8-5e45-4264-bd68-0fe046eb0e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416406167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1416406167
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1872797863
Short name T830
Test name
Test status
Simulation time 533388027 ps
CPU time 1.31 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:44:58 PM PST 24
Peak memory 198472 kb
Host smart-887456b3-9f23-4a00-9212-84d7d9e3e396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872797863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1872797863
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.249517850
Short name T101
Test name
Test status
Simulation time 18965753578 ps
CPU time 161.2 seconds
Started Mar 07 01:44:56 PM PST 24
Finished Mar 07 01:47:38 PM PST 24
Peak memory 209124 kb
Host smart-b9906f26-4c0e-41e9-b74a-d04a065bcb8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249517850 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.249517850
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3741556258
Short name T531
Test name
Test status
Simulation time 955301701 ps
CPU time 1.85 seconds
Started Mar 07 01:44:52 PM PST 24
Finished Mar 07 01:44:55 PM PST 24
Peak memory 198844 kb
Host smart-4ea0d353-d3a5-4d7a-a33b-6ae55adb574c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741556258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3741556258
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3525635871
Short name T773
Test name
Test status
Simulation time 20528444871 ps
CPU time 31.79 seconds
Started Mar 07 01:44:55 PM PST 24
Finished Mar 07 01:45:29 PM PST 24
Peak memory 200548 kb
Host smart-7c8bfcd5-9fec-430b-b59c-77944e70ae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525635871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3525635871
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.4060352184
Short name T143
Test name
Test status
Simulation time 152701948725 ps
CPU time 241.73 seconds
Started Mar 07 01:47:40 PM PST 24
Finished Mar 07 01:51:42 PM PST 24
Peak memory 199976 kb
Host smart-cbf67a37-23be-43e4-8e44-b812a88b8f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060352184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4060352184
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.795418769
Short name T306
Test name
Test status
Simulation time 41248084881 ps
CPU time 30.91 seconds
Started Mar 07 01:47:40 PM PST 24
Finished Mar 07 01:48:11 PM PST 24
Peak memory 200060 kb
Host smart-68385259-481a-436f-90bb-74c8ac350741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795418769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.795418769
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.244713118
Short name T920
Test name
Test status
Simulation time 61557851021 ps
CPU time 26.55 seconds
Started Mar 07 01:47:45 PM PST 24
Finished Mar 07 01:48:12 PM PST 24
Peak memory 198992 kb
Host smart-f35ad714-77ad-4d09-a944-29f5576c3015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244713118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.244713118
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2354112383
Short name T217
Test name
Test status
Simulation time 6770590310 ps
CPU time 14.98 seconds
Started Mar 07 01:47:39 PM PST 24
Finished Mar 07 01:47:54 PM PST 24
Peak memory 200596 kb
Host smart-b72ea340-f783-447c-9879-516f400e080d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354112383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2354112383
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1378103022
Short name T914
Test name
Test status
Simulation time 35433584530 ps
CPU time 14.34 seconds
Started Mar 07 01:47:40 PM PST 24
Finished Mar 07 01:47:54 PM PST 24
Peak memory 200368 kb
Host smart-e812addd-0aef-404e-9d6f-119146552a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378103022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1378103022
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.771716914
Short name T247
Test name
Test status
Simulation time 25302116259 ps
CPU time 26.55 seconds
Started Mar 07 01:47:51 PM PST 24
Finished Mar 07 01:48:17 PM PST 24
Peak memory 200544 kb
Host smart-a898b627-de35-43eb-bca9-04505358ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771716914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.771716914
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1680020144
Short name T620
Test name
Test status
Simulation time 131748369717 ps
CPU time 26.22 seconds
Started Mar 07 01:47:50 PM PST 24
Finished Mar 07 01:48:16 PM PST 24
Peak memory 200320 kb
Host smart-ba5e7e38-320e-45a1-a62b-4826ba9258c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680020144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1680020144
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2935129546
Short name T302
Test name
Test status
Simulation time 77226985014 ps
CPU time 60.11 seconds
Started Mar 07 01:47:50 PM PST 24
Finished Mar 07 01:48:50 PM PST 24
Peak memory 200472 kb
Host smart-5002bde1-3b26-4cc4-ab6f-f82f37dbfec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935129546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2935129546
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1126268938
Short name T961
Test name
Test status
Simulation time 20053519 ps
CPU time 0.53 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:02 PM PST 24
Peak memory 195792 kb
Host smart-41f4c7d2-eb79-467b-bf84-644359284503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126268938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1126268938
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.488816916
Short name T441
Test name
Test status
Simulation time 69582761101 ps
CPU time 124.73 seconds
Started Mar 07 01:45:02 PM PST 24
Finished Mar 07 01:47:07 PM PST 24
Peak memory 200524 kb
Host smart-b5082480-a2f8-42da-b23d-f5f24be141fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488816916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.488816916
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1341985744
Short name T741
Test name
Test status
Simulation time 37556975014 ps
CPU time 67.69 seconds
Started Mar 07 01:45:02 PM PST 24
Finished Mar 07 01:46:10 PM PST 24
Peak memory 200156 kb
Host smart-73ddb8ee-0728-4a32-8b32-6d817a8d620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341985744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1341985744
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2593991689
Short name T240
Test name
Test status
Simulation time 101827761918 ps
CPU time 155.57 seconds
Started Mar 07 01:44:59 PM PST 24
Finished Mar 07 01:47:35 PM PST 24
Peak memory 200600 kb
Host smart-732871cb-32cf-4c8a-a6ba-6fee6dc22c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593991689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2593991689
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2551862717
Short name T837
Test name
Test status
Simulation time 107883235509 ps
CPU time 46.22 seconds
Started Mar 07 01:45:05 PM PST 24
Finished Mar 07 01:45:51 PM PST 24
Peak memory 199928 kb
Host smart-6d8b5626-3800-49d1-b23e-3d6dfd74413b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551862717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2551862717
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3214366334
Short name T903
Test name
Test status
Simulation time 57947826375 ps
CPU time 100 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:46:41 PM PST 24
Peak memory 200540 kb
Host smart-5130a93e-9d3c-449b-812d-e69ae8b955ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214366334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3214366334
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.143879468
Short name T462
Test name
Test status
Simulation time 10812990135 ps
CPU time 21.35 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:22 PM PST 24
Peak memory 199748 kb
Host smart-2c8d5e0b-445d-48bb-a7da-59c7b8a9e4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143879468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.143879468
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1936961983
Short name T742
Test name
Test status
Simulation time 98484169792 ps
CPU time 35.2 seconds
Started Mar 07 01:45:03 PM PST 24
Finished Mar 07 01:45:38 PM PST 24
Peak memory 198416 kb
Host smart-b158b32e-4a38-4bcc-8dd2-de9f67095fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936961983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1936961983
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3893543696
Short name T400
Test name
Test status
Simulation time 21445063285 ps
CPU time 996.71 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 02:01:38 PM PST 24
Peak memory 200540 kb
Host smart-fde6405b-fe2f-4926-921d-bf319f299637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893543696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3893543696
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2937518730
Short name T492
Test name
Test status
Simulation time 2231394140 ps
CPU time 4.33 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:05 PM PST 24
Peak memory 198760 kb
Host smart-f3551458-887d-457c-aad1-d02c68d8107f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937518730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2937518730
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2397163598
Short name T370
Test name
Test status
Simulation time 33421114089 ps
CPU time 9.22 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:11 PM PST 24
Peak memory 200512 kb
Host smart-37e4dafd-8b12-4973-a910-fed908e13394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397163598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2397163598
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3028713177
Short name T480
Test name
Test status
Simulation time 7064897948 ps
CPU time 6.43 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:08 PM PST 24
Peak memory 196348 kb
Host smart-88e75e8a-dc2a-45ab-b900-32ade05273cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028713177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3028713177
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.34028201
Short name T424
Test name
Test status
Simulation time 720753025 ps
CPU time 1.74 seconds
Started Mar 07 01:44:58 PM PST 24
Finished Mar 07 01:45:00 PM PST 24
Peak memory 198916 kb
Host smart-30a4324e-db04-421c-acdb-d054be6c1de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34028201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.34028201
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4197750649
Short name T106
Test name
Test status
Simulation time 226241791412 ps
CPU time 348.35 seconds
Started Mar 07 01:45:00 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 200540 kb
Host smart-5013aaa9-1cb2-406c-81aa-5ca247d9045d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197750649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4197750649
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3735633328
Short name T995
Test name
Test status
Simulation time 23639199301 ps
CPU time 303.58 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:50:05 PM PST 24
Peak memory 209024 kb
Host smart-ce4903ff-92c5-45ef-ac04-49472275624a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735633328 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3735633328
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4132548614
Short name T635
Test name
Test status
Simulation time 2224579627 ps
CPU time 2.47 seconds
Started Mar 07 01:45:03 PM PST 24
Finished Mar 07 01:45:05 PM PST 24
Peak memory 199532 kb
Host smart-e3e70ead-625a-4567-9df9-5d7b0f5fb053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132548614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4132548614
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4198733975
Short name T134
Test name
Test status
Simulation time 57092218718 ps
CPU time 20.37 seconds
Started Mar 07 01:45:00 PM PST 24
Finished Mar 07 01:45:21 PM PST 24
Peak memory 200648 kb
Host smart-6df462cb-9a3c-4074-a825-5ea52aba4ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198733975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4198733975
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.189481729
Short name T820
Test name
Test status
Simulation time 109343404760 ps
CPU time 34.36 seconds
Started Mar 07 01:47:50 PM PST 24
Finished Mar 07 01:48:25 PM PST 24
Peak memory 200660 kb
Host smart-e14ff3a3-0b11-49c9-8d19-19cf68e3302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189481729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.189481729
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3386015391
Short name T309
Test name
Test status
Simulation time 29781363996 ps
CPU time 48.49 seconds
Started Mar 07 01:47:52 PM PST 24
Finished Mar 07 01:48:41 PM PST 24
Peak memory 200492 kb
Host smart-a9c38f65-f15d-4b57-8bdf-fae4da994bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386015391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3386015391
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1366164026
Short name T929
Test name
Test status
Simulation time 28710133771 ps
CPU time 12.6 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:48:06 PM PST 24
Peak memory 200472 kb
Host smart-f070da3c-c8f3-43dc-8f0a-b6631e4fb922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366164026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1366164026
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2699925440
Short name T805
Test name
Test status
Simulation time 66476219302 ps
CPU time 48.91 seconds
Started Mar 07 01:47:51 PM PST 24
Finished Mar 07 01:48:40 PM PST 24
Peak memory 200532 kb
Host smart-cd926948-79f0-42dc-bc39-4a1f7788f3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699925440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2699925440
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3818522573
Short name T183
Test name
Test status
Simulation time 84785539902 ps
CPU time 85.32 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 200536 kb
Host smart-0627dc17-4dcb-46b3-8aa7-c9b094034b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818522573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3818522573
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1470400758
Short name T252
Test name
Test status
Simulation time 33103747279 ps
CPU time 56.96 seconds
Started Mar 07 01:47:51 PM PST 24
Finished Mar 07 01:48:48 PM PST 24
Peak memory 200500 kb
Host smart-fdaf6109-f288-479a-b07f-06aa7985d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470400758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1470400758
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.4112981105
Short name T479
Test name
Test status
Simulation time 17686262 ps
CPU time 0.57 seconds
Started Mar 07 01:45:06 PM PST 24
Finished Mar 07 01:45:06 PM PST 24
Peak memory 195992 kb
Host smart-c943021e-ca2a-421b-916c-5a08cd9d7cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112981105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.4112981105
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2584731893
Short name T505
Test name
Test status
Simulation time 77076514236 ps
CPU time 37.02 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:39 PM PST 24
Peak memory 200580 kb
Host smart-94eaaae3-f80e-4e60-8853-3bc43a69ed46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584731893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2584731893
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.561385595
Short name T639
Test name
Test status
Simulation time 6432658499 ps
CPU time 10.07 seconds
Started Mar 07 01:45:03 PM PST 24
Finished Mar 07 01:45:13 PM PST 24
Peak memory 199552 kb
Host smart-d0d70c76-dcba-40b1-b435-bef8b816c6fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561385595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.561385595
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.224168366
Short name T998
Test name
Test status
Simulation time 63579566842 ps
CPU time 58.74 seconds
Started Mar 07 01:45:03 PM PST 24
Finished Mar 07 01:46:02 PM PST 24
Peak memory 200540 kb
Host smart-57efb7ea-a78e-47e1-9e75-0ac9d092c2b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224168366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.224168366
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3134736199
Short name T1021
Test name
Test status
Simulation time 7995332067 ps
CPU time 17.74 seconds
Started Mar 07 01:45:03 PM PST 24
Finished Mar 07 01:45:21 PM PST 24
Peak memory 199772 kb
Host smart-2dfe2972-a775-4669-b2c0-06e0dc598885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134736199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3134736199
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1541110545
Short name T142
Test name
Test status
Simulation time 97773418191 ps
CPU time 65.36 seconds
Started Mar 07 01:45:08 PM PST 24
Finished Mar 07 01:46:14 PM PST 24
Peak memory 208928 kb
Host smart-621e9269-91ae-4a6c-b05d-bc69ce007fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541110545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1541110545
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2722608543
Short name T671
Test name
Test status
Simulation time 11700530959 ps
CPU time 166.44 seconds
Started Mar 07 01:45:02 PM PST 24
Finished Mar 07 01:47:48 PM PST 24
Peak memory 200508 kb
Host smart-74ea9952-9975-405f-b0c1-772d47ac3719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722608543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2722608543
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.518357532
Short name T1051
Test name
Test status
Simulation time 3922508806 ps
CPU time 13.17 seconds
Started Mar 07 01:45:03 PM PST 24
Finished Mar 07 01:45:16 PM PST 24
Peak memory 198464 kb
Host smart-5963e65e-0b29-4960-9ba3-fb467829e178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518357532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.518357532
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1537837253
Short name T214
Test name
Test status
Simulation time 216672192472 ps
CPU time 32.15 seconds
Started Mar 07 01:45:03 PM PST 24
Finished Mar 07 01:45:35 PM PST 24
Peak memory 199448 kb
Host smart-28484558-8a98-4d92-868e-1b0e1d1d1cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537837253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1537837253
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2530781775
Short name T512
Test name
Test status
Simulation time 3135903377 ps
CPU time 1.69 seconds
Started Mar 07 01:45:04 PM PST 24
Finished Mar 07 01:45:06 PM PST 24
Peak memory 196248 kb
Host smart-8e3ade72-f599-4042-92f8-a348cc17e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530781775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2530781775
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4149964722
Short name T613
Test name
Test status
Simulation time 934656103 ps
CPU time 1.37 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:03 PM PST 24
Peak memory 199368 kb
Host smart-91040075-5a12-4570-8d4d-ec5e69927525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149964722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4149964722
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2407731577
Short name T983
Test name
Test status
Simulation time 6545979656 ps
CPU time 20.08 seconds
Started Mar 07 01:45:05 PM PST 24
Finished Mar 07 01:45:25 PM PST 24
Peak memory 199984 kb
Host smart-cf0e154e-7af7-4084-b475-bc2ff9ec5a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407731577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2407731577
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.471576734
Short name T881
Test name
Test status
Simulation time 100089212658 ps
CPU time 116.69 seconds
Started Mar 07 01:45:07 PM PST 24
Finished Mar 07 01:47:03 PM PST 24
Peak memory 200660 kb
Host smart-ca0aeea1-1791-4dba-ad00-600524634151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471576734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.471576734
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2413540635
Short name T1060
Test name
Test status
Simulation time 21995277711 ps
CPU time 35.75 seconds
Started Mar 07 01:47:52 PM PST 24
Finished Mar 07 01:48:28 PM PST 24
Peak memory 200100 kb
Host smart-46cbb729-b189-4aa7-a552-ef939f7eb2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413540635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2413540635
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.466066724
Short name T994
Test name
Test status
Simulation time 22159533224 ps
CPU time 35.26 seconds
Started Mar 07 01:47:54 PM PST 24
Finished Mar 07 01:48:29 PM PST 24
Peak memory 200192 kb
Host smart-9e2e7cde-68a4-4602-9365-aa81266f0fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466066724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.466066724
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2169631271
Short name T22
Test name
Test status
Simulation time 41240648344 ps
CPU time 21.03 seconds
Started Mar 07 01:47:54 PM PST 24
Finished Mar 07 01:48:15 PM PST 24
Peak memory 200440 kb
Host smart-20972491-f604-41ee-aae4-74be965efa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169631271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2169631271
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1380908245
Short name T1103
Test name
Test status
Simulation time 25563242669 ps
CPU time 12.36 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:48:05 PM PST 24
Peak memory 200424 kb
Host smart-891ac046-187b-45a8-90af-f10e8d3c012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380908245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1380908245
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2130576797
Short name T330
Test name
Test status
Simulation time 49647109334 ps
CPU time 43.69 seconds
Started Mar 07 01:47:52 PM PST 24
Finished Mar 07 01:48:36 PM PST 24
Peak memory 200512 kb
Host smart-f5e8e95f-f5f5-4bc7-ae0f-974d1ff0ff4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130576797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2130576797
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.659443838
Short name T381
Test name
Test status
Simulation time 18795570407 ps
CPU time 29.32 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 200508 kb
Host smart-f7e02c69-8413-4a8a-b9bc-56ff0baf1f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659443838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.659443838
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3622087522
Short name T1070
Test name
Test status
Simulation time 59651432149 ps
CPU time 16.01 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:48:09 PM PST 24
Peak memory 200560 kb
Host smart-eecf520f-b184-4f0f-815c-6a1cc9e3f8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622087522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3622087522
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4222020726
Short name T844
Test name
Test status
Simulation time 20897649959 ps
CPU time 11.56 seconds
Started Mar 07 01:47:52 PM PST 24
Finished Mar 07 01:48:04 PM PST 24
Peak memory 200248 kb
Host smart-84b649d6-5dd8-4b52-904a-87ed8454aced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222020726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4222020726
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3141447639
Short name T769
Test name
Test status
Simulation time 13556561 ps
CPU time 0.56 seconds
Started Mar 07 01:45:09 PM PST 24
Finished Mar 07 01:45:10 PM PST 24
Peak memory 195960 kb
Host smart-53c600cb-5630-4008-adcb-9a693332e439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141447639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3141447639
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.92279032
Short name T394
Test name
Test status
Simulation time 26871899586 ps
CPU time 26.42 seconds
Started Mar 07 01:45:08 PM PST 24
Finished Mar 07 01:45:36 PM PST 24
Peak memory 200520 kb
Host smart-bdd1135b-6488-436c-8838-1abcb36d17da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92279032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.92279032
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.736087268
Short name T348
Test name
Test status
Simulation time 201800539363 ps
CPU time 36.86 seconds
Started Mar 07 01:45:05 PM PST 24
Finished Mar 07 01:45:42 PM PST 24
Peak memory 199852 kb
Host smart-e6978317-85b7-4184-bd9d-fde194dc1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736087268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.736087268
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1207716145
Short name T485
Test name
Test status
Simulation time 88897213441 ps
CPU time 145.67 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:47:36 PM PST 24
Peak memory 200612 kb
Host smart-e9c73997-c0d9-4a36-ab64-5430416066a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207716145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1207716145
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3895496481
Short name T1101
Test name
Test status
Simulation time 4612106280 ps
CPU time 2.66 seconds
Started Mar 07 01:45:09 PM PST 24
Finished Mar 07 01:45:12 PM PST 24
Peak memory 197572 kb
Host smart-fed9d777-847f-4931-a56c-fac3e5d9cafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895496481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3895496481
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3098678880
Short name T1055
Test name
Test status
Simulation time 77027140614 ps
CPU time 134.98 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:47:25 PM PST 24
Peak memory 199908 kb
Host smart-123d88d7-eaaf-425e-8ac4-1a82d9f8f96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098678880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3098678880
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3391122600
Short name T393
Test name
Test status
Simulation time 9431466542 ps
CPU time 526.12 seconds
Started Mar 07 01:45:08 PM PST 24
Finished Mar 07 01:53:55 PM PST 24
Peak memory 200544 kb
Host smart-a462a62b-807b-49c6-9b67-5bd2e847c8ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391122600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3391122600
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1522255548
Short name T488
Test name
Test status
Simulation time 5810629137 ps
CPU time 14.49 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:45:24 PM PST 24
Peak memory 199408 kb
Host smart-149c3dcf-af13-4d0e-bd40-51d778001465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522255548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1522255548
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2770303184
Short name T182
Test name
Test status
Simulation time 42052181270 ps
CPU time 56.08 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:46:06 PM PST 24
Peak memory 199656 kb
Host smart-e6f84c65-9df7-40f1-a2e8-02c5a110bcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770303184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2770303184
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.570841444
Short name T1027
Test name
Test status
Simulation time 2732518452 ps
CPU time 5.14 seconds
Started Mar 07 01:45:07 PM PST 24
Finished Mar 07 01:45:13 PM PST 24
Peak memory 196024 kb
Host smart-6247a0c3-ce5d-480a-bb5f-ca8d2f89ae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570841444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.570841444
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.4265350623
Short name T884
Test name
Test status
Simulation time 5490253361 ps
CPU time 7.77 seconds
Started Mar 07 01:45:05 PM PST 24
Finished Mar 07 01:45:13 PM PST 24
Peak memory 199976 kb
Host smart-bbc2880b-eecd-4313-bddd-1266994d9723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265350623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.4265350623
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3136497951
Short name T481
Test name
Test status
Simulation time 926717684 ps
CPU time 1.37 seconds
Started Mar 07 01:45:09 PM PST 24
Finished Mar 07 01:45:11 PM PST 24
Peak memory 198748 kb
Host smart-658ea638-0329-4bf5-9890-3b3e5aca7310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136497951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3136497951
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2044390411
Short name T606
Test name
Test status
Simulation time 34984304339 ps
CPU time 55.48 seconds
Started Mar 07 01:45:01 PM PST 24
Finished Mar 07 01:45:57 PM PST 24
Peak memory 200592 kb
Host smart-1ae4d16c-f76a-4584-a757-56d0d0e81ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044390411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2044390411
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.639748669
Short name T47
Test name
Test status
Simulation time 29100819810 ps
CPU time 56.15 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:48:49 PM PST 24
Peak memory 200568 kb
Host smart-55fa23a5-e4dc-444a-9b53-4282c6647726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639748669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.639748669
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3917908006
Short name T129
Test name
Test status
Simulation time 93692908084 ps
CPU time 43.15 seconds
Started Mar 07 01:47:54 PM PST 24
Finished Mar 07 01:48:37 PM PST 24
Peak memory 200608 kb
Host smart-24ce0a3c-3f4c-4eec-ac9b-c6ac909a20a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917908006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3917908006
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1850203609
Short name T189
Test name
Test status
Simulation time 138254270383 ps
CPU time 200.43 seconds
Started Mar 07 01:47:53 PM PST 24
Finished Mar 07 01:51:14 PM PST 24
Peak memory 200584 kb
Host smart-2343e39c-8255-4c11-ae22-d75468b4cfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850203609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1850203609
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4069607892
Short name T631
Test name
Test status
Simulation time 61455856360 ps
CPU time 28.98 seconds
Started Mar 07 01:47:56 PM PST 24
Finished Mar 07 01:48:25 PM PST 24
Peak memory 200444 kb
Host smart-af0f9ad4-13e1-445f-8138-0550469c5e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069607892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4069607892
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1922375563
Short name T283
Test name
Test status
Simulation time 7095548928 ps
CPU time 12.66 seconds
Started Mar 07 01:48:00 PM PST 24
Finished Mar 07 01:48:13 PM PST 24
Peak memory 199656 kb
Host smart-961b589d-c39d-4b0d-b349-71a63ada13d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922375563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1922375563
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.922077495
Short name T135
Test name
Test status
Simulation time 45387136585 ps
CPU time 38.43 seconds
Started Mar 07 01:47:59 PM PST 24
Finished Mar 07 01:48:38 PM PST 24
Peak memory 200592 kb
Host smart-7b48cf6f-a906-451a-a14e-dd36fddd4c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922077495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.922077495
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.653618733
Short name T1062
Test name
Test status
Simulation time 98693121115 ps
CPU time 40.76 seconds
Started Mar 07 01:48:01 PM PST 24
Finished Mar 07 01:48:42 PM PST 24
Peak memory 200516 kb
Host smart-a65d27fe-20e5-4073-9650-c8b152a78f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653618733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.653618733
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2401572828
Short name T294
Test name
Test status
Simulation time 143663464674 ps
CPU time 59.16 seconds
Started Mar 07 01:47:58 PM PST 24
Finished Mar 07 01:48:58 PM PST 24
Peak memory 200560 kb
Host smart-b100f25f-9d40-4b2b-ac40-bc5992ea87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401572828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2401572828
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2269941603
Short name T403
Test name
Test status
Simulation time 35123073217 ps
CPU time 34.15 seconds
Started Mar 07 01:48:00 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 199756 kb
Host smart-6b2e6965-84ce-4a94-bfa8-a23cb4b70568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269941603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2269941603
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2595855297
Short name T25
Test name
Test status
Simulation time 34910392 ps
CPU time 0.55 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:45:11 PM PST 24
Peak memory 194896 kb
Host smart-86d70a3a-6f4b-47df-bbf9-40ed1b55bc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595855297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2595855297
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4179004608
Short name T991
Test name
Test status
Simulation time 119684707092 ps
CPU time 177.45 seconds
Started Mar 07 01:45:15 PM PST 24
Finished Mar 07 01:48:12 PM PST 24
Peak memory 200532 kb
Host smart-0f69b9f0-04d5-4d24-8f2e-925312cf5288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179004608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4179004608
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2027395023
Short name T507
Test name
Test status
Simulation time 554388402981 ps
CPU time 79.52 seconds
Started Mar 07 01:45:12 PM PST 24
Finished Mar 07 01:46:32 PM PST 24
Peak memory 200084 kb
Host smart-f5d40630-4a26-4628-a9c8-16aa87398597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027395023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2027395023
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.2213226055
Short name T1099
Test name
Test status
Simulation time 34871915132 ps
CPU time 19.99 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:45:30 PM PST 24
Peak memory 199740 kb
Host smart-bcee3eda-5a08-4107-8107-c6fe49a3514d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213226055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2213226055
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.746612592
Short name T638
Test name
Test status
Simulation time 76143297215 ps
CPU time 240.27 seconds
Started Mar 07 01:45:12 PM PST 24
Finished Mar 07 01:49:13 PM PST 24
Peak memory 200456 kb
Host smart-bf0bb08f-3ca4-494b-9928-1486d88efbfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746612592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.746612592
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3355917278
Short name T236
Test name
Test status
Simulation time 93968361259 ps
CPU time 20.26 seconds
Started Mar 07 01:45:14 PM PST 24
Finished Mar 07 01:45:34 PM PST 24
Peak memory 197944 kb
Host smart-56c4ebce-1cd7-4cf0-9910-09bb7bb189a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355917278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3355917278
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1763177948
Short name T506
Test name
Test status
Simulation time 17363929168 ps
CPU time 168.41 seconds
Started Mar 07 01:45:07 PM PST 24
Finished Mar 07 01:47:56 PM PST 24
Peak memory 200556 kb
Host smart-da491e55-3039-4535-be29-1a18dacd688f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763177948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1763177948
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3324969783
Short name T661
Test name
Test status
Simulation time 4943370876 ps
CPU time 34.28 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:45:45 PM PST 24
Peak memory 199496 kb
Host smart-7f4437ac-ee5a-4124-9a33-4bf0a68f588a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324969783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3324969783
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.293860137
Short name T894
Test name
Test status
Simulation time 175096086667 ps
CPU time 45.18 seconds
Started Mar 07 01:45:08 PM PST 24
Finished Mar 07 01:45:54 PM PST 24
Peak memory 200548 kb
Host smart-71f8fa5d-dbfc-433d-af15-8eff9688dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293860137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.293860137
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2348176184
Short name T860
Test name
Test status
Simulation time 576976787 ps
CPU time 0.98 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:45:11 PM PST 24
Peak memory 195936 kb
Host smart-c2301044-3ef2-49c7-9eb4-f78ed93cd13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348176184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2348176184
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2447298644
Short name T491
Test name
Test status
Simulation time 275615205 ps
CPU time 1.11 seconds
Started Mar 07 01:45:15 PM PST 24
Finished Mar 07 01:45:17 PM PST 24
Peak memory 198748 kb
Host smart-e9845d5d-6c3f-4170-8e6d-bbf4bddc03b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447298644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2447298644
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.904895567
Short name T24
Test name
Test status
Simulation time 18982026736 ps
CPU time 223.93 seconds
Started Mar 07 01:45:15 PM PST 24
Finished Mar 07 01:48:59 PM PST 24
Peak memory 217276 kb
Host smart-e4a4e207-7338-4fd8-bbb1-4d94f6bbbf45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904895567 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.904895567
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3862892451
Short name T478
Test name
Test status
Simulation time 589588431 ps
CPU time 1.7 seconds
Started Mar 07 01:45:09 PM PST 24
Finished Mar 07 01:45:11 PM PST 24
Peak memory 198304 kb
Host smart-af30f90b-c613-473d-b36c-3f0b7980bfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862892451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3862892451
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1633048107
Short name T392
Test name
Test status
Simulation time 152583989900 ps
CPU time 106.53 seconds
Started Mar 07 01:45:08 PM PST 24
Finished Mar 07 01:46:56 PM PST 24
Peak memory 200500 kb
Host smart-553cc5f9-695e-4765-aab9-c630c0c80791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633048107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1633048107
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3175620756
Short name T144
Test name
Test status
Simulation time 148346096349 ps
CPU time 119.36 seconds
Started Mar 07 01:48:02 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 200484 kb
Host smart-e6928d1f-8a26-47b4-8182-6ee2a1c00c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175620756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3175620756
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3718413320
Short name T116
Test name
Test status
Simulation time 23063846285 ps
CPU time 40.19 seconds
Started Mar 07 01:47:58 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 200552 kb
Host smart-90166116-b1ec-47c1-8eb3-2be57114108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718413320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3718413320
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2305180421
Short name T845
Test name
Test status
Simulation time 45209483091 ps
CPU time 16.38 seconds
Started Mar 07 01:47:59 PM PST 24
Finished Mar 07 01:48:16 PM PST 24
Peak memory 200484 kb
Host smart-67559b89-8d7e-4918-8158-48503c85eca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305180421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2305180421
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.4234740564
Short name T1093
Test name
Test status
Simulation time 17041133620 ps
CPU time 26.94 seconds
Started Mar 07 01:48:04 PM PST 24
Finished Mar 07 01:48:31 PM PST 24
Peak memory 200272 kb
Host smart-92a1d951-39e0-4e7f-9abb-ab0f9e417df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234740564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4234740564
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.446454142
Short name T954
Test name
Test status
Simulation time 81105848024 ps
CPU time 56.73 seconds
Started Mar 07 01:48:01 PM PST 24
Finished Mar 07 01:48:59 PM PST 24
Peak memory 200312 kb
Host smart-08147f2a-9328-44f9-a53d-f459e085e21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446454142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.446454142
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2376784935
Short name T130
Test name
Test status
Simulation time 42710098496 ps
CPU time 15.3 seconds
Started Mar 07 01:48:00 PM PST 24
Finished Mar 07 01:48:16 PM PST 24
Peak memory 200444 kb
Host smart-8742b86a-34c3-486f-bb10-265d604343dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376784935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2376784935
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3389642929
Short name T714
Test name
Test status
Simulation time 37608284038 ps
CPU time 21.24 seconds
Started Mar 07 01:48:03 PM PST 24
Finished Mar 07 01:48:25 PM PST 24
Peak memory 200280 kb
Host smart-180c89e7-506f-4e4f-9cfa-555c3ce7c8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389642929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3389642929
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3155214543
Short name T901
Test name
Test status
Simulation time 118705317977 ps
CPU time 64.72 seconds
Started Mar 07 01:48:03 PM PST 24
Finished Mar 07 01:49:08 PM PST 24
Peak memory 200396 kb
Host smart-101044f2-6ff0-4571-8778-57b30eeb5aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155214543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3155214543
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3751839593
Short name T315
Test name
Test status
Simulation time 24691145347 ps
CPU time 42.08 seconds
Started Mar 07 01:48:01 PM PST 24
Finished Mar 07 01:48:43 PM PST 24
Peak memory 200404 kb
Host smart-02e8139c-c0de-4316-930a-eb60225b1453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751839593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3751839593
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1735333214
Short name T484
Test name
Test status
Simulation time 56622735 ps
CPU time 0.59 seconds
Started Mar 07 01:45:19 PM PST 24
Finished Mar 07 01:45:19 PM PST 24
Peak memory 195976 kb
Host smart-a606ed22-a0d1-45d5-b065-190da2da7e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735333214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1735333214
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1651951709
Short name T421
Test name
Test status
Simulation time 116163811324 ps
CPU time 165.78 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:47:56 PM PST 24
Peak memory 200580 kb
Host smart-15f85cd2-4896-4056-90c4-6726073decd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651951709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1651951709
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1196789845
Short name T913
Test name
Test status
Simulation time 20670949559 ps
CPU time 37.95 seconds
Started Mar 07 01:45:15 PM PST 24
Finished Mar 07 01:45:53 PM PST 24
Peak memory 200276 kb
Host smart-6055bfb9-d679-4b90-884c-816250812a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196789845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1196789845
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.4119881136
Short name T407
Test name
Test status
Simulation time 79339510667 ps
CPU time 36.43 seconds
Started Mar 07 01:45:11 PM PST 24
Finished Mar 07 01:45:47 PM PST 24
Peak memory 200548 kb
Host smart-0c33c5e2-c445-4313-b9e4-ad5b421cdbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119881136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.4119881136
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.561152408
Short name T625
Test name
Test status
Simulation time 107568015049 ps
CPU time 183.56 seconds
Started Mar 07 01:45:14 PM PST 24
Finished Mar 07 01:48:18 PM PST 24
Peak memory 200392 kb
Host smart-d1b90d23-bf8c-43eb-b185-66b462650eb6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561152408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.561152408
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2258688482
Short name T553
Test name
Test status
Simulation time 70350490321 ps
CPU time 315.65 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:50:32 PM PST 24
Peak memory 200548 kb
Host smart-5790a911-385c-4130-83ab-07cc90744430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2258688482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2258688482
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2384716521
Short name T650
Test name
Test status
Simulation time 2577023341 ps
CPU time 5.84 seconds
Started Mar 07 01:45:16 PM PST 24
Finished Mar 07 01:45:22 PM PST 24
Peak memory 198892 kb
Host smart-be881edf-b71a-466f-883b-cc0b772b4dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384716521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2384716521
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.131732456
Short name T832
Test name
Test status
Simulation time 58944632023 ps
CPU time 107.47 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:46:58 PM PST 24
Peak memory 208664 kb
Host smart-3927a6c9-9fad-4245-9143-e38260b20332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131732456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.131732456
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.114681527
Short name T715
Test name
Test status
Simulation time 1416094401 ps
CPU time 0.93 seconds
Started Mar 07 01:45:11 PM PST 24
Finished Mar 07 01:45:13 PM PST 24
Peak memory 195840 kb
Host smart-72ec94ad-c324-4de3-a038-8577a14a0979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114681527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.114681527
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.273142383
Short name T582
Test name
Test status
Simulation time 44178429267 ps
CPU time 19.63 seconds
Started Mar 07 01:45:10 PM PST 24
Finished Mar 07 01:45:30 PM PST 24
Peak memory 199712 kb
Host smart-d18028e6-a6cf-4f9e-9d86-5e3da01bb1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273142383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.273142383
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4695184
Short name T612
Test name
Test status
Simulation time 3994031477 ps
CPU time 7.12 seconds
Started Mar 07 01:45:08 PM PST 24
Finished Mar 07 01:45:16 PM PST 24
Peak memory 196292 kb
Host smart-016c9fc0-1454-4533-8cd1-85425954fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4695184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4695184
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3280376552
Short name T48
Test name
Test status
Simulation time 689977177 ps
CPU time 2.54 seconds
Started Mar 07 01:45:11 PM PST 24
Finished Mar 07 01:45:13 PM PST 24
Peak memory 199036 kb
Host smart-001883e9-f0e8-4fbe-905f-d413fad40b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280376552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3280376552
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1495323257
Short name T310
Test name
Test status
Simulation time 117863665613 ps
CPU time 60.05 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:46:17 PM PST 24
Peak memory 200512 kb
Host smart-a8195ce8-91e3-48ca-b736-a7eef0c69efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495323257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1495323257
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1551105478
Short name T399
Test name
Test status
Simulation time 6832146663 ps
CPU time 18.16 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:45:36 PM PST 24
Peak memory 199988 kb
Host smart-fe410f44-f6e6-461e-9e8a-53d5182435e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551105478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1551105478
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.254226365
Short name T924
Test name
Test status
Simulation time 6027773382 ps
CPU time 11.39 seconds
Started Mar 07 01:45:15 PM PST 24
Finished Mar 07 01:45:27 PM PST 24
Peak memory 200516 kb
Host smart-37aca7b3-9692-47a4-86c9-17800e4c6a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254226365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.254226365
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.760476279
Short name T709
Test name
Test status
Simulation time 89285617675 ps
CPU time 72.05 seconds
Started Mar 07 01:48:00 PM PST 24
Finished Mar 07 01:49:12 PM PST 24
Peak memory 199896 kb
Host smart-eff5d2a6-800c-41e3-b804-7d5dac8a1ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760476279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.760476279
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3911111819
Short name T969
Test name
Test status
Simulation time 67700835134 ps
CPU time 22.42 seconds
Started Mar 07 01:48:00 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 200252 kb
Host smart-5aa0c2e0-60de-4047-af2d-dab6620000ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911111819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3911111819
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1472470767
Short name T227
Test name
Test status
Simulation time 19338729585 ps
CPU time 8.86 seconds
Started Mar 07 01:48:02 PM PST 24
Finished Mar 07 01:48:11 PM PST 24
Peak memory 199876 kb
Host smart-c89d427d-cb31-4140-a80c-1ddf1cdbb7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472470767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1472470767
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3028537853
Short name T1106
Test name
Test status
Simulation time 63159529318 ps
CPU time 15.54 seconds
Started Mar 07 01:48:01 PM PST 24
Finished Mar 07 01:48:17 PM PST 24
Peak memory 200400 kb
Host smart-9631fa6e-fe1a-479e-94f5-7c72fe39f161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028537853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3028537853
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2694697991
Short name T1105
Test name
Test status
Simulation time 26337514947 ps
CPU time 28.54 seconds
Started Mar 07 01:48:03 PM PST 24
Finished Mar 07 01:48:32 PM PST 24
Peak memory 200464 kb
Host smart-6a2f7daa-b6eb-4132-a7b1-c75fabae30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694697991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2694697991
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3238682636
Short name T984
Test name
Test status
Simulation time 18454689883 ps
CPU time 41.86 seconds
Started Mar 07 01:48:00 PM PST 24
Finished Mar 07 01:48:42 PM PST 24
Peak memory 200552 kb
Host smart-cb81dc66-0551-4f17-a4f1-0080b4271f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238682636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3238682636
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.190083769
Short name T717
Test name
Test status
Simulation time 120222605095 ps
CPU time 118.42 seconds
Started Mar 07 01:47:58 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 200556 kb
Host smart-f1523280-8aa1-4714-83f3-9d3886c03d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190083769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.190083769
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1275326494
Short name T4
Test name
Test status
Simulation time 14096923574 ps
CPU time 14.41 seconds
Started Mar 07 01:48:02 PM PST 24
Finished Mar 07 01:48:16 PM PST 24
Peak memory 199956 kb
Host smart-d56d3c01-236a-4a07-bfd4-1dce56a573e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275326494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1275326494
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3378421043
Short name T526
Test name
Test status
Simulation time 109389477554 ps
CPU time 48.27 seconds
Started Mar 07 01:48:06 PM PST 24
Finished Mar 07 01:48:54 PM PST 24
Peak memory 200536 kb
Host smart-fbae3d85-b7a3-4bdf-bc1f-051e5a3ff1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378421043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3378421043
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.627047840
Short name T525
Test name
Test status
Simulation time 14283072 ps
CPU time 0.58 seconds
Started Mar 07 01:45:18 PM PST 24
Finished Mar 07 01:45:19 PM PST 24
Peak memory 195988 kb
Host smart-26ed9b66-d64d-420c-accb-cd3ab1576b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627047840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.627047840
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2058031560
Short name T1054
Test name
Test status
Simulation time 129523055726 ps
CPU time 24.03 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:45:41 PM PST 24
Peak memory 200568 kb
Host smart-6451621c-4a71-48d2-9426-3cdc31db0808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058031560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2058031560
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1612994738
Short name T679
Test name
Test status
Simulation time 37038074818 ps
CPU time 64.06 seconds
Started Mar 07 01:45:19 PM PST 24
Finished Mar 07 01:46:23 PM PST 24
Peak memory 200232 kb
Host smart-fc3ccfd8-c478-44c0-a4b4-8eeff63d6cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612994738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1612994738
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2760120895
Short name T231
Test name
Test status
Simulation time 82892099998 ps
CPU time 140.84 seconds
Started Mar 07 01:45:15 PM PST 24
Finished Mar 07 01:47:36 PM PST 24
Peak memory 200620 kb
Host smart-ef1923db-c2cf-40cd-83ac-046723b3e4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760120895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2760120895
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3143430845
Short name T77
Test name
Test status
Simulation time 284123455959 ps
CPU time 104.52 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:47:18 PM PST 24
Peak memory 200344 kb
Host smart-020c9203-3bb5-443e-9ab4-a94d062473c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143430845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3143430845
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3201288803
Short name T551
Test name
Test status
Simulation time 90804148610 ps
CPU time 239.13 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:49:33 PM PST 24
Peak memory 200496 kb
Host smart-b13c1f26-430a-413c-be99-5e0c9f5d3440
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201288803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3201288803
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2133063398
Short name T987
Test name
Test status
Simulation time 175528287896 ps
CPU time 35.74 seconds
Started Mar 07 01:45:16 PM PST 24
Finished Mar 07 01:45:52 PM PST 24
Peak memory 198788 kb
Host smart-4ccd5fb6-17b4-4ef8-8b9a-16562325f77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133063398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2133063398
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2183498801
Short name T426
Test name
Test status
Simulation time 20230813583 ps
CPU time 220.89 seconds
Started Mar 07 01:45:15 PM PST 24
Finished Mar 07 01:48:56 PM PST 24
Peak memory 200516 kb
Host smart-8e34f25e-8d59-4c1a-9bb7-bcd090d423d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183498801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2183498801
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3652684390
Short name T12
Test name
Test status
Simulation time 5850858610 ps
CPU time 31.31 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:45:48 PM PST 24
Peak memory 199400 kb
Host smart-5256c517-c345-415f-9aba-2abbc4709bf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652684390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3652684390
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.924733144
Short name T511
Test name
Test status
Simulation time 140108906387 ps
CPU time 109.88 seconds
Started Mar 07 01:45:18 PM PST 24
Finished Mar 07 01:47:08 PM PST 24
Peak memory 200232 kb
Host smart-696cece6-ff7f-40e8-8a66-9a0139947947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924733144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.924733144
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1202525478
Short name T728
Test name
Test status
Simulation time 41199602333 ps
CPU time 5.89 seconds
Started Mar 07 01:45:19 PM PST 24
Finished Mar 07 01:45:25 PM PST 24
Peak memory 196340 kb
Host smart-183391b6-f935-4ef5-9b42-a1b3dda57eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202525478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1202525478
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2238879909
Short name T849
Test name
Test status
Simulation time 5801830534 ps
CPU time 10.77 seconds
Started Mar 07 01:45:18 PM PST 24
Finished Mar 07 01:45:29 PM PST 24
Peak memory 200468 kb
Host smart-d539715e-afc7-4ba6-a433-f99f1a974e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238879909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2238879909
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2401902454
Short name T674
Test name
Test status
Simulation time 26291438390 ps
CPU time 16.39 seconds
Started Mar 07 01:45:16 PM PST 24
Finished Mar 07 01:45:32 PM PST 24
Peak memory 200624 kb
Host smart-07cd6ac4-ec99-4d0a-8ea5-6ad2cae6ca30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401902454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2401902454
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3921667356
Short name T796
Test name
Test status
Simulation time 7045523986 ps
CPU time 15.07 seconds
Started Mar 07 01:45:20 PM PST 24
Finished Mar 07 01:45:35 PM PST 24
Peak memory 199456 kb
Host smart-97c63b58-cb0c-4af0-aa2d-968fe93fe5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921667356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3921667356
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1599600966
Short name T167
Test name
Test status
Simulation time 102130435768 ps
CPU time 163.51 seconds
Started Mar 07 01:45:16 PM PST 24
Finished Mar 07 01:47:59 PM PST 24
Peak memory 200436 kb
Host smart-a42a0da9-2227-4f98-99ee-2b25ad81a803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599600966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1599600966
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1181794821
Short name T157
Test name
Test status
Simulation time 151596233494 ps
CPU time 69.41 seconds
Started Mar 07 01:48:07 PM PST 24
Finished Mar 07 01:49:16 PM PST 24
Peak memory 200544 kb
Host smart-77c85774-45b7-4a11-870f-89d5c4692343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181794821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1181794821
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3011675817
Short name T321
Test name
Test status
Simulation time 54496022927 ps
CPU time 42.18 seconds
Started Mar 07 01:48:10 PM PST 24
Finished Mar 07 01:48:53 PM PST 24
Peak memory 200204 kb
Host smart-a15f5463-dcce-4b40-b4e0-28f2a4a7d0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011675817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3011675817
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2453437736
Short name T138
Test name
Test status
Simulation time 371449653244 ps
CPU time 210.05 seconds
Started Mar 07 01:48:07 PM PST 24
Finished Mar 07 01:51:37 PM PST 24
Peak memory 200492 kb
Host smart-6a1d9cca-ad39-413a-b927-3c690e8d0f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453437736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2453437736
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1545293500
Short name T863
Test name
Test status
Simulation time 118874480704 ps
CPU time 211.79 seconds
Started Mar 07 01:48:07 PM PST 24
Finished Mar 07 01:51:40 PM PST 24
Peak memory 200288 kb
Host smart-cbce7aa3-2820-4372-b599-65b921bcbb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545293500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1545293500
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.4156704791
Short name T834
Test name
Test status
Simulation time 24309705561 ps
CPU time 52.33 seconds
Started Mar 07 01:48:05 PM PST 24
Finished Mar 07 01:48:58 PM PST 24
Peak memory 200580 kb
Host smart-fcecb767-3c86-4273-9052-f2ad8bdc8a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156704791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4156704791
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2258470037
Short name T841
Test name
Test status
Simulation time 103972403206 ps
CPU time 168.09 seconds
Started Mar 07 01:48:12 PM PST 24
Finished Mar 07 01:51:00 PM PST 24
Peak memory 200304 kb
Host smart-f6ec967d-e0a7-4d34-b405-5925cf30bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258470037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2258470037
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3236528714
Short name T353
Test name
Test status
Simulation time 49418968137 ps
CPU time 41.54 seconds
Started Mar 07 01:48:07 PM PST 24
Finished Mar 07 01:48:49 PM PST 24
Peak memory 200180 kb
Host smart-a414c141-5cd1-4292-9a66-785f49b3f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236528714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3236528714
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1775291451
Short name T26
Test name
Test status
Simulation time 19638708 ps
CPU time 0.57 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:45:35 PM PST 24
Peak memory 195912 kb
Host smart-093ce242-ed04-4e61-bfb0-c3b251592b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775291451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1775291451
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3710514167
Short name T38
Test name
Test status
Simulation time 30222661719 ps
CPU time 50.51 seconds
Started Mar 07 01:45:19 PM PST 24
Finished Mar 07 01:46:10 PM PST 24
Peak memory 200528 kb
Host smart-172c7cb8-6d72-47de-834b-e9be9bde1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710514167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3710514167
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1847723780
Short name T657
Test name
Test status
Simulation time 78620468506 ps
CPU time 69.77 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:46:44 PM PST 24
Peak memory 200504 kb
Host smart-002cf363-2e3d-4dbc-b70c-6436d49503a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847723780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1847723780
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.2715952500
Short name T520
Test name
Test status
Simulation time 49724019174 ps
CPU time 38.71 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:46:13 PM PST 24
Peak memory 199908 kb
Host smart-7ad9f099-8a8b-497d-92ec-47e62b46bba4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715952500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2715952500
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_loopback.1317254267
Short name T1032
Test name
Test status
Simulation time 2264656738 ps
CPU time 4.09 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:45:21 PM PST 24
Peak memory 196340 kb
Host smart-d4484458-c101-4620-8864-4184426c47c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317254267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1317254267
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3113362854
Short name T5
Test name
Test status
Simulation time 119185406007 ps
CPU time 34.12 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:46:08 PM PST 24
Peak memory 200752 kb
Host smart-5adf0fd1-8a56-40de-9d81-d9d5ed8b20b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113362854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3113362854
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2464909417
Short name T685
Test name
Test status
Simulation time 17904647933 ps
CPU time 977.04 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 02:01:51 PM PST 24
Peak memory 200544 kb
Host smart-65865082-58ad-4d21-8fd2-18b6bb76076f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464909417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2464909417
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1894124376
Short name T957
Test name
Test status
Simulation time 2863387927 ps
CPU time 20.38 seconds
Started Mar 07 01:45:19 PM PST 24
Finished Mar 07 01:45:40 PM PST 24
Peak memory 199152 kb
Host smart-6975d059-7069-41ec-9970-9bb296a02470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1894124376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1894124376
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4250699637
Short name T586
Test name
Test status
Simulation time 200276956203 ps
CPU time 73.86 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:46:32 PM PST 24
Peak memory 200452 kb
Host smart-ff2f9e05-a0cd-4d79-ad61-213947c8c862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250699637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4250699637
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.164059161
Short name T93
Test name
Test status
Simulation time 4650441195 ps
CPU time 7.73 seconds
Started Mar 07 01:45:17 PM PST 24
Finished Mar 07 01:45:25 PM PST 24
Peak memory 196288 kb
Host smart-81a5ef60-2653-4170-8d07-a6a3fbe0a2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164059161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.164059161
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1624518246
Short name T695
Test name
Test status
Simulation time 840088259 ps
CPU time 4.79 seconds
Started Mar 07 01:45:19 PM PST 24
Finished Mar 07 01:45:24 PM PST 24
Peak memory 198360 kb
Host smart-703b53f1-a712-45a8-8369-28823ce7a3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624518246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1624518246
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.434031241
Short name T724
Test name
Test status
Simulation time 858017577 ps
CPU time 1.45 seconds
Started Mar 07 01:45:18 PM PST 24
Finished Mar 07 01:45:20 PM PST 24
Peak memory 198540 kb
Host smart-dbd5f873-eeb4-42ed-a4b0-d0873dd19b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434031241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.434031241
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3101203793
Short name T703
Test name
Test status
Simulation time 63777543788 ps
CPU time 15.42 seconds
Started Mar 07 01:45:20 PM PST 24
Finished Mar 07 01:45:36 PM PST 24
Peak memory 198452 kb
Host smart-fefdb12e-ab23-4745-b73d-5afcaba1fd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101203793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3101203793
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4225852911
Short name T90
Test name
Test status
Simulation time 44951787292 ps
CPU time 26.38 seconds
Started Mar 07 01:48:06 PM PST 24
Finished Mar 07 01:48:33 PM PST 24
Peak memory 199932 kb
Host smart-11a253d0-ec92-4d8f-9f26-a9939a9b3d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225852911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4225852911
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.409568060
Short name T365
Test name
Test status
Simulation time 44024358729 ps
CPU time 5.07 seconds
Started Mar 07 01:48:08 PM PST 24
Finished Mar 07 01:48:13 PM PST 24
Peak memory 200548 kb
Host smart-4a7e0083-db6a-466a-b949-67b7ee4764f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409568060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.409568060
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3731047477
Short name T154
Test name
Test status
Simulation time 34659508901 ps
CPU time 14.76 seconds
Started Mar 07 01:48:10 PM PST 24
Finished Mar 07 01:48:25 PM PST 24
Peak memory 198912 kb
Host smart-83c38647-b62b-4b26-95b4-e4b022858c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731047477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3731047477
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3512489569
Short name T229
Test name
Test status
Simulation time 21808730237 ps
CPU time 49.42 seconds
Started Mar 07 01:48:08 PM PST 24
Finished Mar 07 01:48:58 PM PST 24
Peak memory 200620 kb
Host smart-e5d5c5bf-ef77-482e-8fa0-64f301e967a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512489569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3512489569
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2545068414
Short name T809
Test name
Test status
Simulation time 47563515379 ps
CPU time 17.16 seconds
Started Mar 07 01:48:06 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 199420 kb
Host smart-9e1d0c1a-1508-4ed3-b97e-ce94b79b85ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545068414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2545068414
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1865468041
Short name T1009
Test name
Test status
Simulation time 232436659937 ps
CPU time 150.65 seconds
Started Mar 07 01:48:11 PM PST 24
Finished Mar 07 01:50:42 PM PST 24
Peak memory 200508 kb
Host smart-cc280dcb-53d1-4ed9-88c5-66455262ca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865468041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1865468041
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.503608604
Short name T203
Test name
Test status
Simulation time 18853684682 ps
CPU time 7.09 seconds
Started Mar 07 01:48:07 PM PST 24
Finished Mar 07 01:48:15 PM PST 24
Peak memory 198872 kb
Host smart-7f1de7f7-65bf-4c83-99bd-c3dd3a51f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503608604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.503608604
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2707363307
Short name T233
Test name
Test status
Simulation time 244272260305 ps
CPU time 68.99 seconds
Started Mar 07 01:48:11 PM PST 24
Finished Mar 07 01:49:20 PM PST 24
Peak memory 200508 kb
Host smart-8572f877-16d0-4b53-8e15-2583ad11b485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707363307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2707363307
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2352461694
Short name T788
Test name
Test status
Simulation time 6875833418 ps
CPU time 7.84 seconds
Started Mar 07 01:48:08 PM PST 24
Finished Mar 07 01:48:16 PM PST 24
Peak memory 200400 kb
Host smart-90463b96-af87-41b1-8abe-f5970da13571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352461694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2352461694
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2984640632
Short name T158
Test name
Test status
Simulation time 59896836728 ps
CPU time 24.04 seconds
Started Mar 07 01:48:08 PM PST 24
Finished Mar 07 01:48:32 PM PST 24
Peak memory 200472 kb
Host smart-634bc6cb-42d0-4441-8bed-7b7f52c9c821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984640632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2984640632
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2266865878
Short name T1066
Test name
Test status
Simulation time 13726691 ps
CPU time 0.53 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:45:32 PM PST 24
Peak memory 195056 kb
Host smart-e2493cc2-2c23-4368-9f09-41165b89f8a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266865878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2266865878
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1998497609
Short name T560
Test name
Test status
Simulation time 70123450037 ps
CPU time 74.59 seconds
Started Mar 07 01:45:21 PM PST 24
Finished Mar 07 01:46:36 PM PST 24
Peak memory 200612 kb
Host smart-5a747d1e-1304-457a-b36f-0af91b09668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998497609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1998497609
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.643880635
Short name T185
Test name
Test status
Simulation time 119298549233 ps
CPU time 186.65 seconds
Started Mar 07 01:45:27 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 200592 kb
Host smart-0dbfd1d0-524c-4ce5-8a47-16248f1e590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643880635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.643880635
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.1124297156
Short name T1037
Test name
Test status
Simulation time 562969487999 ps
CPU time 193.79 seconds
Started Mar 07 01:45:30 PM PST 24
Finished Mar 07 01:48:45 PM PST 24
Peak memory 200328 kb
Host smart-9e94c159-2f1b-4c2c-9838-2bfc8327115d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124297156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1124297156
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.512302730
Short name T922
Test name
Test status
Simulation time 134176520429 ps
CPU time 384.56 seconds
Started Mar 07 01:45:30 PM PST 24
Finished Mar 07 01:51:55 PM PST 24
Peak memory 200596 kb
Host smart-b4d30e94-b9e8-4d9c-9b0e-02d0dffb91f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512302730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.512302730
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3707210645
Short name T689
Test name
Test status
Simulation time 7105994263 ps
CPU time 16.6 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:45:48 PM PST 24
Peak memory 198624 kb
Host smart-43059c64-87b0-48a7-8f85-9d7291d8b1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707210645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3707210645
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1808375675
Short name T882
Test name
Test status
Simulation time 49742596966 ps
CPU time 75.69 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:46:47 PM PST 24
Peak memory 200176 kb
Host smart-a131181d-7f1f-4f24-a230-31b1fc673a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808375675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1808375675
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1552721916
Short name T968
Test name
Test status
Simulation time 20208862251 ps
CPU time 402.46 seconds
Started Mar 07 01:45:29 PM PST 24
Finished Mar 07 01:52:12 PM PST 24
Peak memory 200472 kb
Host smart-f0838f27-d28f-421d-98c4-a61f54fcda42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552721916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1552721916
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3455125511
Short name T528
Test name
Test status
Simulation time 7701402991 ps
CPU time 72.61 seconds
Started Mar 07 01:45:32 PM PST 24
Finished Mar 07 01:46:44 PM PST 24
Peak memory 199068 kb
Host smart-132a4f6d-532a-48cf-9f63-25040680c6c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455125511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3455125511
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2365855290
Short name T343
Test name
Test status
Simulation time 22072679746 ps
CPU time 35.16 seconds
Started Mar 07 01:45:33 PM PST 24
Finished Mar 07 01:46:08 PM PST 24
Peak memory 199576 kb
Host smart-813da7ef-297f-4535-9b31-0f318e528ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365855290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2365855290
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1464309761
Short name T997
Test name
Test status
Simulation time 4547962024 ps
CPU time 1.78 seconds
Started Mar 07 01:45:29 PM PST 24
Finished Mar 07 01:45:31 PM PST 24
Peak memory 196372 kb
Host smart-b08fdd06-e9b6-43d4-a6fe-d40bf8547eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464309761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1464309761
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1520607889
Short name T1084
Test name
Test status
Simulation time 660705943 ps
CPU time 2.56 seconds
Started Mar 07 01:45:20 PM PST 24
Finished Mar 07 01:45:23 PM PST 24
Peak memory 198584 kb
Host smart-1c9f9e44-5c93-4be2-9aa1-d742f0c8d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520607889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1520607889
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3153728031
Short name T958
Test name
Test status
Simulation time 28975511765 ps
CPU time 14.83 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:45:46 PM PST 24
Peak memory 200616 kb
Host smart-192341c7-ace1-4c2a-ac2a-f5ac6c38aff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153728031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3153728031
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3266406250
Short name T791
Test name
Test status
Simulation time 6255629008 ps
CPU time 18.08 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:45:49 PM PST 24
Peak memory 200448 kb
Host smart-29d4d764-8416-4d44-974c-ff942c25cfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266406250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3266406250
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3511258611
Short name T420
Test name
Test status
Simulation time 30466518205 ps
CPU time 91.76 seconds
Started Mar 07 01:45:15 PM PST 24
Finished Mar 07 01:46:47 PM PST 24
Peak memory 200552 kb
Host smart-de2f3ef0-08dc-4fd4-b2d1-1f0388ff3635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511258611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3511258611
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1891790426
Short name T186
Test name
Test status
Simulation time 82157742616 ps
CPU time 30.64 seconds
Started Mar 07 01:48:12 PM PST 24
Finished Mar 07 01:48:43 PM PST 24
Peak memory 199836 kb
Host smart-e8525672-1ac2-4a8f-bf40-d9efd702897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891790426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1891790426
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.638530149
Short name T300
Test name
Test status
Simulation time 36721299521 ps
CPU time 53.69 seconds
Started Mar 07 01:48:06 PM PST 24
Finished Mar 07 01:49:00 PM PST 24
Peak memory 200032 kb
Host smart-d5e26598-7ad5-48e9-8362-5c045dd670e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638530149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.638530149
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2632399618
Short name T152
Test name
Test status
Simulation time 32144737121 ps
CPU time 14.78 seconds
Started Mar 07 01:48:07 PM PST 24
Finished Mar 07 01:48:22 PM PST 24
Peak memory 200528 kb
Host smart-ce2246e4-5d69-4b3b-84bd-b5b31323eadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632399618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2632399618
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2099436372
Short name T1074
Test name
Test status
Simulation time 38897310724 ps
CPU time 61.97 seconds
Started Mar 07 01:48:06 PM PST 24
Finished Mar 07 01:49:08 PM PST 24
Peak memory 200228 kb
Host smart-90a6f5ef-5aa4-40ed-9d9b-e454b62a6b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099436372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2099436372
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.722871096
Short name T327
Test name
Test status
Simulation time 94049755076 ps
CPU time 43.14 seconds
Started Mar 07 01:48:09 PM PST 24
Finished Mar 07 01:48:52 PM PST 24
Peak memory 200492 kb
Host smart-22c2a400-46c0-4756-83a0-51114b5f6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722871096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.722871096
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1216436515
Short name T192
Test name
Test status
Simulation time 111761153059 ps
CPU time 173.11 seconds
Started Mar 07 01:48:15 PM PST 24
Finished Mar 07 01:51:08 PM PST 24
Peak memory 200140 kb
Host smart-e79b4dc7-228f-4fc8-9f5d-ae059bf716f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216436515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1216436515
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2508394040
Short name T1079
Test name
Test status
Simulation time 58922734450 ps
CPU time 40.51 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:57 PM PST 24
Peak memory 200464 kb
Host smart-8e8c69e9-9718-4cbf-a6bb-ed87a10bfd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508394040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2508394040
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4282111454
Short name T943
Test name
Test status
Simulation time 143259030283 ps
CPU time 105.89 seconds
Started Mar 07 01:48:15 PM PST 24
Finished Mar 07 01:50:01 PM PST 24
Peak memory 200348 kb
Host smart-2672b1a5-1cd9-437a-b9a7-c2aedaf5464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282111454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4282111454
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.483427089
Short name T562
Test name
Test status
Simulation time 36139637 ps
CPU time 0.56 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:44:00 PM PST 24
Peak memory 195988 kb
Host smart-97cf4cf2-dda7-438e-9f6a-8d053ea8902b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483427089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.483427089
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.4050702061
Short name T431
Test name
Test status
Simulation time 175463748241 ps
CPU time 269.89 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:48:18 PM PST 24
Peak memory 200184 kb
Host smart-b97f20b1-06c1-4c3a-bf6e-a8af5e8d8409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050702061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4050702061
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3230935997
Short name T877
Test name
Test status
Simulation time 18217120129 ps
CPU time 18.37 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:44:06 PM PST 24
Peak memory 200528 kb
Host smart-64438f02-4ba9-42fc-a6f0-d00b8f3914e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230935997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3230935997
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1566278384
Short name T126
Test name
Test status
Simulation time 80292959715 ps
CPU time 44.85 seconds
Started Mar 07 01:43:47 PM PST 24
Finished Mar 07 01:44:32 PM PST 24
Peak memory 200556 kb
Host smart-680ac4b9-ddd8-4d94-bbb7-f8d70c4b87c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566278384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1566278384
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1393890528
Short name T454
Test name
Test status
Simulation time 1022360028180 ps
CPU time 764.61 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:56:34 PM PST 24
Peak memory 198928 kb
Host smart-7614b0f3-9719-4cbb-9c9a-7137f50e2c1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393890528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1393890528
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3472428271
Short name T297
Test name
Test status
Simulation time 118927319032 ps
CPU time 802.17 seconds
Started Mar 07 01:43:58 PM PST 24
Finished Mar 07 01:57:20 PM PST 24
Peak memory 200524 kb
Host smart-9f9b7eb6-4f37-4479-bcef-af9adfddcf2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472428271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3472428271
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.745694363
Short name T476
Test name
Test status
Simulation time 3825387709 ps
CPU time 6.52 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:44:04 PM PST 24
Peak memory 196532 kb
Host smart-966e87fe-70d9-4d9e-9e63-15a828999795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745694363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.745694363
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.531535819
Short name T149
Test name
Test status
Simulation time 50705013602 ps
CPU time 83.55 seconds
Started Mar 07 01:43:44 PM PST 24
Finished Mar 07 01:45:08 PM PST 24
Peak memory 200840 kb
Host smart-69aaf278-2adb-493b-86a0-7eb609d0aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531535819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.531535819
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3290519075
Short name T1057
Test name
Test status
Simulation time 19011679568 ps
CPU time 260.39 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:48:19 PM PST 24
Peak memory 200608 kb
Host smart-3bc9508d-ff7d-4be7-b665-7136a54b4817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290519075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3290519075
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1491749899
Short name T855
Test name
Test status
Simulation time 4539713762 ps
CPU time 4.02 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:43:53 PM PST 24
Peak memory 199260 kb
Host smart-522a8684-4509-46d6-9fff-160de9b4ddf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491749899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1491749899
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3366976362
Short name T1047
Test name
Test status
Simulation time 23584109589 ps
CPU time 32.39 seconds
Started Mar 07 01:43:49 PM PST 24
Finished Mar 07 01:44:22 PM PST 24
Peak memory 200264 kb
Host smart-6f479b3d-f148-4cc3-9832-9f9fec437ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366976362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3366976362
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3550839595
Short name T989
Test name
Test status
Simulation time 5028272856 ps
CPU time 1.83 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:43:47 PM PST 24
Peak memory 196308 kb
Host smart-798837cd-f92f-4ae8-9fe2-223b60d8345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550839595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3550839595
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1325842093
Short name T88
Test name
Test status
Simulation time 65333941 ps
CPU time 0.84 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:44:00 PM PST 24
Peak memory 217920 kb
Host smart-24db52da-2eb3-456d-909e-2f923d8130f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325842093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1325842093
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.467746314
Short name T980
Test name
Test status
Simulation time 296864423 ps
CPU time 1.5 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:43:49 PM PST 24
Peak memory 198812 kb
Host smart-ac01f7c6-c5c1-4bac-83c9-7fdae98103be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467746314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.467746314
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2762755524
Short name T359
Test name
Test status
Simulation time 880148520906 ps
CPU time 342.21 seconds
Started Mar 07 01:43:55 PM PST 24
Finished Mar 07 01:49:38 PM PST 24
Peak memory 200552 kb
Host smart-9b26404c-4cc2-4b9c-a680-ad338da7dc76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762755524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2762755524
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.4209052260
Short name T32
Test name
Test status
Simulation time 58374645345 ps
CPU time 494.5 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:52:12 PM PST 24
Peak memory 216360 kb
Host smart-b583c2cf-782a-44b1-a227-3e843ad297a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209052260 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.4209052260
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.583803533
Short name T1104
Test name
Test status
Simulation time 1221868119 ps
CPU time 2.82 seconds
Started Mar 07 01:43:45 PM PST 24
Finished Mar 07 01:43:48 PM PST 24
Peak memory 200300 kb
Host smart-1af23eec-9d2b-45d1-b977-97a61bd453d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583803533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.583803533
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1473463148
Short name T798
Test name
Test status
Simulation time 404593373223 ps
CPU time 41.91 seconds
Started Mar 07 01:43:48 PM PST 24
Finished Mar 07 01:44:30 PM PST 24
Peak memory 200512 kb
Host smart-60288ce6-b65e-465b-bbb9-b79a86953b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473463148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1473463148
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3552564514
Short name T738
Test name
Test status
Simulation time 42034946 ps
CPU time 0.57 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:45:35 PM PST 24
Peak memory 196008 kb
Host smart-139cbffd-d2d5-4a1a-9850-73d16eba45d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552564514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3552564514
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.885466528
Short name T536
Test name
Test status
Simulation time 137926968078 ps
CPU time 53.01 seconds
Started Mar 07 01:45:30 PM PST 24
Finished Mar 07 01:46:23 PM PST 24
Peak memory 200580 kb
Host smart-199bc74d-1bf7-4bbb-b7b7-3e5795654e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885466528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.885466528
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2775932549
Short name T1052
Test name
Test status
Simulation time 102382296383 ps
CPU time 37.83 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:46:09 PM PST 24
Peak memory 200588 kb
Host smart-780b6e77-ebe4-471f-bf97-dca3742ac808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775932549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2775932549
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1317137174
Short name T711
Test name
Test status
Simulation time 5751484845 ps
CPU time 4.87 seconds
Started Mar 07 01:45:33 PM PST 24
Finished Mar 07 01:45:38 PM PST 24
Peak memory 196032 kb
Host smart-378ca3cf-e8db-468d-8c37-111a6324dbb4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317137174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1317137174
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2653229786
Short name T794
Test name
Test status
Simulation time 256020960715 ps
CPU time 288.38 seconds
Started Mar 07 01:45:33 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 200536 kb
Host smart-99e06722-a664-4281-aa68-a77ba2ee38da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653229786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2653229786
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3043861753
Short name T450
Test name
Test status
Simulation time 6227973073 ps
CPU time 8.91 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:45:43 PM PST 24
Peak memory 200368 kb
Host smart-d0d27c89-3786-42fe-9436-2cde72196084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043861753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3043861753
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2068626852
Short name T416
Test name
Test status
Simulation time 62705609741 ps
CPU time 55.57 seconds
Started Mar 07 01:45:35 PM PST 24
Finished Mar 07 01:46:31 PM PST 24
Peak memory 199264 kb
Host smart-a4bdf458-d3e1-4ae9-8e22-bb0275c64d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068626852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2068626852
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3538252074
Short name T603
Test name
Test status
Simulation time 17167219462 ps
CPU time 242.1 seconds
Started Mar 07 01:45:35 PM PST 24
Finished Mar 07 01:49:38 PM PST 24
Peak memory 200140 kb
Host smart-e944aa95-269b-48d1-80a4-eb0d36d5ab6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538252074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3538252074
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3827883317
Short name T627
Test name
Test status
Simulation time 6396710973 ps
CPU time 48.91 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:46:20 PM PST 24
Peak memory 198864 kb
Host smart-23babe7f-7374-4989-9ed6-e2cd85b4441f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827883317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3827883317
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3028488065
Short name T251
Test name
Test status
Simulation time 186562284215 ps
CPU time 146.37 seconds
Started Mar 07 01:45:33 PM PST 24
Finished Mar 07 01:48:00 PM PST 24
Peak memory 200560 kb
Host smart-9c8dcb33-d669-469d-ba38-7313292a7351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028488065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3028488065
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3495635696
Short name T694
Test name
Test status
Simulation time 5038083961 ps
CPU time 9.07 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:45:40 PM PST 24
Peak memory 196364 kb
Host smart-15a20b18-6275-43b2-b8c6-5cddd0194670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495635696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3495635696
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1761615653
Short name T818
Test name
Test status
Simulation time 663457047 ps
CPU time 1.88 seconds
Started Mar 07 01:45:31 PM PST 24
Finished Mar 07 01:45:34 PM PST 24
Peak memory 198868 kb
Host smart-1b5c9074-f9f4-441b-8547-dc9e9ce49327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761615653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1761615653
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3516816851
Short name T423
Test name
Test status
Simulation time 1628191858 ps
CPU time 4.71 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:45:39 PM PST 24
Peak memory 199784 kb
Host smart-c6ac0951-1654-4ba5-a9f2-ecd4a6797b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516816851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3516816851
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3306440142
Short name T6
Test name
Test status
Simulation time 11219968948 ps
CPU time 13.55 seconds
Started Mar 07 01:45:32 PM PST 24
Finished Mar 07 01:45:46 PM PST 24
Peak memory 200532 kb
Host smart-5a33adb5-8cec-4caa-913c-1745c1ea2898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306440142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3306440142
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.921380270
Short name T948
Test name
Test status
Simulation time 42708286 ps
CPU time 0.53 seconds
Started Mar 07 01:45:38 PM PST 24
Finished Mar 07 01:45:39 PM PST 24
Peak memory 196016 kb
Host smart-67d90da1-3ee1-4d15-9cff-0397fa427ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921380270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.921380270
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2976493552
Short name T316
Test name
Test status
Simulation time 210267967384 ps
CPU time 55.21 seconds
Started Mar 07 01:45:37 PM PST 24
Finished Mar 07 01:46:33 PM PST 24
Peak memory 200608 kb
Host smart-470cb299-341f-4a5b-bd55-4d0850f4d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976493552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2976493552
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1040845683
Short name T753
Test name
Test status
Simulation time 36721946384 ps
CPU time 30.65 seconds
Started Mar 07 01:45:33 PM PST 24
Finished Mar 07 01:46:04 PM PST 24
Peak memory 200328 kb
Host smart-88ac7801-95ba-4471-a744-3b8042d27960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040845683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1040845683
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.70152306
Short name T477
Test name
Test status
Simulation time 75245641309 ps
CPU time 185.18 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:48:47 PM PST 24
Peak memory 200428 kb
Host smart-fce8f918-2182-437c-9764-8e568570e75f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70152306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.70152306
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1815709084
Short name T534
Test name
Test status
Simulation time 4566502221 ps
CPU time 2.75 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:45:45 PM PST 24
Peak memory 198076 kb
Host smart-8f4b4bc5-b51b-40d7-bed8-60cc6a1ddd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815709084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1815709084
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3512751058
Short name T548
Test name
Test status
Simulation time 6198983022 ps
CPU time 10.98 seconds
Started Mar 07 01:45:36 PM PST 24
Finished Mar 07 01:45:47 PM PST 24
Peak memory 198240 kb
Host smart-bbe2d7d0-d69f-4a0f-b46d-8f9d76fc3789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512751058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3512751058
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1283500013
Short name T1008
Test name
Test status
Simulation time 10293153493 ps
CPU time 282.17 seconds
Started Mar 07 01:45:39 PM PST 24
Finished Mar 07 01:50:21 PM PST 24
Peak memory 200500 kb
Host smart-7ad2d389-6ae6-438d-bf60-cce18b493bce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1283500013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1283500013
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.674262823
Short name T13
Test name
Test status
Simulation time 4077783585 ps
CPU time 8.2 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:45:42 PM PST 24
Peak memory 198900 kb
Host smart-e908b548-5d2a-4d73-80f9-552e3a5c1aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674262823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.674262823
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3931954320
Short name T816
Test name
Test status
Simulation time 1483647005 ps
CPU time 1.86 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:45:36 PM PST 24
Peak memory 195968 kb
Host smart-c9327603-c25e-4079-800e-06ebeb154c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931954320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3931954320
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3984280056
Short name T509
Test name
Test status
Simulation time 5285576274 ps
CPU time 9.52 seconds
Started Mar 07 01:45:32 PM PST 24
Finished Mar 07 01:45:41 PM PST 24
Peak memory 199532 kb
Host smart-a0362cf7-b6bd-4667-bab2-603eb9706762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984280056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3984280056
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1516544011
Short name T75
Test name
Test status
Simulation time 85018517482 ps
CPU time 279.99 seconds
Started Mar 07 01:45:41 PM PST 24
Finished Mar 07 01:50:21 PM PST 24
Peak memory 200536 kb
Host smart-f097453d-776d-4523-8b18-4cac71a479d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516544011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1516544011
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3505461420
Short name T53
Test name
Test status
Simulation time 84425373496 ps
CPU time 699.84 seconds
Started Mar 07 01:45:40 PM PST 24
Finished Mar 07 01:57:20 PM PST 24
Peak memory 217172 kb
Host smart-50cb4923-cc96-4d0e-9b2a-666af51cad24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505461420 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3505461420
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1546031023
Short name T14
Test name
Test status
Simulation time 1068112207 ps
CPU time 3.66 seconds
Started Mar 07 01:45:39 PM PST 24
Finished Mar 07 01:45:43 PM PST 24
Peak memory 198484 kb
Host smart-3c851364-4356-4872-9d05-b1d6635a2171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546031023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1546031023
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1598542259
Short name T541
Test name
Test status
Simulation time 102105215431 ps
CPU time 42.81 seconds
Started Mar 07 01:45:34 PM PST 24
Finished Mar 07 01:46:17 PM PST 24
Peak memory 200500 kb
Host smart-80d5d6e4-5558-4189-94ed-9b55160d434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598542259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1598542259
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1221521604
Short name T494
Test name
Test status
Simulation time 11746359 ps
CPU time 0.57 seconds
Started Mar 07 01:45:47 PM PST 24
Finished Mar 07 01:45:48 PM PST 24
Peak memory 195984 kb
Host smart-823193a2-480b-49fe-b60b-3a944b2426a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221521604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1221521604
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3505591966
Short name T693
Test name
Test status
Simulation time 19313766092 ps
CPU time 29.05 seconds
Started Mar 07 01:45:39 PM PST 24
Finished Mar 07 01:46:08 PM PST 24
Peak memory 200336 kb
Host smart-5aa16bc5-1d68-4a31-9c39-9c3de07c3123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505591966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3505591966
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2077308848
Short name T1058
Test name
Test status
Simulation time 127843827775 ps
CPU time 180.18 seconds
Started Mar 07 01:45:39 PM PST 24
Finished Mar 07 01:48:40 PM PST 24
Peak memory 199748 kb
Host smart-aa5f22a0-cbdd-45e2-8b86-7406aa5b5cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077308848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2077308848
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.3860546145
Short name T584
Test name
Test status
Simulation time 239390353392 ps
CPU time 363.88 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:51:46 PM PST 24
Peak memory 197264 kb
Host smart-b383e920-72f2-4b02-b7a3-2a3de3e5e1fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860546145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3860546145
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3728644752
Short name T648
Test name
Test status
Simulation time 45962123471 ps
CPU time 110.79 seconds
Started Mar 07 01:45:48 PM PST 24
Finished Mar 07 01:47:39 PM PST 24
Peak memory 200484 kb
Host smart-7a0312f4-1d88-43c2-91b8-05d9eb41d916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728644752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3728644752
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1435491289
Short name T21
Test name
Test status
Simulation time 5895775450 ps
CPU time 6.19 seconds
Started Mar 07 01:45:39 PM PST 24
Finished Mar 07 01:45:46 PM PST 24
Peak memory 198252 kb
Host smart-96571a0f-d3ae-4f03-8f57-50a416924ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435491289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1435491289
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.896657061
Short name T558
Test name
Test status
Simulation time 99676740801 ps
CPU time 49.79 seconds
Started Mar 07 01:45:40 PM PST 24
Finished Mar 07 01:46:30 PM PST 24
Peak memory 200844 kb
Host smart-a6434db3-01ba-457c-bca6-263e900dbb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896657061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.896657061
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.139821656
Short name T540
Test name
Test status
Simulation time 23827210427 ps
CPU time 103.23 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:47:26 PM PST 24
Peak memory 200612 kb
Host smart-d67d341f-986b-4c22-9471-925e792b11f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139821656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.139821656
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3568678432
Short name T780
Test name
Test status
Simulation time 4851119229 ps
CPU time 39.15 seconds
Started Mar 07 01:45:39 PM PST 24
Finished Mar 07 01:46:18 PM PST 24
Peak memory 199344 kb
Host smart-160ba93c-7f1c-458b-a3bd-24ee3a5448d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568678432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3568678432
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1624812225
Short name T618
Test name
Test status
Simulation time 114829707508 ps
CPU time 50.6 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:46:33 PM PST 24
Peak memory 199932 kb
Host smart-034adbef-f19c-487e-95f9-b4c7f130d50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624812225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1624812225
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1183816890
Short name T471
Test name
Test status
Simulation time 39335140737 ps
CPU time 15.97 seconds
Started Mar 07 01:45:41 PM PST 24
Finished Mar 07 01:45:57 PM PST 24
Peak memory 196028 kb
Host smart-0b01ae04-089e-4c40-9eb6-fa4d6c1721e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183816890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1183816890
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3079108804
Short name T643
Test name
Test status
Simulation time 719989921 ps
CPU time 2.26 seconds
Started Mar 07 01:45:40 PM PST 24
Finished Mar 07 01:45:42 PM PST 24
Peak memory 199004 kb
Host smart-1b2a28f6-004b-4021-bfdc-66ef9c8f790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079108804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3079108804
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1606541997
Short name T752
Test name
Test status
Simulation time 57027258457 ps
CPU time 104.79 seconds
Started Mar 07 01:45:39 PM PST 24
Finished Mar 07 01:47:24 PM PST 24
Peak memory 200604 kb
Host smart-f13af74e-2756-4db4-9919-4ce25224febf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606541997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1606541997
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2447413782
Short name T412
Test name
Test status
Simulation time 6415079725 ps
CPU time 15.47 seconds
Started Mar 07 01:45:46 PM PST 24
Finished Mar 07 01:46:03 PM PST 24
Peak memory 199520 kb
Host smart-221cd78c-19e2-42bc-b114-12244a41012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447413782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2447413782
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2724747894
Short name T120
Test name
Test status
Simulation time 4600774818 ps
CPU time 8.69 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:45:51 PM PST 24
Peak memory 199660 kb
Host smart-7f165644-3a73-4743-ae32-146f9705eca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724747894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2724747894
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.969746694
Short name T499
Test name
Test status
Simulation time 12147115 ps
CPU time 0.55 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:45:43 PM PST 24
Peak memory 195024 kb
Host smart-776b13ac-b85b-48a2-b808-283bf3634e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969746694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.969746694
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1001709014
Short name T244
Test name
Test status
Simulation time 105590784281 ps
CPU time 174.84 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:48:38 PM PST 24
Peak memory 200520 kb
Host smart-0a0acc60-915a-44e3-85a1-a9f3e5a0cac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001709014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1001709014
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1021328553
Short name T532
Test name
Test status
Simulation time 125673895286 ps
CPU time 352.33 seconds
Started Mar 07 01:45:39 PM PST 24
Finished Mar 07 01:51:32 PM PST 24
Peak memory 200496 kb
Host smart-e67d5ea1-d4d1-46a6-af57-f648966633b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021328553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1021328553
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3573160393
Short name T764
Test name
Test status
Simulation time 149621756137 ps
CPU time 200.61 seconds
Started Mar 07 01:45:41 PM PST 24
Finished Mar 07 01:49:02 PM PST 24
Peak memory 200432 kb
Host smart-01f01fb2-aac3-421b-9409-d12b4beb05c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573160393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3573160393
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.843987096
Short name T653
Test name
Test status
Simulation time 299023412071 ps
CPU time 66.82 seconds
Started Mar 07 01:45:45 PM PST 24
Finished Mar 07 01:46:52 PM PST 24
Peak memory 198212 kb
Host smart-41126674-051c-4bed-b928-4b2145c79e52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843987096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.843987096
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2876700194
Short name T977
Test name
Test status
Simulation time 109204764050 ps
CPU time 289.03 seconds
Started Mar 07 01:45:44 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 200516 kb
Host smart-0d0a74e8-23f5-4d0a-a757-fc73fd33aa68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876700194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2876700194
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3531940292
Short name T451
Test name
Test status
Simulation time 6114296294 ps
CPU time 10.55 seconds
Started Mar 07 01:45:43 PM PST 24
Finished Mar 07 01:45:53 PM PST 24
Peak memory 199048 kb
Host smart-fb643b47-d168-4378-879a-1b320712b868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531940292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3531940292
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2567644952
Short name T529
Test name
Test status
Simulation time 172264318942 ps
CPU time 109.73 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:47:32 PM PST 24
Peak memory 208948 kb
Host smart-676d9c8a-40dd-45a1-b4f8-1d6fd60b6c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567644952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2567644952
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2576307463
Short name T1107
Test name
Test status
Simulation time 13692601111 ps
CPU time 351.65 seconds
Started Mar 07 01:45:43 PM PST 24
Finished Mar 07 01:51:35 PM PST 24
Peak memory 200568 kb
Host smart-6f5dbcd9-5c0d-48aa-99b9-475281c2ae9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2576307463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2576307463
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.746140910
Short name T975
Test name
Test status
Simulation time 2646716235 ps
CPU time 16.73 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:46:00 PM PST 24
Peak memory 199204 kb
Host smart-5714bca4-e861-42dc-9222-be603dfa79cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746140910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.746140910
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2853921017
Short name T889
Test name
Test status
Simulation time 402044271596 ps
CPU time 413.55 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:52:36 PM PST 24
Peak memory 200484 kb
Host smart-c4667123-972e-4655-98ab-1b6a11ba4a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853921017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2853921017
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.895374173
Short name T1015
Test name
Test status
Simulation time 5823871894 ps
CPU time 9.56 seconds
Started Mar 07 01:45:43 PM PST 24
Finished Mar 07 01:45:52 PM PST 24
Peak memory 196252 kb
Host smart-a067c0fb-c4c9-421e-9824-1670b96c20ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895374173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.895374173
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.4107112828
Short name T964
Test name
Test status
Simulation time 529289273 ps
CPU time 1.37 seconds
Started Mar 07 01:45:47 PM PST 24
Finished Mar 07 01:45:48 PM PST 24
Peak memory 198788 kb
Host smart-16733c5f-7938-4fea-84b8-5e413b09091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107112828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.4107112828
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2818486319
Short name T109
Test name
Test status
Simulation time 270575358764 ps
CPU time 124.61 seconds
Started Mar 07 01:45:43 PM PST 24
Finished Mar 07 01:47:48 PM PST 24
Peak memory 200684 kb
Host smart-83c1e16e-6e0f-42d6-941c-2971970371cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818486319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2818486319
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1655273445
Short name T556
Test name
Test status
Simulation time 1440479907 ps
CPU time 1.42 seconds
Started Mar 07 01:45:40 PM PST 24
Finished Mar 07 01:45:41 PM PST 24
Peak memory 197928 kb
Host smart-c92505a4-cdb9-4dbc-9ed5-5157e76d5181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655273445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1655273445
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1841381477
Short name T572
Test name
Test status
Simulation time 59124535774 ps
CPU time 101.48 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:47:23 PM PST 24
Peak memory 200556 kb
Host smart-adf93df6-ab9b-4023-84b9-717ad8829aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841381477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1841381477
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1175828163
Short name T852
Test name
Test status
Simulation time 35708283 ps
CPU time 0.55 seconds
Started Mar 07 01:45:46 PM PST 24
Finished Mar 07 01:45:47 PM PST 24
Peak memory 196020 kb
Host smart-e10e4efb-e2c2-4364-a69c-6659fea97d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175828163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1175828163
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3543730987
Short name T380
Test name
Test status
Simulation time 222442582757 ps
CPU time 41.55 seconds
Started Mar 07 01:45:44 PM PST 24
Finished Mar 07 01:46:26 PM PST 24
Peak memory 200584 kb
Host smart-56e94796-115e-4d37-b813-b207670f83c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543730987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3543730987
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1004728110
Short name T966
Test name
Test status
Simulation time 47027039159 ps
CPU time 85.61 seconds
Started Mar 07 01:45:42 PM PST 24
Finished Mar 07 01:47:08 PM PST 24
Peak memory 200512 kb
Host smart-0f82edfa-54d7-48d1-9c4e-05d1f80b8586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004728110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1004728110
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.847360233
Short name T174
Test name
Test status
Simulation time 5208422350 ps
CPU time 8.6 seconds
Started Mar 07 01:45:43 PM PST 24
Finished Mar 07 01:45:52 PM PST 24
Peak memory 200524 kb
Host smart-658225c8-adb5-4a38-b475-b47662e50342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847360233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.847360233
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1772032337
Short name T16
Test name
Test status
Simulation time 392127456805 ps
CPU time 73.9 seconds
Started Mar 07 01:45:46 PM PST 24
Finished Mar 07 01:47:00 PM PST 24
Peak memory 199720 kb
Host smart-9dcbcab2-3574-479b-b492-93809aaac049
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772032337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1772032337
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.824753956
Short name T406
Test name
Test status
Simulation time 62980443527 ps
CPU time 197.11 seconds
Started Mar 07 01:45:43 PM PST 24
Finished Mar 07 01:49:00 PM PST 24
Peak memory 200572 kb
Host smart-955cb0de-fb5e-4b61-a466-e8f037fe35ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824753956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.824753956
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3996688601
Short name T452
Test name
Test status
Simulation time 7872928787 ps
CPU time 14.44 seconds
Started Mar 07 01:45:45 PM PST 24
Finished Mar 07 01:46:00 PM PST 24
Peak memory 198992 kb
Host smart-f57052bc-ee7b-4916-96a2-214c39de88a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996688601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3996688601
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1245172261
Short name T759
Test name
Test status
Simulation time 87809959097 ps
CPU time 51.28 seconds
Started Mar 07 01:45:46 PM PST 24
Finished Mar 07 01:46:37 PM PST 24
Peak memory 200788 kb
Host smart-71dee34e-9a4a-4847-b350-85749066969a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245172261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1245172261
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2748057413
Short name T413
Test name
Test status
Simulation time 22839329522 ps
CPU time 94.47 seconds
Started Mar 07 01:45:46 PM PST 24
Finished Mar 07 01:47:20 PM PST 24
Peak memory 200480 kb
Host smart-deaa2504-fde7-47b6-8ece-4529227a6090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2748057413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2748057413
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2118836293
Short name T538
Test name
Test status
Simulation time 4689545071 ps
CPU time 13.86 seconds
Started Mar 07 01:45:46 PM PST 24
Finished Mar 07 01:45:59 PM PST 24
Peak memory 199400 kb
Host smart-4fe2c201-f470-459e-a41d-23fbc55150e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118836293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2118836293
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3089628612
Short name T270
Test name
Test status
Simulation time 58431358196 ps
CPU time 49.2 seconds
Started Mar 07 01:45:45 PM PST 24
Finished Mar 07 01:46:35 PM PST 24
Peak memory 199696 kb
Host smart-35fdf8a5-546f-4e6e-9569-6ddda7e8fbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089628612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3089628612
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1809643483
Short name T956
Test name
Test status
Simulation time 44305153735 ps
CPU time 17.88 seconds
Started Mar 07 01:45:44 PM PST 24
Finished Mar 07 01:46:02 PM PST 24
Peak memory 195952 kb
Host smart-5f33b889-1c71-4406-82d9-95d26f4e9f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809643483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1809643483
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3552870816
Short name T1049
Test name
Test status
Simulation time 490303702 ps
CPU time 1.3 seconds
Started Mar 07 01:45:43 PM PST 24
Finished Mar 07 01:45:45 PM PST 24
Peak memory 198440 kb
Host smart-d153618e-eef3-43f7-aa88-820b37f031f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552870816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3552870816
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.4029787836
Short name T698
Test name
Test status
Simulation time 1884708670003 ps
CPU time 3588.55 seconds
Started Mar 07 01:45:50 PM PST 24
Finished Mar 07 02:45:39 PM PST 24
Peak memory 200576 kb
Host smart-1e263876-bc30-4bed-994f-250603279775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029787836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4029787836
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2128216483
Short name T696
Test name
Test status
Simulation time 604317452 ps
CPU time 1.55 seconds
Started Mar 07 01:45:44 PM PST 24
Finished Mar 07 01:45:46 PM PST 24
Peak memory 198624 kb
Host smart-be7747b5-4ada-456d-b3f2-7a29695d2b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128216483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2128216483
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.4041032371
Short name T910
Test name
Test status
Simulation time 13481587625 ps
CPU time 11.5 seconds
Started Mar 07 01:45:44 PM PST 24
Finished Mar 07 01:45:55 PM PST 24
Peak memory 200420 kb
Host smart-40ad8c53-61cf-4f72-964e-15eee77a32a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041032371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4041032371
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2460035608
Short name T1059
Test name
Test status
Simulation time 13836947 ps
CPU time 0.55 seconds
Started Mar 07 01:45:48 PM PST 24
Finished Mar 07 01:45:48 PM PST 24
Peak memory 195940 kb
Host smart-d7d831fd-2fde-4d32-9f68-1c06cbe0f45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460035608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2460035608
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3023718746
Short name T568
Test name
Test status
Simulation time 175701380809 ps
CPU time 103.56 seconds
Started Mar 07 01:45:48 PM PST 24
Finished Mar 07 01:47:32 PM PST 24
Peak memory 200564 kb
Host smart-1507d7b6-c2ab-409f-9c5a-fd21ee4da601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023718746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3023718746
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3169123666
Short name T543
Test name
Test status
Simulation time 15254484312 ps
CPU time 23.89 seconds
Started Mar 07 01:45:48 PM PST 24
Finished Mar 07 01:46:12 PM PST 24
Peak memory 198908 kb
Host smart-967bca8d-898d-4196-9ff0-dd0961ae8a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169123666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3169123666
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2939195027
Short name T97
Test name
Test status
Simulation time 64126769159 ps
CPU time 28.65 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:46:18 PM PST 24
Peak memory 200528 kb
Host smart-9b013d52-7ef3-41ae-9762-32c2030357b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939195027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2939195027
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2141859294
Short name T425
Test name
Test status
Simulation time 104224477925 ps
CPU time 188.87 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:48:58 PM PST 24
Peak memory 200528 kb
Host smart-91519bfd-d454-4c58-adc4-29f91356996a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141859294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2141859294
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.305703582
Short name T473
Test name
Test status
Simulation time 9611247185 ps
CPU time 10.6 seconds
Started Mar 07 01:45:54 PM PST 24
Finished Mar 07 01:46:06 PM PST 24
Peak memory 198772 kb
Host smart-ed943046-fb1e-4809-99b9-fac0dc9e8e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305703582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.305703582
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1617251436
Short name T493
Test name
Test status
Simulation time 103359661041 ps
CPU time 79.95 seconds
Started Mar 07 01:45:52 PM PST 24
Finished Mar 07 01:47:12 PM PST 24
Peak memory 197884 kb
Host smart-9b4f8bb6-3276-4ac7-a5d4-7b1c57aebd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617251436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1617251436
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.750775444
Short name T574
Test name
Test status
Simulation time 5926665979 ps
CPU time 125.7 seconds
Started Mar 07 01:45:47 PM PST 24
Finished Mar 07 01:47:53 PM PST 24
Peak memory 200460 kb
Host smart-fb84bd34-ccdf-4733-ab0b-f738b2442173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750775444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.750775444
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1696892679
Short name T592
Test name
Test status
Simulation time 4842552820 ps
CPU time 42.45 seconds
Started Mar 07 01:45:53 PM PST 24
Finished Mar 07 01:46:37 PM PST 24
Peak memory 198840 kb
Host smart-3cbf518d-53c2-4711-abbb-c4c8f1c02708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1696892679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1696892679
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1089387204
Short name T842
Test name
Test status
Simulation time 39128281583 ps
CPU time 55.2 seconds
Started Mar 07 01:45:47 PM PST 24
Finished Mar 07 01:46:42 PM PST 24
Peak memory 199844 kb
Host smart-239ed4dc-0ed3-4ef6-ad29-a28206aaf34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089387204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1089387204
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3846478842
Short name T835
Test name
Test status
Simulation time 2194369607 ps
CPU time 4.36 seconds
Started Mar 07 01:45:50 PM PST 24
Finished Mar 07 01:45:54 PM PST 24
Peak memory 196104 kb
Host smart-6becc894-1e1f-4282-b018-299d1082d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846478842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3846478842
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3346143064
Short name T915
Test name
Test status
Simulation time 634779348 ps
CPU time 2.19 seconds
Started Mar 07 01:45:44 PM PST 24
Finished Mar 07 01:45:47 PM PST 24
Peak memory 198920 kb
Host smart-491111f2-245b-4098-a050-adf302a47591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346143064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3346143064
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1829980513
Short name T125
Test name
Test status
Simulation time 406595309163 ps
CPU time 509.06 seconds
Started Mar 07 01:45:53 PM PST 24
Finished Mar 07 01:54:22 PM PST 24
Peak memory 200512 kb
Host smart-16949078-ab6e-4448-b83c-75c90dda0713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829980513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1829980513
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3545667569
Short name T465
Test name
Test status
Simulation time 6723980820 ps
CPU time 13.69 seconds
Started Mar 07 01:45:56 PM PST 24
Finished Mar 07 01:46:10 PM PST 24
Peak memory 199676 kb
Host smart-b9b9e4c8-c1e8-411f-a023-cd281c9ab1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545667569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3545667569
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1129618210
Short name T565
Test name
Test status
Simulation time 38368147454 ps
CPU time 58.36 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 200600 kb
Host smart-c58ba542-c39d-4d7c-a7a5-f5f6c8619681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129618210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1129618210
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3017357592
Short name T514
Test name
Test status
Simulation time 25387924 ps
CPU time 0.61 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:45:50 PM PST 24
Peak memory 196012 kb
Host smart-769f4109-2e4e-4823-ab18-60a613e8f485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017357592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3017357592
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2028088265
Short name T594
Test name
Test status
Simulation time 263647068747 ps
CPU time 491.02 seconds
Started Mar 07 01:45:52 PM PST 24
Finished Mar 07 01:54:03 PM PST 24
Peak memory 200548 kb
Host smart-80f9baa7-8083-465d-89f9-7c93d0cbff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028088265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2028088265
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3321200636
Short name T1019
Test name
Test status
Simulation time 32380982112 ps
CPU time 33.9 seconds
Started Mar 07 01:45:51 PM PST 24
Finished Mar 07 01:46:25 PM PST 24
Peak memory 200604 kb
Host smart-3fc0808a-eacb-4416-8b45-09dca60c8c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321200636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3321200636
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2013276060
Short name T108
Test name
Test status
Simulation time 33277161616 ps
CPU time 50.01 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:46:39 PM PST 24
Peak memory 200504 kb
Host smart-f90d256f-84c7-40a8-b741-a5ee621e7604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013276060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2013276060
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1168490947
Short name T614
Test name
Test status
Simulation time 110899444375 ps
CPU time 657.47 seconds
Started Mar 07 01:45:52 PM PST 24
Finished Mar 07 01:56:49 PM PST 24
Peak memory 200548 kb
Host smart-ff128c35-8cd7-41c9-9113-23c8a3e68229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168490947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1168490947
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2383305741
Short name T1053
Test name
Test status
Simulation time 5738144919 ps
CPU time 10.45 seconds
Started Mar 07 01:45:56 PM PST 24
Finished Mar 07 01:46:07 PM PST 24
Peak memory 198788 kb
Host smart-008b2feb-9b3f-4f5d-9d48-58ac92a445a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383305741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2383305741
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3788784972
Short name T861
Test name
Test status
Simulation time 63668004594 ps
CPU time 114.61 seconds
Started Mar 07 01:45:55 PM PST 24
Finished Mar 07 01:47:50 PM PST 24
Peak memory 200400 kb
Host smart-9fcbc073-1c9e-415c-b968-c2080a711292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788784972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3788784972
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3821375275
Short name T838
Test name
Test status
Simulation time 6494498794 ps
CPU time 369.47 seconds
Started Mar 07 01:45:53 PM PST 24
Finished Mar 07 01:52:02 PM PST 24
Peak memory 200504 kb
Host smart-874235e1-794f-4384-acd2-2575e2c25284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821375275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3821375275
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3638673604
Short name T1012
Test name
Test status
Simulation time 4613240430 ps
CPU time 35.43 seconds
Started Mar 07 01:45:56 PM PST 24
Finished Mar 07 01:46:32 PM PST 24
Peak memory 199236 kb
Host smart-4008b40f-011a-4c2a-add5-590cf054bfde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638673604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3638673604
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2434503939
Short name T1014
Test name
Test status
Simulation time 122748964753 ps
CPU time 105.42 seconds
Started Mar 07 01:45:50 PM PST 24
Finished Mar 07 01:47:35 PM PST 24
Peak memory 200204 kb
Host smart-8172c25e-aca2-4473-aba2-a078c8ef197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434503939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2434503939
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1534375309
Short name T666
Test name
Test status
Simulation time 6199872832 ps
CPU time 3.26 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:45:52 PM PST 24
Peak memory 196372 kb
Host smart-64b12e80-2d65-4930-a6ef-5850d56e7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534375309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1534375309
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1034887038
Short name T8
Test name
Test status
Simulation time 11082584239 ps
CPU time 9.07 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:45:58 PM PST 24
Peak memory 200108 kb
Host smart-acbad494-5658-488d-8ea6-96091f16001f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034887038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1034887038
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1998669008
Short name T434
Test name
Test status
Simulation time 790483070 ps
CPU time 1.68 seconds
Started Mar 07 01:45:53 PM PST 24
Finished Mar 07 01:45:55 PM PST 24
Peak memory 198636 kb
Host smart-233b0d02-e08f-4f1e-bec5-19dac40d6f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998669008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1998669008
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.303775696
Short name T996
Test name
Test status
Simulation time 42803117090 ps
CPU time 33.01 seconds
Started Mar 07 01:45:51 PM PST 24
Finished Mar 07 01:46:24 PM PST 24
Peak memory 200484 kb
Host smart-c5032c0b-a6c0-49c6-923a-401ae825428d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303775696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.303775696
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1385731918
Short name T940
Test name
Test status
Simulation time 11961259 ps
CPU time 0.57 seconds
Started Mar 07 01:45:54 PM PST 24
Finished Mar 07 01:45:55 PM PST 24
Peak memory 195828 kb
Host smart-988c65cf-c3e8-4a63-acb6-3b7d87432f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385731918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1385731918
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.523495209
Short name T656
Test name
Test status
Simulation time 198027563243 ps
CPU time 163.61 seconds
Started Mar 07 01:45:56 PM PST 24
Finished Mar 07 01:48:40 PM PST 24
Peak memory 200528 kb
Host smart-a54ab717-3a75-4f99-a0d7-ff38a25986f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523495209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.523495209
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.852634146
Short name T544
Test name
Test status
Simulation time 194653791856 ps
CPU time 246.12 seconds
Started Mar 07 01:45:47 PM PST 24
Finished Mar 07 01:49:54 PM PST 24
Peak memory 200516 kb
Host smart-91b55058-ed14-46ae-b221-b6de9912dc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852634146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.852634146
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3633421034
Short name T249
Test name
Test status
Simulation time 18087530055 ps
CPU time 15.97 seconds
Started Mar 07 01:45:54 PM PST 24
Finished Mar 07 01:46:10 PM PST 24
Peak memory 200468 kb
Host smart-89603214-5cb0-4294-bd5b-4f09dd1db1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633421034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3633421034
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1802973523
Short name T1091
Test name
Test status
Simulation time 244983779413 ps
CPU time 364.37 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:51:54 PM PST 24
Peak memory 200500 kb
Host smart-69f95e20-450d-4cd4-b2f9-c5afafa910d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802973523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1802973523
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1824215715
Short name T442
Test name
Test status
Simulation time 55839503134 ps
CPU time 208.72 seconds
Started Mar 07 01:45:46 PM PST 24
Finished Mar 07 01:49:16 PM PST 24
Peak memory 200136 kb
Host smart-c0876fa5-20d1-4320-bfa9-770278aee099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824215715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1824215715
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.946371147
Short name T486
Test name
Test status
Simulation time 4216453956 ps
CPU time 5.63 seconds
Started Mar 07 01:45:51 PM PST 24
Finished Mar 07 01:45:57 PM PST 24
Peak memory 198900 kb
Host smart-c5147366-be1c-469a-87df-3f7e3b941f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946371147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.946371147
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.565049751
Short name T891
Test name
Test status
Simulation time 133369031630 ps
CPU time 58.29 seconds
Started Mar 07 01:45:51 PM PST 24
Finished Mar 07 01:46:49 PM PST 24
Peak memory 200392 kb
Host smart-5b75a805-1d0f-441b-ada5-d3a84bee161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565049751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.565049751
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2718046593
Short name T549
Test name
Test status
Simulation time 11226109760 ps
CPU time 170.39 seconds
Started Mar 07 01:45:52 PM PST 24
Finished Mar 07 01:48:42 PM PST 24
Peak memory 200488 kb
Host smart-739b5896-40cc-4a45-a4cd-7d2ef1941fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718046593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2718046593
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1680941935
Short name T1067
Test name
Test status
Simulation time 5813007249 ps
CPU time 11.97 seconds
Started Mar 07 01:45:48 PM PST 24
Finished Mar 07 01:46:00 PM PST 24
Peak memory 198848 kb
Host smart-db173366-4c6f-4d63-b42e-64b997e1d899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1680941935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1680941935
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1829077382
Short name T1078
Test name
Test status
Simulation time 174749514291 ps
CPU time 258.91 seconds
Started Mar 07 01:45:50 PM PST 24
Finished Mar 07 01:50:09 PM PST 24
Peak memory 200164 kb
Host smart-05c862ea-b0df-4e40-a300-90f4fb352976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829077382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1829077382
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1831326242
Short name T688
Test name
Test status
Simulation time 3190378457 ps
CPU time 2.08 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:45:51 PM PST 24
Peak memory 196168 kb
Host smart-b56b5e48-8b27-4a88-a971-3e016da3e01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831326242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1831326242
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.4024502499
Short name T92
Test name
Test status
Simulation time 267272621 ps
CPU time 1.34 seconds
Started Mar 07 01:45:52 PM PST 24
Finished Mar 07 01:45:53 PM PST 24
Peak memory 198468 kb
Host smart-a0244904-7663-4578-9070-aadf4ca4376f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024502499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.4024502499
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2357877883
Short name T971
Test name
Test status
Simulation time 451724385 ps
CPU time 1.01 seconds
Started Mar 07 01:45:51 PM PST 24
Finished Mar 07 01:45:53 PM PST 24
Peak memory 198208 kb
Host smart-1ab7eb64-8d97-47ea-9be0-dc5171e3be55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357877883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2357877883
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2992298097
Short name T751
Test name
Test status
Simulation time 18872770717 ps
CPU time 31.19 seconds
Started Mar 07 01:45:49 PM PST 24
Finished Mar 07 01:46:20 PM PST 24
Peak memory 200540 kb
Host smart-b38fb404-0bb3-46de-8f11-e43eccf4d278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992298097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2992298097
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1630547291
Short name T810
Test name
Test status
Simulation time 29596917 ps
CPU time 0.56 seconds
Started Mar 07 01:45:59 PM PST 24
Finished Mar 07 01:45:59 PM PST 24
Peak memory 196016 kb
Host smart-2d1cb5c0-0d51-480f-abb3-5de2935ff7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630547291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1630547291
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.107713198
Short name T692
Test name
Test status
Simulation time 27245112640 ps
CPU time 12.67 seconds
Started Mar 07 01:46:00 PM PST 24
Finished Mar 07 01:46:13 PM PST 24
Peak memory 200516 kb
Host smart-5f6ecc35-5e75-4c83-8bb9-02826ad66d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107713198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.107713198
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2545204891
Short name T487
Test name
Test status
Simulation time 192498756983 ps
CPU time 68.96 seconds
Started Mar 07 01:45:55 PM PST 24
Finished Mar 07 01:47:04 PM PST 24
Peak memory 199220 kb
Host smart-b597b226-7d24-46d8-ace2-8336720adbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545204891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2545204891
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2003379786
Short name T169
Test name
Test status
Simulation time 12894351090 ps
CPU time 22.25 seconds
Started Mar 07 01:45:54 PM PST 24
Finished Mar 07 01:46:17 PM PST 24
Peak memory 200396 kb
Host smart-881c7d32-8f41-40f6-82f8-ad85cc045973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003379786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2003379786
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1145376740
Short name T428
Test name
Test status
Simulation time 183896802978 ps
CPU time 270.73 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 200360 kb
Host smart-8a19646f-02a0-4485-9144-070777da957b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145376740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1145376740
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.424140719
Short name T801
Test name
Test status
Simulation time 144419999718 ps
CPU time 249.23 seconds
Started Mar 07 01:45:55 PM PST 24
Finished Mar 07 01:50:04 PM PST 24
Peak memory 200432 kb
Host smart-618d781e-47dc-4b35-aa3d-1b99d3068f8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424140719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.424140719
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1085855985
Short name T670
Test name
Test status
Simulation time 4626445500 ps
CPU time 8.38 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:46:06 PM PST 24
Peak memory 199580 kb
Host smart-c2f44fb8-bd05-424c-9b78-4ce31f6158ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085855985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1085855985
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2301507453
Short name T928
Test name
Test status
Simulation time 18102018946 ps
CPU time 30.9 seconds
Started Mar 07 01:46:01 PM PST 24
Finished Mar 07 01:46:32 PM PST 24
Peak memory 198164 kb
Host smart-8b4dd262-6c43-4047-b66c-4bdeed656653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301507453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2301507453
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3786061882
Short name T1026
Test name
Test status
Simulation time 4278693965 ps
CPU time 104.59 seconds
Started Mar 07 01:45:56 PM PST 24
Finished Mar 07 01:47:41 PM PST 24
Peak memory 200564 kb
Host smart-abff9f3c-36c2-44fc-ac11-499fef431912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3786061882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3786061882
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.602190951
Short name T654
Test name
Test status
Simulation time 7497646259 ps
CPU time 5.29 seconds
Started Mar 07 01:45:56 PM PST 24
Finished Mar 07 01:46:01 PM PST 24
Peak memory 199216 kb
Host smart-2ce0cde4-8ba3-476c-be7d-7b0e76bb9118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602190951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.602190951
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1532148011
Short name T663
Test name
Test status
Simulation time 54930823151 ps
CPU time 101.19 seconds
Started Mar 07 01:46:00 PM PST 24
Finished Mar 07 01:47:41 PM PST 24
Peak memory 200484 kb
Host smart-fb82c6a9-b223-4935-88cc-12f23cd6b87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532148011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1532148011
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3614938652
Short name T440
Test name
Test status
Simulation time 35899604952 ps
CPU time 27.17 seconds
Started Mar 07 01:46:01 PM PST 24
Finished Mar 07 01:46:29 PM PST 24
Peak memory 196012 kb
Host smart-7a7afbb5-64f9-4eb6-a300-56ad93000cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614938652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3614938652
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2030373741
Short name T527
Test name
Test status
Simulation time 288499413 ps
CPU time 1.66 seconds
Started Mar 07 01:45:54 PM PST 24
Finished Mar 07 01:45:56 PM PST 24
Peak memory 198832 kb
Host smart-c96df08b-6864-4489-a5a3-81e651ff0e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030373741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2030373741
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1082706383
Short name T52
Test name
Test status
Simulation time 210730022957 ps
CPU time 1091.87 seconds
Started Mar 07 01:45:56 PM PST 24
Finished Mar 07 02:04:09 PM PST 24
Peak memory 217356 kb
Host smart-cfa87f85-bcd3-443f-a0b7-efcba68e5629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082706383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1082706383
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.886478289
Short name T944
Test name
Test status
Simulation time 2181248080 ps
CPU time 2.32 seconds
Started Mar 07 01:45:58 PM PST 24
Finished Mar 07 01:46:01 PM PST 24
Peak memory 198576 kb
Host smart-20df4cfe-3da0-41f8-b769-54cf8ca3a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886478289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.886478289
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3210100855
Short name T521
Test name
Test status
Simulation time 7057790452 ps
CPU time 5.48 seconds
Started Mar 07 01:45:53 PM PST 24
Finished Mar 07 01:45:58 PM PST 24
Peak memory 196456 kb
Host smart-9fb15e0f-7233-4cfa-b0f0-750903355172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210100855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3210100855
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.704359669
Short name T1018
Test name
Test status
Simulation time 11834741 ps
CPU time 0.6 seconds
Started Mar 07 01:45:56 PM PST 24
Finished Mar 07 01:45:57 PM PST 24
Peak memory 195988 kb
Host smart-9e69a8c9-34cf-4831-a29b-d66d8e6faedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704359669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.704359669
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2619186017
Short name T344
Test name
Test status
Simulation time 226748939294 ps
CPU time 101.13 seconds
Started Mar 07 01:45:58 PM PST 24
Finished Mar 07 01:47:39 PM PST 24
Peak memory 200496 kb
Host smart-7fbdb502-3bff-43b5-9a8c-476001e470c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619186017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2619186017
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1906180080
Short name T813
Test name
Test status
Simulation time 73434239841 ps
CPU time 27.53 seconds
Started Mar 07 01:45:55 PM PST 24
Finished Mar 07 01:46:24 PM PST 24
Peak memory 200332 kb
Host smart-a7397d2a-9fc6-4fec-875d-2af0082384a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906180080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1906180080
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1681166585
Short name T301
Test name
Test status
Simulation time 111201192414 ps
CPU time 181.98 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:48:59 PM PST 24
Peak memory 200500 kb
Host smart-cffabcbc-79f8-4d49-b882-858bb0c6b9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681166585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1681166585
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2380478096
Short name T836
Test name
Test status
Simulation time 92039417423 ps
CPU time 42.5 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:46:40 PM PST 24
Peak memory 199680 kb
Host smart-b33aea42-19b9-4a7a-ba03-42ffaa862364
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380478096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2380478096
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.939117176
Short name T504
Test name
Test status
Simulation time 94536855579 ps
CPU time 170.58 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:48:48 PM PST 24
Peak memory 200240 kb
Host smart-398a69d1-e7cb-41ca-8819-50b5d33f8882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939117176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.939117176
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.260666946
Short name T1076
Test name
Test status
Simulation time 6020241657 ps
CPU time 16.13 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:46:14 PM PST 24
Peak memory 198736 kb
Host smart-8c71d57f-7c34-4696-a994-df7fc4062de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260666946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.260666946
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1020873404
Short name T974
Test name
Test status
Simulation time 171802384179 ps
CPU time 128.1 seconds
Started Mar 07 01:46:00 PM PST 24
Finished Mar 07 01:48:09 PM PST 24
Peak memory 200432 kb
Host smart-d7c7f555-c88c-4971-9045-d036c735817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020873404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1020873404
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3216669974
Short name T633
Test name
Test status
Simulation time 9212922731 ps
CPU time 405.55 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:52:43 PM PST 24
Peak memory 200272 kb
Host smart-c5091331-2c3e-421e-920e-a04509dcf0da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216669974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3216669974
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1253497821
Short name T812
Test name
Test status
Simulation time 4894558606 ps
CPU time 21.06 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:46:18 PM PST 24
Peak memory 199300 kb
Host smart-884675ed-abd8-42ed-a0f7-40415a1d5de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253497821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1253497821
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.714258255
Short name T358
Test name
Test status
Simulation time 141002741663 ps
CPU time 196.73 seconds
Started Mar 07 01:45:53 PM PST 24
Finished Mar 07 01:49:11 PM PST 24
Peak memory 199832 kb
Host smart-a7651faf-0910-485a-ab75-c1bdf0a640e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714258255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.714258255
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1686910136
Short name T682
Test name
Test status
Simulation time 4319558953 ps
CPU time 1.98 seconds
Started Mar 07 01:45:55 PM PST 24
Finished Mar 07 01:45:57 PM PST 24
Peak memory 196560 kb
Host smart-624fe1a6-715e-4010-abd7-6889f1bcd87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686910136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1686910136
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3154201024
Short name T629
Test name
Test status
Simulation time 667245552 ps
CPU time 2.49 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:46:00 PM PST 24
Peak memory 198776 kb
Host smart-c3c3be43-e6a4-4557-bfa5-16a52ead447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154201024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3154201024
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.273157522
Short name T898
Test name
Test status
Simulation time 414269803720 ps
CPU time 715.28 seconds
Started Mar 07 01:45:54 PM PST 24
Finished Mar 07 01:57:50 PM PST 24
Peak memory 200556 kb
Host smart-5209f4e6-4b82-4115-9fed-f29155fb1077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273157522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.273157522
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.4071445239
Short name T982
Test name
Test status
Simulation time 6573071656 ps
CPU time 31.05 seconds
Started Mar 07 01:45:57 PM PST 24
Finished Mar 07 01:46:28 PM PST 24
Peak memory 199980 kb
Host smart-7e1d286e-ea61-40c5-a0d0-f4971db1944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071445239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.4071445239
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2533979512
Short name T870
Test name
Test status
Simulation time 48416384471 ps
CPU time 45.82 seconds
Started Mar 07 01:45:54 PM PST 24
Finished Mar 07 01:46:41 PM PST 24
Peak memory 200536 kb
Host smart-5fd3a9f0-1f55-454a-ba7f-e4d7a6f94eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533979512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2533979512
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1625173297
Short name T795
Test name
Test status
Simulation time 14443331 ps
CPU time 0.55 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:44:00 PM PST 24
Peak memory 195048 kb
Host smart-1a680e71-32d6-41aa-846d-dd4b1c7f49a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625173297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1625173297
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3319151742
Short name T909
Test name
Test status
Simulation time 139669067396 ps
CPU time 102.42 seconds
Started Mar 07 01:43:55 PM PST 24
Finished Mar 07 01:45:38 PM PST 24
Peak memory 200520 kb
Host smart-ee8e69a5-c450-41fa-8194-8d0d77cbcfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319151742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3319151742
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3655431324
Short name T44
Test name
Test status
Simulation time 58396332357 ps
CPU time 21.43 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:21 PM PST 24
Peak memory 199652 kb
Host smart-ba6c3b40-be11-4317-8e85-83a37b4236a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655431324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3655431324
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.63728759
Short name T1029
Test name
Test status
Simulation time 109697916088 ps
CPU time 15.23 seconds
Started Mar 07 01:43:55 PM PST 24
Finished Mar 07 01:44:11 PM PST 24
Peak memory 200516 kb
Host smart-542aa606-e8ac-4d9b-b723-e3f609863210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63728759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.63728759
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3794477506
Short name T734
Test name
Test status
Simulation time 853182362074 ps
CPU time 1224.46 seconds
Started Mar 07 01:43:56 PM PST 24
Finished Mar 07 02:04:21 PM PST 24
Peak memory 199856 kb
Host smart-59487c1b-9c98-4872-bd13-eefdbd61d52b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794477506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3794477506
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2138223403
Short name T771
Test name
Test status
Simulation time 153896452690 ps
CPU time 179.89 seconds
Started Mar 07 01:43:56 PM PST 24
Finished Mar 07 01:46:56 PM PST 24
Peak memory 200508 kb
Host smart-0776a7be-0ed6-4305-969e-9ff967beac4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138223403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2138223403
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1468915975
Short name T970
Test name
Test status
Simulation time 10051931703 ps
CPU time 6.41 seconds
Started Mar 07 01:43:56 PM PST 24
Finished Mar 07 01:44:03 PM PST 24
Peak memory 199276 kb
Host smart-a2afd5f5-0cb4-4bcc-b5aa-433a3129abfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468915975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1468915975
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1049928857
Short name T641
Test name
Test status
Simulation time 61176311527 ps
CPU time 31.36 seconds
Started Mar 07 01:43:56 PM PST 24
Finished Mar 07 01:44:28 PM PST 24
Peak memory 200712 kb
Host smart-a085325b-e79b-45f0-917a-125fbdc61d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049928857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1049928857
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3394312152
Short name T854
Test name
Test status
Simulation time 13329138994 ps
CPU time 189.3 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:47:06 PM PST 24
Peak memory 200516 kb
Host smart-a1f0f16b-bee7-4e57-8f0d-44f8fb13084d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394312152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3394312152
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.657883005
Short name T517
Test name
Test status
Simulation time 2885834699 ps
CPU time 4.94 seconds
Started Mar 07 01:43:55 PM PST 24
Finished Mar 07 01:44:00 PM PST 24
Peak memory 198972 kb
Host smart-96eb0c25-758e-4c19-8cd9-af96815c4d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657883005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.657883005
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3979601991
Short name T1065
Test name
Test status
Simulation time 18649895643 ps
CPU time 30.68 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:44:30 PM PST 24
Peak memory 200040 kb
Host smart-892b8bfe-df61-4c8e-862d-24bc3359e8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979601991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3979601991
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.384791570
Short name T646
Test name
Test status
Simulation time 491387458 ps
CPU time 1.33 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:01 PM PST 24
Peak memory 195852 kb
Host smart-0f78947f-51e7-4339-9778-0f28d6557bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384791570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.384791570
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3806469570
Short name T30
Test name
Test status
Simulation time 692621987 ps
CPU time 0.92 seconds
Started Mar 07 01:44:01 PM PST 24
Finished Mar 07 01:44:02 PM PST 24
Peak memory 217864 kb
Host smart-d7fbcbc2-c615-4302-9199-3c0211a4a067
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806469570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3806469570
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1949465826
Short name T607
Test name
Test status
Simulation time 490036465 ps
CPU time 2.2 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:43:59 PM PST 24
Peak memory 198332 kb
Host smart-dc776e3e-a69e-4b25-9d8e-59e2bdd070ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949465826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1949465826
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1634940834
Short name T1006
Test name
Test status
Simulation time 2442384667056 ps
CPU time 4529.7 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 02:59:29 PM PST 24
Peak memory 200620 kb
Host smart-00365d12-92ab-45b7-ab70-4c1bb95860d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634940834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1634940834
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.296997919
Short name T851
Test name
Test status
Simulation time 707697334 ps
CPU time 2 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:03 PM PST 24
Peak memory 198684 kb
Host smart-24164e23-7d5c-413b-bf37-3de2f8d3e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296997919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.296997919
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3786116550
Short name T112
Test name
Test status
Simulation time 16642727005 ps
CPU time 11.75 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:13 PM PST 24
Peak memory 200436 kb
Host smart-c4cec65f-bf56-4954-9fb5-556e9e00abf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786116550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3786116550
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.504036755
Short name T684
Test name
Test status
Simulation time 17136803 ps
CPU time 0.55 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:46:06 PM PST 24
Peak memory 195040 kb
Host smart-c1630a36-7c1d-48ab-9a8b-858312c70357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504036755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.504036755
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.509790963
Short name T713
Test name
Test status
Simulation time 91914085129 ps
CPU time 60.07 seconds
Started Mar 07 01:46:05 PM PST 24
Finished Mar 07 01:47:06 PM PST 24
Peak memory 200496 kb
Host smart-35d112d1-6045-4fe8-af30-2b52d6706a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509790963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.509790963
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3491386677
Short name T912
Test name
Test status
Simulation time 27509068215 ps
CPU time 14.3 seconds
Started Mar 07 01:46:07 PM PST 24
Finished Mar 07 01:46:21 PM PST 24
Peak memory 198572 kb
Host smart-8a4897fa-fdf4-4381-9ffb-dcf40ff0e286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491386677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3491386677
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3890085818
Short name T667
Test name
Test status
Simulation time 26265609363 ps
CPU time 39.82 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:46:46 PM PST 24
Peak memory 200588 kb
Host smart-41b5ccb1-1ea4-4405-947c-1bed74f0c501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890085818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3890085818
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1483531179
Short name T587
Test name
Test status
Simulation time 279665797343 ps
CPU time 248.95 seconds
Started Mar 07 01:46:07 PM PST 24
Finished Mar 07 01:50:16 PM PST 24
Peak memory 200588 kb
Host smart-dfdc5e26-2438-44e7-9cc9-e9c4ab4b281f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483531179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1483531179
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.390020898
Short name T857
Test name
Test status
Simulation time 174658277196 ps
CPU time 352.41 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:51:58 PM PST 24
Peak memory 200532 kb
Host smart-3a5d26ef-b038-42ba-8655-a8863849aac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390020898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.390020898
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3649979850
Short name T1033
Test name
Test status
Simulation time 60141815010 ps
CPU time 107.67 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:47:54 PM PST 24
Peak memory 199216 kb
Host smart-ed02cf0e-7649-453e-9d85-d7fe084fbe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649979850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3649979850
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3175992984
Short name T1081
Test name
Test status
Simulation time 15837044628 ps
CPU time 548.1 seconds
Started Mar 07 01:46:07 PM PST 24
Finished Mar 07 01:55:15 PM PST 24
Peak memory 200524 kb
Host smart-797ea97f-d1b1-498c-940b-f79d0e0515b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175992984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3175992984
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2045092949
Short name T720
Test name
Test status
Simulation time 5939153573 ps
CPU time 53.05 seconds
Started Mar 07 01:46:07 PM PST 24
Finished Mar 07 01:47:00 PM PST 24
Peak memory 198928 kb
Host smart-b808f064-c714-423f-b080-7eb4941a661d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045092949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2045092949
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1375295362
Short name T401
Test name
Test status
Simulation time 4822331277 ps
CPU time 7.21 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:46:13 PM PST 24
Peak memory 196264 kb
Host smart-f21b2c75-6ca6-4864-b276-ebe666f874a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375295362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1375295362
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2318890960
Short name T803
Test name
Test status
Simulation time 6252041974 ps
CPU time 9.82 seconds
Started Mar 07 01:46:09 PM PST 24
Finished Mar 07 01:46:19 PM PST 24
Peak memory 199936 kb
Host smart-5d78cf5a-8381-4468-8d56-a3c199879078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318890960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2318890960
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.217598471
Short name T545
Test name
Test status
Simulation time 147858291636 ps
CPU time 340.36 seconds
Started Mar 07 01:46:09 PM PST 24
Finished Mar 07 01:51:50 PM PST 24
Peak memory 208932 kb
Host smart-481cf4e0-d4f6-41cd-b9b3-f3a6d84cde23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217598471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.217598471
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1412033725
Short name T908
Test name
Test status
Simulation time 1400012000 ps
CPU time 2.04 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:46:09 PM PST 24
Peak memory 198912 kb
Host smart-ca8a8763-f30f-449f-ba40-728997483f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412033725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1412033725
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3005271428
Short name T1041
Test name
Test status
Simulation time 85615537028 ps
CPU time 58.44 seconds
Started Mar 07 01:46:09 PM PST 24
Finished Mar 07 01:47:08 PM PST 24
Peak memory 200532 kb
Host smart-6508f817-b952-48a3-8c78-9c5033013316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005271428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3005271428
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2863070733
Short name T1034
Test name
Test status
Simulation time 11590711 ps
CPU time 0.55 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:46:16 PM PST 24
Peak memory 195924 kb
Host smart-ff448b10-05f0-48b2-bf6d-957e951964d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863070733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2863070733
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1515393899
Short name T876
Test name
Test status
Simulation time 292383577949 ps
CPU time 207.54 seconds
Started Mar 07 01:46:05 PM PST 24
Finished Mar 07 01:49:33 PM PST 24
Peak memory 200604 kb
Host smart-11998d91-7e65-4293-83e5-8da90a6fb1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515393899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1515393899
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1592605199
Short name T277
Test name
Test status
Simulation time 17829444111 ps
CPU time 28.38 seconds
Started Mar 07 01:46:05 PM PST 24
Finished Mar 07 01:46:33 PM PST 24
Peak memory 200408 kb
Host smart-90fae5a8-2f84-4fad-afb1-f2a643661f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592605199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1592605199
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1034415727
Short name T333
Test name
Test status
Simulation time 117632269696 ps
CPU time 74.24 seconds
Started Mar 07 01:46:07 PM PST 24
Finished Mar 07 01:47:21 PM PST 24
Peak memory 200564 kb
Host smart-67469ea0-280a-4404-b44b-90439d170d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034415727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1034415727
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1208976601
Short name T496
Test name
Test status
Simulation time 116027416281 ps
CPU time 91.03 seconds
Started Mar 07 01:46:11 PM PST 24
Finished Mar 07 01:47:42 PM PST 24
Peak memory 198960 kb
Host smart-a00f1956-736e-49d8-ad26-13797062d6ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208976601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1208976601
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1440229440
Short name T498
Test name
Test status
Simulation time 137652747560 ps
CPU time 574.38 seconds
Started Mar 07 01:46:07 PM PST 24
Finished Mar 07 01:55:41 PM PST 24
Peak memory 200536 kb
Host smart-526455c9-807f-4da8-b4f6-e06e09e930f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1440229440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1440229440
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3300213511
Short name T917
Test name
Test status
Simulation time 43746679 ps
CPU time 0.56 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:46:07 PM PST 24
Peak memory 195972 kb
Host smart-196fe850-db3e-4098-be06-c9d9703a48be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300213511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3300213511
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2302213415
Short name T637
Test name
Test status
Simulation time 20275398421 ps
CPU time 14.98 seconds
Started Mar 07 01:46:05 PM PST 24
Finished Mar 07 01:46:21 PM PST 24
Peak memory 195256 kb
Host smart-152fb403-ea23-4b82-be86-e028a6d40982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302213415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2302213415
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.4028865276
Short name T1100
Test name
Test status
Simulation time 20013672361 ps
CPU time 562.13 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:55:28 PM PST 24
Peak memory 200476 kb
Host smart-3cd8a2ab-7b8e-4707-a8f2-e890c0d7f952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028865276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4028865276
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.623471139
Short name T754
Test name
Test status
Simulation time 5826711242 ps
CPU time 47.35 seconds
Started Mar 07 01:46:07 PM PST 24
Finished Mar 07 01:46:54 PM PST 24
Peak memory 198944 kb
Host smart-d40f9e20-9f3a-41cd-a9b9-51ef362a3aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623471139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.623471139
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.750974081
Short name T172
Test name
Test status
Simulation time 34647082177 ps
CPU time 17.34 seconds
Started Mar 07 01:46:06 PM PST 24
Finished Mar 07 01:46:23 PM PST 24
Peak memory 199656 kb
Host smart-4345ca8a-8d26-4013-9454-b42f606b98eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750974081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.750974081
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2510247019
Short name T564
Test name
Test status
Simulation time 2069628939 ps
CPU time 1.43 seconds
Started Mar 07 01:46:08 PM PST 24
Finished Mar 07 01:46:10 PM PST 24
Peak memory 195908 kb
Host smart-69f26f26-d8c8-4600-9c3d-bb7ed6800569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510247019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2510247019
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3338725521
Short name T575
Test name
Test status
Simulation time 295893890 ps
CPU time 1.04 seconds
Started Mar 07 01:46:09 PM PST 24
Finished Mar 07 01:46:10 PM PST 24
Peak memory 198256 kb
Host smart-e17cfa06-fad9-42d3-9a6b-3cde8fd9fa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338725521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3338725521
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1555892722
Short name T605
Test name
Test status
Simulation time 774586439114 ps
CPU time 916.19 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 02:01:33 PM PST 24
Peak memory 200540 kb
Host smart-28c0fba5-697a-4a82-b2d8-aa281b46b9a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555892722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1555892722
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2346886121
Short name T497
Test name
Test status
Simulation time 6966659851 ps
CPU time 22.81 seconds
Started Mar 07 01:46:04 PM PST 24
Finished Mar 07 01:46:27 PM PST 24
Peak memory 199176 kb
Host smart-ac396309-a3c9-409c-9f68-e222c4be35c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346886121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2346886121
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2022110860
Short name T1050
Test name
Test status
Simulation time 111247437113 ps
CPU time 213.25 seconds
Started Mar 07 01:46:05 PM PST 24
Finished Mar 07 01:49:38 PM PST 24
Peak memory 200496 kb
Host smart-ba755d67-8243-4703-a9f0-0ad382703058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022110860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2022110860
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4074670152
Short name T907
Test name
Test status
Simulation time 17135117 ps
CPU time 0.57 seconds
Started Mar 07 01:46:17 PM PST 24
Finished Mar 07 01:46:18 PM PST 24
Peak memory 196004 kb
Host smart-3587b8dc-9950-46ef-9a19-6e8886a079c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074670152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4074670152
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.704663855
Short name T314
Test name
Test status
Simulation time 40966850257 ps
CPU time 33.19 seconds
Started Mar 07 01:46:15 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 200572 kb
Host smart-a1e21289-16fa-4afd-8e35-6f64aa0da904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704663855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.704663855
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1027726669
Short name T375
Test name
Test status
Simulation time 248745780459 ps
CPU time 54.68 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:47:10 PM PST 24
Peak memory 200408 kb
Host smart-8bb383a6-e4e5-4d1c-a4a6-0a90ddd20919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027726669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1027726669
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3816867245
Short name T263
Test name
Test status
Simulation time 146052412286 ps
CPU time 204.4 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:49:40 PM PST 24
Peak memory 200088 kb
Host smart-ffeff437-7b88-4389-ba74-e7056e128497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816867245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3816867245
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2729547269
Short name T1010
Test name
Test status
Simulation time 78062013810 ps
CPU time 32.7 seconds
Started Mar 07 01:46:15 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 199028 kb
Host smart-9ad84454-9878-4f37-82c8-313d0686fcc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729547269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2729547269
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3954380250
Short name T729
Test name
Test status
Simulation time 132550075801 ps
CPU time 443.91 seconds
Started Mar 07 01:46:17 PM PST 24
Finished Mar 07 01:53:41 PM PST 24
Peak memory 200436 kb
Host smart-b9567be2-e7cd-49d4-8579-3847a1c3d364
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954380250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3954380250
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.4143990989
Short name T20
Test name
Test status
Simulation time 3996441270 ps
CPU time 2.85 seconds
Started Mar 07 01:46:18 PM PST 24
Finished Mar 07 01:46:21 PM PST 24
Peak memory 198132 kb
Host smart-89b30505-1469-41ed-b3f8-c7764ec5e37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143990989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4143990989
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3979542361
Short name T952
Test name
Test status
Simulation time 93355500190 ps
CPU time 76.3 seconds
Started Mar 07 01:46:15 PM PST 24
Finished Mar 07 01:47:31 PM PST 24
Peak memory 200516 kb
Host smart-e1e4e06f-1302-4ea1-8195-1675e7d2a3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979542361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3979542361
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1782614270
Short name T823
Test name
Test status
Simulation time 21999680568 ps
CPU time 637.57 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:56:55 PM PST 24
Peak memory 200532 kb
Host smart-16b9f33d-4f9a-4554-86a7-c9e7e3491e73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782614270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1782614270
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2272955640
Short name T539
Test name
Test status
Simulation time 6398193955 ps
CPU time 14.61 seconds
Started Mar 07 01:46:15 PM PST 24
Finished Mar 07 01:46:30 PM PST 24
Peak memory 199452 kb
Host smart-b604f7bf-7464-414a-b192-eac715c31301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272955640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2272955640
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4127119384
Short name T978
Test name
Test status
Simulation time 146180200775 ps
CPU time 206.71 seconds
Started Mar 07 01:46:15 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 199836 kb
Host smart-3affc649-d82f-4e76-9ad3-b81f22323cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127119384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4127119384
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3548801663
Short name T802
Test name
Test status
Simulation time 2790198621 ps
CPU time 3.18 seconds
Started Mar 07 01:46:18 PM PST 24
Finished Mar 07 01:46:21 PM PST 24
Peak memory 196072 kb
Host smart-cd213435-9833-44c0-862b-03a2dedbf7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548801663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3548801663
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1185935206
Short name T758
Test name
Test status
Simulation time 920167967 ps
CPU time 2.19 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:46:18 PM PST 24
Peak memory 198952 kb
Host smart-338458d8-6265-4e3e-bb97-d929e23d482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185935206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1185935206
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1750772745
Short name T176
Test name
Test status
Simulation time 67545375610 ps
CPU time 1113.2 seconds
Started Mar 07 01:46:15 PM PST 24
Finished Mar 07 02:04:49 PM PST 24
Peak memory 208872 kb
Host smart-e810aeae-8d9f-4f33-b29f-00bba1bbc653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750772745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1750772745
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.233045418
Short name T677
Test name
Test status
Simulation time 1409953898 ps
CPU time 1.6 seconds
Started Mar 07 01:46:17 PM PST 24
Finished Mar 07 01:46:19 PM PST 24
Peak memory 198740 kb
Host smart-01e912e9-9774-462d-a0f7-12cc1d1fcdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233045418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.233045418
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3130142915
Short name T436
Test name
Test status
Simulation time 56044556046 ps
CPU time 21.14 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:46:38 PM PST 24
Peak memory 200536 kb
Host smart-48116ad5-e797-47a3-be95-8648f4e2ad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130142915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3130142915
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3916630394
Short name T735
Test name
Test status
Simulation time 19835520 ps
CPU time 0.54 seconds
Started Mar 07 01:46:20 PM PST 24
Finished Mar 07 01:46:20 PM PST 24
Peak memory 195976 kb
Host smart-45f8cf71-c683-4132-91a5-d63a34451c72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916630394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3916630394
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2202514041
Short name T495
Test name
Test status
Simulation time 97930401586 ps
CPU time 277.04 seconds
Started Mar 07 01:46:21 PM PST 24
Finished Mar 07 01:50:58 PM PST 24
Peak memory 200580 kb
Host smart-33342dc0-1d1b-4e3e-917c-326139202a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202514041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2202514041
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1470121607
Short name T885
Test name
Test status
Simulation time 32908819454 ps
CPU time 59.34 seconds
Started Mar 07 01:46:17 PM PST 24
Finished Mar 07 01:47:16 PM PST 24
Peak memory 200216 kb
Host smart-5118c35e-aca8-4f3c-9bc9-10a5abede876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470121607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1470121607
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1188130131
Short name T573
Test name
Test status
Simulation time 54446341780 ps
CPU time 228.49 seconds
Started Mar 07 01:46:17 PM PST 24
Finished Mar 07 01:50:06 PM PST 24
Peak memory 200460 kb
Host smart-45ea03b6-a0b0-41c1-80ab-b9cbed8b28cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188130131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1188130131
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3854336048
Short name T827
Test name
Test status
Simulation time 9420296290 ps
CPU time 17.94 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:46:34 PM PST 24
Peak memory 200284 kb
Host smart-e5721e81-9317-4ecb-92a4-a5cb650c25ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854336048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3854336048
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2369670158
Short name T762
Test name
Test status
Simulation time 64681542749 ps
CPU time 28.03 seconds
Started Mar 07 01:46:21 PM PST 24
Finished Mar 07 01:46:49 PM PST 24
Peak memory 199292 kb
Host smart-8c7ef954-9cbb-401e-92c5-6f47ed4a9246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369670158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2369670158
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3211018573
Short name T1095
Test name
Test status
Simulation time 31121837142 ps
CPU time 191.44 seconds
Started Mar 07 01:46:20 PM PST 24
Finished Mar 07 01:49:32 PM PST 24
Peak memory 200552 kb
Host smart-ac1f7822-d1da-431e-8a04-b0e465bb64c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211018573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3211018573
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3964940446
Short name T49
Test name
Test status
Simulation time 5551132276 ps
CPU time 24.03 seconds
Started Mar 07 01:46:19 PM PST 24
Finished Mar 07 01:46:43 PM PST 24
Peak memory 198756 kb
Host smart-8e2ade4f-f63e-4e35-a179-c59fd65dd358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964940446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3964940446
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2933552115
Short name T1045
Test name
Test status
Simulation time 37873603540 ps
CPU time 67.22 seconds
Started Mar 07 01:46:17 PM PST 24
Finished Mar 07 01:47:24 PM PST 24
Peak memory 196436 kb
Host smart-6e949e33-60bb-464b-98f1-049c61542466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933552115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2933552115
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1233217745
Short name T608
Test name
Test status
Simulation time 708050909 ps
CPU time 1.7 seconds
Started Mar 07 01:46:16 PM PST 24
Finished Mar 07 01:46:18 PM PST 24
Peak memory 198800 kb
Host smart-ab0542aa-b504-4d59-8f2e-884eab398551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233217745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1233217745
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2470441952
Short name T988
Test name
Test status
Simulation time 351688719024 ps
CPU time 1126.09 seconds
Started Mar 07 01:46:18 PM PST 24
Finished Mar 07 02:05:04 PM PST 24
Peak memory 200556 kb
Host smart-d20902d3-6fc4-4ac1-9681-0c9afb34ef77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470441952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2470441952
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1324264609
Short name T433
Test name
Test status
Simulation time 6353879640 ps
CPU time 30.82 seconds
Started Mar 07 01:46:17 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 199996 kb
Host smart-cf4870e8-869b-407b-85b6-7a67ef26afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324264609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1324264609
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1193673595
Short name T411
Test name
Test status
Simulation time 25855175310 ps
CPU time 28.96 seconds
Started Mar 07 01:46:19 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 200492 kb
Host smart-42221a3f-6c6c-4dc7-a709-bd07383e5ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193673595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1193673595
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2824031121
Short name T460
Test name
Test status
Simulation time 48702946 ps
CPU time 0.53 seconds
Started Mar 07 01:46:24 PM PST 24
Finished Mar 07 01:46:26 PM PST 24
Peak memory 195972 kb
Host smart-ade9f511-334f-42a6-bc8e-8bd9b6c321bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824031121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2824031121
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4069156408
Short name T899
Test name
Test status
Simulation time 37295074716 ps
CPU time 58.54 seconds
Started Mar 07 01:46:20 PM PST 24
Finished Mar 07 01:47:19 PM PST 24
Peak memory 200544 kb
Host smart-4bc193d0-dcb9-4a8d-932c-85414a6e255d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069156408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4069156408
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1285251396
Short name T781
Test name
Test status
Simulation time 48292177085 ps
CPU time 77.12 seconds
Started Mar 07 01:46:28 PM PST 24
Finished Mar 07 01:47:46 PM PST 24
Peak memory 200500 kb
Host smart-ebc6e209-3836-4dfc-a75d-753803a7bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285251396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1285251396
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.1549628128
Short name T636
Test name
Test status
Simulation time 26327030264 ps
CPU time 19.58 seconds
Started Mar 07 01:46:20 PM PST 24
Finished Mar 07 01:46:40 PM PST 24
Peak memory 197132 kb
Host smart-4b8f065e-0518-4fe6-a13f-907efbeecc6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549628128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1549628128
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2021818681
Short name T953
Test name
Test status
Simulation time 142957303924 ps
CPU time 913.59 seconds
Started Mar 07 01:46:23 PM PST 24
Finished Mar 07 02:01:37 PM PST 24
Peak memory 200468 kb
Host smart-185ebac3-0fe3-4bd2-9ea4-66f0f44b1c9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021818681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2021818681
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3005811835
Short name T461
Test name
Test status
Simulation time 10872972453 ps
CPU time 6.3 seconds
Started Mar 07 01:46:23 PM PST 24
Finished Mar 07 01:46:29 PM PST 24
Peak memory 199048 kb
Host smart-e11e98cb-9c0b-4737-919d-119c73fac25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005811835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3005811835
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2604288713
Short name T583
Test name
Test status
Simulation time 25645456690 ps
CPU time 21.99 seconds
Started Mar 07 01:46:28 PM PST 24
Finished Mar 07 01:46:51 PM PST 24
Peak memory 198088 kb
Host smart-168f1fc3-43fc-4cfe-badf-0f3c730e8a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604288713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2604288713
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3666120134
Short name T535
Test name
Test status
Simulation time 3009322057 ps
CPU time 81.69 seconds
Started Mar 07 01:46:22 PM PST 24
Finished Mar 07 01:47:44 PM PST 24
Peak memory 200536 kb
Host smart-7dfd64de-ea72-4921-b00a-7f669fe43a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666120134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3666120134
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3379266526
Short name T797
Test name
Test status
Simulation time 1699023607 ps
CPU time 6.09 seconds
Started Mar 07 01:46:19 PM PST 24
Finished Mar 07 01:46:25 PM PST 24
Peak memory 198680 kb
Host smart-3207cc16-a387-47f4-bef4-43c04b3be7d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3379266526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3379266526
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.7639140
Short name T1028
Test name
Test status
Simulation time 5018102643 ps
CPU time 4.89 seconds
Started Mar 07 01:46:20 PM PST 24
Finished Mar 07 01:46:25 PM PST 24
Peak memory 196384 kb
Host smart-78d2fddb-b98c-4ee7-9dfa-96f355885212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7639140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.7639140
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2482859506
Short name T588
Test name
Test status
Simulation time 5987220310 ps
CPU time 16.56 seconds
Started Mar 07 01:46:18 PM PST 24
Finished Mar 07 01:46:34 PM PST 24
Peak memory 199928 kb
Host smart-411cdc74-69d7-41ce-9bb6-000d09de256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482859506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2482859506
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3122178261
Short name T537
Test name
Test status
Simulation time 438377518 ps
CPU time 1.49 seconds
Started Mar 07 01:46:28 PM PST 24
Finished Mar 07 01:46:31 PM PST 24
Peak memory 198516 kb
Host smart-977140b8-021c-4b29-9a11-be42cb3a13a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122178261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3122178261
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.903964524
Short name T779
Test name
Test status
Simulation time 61425718282 ps
CPU time 103.73 seconds
Started Mar 07 01:46:20 PM PST 24
Finished Mar 07 01:48:04 PM PST 24
Peak memory 200520 kb
Host smart-0ec0fe06-8f14-4192-bcac-bf7edf02d338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903964524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.903964524
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3108098420
Short name T597
Test name
Test status
Simulation time 20896964 ps
CPU time 0.54 seconds
Started Mar 07 01:46:24 PM PST 24
Finished Mar 07 01:46:25 PM PST 24
Peak memory 195984 kb
Host smart-cafdc0d1-7b8e-4fb7-bb63-114611f23744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108098420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3108098420
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.283079099
Short name T404
Test name
Test status
Simulation time 27400541502 ps
CPU time 30.89 seconds
Started Mar 07 01:46:23 PM PST 24
Finished Mar 07 01:46:54 PM PST 24
Peak memory 200540 kb
Host smart-984b6ee2-10f3-4763-b98e-94888b15ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283079099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.283079099
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1668506214
Short name T967
Test name
Test status
Simulation time 17651931132 ps
CPU time 31.37 seconds
Started Mar 07 01:46:24 PM PST 24
Finished Mar 07 01:46:56 PM PST 24
Peak memory 199536 kb
Host smart-f212bc4c-afff-4810-9751-20b150629270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668506214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1668506214
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2818025567
Short name T148
Test name
Test status
Simulation time 60591365061 ps
CPU time 77.68 seconds
Started Mar 07 01:46:24 PM PST 24
Finished Mar 07 01:47:43 PM PST 24
Peak memory 200616 kb
Host smart-e8b22894-febb-4821-b496-24ff95def91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818025567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2818025567
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.430258068
Short name T790
Test name
Test status
Simulation time 571057200493 ps
CPU time 717.07 seconds
Started Mar 07 01:46:25 PM PST 24
Finished Mar 07 01:58:23 PM PST 24
Peak memory 198636 kb
Host smart-924e951d-79d3-4967-b9b4-d3ff5bf8e4bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430258068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.430258068
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.308931223
Short name T522
Test name
Test status
Simulation time 90300843307 ps
CPU time 616.99 seconds
Started Mar 07 01:46:38 PM PST 24
Finished Mar 07 01:56:55 PM PST 24
Peak memory 200584 kb
Host smart-c6e992d6-ea99-41a9-b51d-be7e55be0df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308931223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.308931223
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1678458061
Short name T469
Test name
Test status
Simulation time 5553424804 ps
CPU time 10.2 seconds
Started Mar 07 01:46:25 PM PST 24
Finished Mar 07 01:46:35 PM PST 24
Peak memory 199004 kb
Host smart-3c0d14b6-fdb5-41e7-bf26-4be5444fb5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678458061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1678458061
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1891898380
Short name T644
Test name
Test status
Simulation time 49066180780 ps
CPU time 19.96 seconds
Started Mar 07 01:46:26 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 194460 kb
Host smart-efad092b-ec4c-47d3-9a75-c9625241076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891898380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1891898380
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3018961430
Short name T1069
Test name
Test status
Simulation time 30639249650 ps
CPU time 1662.41 seconds
Started Mar 07 01:46:23 PM PST 24
Finished Mar 07 02:14:06 PM PST 24
Peak memory 200604 kb
Host smart-34b19d3c-9b16-4a64-8d74-0744c6c0201d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018961430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3018961430
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2794604820
Short name T973
Test name
Test status
Simulation time 5878245526 ps
CPU time 52.35 seconds
Started Mar 07 01:46:24 PM PST 24
Finished Mar 07 01:47:17 PM PST 24
Peak memory 199284 kb
Host smart-0d22a570-b159-4e72-afb9-ded9679f9970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794604820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2794604820
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2473964682
Short name T345
Test name
Test status
Simulation time 276591054267 ps
CPU time 229.16 seconds
Started Mar 07 01:46:24 PM PST 24
Finished Mar 07 01:50:14 PM PST 24
Peak memory 200544 kb
Host smart-b850128b-87c5-4fc1-85a0-43b3b568f932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473964682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2473964682
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4120625248
Short name T668
Test name
Test status
Simulation time 37645305819 ps
CPU time 64.98 seconds
Started Mar 07 01:46:24 PM PST 24
Finished Mar 07 01:47:30 PM PST 24
Peak memory 196000 kb
Host smart-04327a4e-ed7e-4e8d-8973-64d27cb9eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120625248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4120625248
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2502194771
Short name T871
Test name
Test status
Simulation time 669361450 ps
CPU time 3.12 seconds
Started Mar 07 01:46:25 PM PST 24
Finished Mar 07 01:46:29 PM PST 24
Peak memory 198800 kb
Host smart-2b39d76a-863d-4b78-8045-d9aaf8117bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502194771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2502194771
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1130468045
Short name T604
Test name
Test status
Simulation time 64856767263 ps
CPU time 301.22 seconds
Started Mar 07 01:46:26 PM PST 24
Finished Mar 07 01:51:28 PM PST 24
Peak memory 209000 kb
Host smart-4be654c4-50a5-4402-b82f-dd01cc3958cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130468045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1130468045
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2885178499
Short name T35
Test name
Test status
Simulation time 11482252126 ps
CPU time 128 seconds
Started Mar 07 01:46:26 PM PST 24
Finished Mar 07 01:48:36 PM PST 24
Peak memory 216544 kb
Host smart-aba893c6-9ae5-4b4a-8203-35c3527f525e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885178499 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2885178499
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1278915156
Short name T934
Test name
Test status
Simulation time 7629552229 ps
CPU time 13.04 seconds
Started Mar 07 01:46:23 PM PST 24
Finished Mar 07 01:46:36 PM PST 24
Peak memory 200000 kb
Host smart-82c102ad-4849-4f5e-9f3a-8c3defe68ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278915156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1278915156
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1907632089
Short name T853
Test name
Test status
Simulation time 196283560751 ps
CPU time 39.49 seconds
Started Mar 07 01:46:25 PM PST 24
Finished Mar 07 01:47:05 PM PST 24
Peak memory 200584 kb
Host smart-322cfcc1-3873-49ef-9adc-6a1287786b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907632089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1907632089
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.838388458
Short name T765
Test name
Test status
Simulation time 14884995 ps
CPU time 0.64 seconds
Started Mar 07 01:46:29 PM PST 24
Finished Mar 07 01:46:31 PM PST 24
Peak memory 195992 kb
Host smart-df0f0c93-4d30-4426-8e97-71dcc9801f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838388458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.838388458
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2437528491
Short name T807
Test name
Test status
Simulation time 29307924946 ps
CPU time 53.56 seconds
Started Mar 07 01:46:28 PM PST 24
Finished Mar 07 01:47:22 PM PST 24
Peak memory 200604 kb
Host smart-b2297673-dbda-43dc-b516-614fba9106a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437528491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2437528491
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1019258542
Short name T387
Test name
Test status
Simulation time 27505188611 ps
CPU time 11.33 seconds
Started Mar 07 01:46:25 PM PST 24
Finished Mar 07 01:46:37 PM PST 24
Peak memory 199500 kb
Host smart-67bdc723-c488-41ea-9620-12c16facd161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019258542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1019258542
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2541386799
Short name T1096
Test name
Test status
Simulation time 39832964940 ps
CPU time 19.78 seconds
Started Mar 07 01:46:27 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 200304 kb
Host smart-9be561a8-1872-4169-ad14-4d7977b026a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541386799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2541386799
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3800778471
Short name T164
Test name
Test status
Simulation time 587100525162 ps
CPU time 229.44 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:50:29 PM PST 24
Peak memory 200488 kb
Host smart-72590962-4760-4f52-9d38-4e09c473bcce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800778471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3800778471
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1333299271
Short name T547
Test name
Test status
Simulation time 52417746760 ps
CPU time 228.71 seconds
Started Mar 07 01:46:25 PM PST 24
Finished Mar 07 01:50:15 PM PST 24
Peak memory 200488 kb
Host smart-43dc2979-eb60-4028-832a-cc38f21b6c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333299271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1333299271
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1621539169
Short name T550
Test name
Test status
Simulation time 2388028254 ps
CPU time 1.48 seconds
Started Mar 07 01:46:27 PM PST 24
Finished Mar 07 01:46:29 PM PST 24
Peak memory 197392 kb
Host smart-76f7b002-99eb-4540-91fc-e7e0c238b889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621539169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1621539169
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.392673616
Short name T645
Test name
Test status
Simulation time 151841314626 ps
CPU time 70.96 seconds
Started Mar 07 01:46:28 PM PST 24
Finished Mar 07 01:47:40 PM PST 24
Peak memory 200320 kb
Host smart-8e520008-0b2b-4ba7-9bbd-c56a2c21f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392673616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.392673616
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1031712359
Short name T1023
Test name
Test status
Simulation time 10325431354 ps
CPU time 313.62 seconds
Started Mar 07 01:46:38 PM PST 24
Finished Mar 07 01:51:52 PM PST 24
Peak memory 200524 kb
Host smart-19b46744-3357-44f6-9c85-a365a2e4210f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031712359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1031712359
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1988786120
Short name T456
Test name
Test status
Simulation time 2045998533 ps
CPU time 1.58 seconds
Started Mar 07 01:46:32 PM PST 24
Finished Mar 07 01:46:34 PM PST 24
Peak memory 198248 kb
Host smart-8c65990e-2cd0-48f2-a895-fb2fef8324bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988786120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1988786120
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4266221917
Short name T415
Test name
Test status
Simulation time 50207736107 ps
CPU time 60.35 seconds
Started Mar 07 01:46:24 PM PST 24
Finished Mar 07 01:47:25 PM PST 24
Peak memory 200512 kb
Host smart-7122662f-e0fd-428f-8d48-3de8a723de96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266221917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4266221917
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.4280219393
Short name T1040
Test name
Test status
Simulation time 51713680041 ps
CPU time 20.01 seconds
Started Mar 07 01:46:38 PM PST 24
Finished Mar 07 01:46:58 PM PST 24
Peak memory 196300 kb
Host smart-64b99a19-a34f-4dbc-bf15-f259fc119df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280219393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.4280219393
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.208760056
Short name T624
Test name
Test status
Simulation time 566339150 ps
CPU time 1.72 seconds
Started Mar 07 01:46:37 PM PST 24
Finished Mar 07 01:46:39 PM PST 24
Peak memory 198652 kb
Host smart-7ec2bcd1-b689-409c-94d8-4c52136e7999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208760056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.208760056
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1415702793
Short name T524
Test name
Test status
Simulation time 499207459 ps
CPU time 2.23 seconds
Started Mar 07 01:46:28 PM PST 24
Finished Mar 07 01:46:31 PM PST 24
Peak memory 199052 kb
Host smart-3374f0be-68e1-43ee-9dc6-1dcb183d3992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415702793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1415702793
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.372558569
Short name T919
Test name
Test status
Simulation time 66292159974 ps
CPU time 133.81 seconds
Started Mar 07 01:46:37 PM PST 24
Finished Mar 07 01:48:51 PM PST 24
Peak memory 200372 kb
Host smart-b4df1f7e-e88b-4d8b-a280-cb70e34cb228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372558569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.372558569
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1403190007
Short name T1042
Test name
Test status
Simulation time 16696601 ps
CPU time 0.56 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:46:40 PM PST 24
Peak memory 194892 kb
Host smart-d11091eb-fe9e-4ba9-a5c7-2034274f0c67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403190007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1403190007
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.4267424556
Short name T533
Test name
Test status
Simulation time 66668988531 ps
CPU time 26.85 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:47:06 PM PST 24
Peak memory 200448 kb
Host smart-ec6815e2-d162-4a8c-94db-f9153efaba76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267424556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4267424556
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.997262767
Short name T371
Test name
Test status
Simulation time 138045839037 ps
CPU time 54.57 seconds
Started Mar 07 01:46:37 PM PST 24
Finished Mar 07 01:47:32 PM PST 24
Peak memory 200512 kb
Host smart-5a3eccdd-cace-467e-a216-1babc9b3e604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997262767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.997262767
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1084358276
Short name T736
Test name
Test status
Simulation time 10667792093 ps
CPU time 18.92 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:46:58 PM PST 24
Peak memory 200536 kb
Host smart-b19d2c74-3bbc-43f3-ace7-eaad754d15da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084358276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1084358276
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.636327458
Short name T875
Test name
Test status
Simulation time 134503212741 ps
CPU time 100.32 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:48:20 PM PST 24
Peak memory 200436 kb
Host smart-d536255f-ffae-4851-ac43-84f183c2b8c2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636327458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.636327458
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3959948258
Short name T942
Test name
Test status
Simulation time 204810092342 ps
CPU time 280.53 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:51:20 PM PST 24
Peak memory 200556 kb
Host smart-0bb7eb0b-e652-40cd-8197-3b085df656fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959948258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3959948258
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.128571625
Short name T50
Test name
Test status
Simulation time 11384970489 ps
CPU time 7.59 seconds
Started Mar 07 01:46:40 PM PST 24
Finished Mar 07 01:46:48 PM PST 24
Peak memory 198840 kb
Host smart-4d19bd45-7f3d-4c7f-9c8a-16741f7ee7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128571625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.128571625
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.4091804982
Short name T819
Test name
Test status
Simulation time 146076642667 ps
CPU time 160.81 seconds
Started Mar 07 01:46:28 PM PST 24
Finished Mar 07 01:49:10 PM PST 24
Peak memory 199960 kb
Host smart-2950ef7a-39f7-405d-bed8-00305a8c22c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091804982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.4091804982
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.228325202
Short name T874
Test name
Test status
Simulation time 12219515487 ps
CPU time 722.63 seconds
Started Mar 07 01:46:40 PM PST 24
Finished Mar 07 01:58:43 PM PST 24
Peak memory 200552 kb
Host smart-1c39b3fa-de58-4103-a4aa-9bf9dabbd264
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228325202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.228325202
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.578721510
Short name T737
Test name
Test status
Simulation time 7430612452 ps
CPU time 66.46 seconds
Started Mar 07 01:46:27 PM PST 24
Finished Mar 07 01:47:34 PM PST 24
Peak memory 199368 kb
Host smart-f10a6555-05a1-4acc-bf08-c0e0fc580184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578721510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.578721510
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2357409435
Short name T379
Test name
Test status
Simulation time 28484509066 ps
CPU time 45.5 seconds
Started Mar 07 01:46:35 PM PST 24
Finished Mar 07 01:47:21 PM PST 24
Peak memory 199396 kb
Host smart-ec6f7146-308f-40bd-8d13-48ab12a4d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357409435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2357409435
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1726504169
Short name T918
Test name
Test status
Simulation time 443871678 ps
CPU time 1.36 seconds
Started Mar 07 01:46:31 PM PST 24
Finished Mar 07 01:46:33 PM PST 24
Peak memory 195836 kb
Host smart-cddc8f87-e81c-45e7-b54a-d0347ad368f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726504169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1726504169
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.842005376
Short name T595
Test name
Test status
Simulation time 5684081390 ps
CPU time 7.92 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:46:47 PM PST 24
Peak memory 199324 kb
Host smart-2bef82f6-eb59-45ff-9857-d789ecc96aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842005376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.842005376
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2841098577
Short name T733
Test name
Test status
Simulation time 228372794136 ps
CPU time 82.51 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:48:02 PM PST 24
Peak memory 200504 kb
Host smart-30f9cf05-3c8e-45ce-8f7a-968b84cb7023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841098577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2841098577
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2791104948
Short name T690
Test name
Test status
Simulation time 1829276487 ps
CPU time 2.22 seconds
Started Mar 07 01:46:41 PM PST 24
Finished Mar 07 01:46:44 PM PST 24
Peak memory 198352 kb
Host smart-d9f2f00d-2e1a-4477-87ee-5564bc93d102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791104948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2791104948
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.37645630
Short name T990
Test name
Test status
Simulation time 63774799085 ps
CPU time 102.68 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:48:22 PM PST 24
Peak memory 200572 kb
Host smart-7bcf0355-b48a-4086-a884-c0996001c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37645630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.37645630
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.672221630
Short name T981
Test name
Test status
Simulation time 11371045 ps
CPU time 0.55 seconds
Started Mar 07 01:46:40 PM PST 24
Finished Mar 07 01:46:41 PM PST 24
Peak memory 195944 kb
Host smart-b16c9906-44fc-4781-8daa-6b63fa2f544a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672221630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.672221630
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.418647700
Short name T936
Test name
Test status
Simulation time 56506714241 ps
CPU time 34.33 seconds
Started Mar 07 01:46:37 PM PST 24
Finished Mar 07 01:47:12 PM PST 24
Peak memory 200584 kb
Host smart-8f785165-254d-4898-8c55-ccd732a0733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418647700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.418647700
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.7478719
Short name T1094
Test name
Test status
Simulation time 27171602084 ps
CPU time 35.16 seconds
Started Mar 07 01:46:34 PM PST 24
Finished Mar 07 01:47:09 PM PST 24
Peak memory 200424 kb
Host smart-4ba0116b-08aa-48f5-a725-05165d26cf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7478719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.7478719
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.2866247940
Short name T96
Test name
Test status
Simulation time 333959682842 ps
CPU time 61.84 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:47:45 PM PST 24
Peak memory 198816 kb
Host smart-ed99d593-f365-4860-9ef3-847d9b5bf39c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866247940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2866247940
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_loopback.2297406505
Short name T513
Test name
Test status
Simulation time 6371722672 ps
CPU time 4.22 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:46:47 PM PST 24
Peak memory 199072 kb
Host smart-b59db4c9-b778-4972-bad0-359878c7f101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297406505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2297406505
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2953103418
Short name T579
Test name
Test status
Simulation time 75038468890 ps
CPU time 60.23 seconds
Started Mar 07 01:46:41 PM PST 24
Finished Mar 07 01:47:41 PM PST 24
Peak memory 198212 kb
Host smart-44aa1775-28da-4121-9295-874c41f2d8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953103418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2953103418
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3072115814
Short name T430
Test name
Test status
Simulation time 15776474549 ps
CPU time 664.09 seconds
Started Mar 07 01:46:40 PM PST 24
Finished Mar 07 01:57:44 PM PST 24
Peak memory 200472 kb
Host smart-352d9f82-d36c-480a-9d19-497c06b11412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072115814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3072115814
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2870223410
Short name T589
Test name
Test status
Simulation time 2117324487 ps
CPU time 12.48 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:46:52 PM PST 24
Peak memory 198728 kb
Host smart-736e8f2c-dc77-4706-8351-537f352a58d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870223410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2870223410
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2099326655
Short name T1088
Test name
Test status
Simulation time 59850908225 ps
CPU time 23.4 seconds
Started Mar 07 01:46:41 PM PST 24
Finished Mar 07 01:47:05 PM PST 24
Peak memory 200220 kb
Host smart-4c185669-2760-4d85-881d-122b023af635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099326655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2099326655
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3993895463
Short name T783
Test name
Test status
Simulation time 4892115163 ps
CPU time 8.72 seconds
Started Mar 07 01:46:32 PM PST 24
Finished Mar 07 01:46:41 PM PST 24
Peak memory 196436 kb
Host smart-f1e6a0a2-1ffd-427d-8d77-da97aede5083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993895463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3993895463
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3494341914
Short name T900
Test name
Test status
Simulation time 560445416 ps
CPU time 1.86 seconds
Started Mar 07 01:46:34 PM PST 24
Finished Mar 07 01:46:36 PM PST 24
Peak memory 198644 kb
Host smart-def6b578-4a8a-4ed5-98b3-6119a2a41cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494341914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3494341914
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.612950155
Short name T334
Test name
Test status
Simulation time 97820756070 ps
CPU time 531.97 seconds
Started Mar 07 01:46:37 PM PST 24
Finished Mar 07 01:55:30 PM PST 24
Peak memory 200596 kb
Host smart-46a6b32d-a0af-457c-8ee8-ca59d0ab15b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612950155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.612950155
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.962555653
Short name T673
Test name
Test status
Simulation time 1221628725 ps
CPU time 2.46 seconds
Started Mar 07 01:46:37 PM PST 24
Finished Mar 07 01:46:39 PM PST 24
Peak memory 199508 kb
Host smart-ea1ff0f7-d75d-4860-bdf1-d0748241045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962555653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.962555653
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.920883067
Short name T1039
Test name
Test status
Simulation time 123060623881 ps
CPU time 72.27 seconds
Started Mar 07 01:46:35 PM PST 24
Finished Mar 07 01:47:48 PM PST 24
Peak memory 200488 kb
Host smart-a8525605-7bd9-471e-aa39-697e09ea9346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920883067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.920883067
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1268299097
Short name T895
Test name
Test status
Simulation time 45785603 ps
CPU time 0.56 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:46:44 PM PST 24
Peak memory 195964 kb
Host smart-e7eab56a-0501-49ce-9a04-f83c3c06fb08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268299097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1268299097
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3647948943
Short name T886
Test name
Test status
Simulation time 128034421164 ps
CPU time 11.29 seconds
Started Mar 07 01:46:35 PM PST 24
Finished Mar 07 01:46:47 PM PST 24
Peak memory 200572 kb
Host smart-e4ae4453-903b-4dc2-8d51-16f5b4750507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647948943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3647948943
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3963983309
Short name T160
Test name
Test status
Simulation time 12686867867 ps
CPU time 16.07 seconds
Started Mar 07 01:46:35 PM PST 24
Finished Mar 07 01:46:52 PM PST 24
Peak memory 200512 kb
Host smart-ec039294-fdb4-4c7c-88ae-275a56a7c5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963983309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3963983309
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3181222997
Short name T11
Test name
Test status
Simulation time 687699449326 ps
CPU time 567.22 seconds
Started Mar 07 01:46:39 PM PST 24
Finished Mar 07 01:56:07 PM PST 24
Peak memory 199284 kb
Host smart-3f186a28-80a2-4455-bdf4-1276491f0191
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181222997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3181222997
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2796454859
Short name T555
Test name
Test status
Simulation time 196484091034 ps
CPU time 428.27 seconds
Started Mar 07 01:46:46 PM PST 24
Finished Mar 07 01:53:54 PM PST 24
Peak memory 200600 kb
Host smart-1d23c4d6-f3c5-4e9b-a545-3a2154dcef95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796454859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2796454859
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1598818965
Short name T530
Test name
Test status
Simulation time 2327358674 ps
CPU time 1.24 seconds
Started Mar 07 01:46:42 PM PST 24
Finished Mar 07 01:46:44 PM PST 24
Peak memory 198312 kb
Host smart-c2f3a506-01e8-40a1-bc61-91bd434ebfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598818965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1598818965
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2164202925
Short name T542
Test name
Test status
Simulation time 48858081630 ps
CPU time 36.68 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:47:20 PM PST 24
Peak memory 197440 kb
Host smart-8306b938-d2f5-46f1-8db2-51745f345f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164202925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2164202925
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3268798281
Short name T1020
Test name
Test status
Simulation time 40532896295 ps
CPU time 2102.88 seconds
Started Mar 07 01:46:45 PM PST 24
Finished Mar 07 02:21:48 PM PST 24
Peak memory 200452 kb
Host smart-7a8bed3b-d063-4f47-a4f4-fb7bed6508ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268798281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3268798281
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.378859092
Short name T950
Test name
Test status
Simulation time 7553028431 ps
CPU time 32.41 seconds
Started Mar 07 01:46:35 PM PST 24
Finished Mar 07 01:47:08 PM PST 24
Peak memory 199136 kb
Host smart-2430660b-1f05-4fa4-801e-05454ac91e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378859092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.378859092
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2125652145
Short name T1075
Test name
Test status
Simulation time 41489894137 ps
CPU time 18.12 seconds
Started Mar 07 01:46:42 PM PST 24
Finished Mar 07 01:47:00 PM PST 24
Peak memory 196364 kb
Host smart-04db7560-0fbb-4287-9055-5abace967772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125652145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2125652145
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1738579009
Short name T444
Test name
Test status
Simulation time 890721735 ps
CPU time 3.23 seconds
Started Mar 07 01:46:38 PM PST 24
Finished Mar 07 01:46:41 PM PST 24
Peak memory 199896 kb
Host smart-58050f76-ddf3-4456-a26c-84013b496e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738579009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1738579009
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1867449784
Short name T615
Test name
Test status
Simulation time 166016509995 ps
CPU time 173.75 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:49:37 PM PST 24
Peak memory 200584 kb
Host smart-1ab1b254-c675-4272-8900-4d91fc5113a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867449784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1867449784
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3890381680
Short name T448
Test name
Test status
Simulation time 217481257177 ps
CPU time 1655.32 seconds
Started Mar 07 01:46:55 PM PST 24
Finished Mar 07 02:14:31 PM PST 24
Peak memory 225340 kb
Host smart-d88e77a6-158b-4424-acbd-162ba8a92c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890381680 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3890381680
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.56340243
Short name T591
Test name
Test status
Simulation time 651252446 ps
CPU time 2.21 seconds
Started Mar 07 01:46:44 PM PST 24
Finished Mar 07 01:46:47 PM PST 24
Peak memory 199744 kb
Host smart-8ad6138e-e8f9-4df3-8372-36592ec040a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56340243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.56340243
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2172763641
Short name T225
Test name
Test status
Simulation time 69377057009 ps
CPU time 121.42 seconds
Started Mar 07 01:46:33 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 200620 kb
Host smart-7559b58b-d782-47ab-afba-c381a78cf86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172763641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2172763641
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3779648735
Short name T490
Test name
Test status
Simulation time 11178583 ps
CPU time 0.54 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:43:58 PM PST 24
Peak memory 196016 kb
Host smart-f6417786-b394-4cfd-821f-f15ad8d727df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779648735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3779648735
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3032042597
Short name T873
Test name
Test status
Simulation time 87105842298 ps
CPU time 131.32 seconds
Started Mar 07 01:43:58 PM PST 24
Finished Mar 07 01:46:09 PM PST 24
Peak memory 200596 kb
Host smart-d2967ebd-e231-43a0-b019-d3f5ab4c4c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032042597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3032042597
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.74009142
Short name T992
Test name
Test status
Simulation time 199953299665 ps
CPU time 213.85 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:47:31 PM PST 24
Peak memory 200528 kb
Host smart-8a07fbe6-5ff8-4988-84fb-a405c721435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74009142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.74009142
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2548687270
Short name T339
Test name
Test status
Simulation time 7968999570 ps
CPU time 25.99 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:27 PM PST 24
Peak memory 200588 kb
Host smart-55a7646b-c1b6-4b70-a930-7788e9d36853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548687270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2548687270
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2113853099
Short name T1073
Test name
Test status
Simulation time 58933480388 ps
CPU time 34.04 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:44:32 PM PST 24
Peak memory 200516 kb
Host smart-bced73df-e4ad-4294-884f-6cab996b2333
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113853099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2113853099
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2215592905
Short name T500
Test name
Test status
Simulation time 75989810243 ps
CPU time 469.86 seconds
Started Mar 07 01:43:58 PM PST 24
Finished Mar 07 01:51:48 PM PST 24
Peak memory 200544 kb
Host smart-68493788-fe6e-4e2e-b741-17eae5c4b31c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215592905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2215592905
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2740571172
Short name T937
Test name
Test status
Simulation time 2364999406 ps
CPU time 2.62 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:43:59 PM PST 24
Peak memory 198820 kb
Host smart-0b7a4bed-326c-4117-bafc-9260b20ef730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740571172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2740571172
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2283135963
Short name T1003
Test name
Test status
Simulation time 28214983221 ps
CPU time 27.37 seconds
Started Mar 07 01:43:55 PM PST 24
Finished Mar 07 01:44:23 PM PST 24
Peak memory 200392 kb
Host smart-25cb2b47-32ce-495b-9465-8a03523bfe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283135963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2283135963
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2586709941
Short name T892
Test name
Test status
Simulation time 16436850575 ps
CPU time 415.4 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:50:55 PM PST 24
Peak memory 200588 kb
Host smart-ef236614-5387-4a63-a957-fac8487493b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586709941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2586709941
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3596684464
Short name T757
Test name
Test status
Simulation time 5849361100 ps
CPU time 38.16 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:44:38 PM PST 24
Peak memory 199436 kb
Host smart-ed414712-bc27-4feb-8068-fad670a128a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596684464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3596684464
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1107944704
Short name T1004
Test name
Test status
Simulation time 120829394886 ps
CPU time 160.99 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:46:38 PM PST 24
Peak memory 200508 kb
Host smart-a706bb4f-bd1c-47d5-88c8-250f81b2e0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107944704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1107944704
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.312618612
Short name T1071
Test name
Test status
Simulation time 3443360893 ps
CPU time 3.09 seconds
Started Mar 07 01:43:55 PM PST 24
Finished Mar 07 01:43:58 PM PST 24
Peak memory 196356 kb
Host smart-8fe5d499-7c06-4efd-bfe4-eaa9d96f91ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312618612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.312618612
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.549859597
Short name T438
Test name
Test status
Simulation time 5527315113 ps
CPU time 19.47 seconds
Started Mar 07 01:43:58 PM PST 24
Finished Mar 07 01:44:18 PM PST 24
Peak memory 200056 kb
Host smart-cb869b4e-4cf4-4af4-94da-f61d78f3f65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549859597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.549859597
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1123480591
Short name T931
Test name
Test status
Simulation time 16339803552 ps
CPU time 140.4 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:46:19 PM PST 24
Peak memory 216960 kb
Host smart-d4e01233-cbd7-4469-8833-a5d8c6cc0acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123480591 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1123480591
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.701743172
Short name T45
Test name
Test status
Simulation time 851636520 ps
CPU time 2.97 seconds
Started Mar 07 01:43:58 PM PST 24
Finished Mar 07 01:44:01 PM PST 24
Peak memory 199416 kb
Host smart-9217a4f8-c417-4393-bbee-feac06aa99f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701743172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.701743172
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1744704288
Short name T1090
Test name
Test status
Simulation time 62531813321 ps
CPU time 102.61 seconds
Started Mar 07 01:43:58 PM PST 24
Finished Mar 07 01:45:41 PM PST 24
Peak memory 200564 kb
Host smart-bb18a2fc-8df4-475f-8ec7-7321529393f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744704288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1744704288
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2526410121
Short name T893
Test name
Test status
Simulation time 45633180166 ps
CPU time 34.36 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:47:17 PM PST 24
Peak memory 200524 kb
Host smart-cca4a75c-f724-480c-9887-0df653f7406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526410121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2526410121
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.4280473417
Short name T218
Test name
Test status
Simulation time 53546964696 ps
CPU time 44.04 seconds
Started Mar 07 01:46:42 PM PST 24
Finished Mar 07 01:47:27 PM PST 24
Peak memory 200388 kb
Host smart-58a07915-300c-4bb8-b34a-1032d8545017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280473417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4280473417
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2011831611
Short name T683
Test name
Test status
Simulation time 119775522461 ps
CPU time 273.81 seconds
Started Mar 07 01:46:42 PM PST 24
Finished Mar 07 01:51:16 PM PST 24
Peak memory 217464 kb
Host smart-d6523efe-e25a-416b-8b18-2a0a26ce8c8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011831611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2011831611
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1241052153
Short name T567
Test name
Test status
Simulation time 15927320948 ps
CPU time 8.18 seconds
Started Mar 07 01:46:42 PM PST 24
Finished Mar 07 01:46:50 PM PST 24
Peak memory 200480 kb
Host smart-cbf395c0-d45b-4bf9-ad50-2966b220ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241052153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1241052153
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1754815783
Short name T723
Test name
Test status
Simulation time 59809143377 ps
CPU time 99.61 seconds
Started Mar 07 01:46:42 PM PST 24
Finished Mar 07 01:48:22 PM PST 24
Peak memory 199176 kb
Host smart-231b6163-dcb7-4842-958e-9a73427cc1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754815783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1754815783
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3549547630
Short name T447
Test name
Test status
Simulation time 49038569509 ps
CPU time 301.58 seconds
Started Mar 07 01:46:44 PM PST 24
Finished Mar 07 01:51:46 PM PST 24
Peak memory 217304 kb
Host smart-a00eced7-7894-46c3-9ebc-29116134d9ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549547630 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3549547630
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.409649935
Short name T976
Test name
Test status
Simulation time 113643786590 ps
CPU time 198.26 seconds
Started Mar 07 01:46:42 PM PST 24
Finished Mar 07 01:50:00 PM PST 24
Peak memory 200592 kb
Host smart-a9697f4a-fa6a-4097-b9f3-88a83843bba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409649935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.409649935
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2244027024
Short name T34
Test name
Test status
Simulation time 29427033583 ps
CPU time 355.73 seconds
Started Mar 07 01:46:47 PM PST 24
Finished Mar 07 01:52:44 PM PST 24
Peak memory 216296 kb
Host smart-487b5edc-e7ae-450d-8de6-e4ace07f1baa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244027024 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2244027024
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2308589338
Short name T266
Test name
Test status
Simulation time 30368588966 ps
CPU time 48.43 seconds
Started Mar 07 01:46:48 PM PST 24
Finished Mar 07 01:47:37 PM PST 24
Peak memory 200608 kb
Host smart-5acd27f2-afca-422f-aa91-9b02141da840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308589338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2308589338
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2342734405
Short name T740
Test name
Test status
Simulation time 49860254955 ps
CPU time 545.39 seconds
Started Mar 07 01:46:45 PM PST 24
Finished Mar 07 01:55:50 PM PST 24
Peak memory 216120 kb
Host smart-fc6b3294-ce2c-4fad-a0ea-0789aee58fe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342734405 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2342734405
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.119968426
Short name T317
Test name
Test status
Simulation time 117091343028 ps
CPU time 107.34 seconds
Started Mar 07 01:46:44 PM PST 24
Finished Mar 07 01:48:31 PM PST 24
Peak memory 200544 kb
Host smart-7dbd040c-d060-40fb-acef-7eb7d4cebc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119968426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.119968426
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.687394165
Short name T311
Test name
Test status
Simulation time 110091067104 ps
CPU time 133.63 seconds
Started Mar 07 01:46:42 PM PST 24
Finished Mar 07 01:48:56 PM PST 24
Peak memory 200472 kb
Host smart-a9c459cb-1119-427b-909b-b2d0ece90877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687394165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.687394165
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.189961806
Short name T828
Test name
Test status
Simulation time 11931600 ps
CPU time 0.58 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:02 PM PST 24
Peak memory 194956 kb
Host smart-32c2a9d8-cad6-48c1-b335-b5836862feb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189961806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.189961806
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.901285796
Short name T146
Test name
Test status
Simulation time 76652850511 ps
CPU time 57.29 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:58 PM PST 24
Peak memory 200516 kb
Host smart-e8c32a7d-1138-487a-9c1a-7c28dc3c2644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901285796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.901285796
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2316646294
Short name T212
Test name
Test status
Simulation time 114704807058 ps
CPU time 19.85 seconds
Started Mar 07 01:43:56 PM PST 24
Finished Mar 07 01:44:16 PM PST 24
Peak memory 200284 kb
Host smart-22641670-11fc-4d4f-9959-cbf76cfe823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316646294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2316646294
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.2670607790
Short name T110
Test name
Test status
Simulation time 247340286818 ps
CPU time 150.29 seconds
Started Mar 07 01:44:03 PM PST 24
Finished Mar 07 01:46:33 PM PST 24
Peak memory 200608 kb
Host smart-861958a1-97b1-4956-b3cc-b473b4efbe7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670607790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2670607790
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3286135642
Short name T397
Test name
Test status
Simulation time 265611127934 ps
CPU time 336.07 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:49:36 PM PST 24
Peak memory 200568 kb
Host smart-2d7af392-c050-4de9-93ff-9a0756623d87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286135642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3286135642
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.911382817
Short name T960
Test name
Test status
Simulation time 7760493871 ps
CPU time 11.44 seconds
Started Mar 07 01:43:57 PM PST 24
Finished Mar 07 01:44:09 PM PST 24
Peak memory 198864 kb
Host smart-ee1ce23e-f95f-403c-ac16-41d35f06cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911382817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.911382817
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.2508664924
Short name T242
Test name
Test status
Simulation time 6755529410 ps
CPU time 385.78 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 200528 kb
Host smart-6fcba12b-a524-4316-a1f5-7dda540bc044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508664924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2508664924
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3205797519
Short name T718
Test name
Test status
Simulation time 2327156417 ps
CPU time 16.45 seconds
Started Mar 07 01:44:03 PM PST 24
Finished Mar 07 01:44:19 PM PST 24
Peak memory 199056 kb
Host smart-03e9cb71-07ce-407f-8313-faa90605879c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205797519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3205797519
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.280529745
Short name T165
Test name
Test status
Simulation time 21907453406 ps
CPU time 33.87 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:34 PM PST 24
Peak memory 199824 kb
Host smart-ad13e6fc-321f-4a4c-8331-f2d26776f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280529745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.280529745
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.606665111
Short name T1035
Test name
Test status
Simulation time 38633846078 ps
CPU time 56.39 seconds
Started Mar 07 01:43:56 PM PST 24
Finished Mar 07 01:44:53 PM PST 24
Peak memory 196256 kb
Host smart-9cc83068-977a-4bf6-82d4-ab13acf920db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606665111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.606665111
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1684649360
Short name T927
Test name
Test status
Simulation time 582089681 ps
CPU time 2.03 seconds
Started Mar 07 01:44:02 PM PST 24
Finished Mar 07 01:44:05 PM PST 24
Peak memory 199868 kb
Host smart-81b8cd63-0a7a-42d9-a83c-f6314b1e67c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684649360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1684649360
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1295143627
Short name T710
Test name
Test status
Simulation time 811483529149 ps
CPU time 417.75 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:50:58 PM PST 24
Peak memory 200536 kb
Host smart-3e8301e4-3d9d-48e4-872a-00c0b7cc4b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295143627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1295143627
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2283875517
Short name T402
Test name
Test status
Simulation time 2446811052 ps
CPU time 2.41 seconds
Started Mar 07 01:43:59 PM PST 24
Finished Mar 07 01:44:02 PM PST 24
Peak memory 199052 kb
Host smart-f35ea9a9-3dda-49b7-91f8-c21ef6474027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283875517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2283875517
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3390011865
Short name T843
Test name
Test status
Simulation time 53926272276 ps
CPU time 12 seconds
Started Mar 07 01:44:01 PM PST 24
Finished Mar 07 01:44:13 PM PST 24
Peak memory 197872 kb
Host smart-dfa0e076-7ff7-4f3c-ab4b-713d66c18900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390011865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3390011865
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1452884795
Short name T749
Test name
Test status
Simulation time 132547891430 ps
CPU time 220.69 seconds
Started Mar 07 01:46:56 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 200512 kb
Host smart-1f2e69ac-c121-40f4-9011-3c1a3b031247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452884795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1452884795
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.4125358408
Short name T280
Test name
Test status
Simulation time 85194764862 ps
CPU time 645.56 seconds
Started Mar 07 01:46:56 PM PST 24
Finished Mar 07 01:57:41 PM PST 24
Peak memory 225484 kb
Host smart-b0758e59-8209-4a39-b26a-0b1650f2a40f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125358408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.4125358408
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2746802939
Short name T785
Test name
Test status
Simulation time 180392041939 ps
CPU time 73.52 seconds
Started Mar 07 01:46:43 PM PST 24
Finished Mar 07 01:47:57 PM PST 24
Peak memory 200008 kb
Host smart-6edc0ae1-2534-425f-ae29-44ae1fd85f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746802939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2746802939
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1215311985
Short name T745
Test name
Test status
Simulation time 151933050152 ps
CPU time 58.83 seconds
Started Mar 07 01:46:47 PM PST 24
Finished Mar 07 01:47:46 PM PST 24
Peak memory 200224 kb
Host smart-e322f029-ba19-4b88-9e0f-def9fd7be3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215311985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1215311985
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2420632523
Short name T373
Test name
Test status
Simulation time 77058480428 ps
CPU time 581.43 seconds
Started Mar 07 01:46:50 PM PST 24
Finished Mar 07 01:56:32 PM PST 24
Peak memory 215784 kb
Host smart-c610fa85-d87c-4357-82f8-977c5b4d948e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420632523 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2420632523
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3729625109
Short name T323
Test name
Test status
Simulation time 117230679522 ps
CPU time 47.49 seconds
Started Mar 07 01:46:52 PM PST 24
Finished Mar 07 01:47:40 PM PST 24
Peak memory 200416 kb
Host smart-a725ac34-6238-49b0-a2ae-591dd018ad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729625109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3729625109
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.4031405733
Short name T100
Test name
Test status
Simulation time 226922664581 ps
CPU time 447.83 seconds
Started Mar 07 01:46:56 PM PST 24
Finished Mar 07 01:54:24 PM PST 24
Peak memory 227544 kb
Host smart-c80d0f2d-7668-45d4-9d6e-12b255072f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031405733 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4031405733
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3223620478
Short name T1044
Test name
Test status
Simulation time 48753734067 ps
CPU time 22.45 seconds
Started Mar 07 01:46:51 PM PST 24
Finished Mar 07 01:47:13 PM PST 24
Peak memory 200440 kb
Host smart-21b0380e-00b4-4e23-92c4-87b8cfefae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223620478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3223620478
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.83718273
Short name T201
Test name
Test status
Simulation time 95060929073 ps
CPU time 123.35 seconds
Started Mar 07 01:46:53 PM PST 24
Finished Mar 07 01:48:57 PM PST 24
Peak memory 200528 kb
Host smart-680cf574-5d7b-4e3b-90cf-a9d91550ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83718273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.83718273
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2457435470
Short name T1097
Test name
Test status
Simulation time 107514549454 ps
CPU time 33.26 seconds
Started Mar 07 01:46:54 PM PST 24
Finished Mar 07 01:47:27 PM PST 24
Peak memory 200516 kb
Host smart-c47c360d-dba2-4129-8906-92b75d69f1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457435470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2457435470
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2709916048
Short name T833
Test name
Test status
Simulation time 38419011267 ps
CPU time 463.27 seconds
Started Mar 07 01:46:52 PM PST 24
Finished Mar 07 01:54:35 PM PST 24
Peak memory 213152 kb
Host smart-1e042f74-2b57-41d2-ac45-b0ec0f92835c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709916048 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2709916048
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1787705294
Short name T255
Test name
Test status
Simulation time 168378793543 ps
CPU time 131.45 seconds
Started Mar 07 01:46:52 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 200556 kb
Host smart-c4fb63a8-8a23-4ce0-98b7-c7725510470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787705294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1787705294
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2274112147
Short name T701
Test name
Test status
Simulation time 37084867 ps
CPU time 0.61 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:44:37 PM PST 24
Peak memory 195904 kb
Host smart-90d4095c-a51d-47d4-8b16-209c734c2e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274112147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2274112147
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3183895073
Short name T1083
Test name
Test status
Simulation time 78591941234 ps
CPU time 121.18 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:46:02 PM PST 24
Peak memory 200524 kb
Host smart-e5e9f614-c6ed-452d-9bd7-273f7f29eed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183895073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3183895073
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1136422015
Short name T962
Test name
Test status
Simulation time 143900612645 ps
CPU time 12.73 seconds
Started Mar 07 01:44:01 PM PST 24
Finished Mar 07 01:44:14 PM PST 24
Peak memory 199076 kb
Host smart-8ba8fc04-5b21-4b3d-ac3c-bae8e94e3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136422015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1136422015
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2801379543
Short name T272
Test name
Test status
Simulation time 114473933051 ps
CPU time 74.61 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:45:15 PM PST 24
Peak memory 200352 kb
Host smart-956e5816-15f4-4dae-85db-a93f388c7f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801379543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2801379543
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2068351490
Short name T632
Test name
Test status
Simulation time 154531993494 ps
CPU time 48.35 seconds
Started Mar 07 01:44:01 PM PST 24
Finished Mar 07 01:44:50 PM PST 24
Peak memory 200448 kb
Host smart-e7350d81-cfd2-4193-8a4d-d4e107de5677
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068351490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2068351490
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.489486989
Short name T502
Test name
Test status
Simulation time 99713913636 ps
CPU time 364.23 seconds
Started Mar 07 01:44:32 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 200624 kb
Host smart-152da113-37be-44b1-960a-a44bc29165e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489486989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.489486989
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2826090956
Short name T826
Test name
Test status
Simulation time 6512673176 ps
CPU time 3.61 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:44:41 PM PST 24
Peak memory 196076 kb
Host smart-c54afed8-9b1d-4cfc-a54e-36086d6bff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826090956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2826090956
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3380624407
Short name T1048
Test name
Test status
Simulation time 134596724153 ps
CPU time 169.52 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:47:27 PM PST 24
Peak memory 200448 kb
Host smart-b0987a90-a197-4b26-a087-b0ec500b97b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380624407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3380624407
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1770495002
Short name T664
Test name
Test status
Simulation time 3531198974 ps
CPU time 195.84 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:47:51 PM PST 24
Peak memory 200520 kb
Host smart-448659a8-1e30-4081-9ff3-2b17ddac117f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770495002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1770495002
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3095911675
Short name T716
Test name
Test status
Simulation time 5431053602 ps
CPU time 50.88 seconds
Started Mar 07 01:44:01 PM PST 24
Finished Mar 07 01:44:52 PM PST 24
Peak memory 199436 kb
Host smart-82c5360e-3ecd-4328-9e40-04e0a9827bc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095911675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3095911675
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1021976608
Short name T523
Test name
Test status
Simulation time 24836529485 ps
CPU time 21.38 seconds
Started Mar 07 01:44:34 PM PST 24
Finished Mar 07 01:44:56 PM PST 24
Peak memory 198464 kb
Host smart-8e4a20ec-9d00-44c1-8474-8bed934af1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021976608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1021976608
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3102195700
Short name T432
Test name
Test status
Simulation time 3098746322 ps
CPU time 2.04 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:44:36 PM PST 24
Peak memory 196044 kb
Host smart-9e206b38-361d-40b8-951b-706f2ed3bd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102195700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3102195700
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.4441886
Short name T429
Test name
Test status
Simulation time 290961511 ps
CPU time 1.37 seconds
Started Mar 07 01:44:01 PM PST 24
Finished Mar 07 01:44:02 PM PST 24
Peak memory 198316 kb
Host smart-4f813c11-0103-49e3-baee-6bb26b831ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4441886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4441886
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.854651611
Short name T593
Test name
Test status
Simulation time 25333983381 ps
CPU time 222.73 seconds
Started Mar 07 01:44:32 PM PST 24
Finished Mar 07 01:48:15 PM PST 24
Peak memory 200584 kb
Host smart-b0e2fb9c-83a3-49bd-87a6-6a78e68419a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854651611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.854651611
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3106580669
Short name T445
Test name
Test status
Simulation time 35199532066 ps
CPU time 229.32 seconds
Started Mar 07 01:44:32 PM PST 24
Finished Mar 07 01:48:22 PM PST 24
Peak memory 216080 kb
Host smart-80ac1e94-e9ad-470b-9b9e-14f1ee0a6599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106580669 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3106580669
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3944936705
Short name T563
Test name
Test status
Simulation time 2177903084 ps
CPU time 2.1 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:44:37 PM PST 24
Peak memory 198536 kb
Host smart-1b600879-5b5f-44d6-9394-16aede877de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944936705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3944936705
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2246599370
Short name T1011
Test name
Test status
Simulation time 15364052829 ps
CPU time 17.37 seconds
Started Mar 07 01:44:00 PM PST 24
Finished Mar 07 01:44:18 PM PST 24
Peak memory 200580 kb
Host smart-994cd087-a205-4f2f-aa71-fbc75917bc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246599370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2246599370
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2385842534
Short name T576
Test name
Test status
Simulation time 95399108093 ps
CPU time 39.14 seconds
Started Mar 07 01:46:50 PM PST 24
Finished Mar 07 01:47:30 PM PST 24
Peak memory 200516 kb
Host smart-2543df10-5999-451d-8020-d538a457644d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385842534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2385842534
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.891895613
Short name T206
Test name
Test status
Simulation time 91548859789 ps
CPU time 863.34 seconds
Started Mar 07 01:46:55 PM PST 24
Finished Mar 07 02:01:18 PM PST 24
Peak memory 225524 kb
Host smart-5e176e07-1460-41d8-b31a-69f124965342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891895613 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.891895613
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.150337055
Short name T787
Test name
Test status
Simulation time 114446380814 ps
CPU time 51.6 seconds
Started Mar 07 01:46:54 PM PST 24
Finished Mar 07 01:47:46 PM PST 24
Peak memory 200484 kb
Host smart-d22a7284-df52-48d7-a366-e470bc642278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150337055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.150337055
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2782140822
Short name T37
Test name
Test status
Simulation time 279263847182 ps
CPU time 825.54 seconds
Started Mar 07 01:46:51 PM PST 24
Finished Mar 07 02:00:37 PM PST 24
Peak memory 223968 kb
Host smart-db8ce335-0dc1-4d63-a5b1-866656e363e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782140822 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2782140822
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1527594854
Short name T198
Test name
Test status
Simulation time 77077653336 ps
CPU time 38.45 seconds
Started Mar 07 01:46:54 PM PST 24
Finished Mar 07 01:47:33 PM PST 24
Peak memory 199840 kb
Host smart-aefa7034-bf23-411d-9465-31bc2bde69e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527594854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1527594854
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1838473913
Short name T905
Test name
Test status
Simulation time 115365958383 ps
CPU time 74.38 seconds
Started Mar 07 01:46:53 PM PST 24
Finished Mar 07 01:48:08 PM PST 24
Peak memory 200332 kb
Host smart-8cc15b48-fbfd-433b-8b19-c144949f8296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838473913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1838473913
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3838185898
Short name T869
Test name
Test status
Simulation time 144541690327 ps
CPU time 108.34 seconds
Started Mar 07 01:46:52 PM PST 24
Finished Mar 07 01:48:40 PM PST 24
Peak memory 200372 kb
Host smart-05a72d4d-1a95-49ca-a074-8f2301d38f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838185898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3838185898
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1309102327
Short name T102
Test name
Test status
Simulation time 199057367312 ps
CPU time 675.52 seconds
Started Mar 07 01:46:50 PM PST 24
Finished Mar 07 01:58:06 PM PST 24
Peak memory 217252 kb
Host smart-546dec63-780a-41cd-8310-3b6ed88d84da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309102327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1309102327
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3391837811
Short name T190
Test name
Test status
Simulation time 63998440919 ps
CPU time 27.04 seconds
Started Mar 07 01:46:52 PM PST 24
Finished Mar 07 01:47:19 PM PST 24
Peak memory 200452 kb
Host smart-3066a0b5-5b92-4754-9adb-a9c9e450d613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391837811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3391837811
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1334078413
Short name T965
Test name
Test status
Simulation time 20111962739 ps
CPU time 275.78 seconds
Started Mar 07 01:46:51 PM PST 24
Finished Mar 07 01:51:27 PM PST 24
Peak memory 216656 kb
Host smart-9e346e00-fee0-4fbd-bbd0-254a2f35ce12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334078413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1334078413
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2149167370
Short name T963
Test name
Test status
Simulation time 42936596132 ps
CPU time 477.55 seconds
Started Mar 07 01:46:50 PM PST 24
Finished Mar 07 01:54:48 PM PST 24
Peak memory 217040 kb
Host smart-97472f22-a923-43d8-af2a-b26d71eef138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149167370 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2149167370
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.676760466
Short name T675
Test name
Test status
Simulation time 10561243601 ps
CPU time 17.39 seconds
Started Mar 07 01:46:51 PM PST 24
Finished Mar 07 01:47:09 PM PST 24
Peak memory 200500 kb
Host smart-7bd47b8d-cd87-44fe-b76b-594475ab6b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676760466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.676760466
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.4246678254
Short name T114
Test name
Test status
Simulation time 12040912189 ps
CPU time 22.32 seconds
Started Mar 07 01:46:53 PM PST 24
Finished Mar 07 01:47:16 PM PST 24
Peak memory 200516 kb
Host smart-30db9348-9551-42fa-9f19-8b225693542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246678254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.4246678254
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2598066385
Short name T972
Test name
Test status
Simulation time 135991542562 ps
CPU time 59.05 seconds
Started Mar 07 01:46:54 PM PST 24
Finished Mar 07 01:47:54 PM PST 24
Peak memory 200492 kb
Host smart-798fd08e-6163-49f7-b75a-0b8ec62d29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598066385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2598066385
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.4242682894
Short name T518
Test name
Test status
Simulation time 25164597 ps
CPU time 0.57 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:44:34 PM PST 24
Peak memory 195964 kb
Host smart-8a7b101c-6646-44ea-881a-7d98bd6945bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242682894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4242682894
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.243974879
Short name T559
Test name
Test status
Simulation time 151304624162 ps
CPU time 61.83 seconds
Started Mar 07 01:44:31 PM PST 24
Finished Mar 07 01:45:33 PM PST 24
Peak memory 200288 kb
Host smart-47fb81e6-b412-4711-a551-9321550feb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243974879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.243974879
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.500129426
Short name T363
Test name
Test status
Simulation time 170195192579 ps
CPU time 304.11 seconds
Started Mar 07 01:44:34 PM PST 24
Finished Mar 07 01:49:39 PM PST 24
Peak memory 199644 kb
Host smart-6d271cdd-3fe3-4da3-b3b6-aabaf0e650d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500129426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.500129426
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3969253920
Short name T775
Test name
Test status
Simulation time 31244776396 ps
CPU time 16.02 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:44:51 PM PST 24
Peak memory 200096 kb
Host smart-d6ecb117-c356-47d6-bc50-dc66c7c915d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969253920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3969253920
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.4008675488
Short name T455
Test name
Test status
Simulation time 559826827961 ps
CPU time 200.04 seconds
Started Mar 07 01:44:39 PM PST 24
Finished Mar 07 01:47:59 PM PST 24
Peak memory 200044 kb
Host smart-2ed42531-2381-43e4-8c4d-6a42593024e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008675488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4008675488
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3932270853
Short name T1072
Test name
Test status
Simulation time 53668945413 ps
CPU time 458.17 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:52:13 PM PST 24
Peak memory 200544 kb
Host smart-941a0f9d-98af-4e55-af4c-780f7b49ea55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932270853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3932270853
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3985731810
Short name T939
Test name
Test status
Simulation time 5685735948 ps
CPU time 11.76 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:44:47 PM PST 24
Peak memory 198980 kb
Host smart-0d9cc9e5-7e43-4e3a-94a4-a2d78830a7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985731810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3985731810
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.401544972
Short name T552
Test name
Test status
Simulation time 18299780472 ps
CPU time 31.73 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:45:05 PM PST 24
Peak memory 198608 kb
Host smart-19364d44-88ae-45fc-aee1-db6922828548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401544972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.401544972
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2080499947
Short name T474
Test name
Test status
Simulation time 6276274518 ps
CPU time 399.62 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:51:18 PM PST 24
Peak memory 200536 kb
Host smart-b4b33325-1192-4b36-bf96-9b12ae3a01a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080499947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2080499947
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2588977106
Short name T921
Test name
Test status
Simulation time 4562439391 ps
CPU time 39.08 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:45:14 PM PST 24
Peak memory 199392 kb
Host smart-b7e16f49-e668-4fbd-8020-f3d66e7902a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588977106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2588977106
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2718906649
Short name T324
Test name
Test status
Simulation time 13490678035 ps
CPU time 20.88 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:44:59 PM PST 24
Peak memory 200480 kb
Host smart-86d1c734-7843-4d2f-a9ac-9ab1b3fc5f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718906649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2718906649
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.4241065522
Short name T435
Test name
Test status
Simulation time 40865280467 ps
CPU time 11.76 seconds
Started Mar 07 01:44:32 PM PST 24
Finished Mar 07 01:44:44 PM PST 24
Peak memory 196068 kb
Host smart-17621480-146b-4082-847f-a38d27639ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241065522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.4241065522
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2767806656
Short name T763
Test name
Test status
Simulation time 671217148 ps
CPU time 3.06 seconds
Started Mar 07 01:44:32 PM PST 24
Finished Mar 07 01:44:35 PM PST 24
Peak memory 198852 kb
Host smart-4f297788-88a0-4d07-bb0b-2faab23556fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767806656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2767806656
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.703511401
Short name T105
Test name
Test status
Simulation time 286898544017 ps
CPU time 405.28 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:51:24 PM PST 24
Peak memory 200464 kb
Host smart-67e1cf29-a42d-4974-b85b-567932d66984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703511401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.703511401
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1485452594
Short name T598
Test name
Test status
Simulation time 1127731942 ps
CPU time 1.97 seconds
Started Mar 07 01:44:31 PM PST 24
Finished Mar 07 01:44:34 PM PST 24
Peak memory 199916 kb
Host smart-d9f9fcab-b758-4cdc-8dce-52244305862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485452594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1485452594
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.479990903
Short name T814
Test name
Test status
Simulation time 57948782190 ps
CPU time 39.17 seconds
Started Mar 07 01:44:38 PM PST 24
Finished Mar 07 01:45:17 PM PST 24
Peak memory 200488 kb
Host smart-2903128f-9835-4a35-bfbf-44d5ff2534ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479990903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.479990903
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3737207570
Short name T347
Test name
Test status
Simulation time 7088175587 ps
CPU time 11.76 seconds
Started Mar 07 01:46:53 PM PST 24
Finished Mar 07 01:47:06 PM PST 24
Peak memory 198344 kb
Host smart-876613a8-1540-4b52-b99d-c15d6b1d8d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737207570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3737207570
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3737082139
Short name T36
Test name
Test status
Simulation time 530300182254 ps
CPU time 754.39 seconds
Started Mar 07 01:46:54 PM PST 24
Finished Mar 07 01:59:29 PM PST 24
Peak memory 228636 kb
Host smart-c623945d-e7ef-4834-a234-59af142ba27f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737082139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3737082139
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.210277330
Short name T219
Test name
Test status
Simulation time 26553232970 ps
CPU time 20.06 seconds
Started Mar 07 01:46:59 PM PST 24
Finished Mar 07 01:47:20 PM PST 24
Peak memory 200484 kb
Host smart-c622d068-6935-4dfe-ad31-e06fc76de8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210277330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.210277330
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1258578152
Short name T364
Test name
Test status
Simulation time 100425691995 ps
CPU time 99.93 seconds
Started Mar 07 01:46:59 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 200520 kb
Host smart-5d6df4a0-eab0-4989-ba87-86fa46610330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258578152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1258578152
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1464850817
Short name T224
Test name
Test status
Simulation time 45341574866 ps
CPU time 73.82 seconds
Started Mar 07 01:46:58 PM PST 24
Finished Mar 07 01:48:12 PM PST 24
Peak memory 200508 kb
Host smart-1a824ac3-9522-4ff1-939c-9e7737d39ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464850817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1464850817
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1549209334
Short name T304
Test name
Test status
Simulation time 133037561844 ps
CPU time 66.21 seconds
Started Mar 07 01:47:00 PM PST 24
Finished Mar 07 01:48:06 PM PST 24
Peak memory 200544 kb
Host smart-390fc33d-8bf5-466e-b642-665278e3249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549209334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1549209334
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1153554563
Short name T792
Test name
Test status
Simulation time 36405980448 ps
CPU time 16.31 seconds
Started Mar 07 01:46:59 PM PST 24
Finished Mar 07 01:47:15 PM PST 24
Peak memory 200008 kb
Host smart-413af241-9638-4d74-9eee-f37cbeeffc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153554563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1153554563
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3417039071
Short name T259
Test name
Test status
Simulation time 77428049555 ps
CPU time 119.61 seconds
Started Mar 07 01:46:59 PM PST 24
Finished Mar 07 01:48:59 PM PST 24
Peak memory 200512 kb
Host smart-b2cd0e8e-e5d1-4bde-851f-43dcafc18dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417039071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3417039071
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3352417742
Short name T305
Test name
Test status
Simulation time 130792336158 ps
CPU time 73 seconds
Started Mar 07 01:47:00 PM PST 24
Finished Mar 07 01:48:13 PM PST 24
Peak memory 199816 kb
Host smart-d7e6ded8-cc24-4086-bf85-0f9f0a42e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352417742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3352417742
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1665800448
Short name T772
Test name
Test status
Simulation time 125715643361 ps
CPU time 262.64 seconds
Started Mar 07 01:46:58 PM PST 24
Finished Mar 07 01:51:21 PM PST 24
Peak memory 214316 kb
Host smart-ca18392c-786c-416a-897e-4f557cf88818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665800448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1665800448
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1984157528
Short name T377
Test name
Test status
Simulation time 284076249603 ps
CPU time 36.32 seconds
Started Mar 07 01:47:01 PM PST 24
Finished Mar 07 01:47:37 PM PST 24
Peak memory 200448 kb
Host smart-6324194e-b0de-4328-9ee7-e2100be8e026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984157528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1984157528
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.760232217
Short name T123
Test name
Test status
Simulation time 34391057618 ps
CPU time 10.87 seconds
Started Mar 07 01:46:58 PM PST 24
Finished Mar 07 01:47:09 PM PST 24
Peak memory 200428 kb
Host smart-46a2c7b2-4432-43eb-9ad2-196faefce3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760232217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.760232217
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.340115886
Short name T767
Test name
Test status
Simulation time 22826506 ps
CPU time 0.56 seconds
Started Mar 07 01:44:34 PM PST 24
Finished Mar 07 01:44:35 PM PST 24
Peak memory 194948 kb
Host smart-eecb8518-6b48-4045-8368-fa77e9bb666f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340115886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.340115886
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3896258967
Short name T351
Test name
Test status
Simulation time 132081586722 ps
CPU time 17.73 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:44:51 PM PST 24
Peak memory 200604 kb
Host smart-09667922-d5d1-4134-9256-0316e975de4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896258967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3896258967
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2831423561
Short name T427
Test name
Test status
Simulation time 73900304565 ps
CPU time 121.19 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:46:36 PM PST 24
Peak memory 199424 kb
Host smart-50cda736-520c-4958-87eb-83f849daae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831423561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2831423561
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.172980858
Short name T150
Test name
Test status
Simulation time 12605434076 ps
CPU time 26.15 seconds
Started Mar 07 01:44:37 PM PST 24
Finished Mar 07 01:45:04 PM PST 24
Peak memory 200612 kb
Host smart-fd788261-0560-4fad-bb68-8ef107520d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172980858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.172980858
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3681512532
Short name T776
Test name
Test status
Simulation time 25976154819 ps
CPU time 23.15 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:44:57 PM PST 24
Peak memory 197276 kb
Host smart-3b51c6e3-e4da-4195-99d0-bb1b65cad06c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681512532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3681512532
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.149788019
Short name T467
Test name
Test status
Simulation time 74423721930 ps
CPU time 433.11 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:51:46 PM PST 24
Peak memory 200508 kb
Host smart-e22cbd7f-5b3c-4f9e-a8e2-4c0d6781a674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149788019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.149788019
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1901668022
Short name T1068
Test name
Test status
Simulation time 3184744695 ps
CPU time 1.37 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:44:36 PM PST 24
Peak memory 197620 kb
Host smart-b2f26e63-540b-494c-9be6-cbec596ec786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901668022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1901668022
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2281304341
Short name T1038
Test name
Test status
Simulation time 76473877566 ps
CPU time 172.09 seconds
Started Mar 07 01:44:32 PM PST 24
Finished Mar 07 01:47:24 PM PST 24
Peak memory 200744 kb
Host smart-d59aa128-fe75-4158-901d-60f917595dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281304341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2281304341
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1201425941
Short name T181
Test name
Test status
Simulation time 9416739451 ps
CPU time 389.7 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:51:03 PM PST 24
Peak memory 200532 kb
Host smart-f8440b87-f149-4582-b5c9-1aeaad78a214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201425941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1201425941
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2372398416
Short name T731
Test name
Test status
Simulation time 7226074600 ps
CPU time 64.43 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:45:40 PM PST 24
Peak memory 199444 kb
Host smart-9582007c-08b2-445a-a2c0-d587963e9c11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372398416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2372398416
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3401786828
Short name T743
Test name
Test status
Simulation time 102845184194 ps
CPU time 167.18 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:47:22 PM PST 24
Peak memory 199644 kb
Host smart-95b8e5ba-7531-4d4b-86bd-cff022d7d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401786828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3401786828
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3113409175
Short name T872
Test name
Test status
Simulation time 29540816937 ps
CPU time 10.13 seconds
Started Mar 07 01:44:35 PM PST 24
Finished Mar 07 01:44:45 PM PST 24
Peak memory 196072 kb
Host smart-b4ebe613-9ddd-49d4-ae9b-77beec3cdc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113409175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3113409175
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.4174527391
Short name T1061
Test name
Test status
Simulation time 481820864 ps
CPU time 1.21 seconds
Started Mar 07 01:44:36 PM PST 24
Finished Mar 07 01:44:38 PM PST 24
Peak memory 198584 kb
Host smart-a013eb94-8e8d-4eee-aa86-7bc95e49566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174527391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4174527391
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3689367891
Short name T140
Test name
Test status
Simulation time 95892131650 ps
CPU time 507.03 seconds
Started Mar 07 01:44:34 PM PST 24
Finished Mar 07 01:53:01 PM PST 24
Peak memory 200604 kb
Host smart-e69b1cb5-7b18-4e34-b653-608e73ed4a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689367891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3689367891
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1019760043
Short name T949
Test name
Test status
Simulation time 2534542952 ps
CPU time 2.64 seconds
Started Mar 07 01:44:33 PM PST 24
Finished Mar 07 01:44:36 PM PST 24
Peak memory 198696 kb
Host smart-428be8f1-3b02-446e-9efa-6b774b2684f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019760043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1019760043
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2945178300
Short name T1017
Test name
Test status
Simulation time 386097767517 ps
CPU time 67.18 seconds
Started Mar 07 01:44:34 PM PST 24
Finished Mar 07 01:45:42 PM PST 24
Peak memory 200500 kb
Host smart-99a3018f-8934-4944-ba98-5a8396aa9561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945178300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2945178300
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.953180093
Short name T906
Test name
Test status
Simulation time 192316922517 ps
CPU time 369.78 seconds
Started Mar 07 01:47:01 PM PST 24
Finished Mar 07 01:53:11 PM PST 24
Peak memory 200524 kb
Host smart-1892c90c-a93f-4264-a577-3339e07019d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953180093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.953180093
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1958690052
Short name T446
Test name
Test status
Simulation time 50541242619 ps
CPU time 305.45 seconds
Started Mar 07 01:46:58 PM PST 24
Finished Mar 07 01:52:04 PM PST 24
Peak memory 217332 kb
Host smart-28d394b2-c6bb-4751-8761-418c8e07ac33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958690052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1958690052
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2334382433
Short name T1022
Test name
Test status
Simulation time 239449740080 ps
CPU time 45.99 seconds
Started Mar 07 01:47:00 PM PST 24
Finished Mar 07 01:47:46 PM PST 24
Peak memory 200524 kb
Host smart-4860666e-558d-4120-a76c-46c67f9f70b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334382433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2334382433
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2151821811
Short name T248
Test name
Test status
Simulation time 93998608204 ps
CPU time 13.88 seconds
Started Mar 07 01:46:58 PM PST 24
Finished Mar 07 01:47:12 PM PST 24
Peak memory 200588 kb
Host smart-9d3095cc-3b13-4a7c-8d41-7342b9bde5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151821811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2151821811
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1398044699
Short name T824
Test name
Test status
Simulation time 22977677120 ps
CPU time 41.75 seconds
Started Mar 07 01:47:04 PM PST 24
Finished Mar 07 01:47:46 PM PST 24
Peak memory 200468 kb
Host smart-b1bc5d72-4f01-4fa4-8764-c0c019f55da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398044699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1398044699
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2001936338
Short name T326
Test name
Test status
Simulation time 22548189678 ps
CPU time 43.15 seconds
Started Mar 07 01:47:11 PM PST 24
Finished Mar 07 01:47:55 PM PST 24
Peak memory 200260 kb
Host smart-18a56531-f4b1-46be-a94e-8b41f152562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001936338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2001936338
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.168585083
Short name T113
Test name
Test status
Simulation time 21285166069 ps
CPU time 36.77 seconds
Started Mar 07 01:47:17 PM PST 24
Finished Mar 07 01:47:54 PM PST 24
Peak memory 200540 kb
Host smart-d29c09da-894b-4277-81e7-32c0aaddcb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168585083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.168585083
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.185299741
Short name T634
Test name
Test status
Simulation time 110672564409 ps
CPU time 93.13 seconds
Started Mar 07 01:47:14 PM PST 24
Finished Mar 07 01:48:47 PM PST 24
Peak memory 200512 kb
Host smart-52df6109-48e6-4ca1-aca0-7efb5cecca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185299741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.185299741
Directory /workspace/99.uart_fifo_reset/latest
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