Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	103512	1			T1	2		T3	78		T4	4
all_values[1]	103512	1			T1	2		T3	78		T4	4
all_values[2]	103512	1			T1	2		T3	78		T4	4
all_values[3]	103512	1			T1	2		T3	78		T4	4
all_values[4]	103512	1			T1	2		T3	78		T4	4
all_values[5]	103512	1			T1	2		T3	78		T4	4
all_values[6]	103512	1			T1	2		T3	78		T4	4
all_values[7]	103512	1			T1	2		T3	78		T4	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

419651

1

T1

16

T3

287

T4

18

auto[1]

408445

1

T3

337

T4

14

T5

1044

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

772493

1

T1

13

T3

544

T4

26

auto[1]

55603

1

T1

3

T3

80

T4

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33061	1			T3	11		T5	134		T6	3
all_values[0]	auto[0]	auto[1]	21667	1			T1	2		T3	34		T4	1
all_values[0]	auto[1]	auto[0]	24115	1			T3	8		T5	138		T16	120
all_values[0]	auto[1]	auto[1]	24669	1			T3	25		T4	3		T6	2
all_values[1]	auto[0]	auto[0]	54796	1			T1	2		T3	16		T4	3
all_values[1]	auto[0]	auto[1]	1416	1			T3	2		T4	1		T8	2
all_values[1]	auto[1]	auto[0]	45936	1			T3	60		T5	88		T6	2
all_values[1]	auto[1]	auto[1]	1364	1			T77	12		T11	2		T40	3
all_values[2]	auto[0]	auto[0]	47200	1			T1	1		T3	51		T4	2
all_values[2]	auto[0]	auto[1]	2357	1			T1	1		T3	13		T5	4
all_values[2]	auto[1]	auto[0]	51922	1			T3	8		T4	1		T5	138
all_values[2]	auto[1]	auto[1]	2033	1			T3	6		T4	1		T5	2
all_values[3]	auto[0]	auto[0]	46728	1			T1	2		T3	63		T4	1
all_values[3]	auto[0]	auto[1]	170	1			T12	1		T78	2		T33	4
all_values[3]	auto[1]	auto[0]	56449	1			T3	15		T4	3		T5	154
all_values[3]	auto[1]	auto[1]	165	1			T11	1		T12	1		T13	3
all_values[4]	auto[0]	auto[0]	51917	1			T1	2		T3	18		T4	4
all_values[4]	auto[0]	auto[1]	319	1			T14	7		T12	1		T13	5
all_values[4]	auto[1]	auto[0]	50871	1			T3	60		T5	71		T6	3
all_values[4]	auto[1]	auto[1]	405	1			T11	1		T15	1		T12	5
all_values[5]	auto[0]	auto[0]	54989	1			T1	2		T3	30		T4	2
all_values[5]	auto[0]	auto[1]	130	1			T11	2		T12	4		T33	1
all_values[5]	auto[1]	auto[0]	48268	1			T3	48		T4	2		T5	102
all_values[5]	auto[1]	auto[1]	125	1			T11	1		T12	2		T78	4
all_values[6]	auto[0]	auto[0]	52548	1			T1	2		T3	29		T4	3
all_values[6]	auto[0]	auto[1]	117	1			T11	3		T12	2		T78	1
all_values[6]	auto[1]	auto[0]	50689	1			T3	49		T4	1		T5	160
all_values[6]	auto[1]	auto[1]	158	1			T11	2		T12	2		T78	2
all_values[7]	auto[0]	auto[0]	51978	1			T1	2		T3	20		T4	1
all_values[7]	auto[0]	auto[1]	258	1			T16	5		T17	3		T11	3
all_values[7]	auto[1]	auto[0]	51026	1			T3	58		T4	3		T5	191
all_values[7]	auto[1]	auto[1]	250	1			T16	1		T11	3		T79	4