Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1841	1			T3	3		T8	1		T16	2
auto[BaudRate115200]	1534	1			T1	1		T3	5		T4	2
auto[BaudRate230400]	1575	1			T3	2		T6	1		T8	1
auto[BaudRate128Kbps]	1584	1			T3	3		T4	2		T6	3
auto[BaudRate256Kbps]	1804	1			T3	1		T4	2		T5	6
auto[BaudRate1Mbps]	1433	1			T1	1		T3	3		T4	1
auto[BaudRate1p5Mbps]	1017	1			T3	2		T5	2		T6	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	949	1			T4	7		T6	9		T21	10
freqs[25]	1205	1			T423	2		T18	2		T92	4
freqs[48]	557	1			T110	9		T14	3		T135	7
freqs[50]	283	1			T1	2		T19	5		T40	5
freqs[100]	1048	1			T17	7		T41	8		T24	39

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	162	1			T21	2		T208	2		T389	1
auto[BaudRate9600]	freqs[25]	190	1			T92	4		T147	2		T78	1
auto[BaudRate9600]	freqs[48]	67	1			T110	1		T135	4		T388	3
auto[BaudRate9600]	freqs[50]	49	1			T19	1		T382	2		T121	1
auto[BaudRate9600]	freqs[100]	164	1			T41	2		T24	7		T221	1
auto[BaudRate115200]	freqs[24]	134	1			T4	2		T21	2		T389	3
auto[BaudRate115200]	freqs[25]	190	1			T78	3		T298	4		T128	1
auto[BaudRate115200]	freqs[48]	59	1			T110	3		T135	1		T388	1
auto[BaudRate115200]	freqs[50]	38	1			T1	1		T382	2		T121	2
auto[BaudRate115200]	freqs[100]	132	1			T17	1		T41	2		T24	10
auto[BaudRate230400]	freqs[24]	131	1			T6	1		T21	1		T208	1
auto[BaudRate230400]	freqs[25]	171	1			T18	1		T147	2		T78	5
auto[BaudRate230400]	freqs[48]	78	1			T110	2		T14	1		T135	1
auto[BaudRate230400]	freqs[50]	29	1			T19	1		T40	2		T382	2
auto[BaudRate230400]	freqs[100]	123	1			T17	2		T24	4		T221	1
auto[BaudRate128Kbps]	freqs[24]	143	1			T4	2		T6	3		T21	2
auto[BaudRate128Kbps]	freqs[25]	188	1			T423	2		T18	1		T78	2
auto[BaudRate128Kbps]	freqs[48]	73	1			T110	1		T14	2		T388	1
auto[BaudRate128Kbps]	freqs[50]	46	1			T19	2		T40	1		T382	4
auto[BaudRate128Kbps]	freqs[100]	151	1			T17	3		T41	2		T24	11
auto[BaudRate256Kbps]	freqs[24]	158	1			T4	2		T6	1		T21	1
auto[BaudRate256Kbps]	freqs[25]	186	1			T147	1		T78	2		T298	21
auto[BaudRate256Kbps]	freqs[48]	78	1			T110	1		T135	1		T34	7
auto[BaudRate256Kbps]	freqs[50]	44	1			T19	1		T40	1		T382	2
auto[BaudRate256Kbps]	freqs[100]	154	1			T17	1		T24	5		T221	1
auto[BaudRate1Mbps]	freqs[24]	164	1			T4	1		T6	3		T21	2
auto[BaudRate1Mbps]	freqs[25]	201	1			T78	4		T298	10		T201	2
auto[BaudRate1Mbps]	freqs[48]	100	1			T34	9		T385	4		T129	2
auto[BaudRate1Mbps]	freqs[50]	32	1			T1	1		T382	2		T401	2
auto[BaudRate1Mbps]	freqs[100]	153	1			T41	2		T221	1		T12	2
auto[BaudRate1p5Mbps]	freqs[25]	79	1			T78	2		T298	1		T128	1
auto[BaudRate1p5Mbps]	freqs[48]	102	1			T110	1		T34	8		T385	2
auto[BaudRate1p5Mbps]	freqs[50]	45	1			T40	1		T382	1		T401	1
auto[BaudRate1p5Mbps]	freqs[100]	171	1			T24	2		T221	2		T12	4

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded