Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	103512	1			T1	2		T3	78		T4	4
all_pins[1]	103512	1			T1	2		T3	78		T4	4
all_pins[2]	103512	1			T1	2		T3	78		T4	4
all_pins[3]	103512	1			T1	2		T3	78		T4	4
all_pins[4]	103512	1			T1	2		T3	78		T4	4
all_pins[5]	103512	1			T1	2		T3	78		T4	4
all_pins[6]	103512	1			T1	2		T3	78		T4	4
all_pins[7]	103512	1			T1	2		T3	78		T4	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	798234	1			T1	16		T3	592		T4	28
values[0x1]	29862	1			T3	32		T4	4		T5	2
transitions[0x0=>0x1]	28923	1			T3	32		T4	4		T5	2
transitions[0x1=>0x0]	28461	1			T3	31		T4	3		T5	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	78800	1			T1	2		T3	53		T4	1
all_pins[0]	values[0x1]	24712	1			T3	25		T4	3		T6	2
all_pins[0]	transitions[0x0=>0x1]	24152	1			T3	25		T4	3		T6	2
all_pins[0]	transitions[0x1=>0x0]	802	1			T77	10		T11	1		T40	3
all_pins[1]	values[0x0]	102150	1			T1	2		T3	78		T4	4
all_pins[1]	values[0x1]	1362	1			T77	12		T11	2		T40	3
all_pins[1]	transitions[0x0=>0x1]	1298	1			T77	12		T11	1		T40	3
all_pins[1]	transitions[0x1=>0x0]	2022	1			T3	6		T4	1		T5	2
all_pins[2]	values[0x0]	101426	1			T1	2		T3	72		T4	3
all_pins[2]	values[0x1]	2086	1			T3	6		T4	1		T5	2
all_pins[2]	transitions[0x0=>0x1]	2045	1			T3	6		T4	1		T5	2
all_pins[2]	transitions[0x1=>0x0]	124	1			T11	1		T12	1		T13	3
all_pins[3]	values[0x0]	103347	1			T1	2		T3	78		T4	4
all_pins[3]	values[0x1]	165	1			T11	1		T12	1		T13	3
all_pins[3]	transitions[0x0=>0x1]	128	1			T11	1		T12	1		T13	3
all_pins[3]	transitions[0x1=>0x0]	368	1			T11	1		T15	1		T12	5
all_pins[4]	values[0x0]	103107	1			T1	2		T3	78		T4	4
all_pins[4]	values[0x1]	405	1			T11	1		T15	1		T12	5
all_pins[4]	transitions[0x0=>0x1]	359	1			T11	1		T15	1		T12	3
all_pins[4]	transitions[0x1=>0x0]	116	1			T14	1		T11	1		T78	3
all_pins[5]	values[0x0]	103350	1			T1	2		T3	78		T4	4
all_pins[5]	values[0x1]	162	1			T14	1		T11	1		T12	2
all_pins[5]	transitions[0x0=>0x1]	118	1			T14	1		T12	2		T78	4
all_pins[5]	transitions[0x1=>0x0]	676	1			T3	1		T9	1		T16	1
all_pins[6]	values[0x0]	102792	1			T1	2		T3	77		T4	4
all_pins[6]	values[0x1]	720	1			T3	1		T9	1		T16	1
all_pins[6]	transitions[0x0=>0x1]	686	1			T3	1		T9	1		T77	4
all_pins[6]	transitions[0x1=>0x0]	216	1			T11	2		T79	4		T12	1
all_pins[7]	values[0x0]	103262	1			T1	2		T3	78		T4	4
all_pins[7]	values[0x1]	250	1			T16	1		T11	3		T79	4
all_pins[7]	transitions[0x0=>0x1]	137	1			T16	1		T11	3		T79	1
all_pins[7]	transitions[0x1=>0x0]	24137	1			T3	24		T4	2		T6	1