Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
7 |
0 |
7 |
100.00 |
Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_watermark_lvl |
7 |
0 |
7 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
7 |
0 |
7 |
100.00 |
User Defined Bins for cp_watermark_lvl
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| all_levels[0] |
5175 |
1 |
|
|
T1 |
2 |
|
T3 |
5 |
|
T5 |
1 |
| all_levels[1] |
4716 |
1 |
|
|
T3 |
21 |
|
T8 |
2 |
|
T16 |
13 |
| all_levels[2] |
6506 |
1 |
|
|
T4 |
1 |
|
T8 |
6 |
|
T9 |
22 |
| all_levels[3] |
4880 |
1 |
|
|
T3 |
4 |
|
T4 |
2 |
|
T5 |
1 |
| all_levels[4] |
5254 |
1 |
|
|
T3 |
6 |
|
T6 |
2 |
|
T8 |
2 |
| all_levels[5] |
7785 |
1 |
|
|
T3 |
4 |
|
T4 |
1 |
|
T6 |
9 |
| all_levels[6] |
12135 |
1 |
|
|
T3 |
19 |
|
T10 |
1 |
|
T45 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |