Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	529	1			T11	7		T12	11		T78	7
all_values[1]	529	1			T11	7		T12	11		T78	7
all_values[2]	529	1			T11	7		T12	11		T78	7
all_values[3]	529	1			T11	7		T12	11		T78	7
all_values[4]	529	1			T11	7		T12	11		T78	7
all_values[5]	529	1			T11	7		T12	11		T78	7
all_values[6]	529	1			T11	7		T12	11		T78	7
all_values[7]	529	1			T11	7		T12	11		T78	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2307

1

T11

28

T12

50

T78

29

auto[1]

1925

1

T11

28

T12

38

T78

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1527

1

T11

23

T12

35

T78

24

auto[1]

2705

1

T11

33

T12

53

T78

32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2496

1

T11

34

T12

54

T78

33

auto[1]

1736

1

T11

22

T12

34

T78

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	165	1			T11	2		T12	2		T78	2
all_values[0]	auto[0]	auto[1]	auto[1]	158	1			T11	1		T12	6		T78	2
all_values[0]	auto[1]	auto[0]	auto[1]	111	1			T11	3		T12	1		T78	1
all_values[0]	auto[1]	auto[1]	auto[1]	95	1			T11	1		T12	2		T78	2
all_values[1]	auto[0]	auto[0]	auto[0]	159	1			T11	4		T12	6		T78	3
all_values[1]	auto[0]	auto[1]	auto[0]	145	1			T12	1		T78	1		T106	1
all_values[1]	auto[1]	auto[0]	auto[1]	123	1			T11	1		T12	2		T78	2
all_values[1]	auto[1]	auto[1]	auto[1]	102	1			T11	2		T12	2		T78	1
all_values[2]	auto[0]	auto[0]	auto[0]	123	1			T11	2		T12	3		T78	3
all_values[2]	auto[0]	auto[0]	auto[1]	63	1			T12	1		T113	1		T22	1
all_values[2]	auto[0]	auto[1]	auto[0]	65	1			T11	2		T12	4		T33	1
all_values[2]	auto[0]	auto[1]	auto[1]	59	1			T11	1		T33	1		T106	1
all_values[2]	auto[1]	auto[0]	auto[1]	123	1			T11	1		T12	3		T78	1
all_values[2]	auto[1]	auto[1]	auto[1]	96	1			T11	1		T78	3		T33	2
all_values[3]	auto[0]	auto[0]	auto[0]	121	1			T11	3		T12	4		T78	3
all_values[3]	auto[0]	auto[0]	auto[1]	51	1			T12	1		T33	3		T106	1
all_values[3]	auto[0]	auto[1]	auto[0]	94	1			T11	1		T12	4		T78	2
all_values[3]	auto[0]	auto[1]	auto[1]	48	1			T12	1		T22	1		T35	1
all_values[3]	auto[1]	auto[0]	auto[1]	123	1			T12	1		T78	2		T33	1
all_values[3]	auto[1]	auto[1]	auto[1]	92	1			T11	3		T33	2		T22	1
all_values[4]	auto[0]	auto[0]	auto[0]	112	1			T11	1		T12	1		T33	2
all_values[4]	auto[0]	auto[0]	auto[1]	48	1			T12	1		T78	2		T33	1
all_values[4]	auto[0]	auto[1]	auto[0]	89	1			T11	5		T12	1		T78	1
all_values[4]	auto[0]	auto[1]	auto[1]	64	1			T12	3		T78	1		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	120	1			T12	2		T78	1		T33	2
all_values[4]	auto[1]	auto[1]	auto[1]	96	1			T11	1		T12	3		T78	2
all_values[5]	auto[0]	auto[0]	auto[0]	107	1			T11	3		T12	2		T78	3
all_values[5]	auto[0]	auto[0]	auto[1]	52	1			T12	1		T106	2		T22	1
all_values[5]	auto[0]	auto[1]	auto[0]	92	1			T12	1		T33	2		T106	1
all_values[5]	auto[0]	auto[1]	auto[1]	54	1			T11	1		T12	1		T78	1
all_values[5]	auto[1]	auto[0]	auto[1]	124	1			T11	2		T12	5		T33	1
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T11	1		T12	1		T78	3
all_values[6]	auto[0]	auto[0]	auto[0]	118	1			T11	1		T12	3		T78	2
all_values[6]	auto[0]	auto[0]	auto[1]	35	1			T11	1		T113	2		T35	1
all_values[6]	auto[0]	auto[1]	auto[0]	76	1			T12	1		T78	1		T106	1
all_values[6]	auto[0]	auto[1]	auto[1]	69	1			T11	1		T12	2		T78	1
all_values[6]	auto[1]	auto[0]	auto[1]	131	1			T11	1		T12	4		T78	1
all_values[6]	auto[1]	auto[1]	auto[1]	100	1			T11	3		T12	1		T78	2
all_values[7]	auto[0]	auto[0]	auto[0]	136	1			T12	2		T78	1		T106	1
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T11	2		T106	2		T22	2
all_values[7]	auto[0]	auto[1]	auto[0]	90	1			T11	1		T12	2		T78	4
all_values[7]	auto[0]	auto[1]	auto[1]	58	1			T11	2		T33	2		T22	1
all_values[7]	auto[1]	auto[0]	auto[1]	117	1			T11	1		T12	5		T78	2
all_values[7]	auto[1]	auto[1]	auto[1]	83	1			T11	1		T12	2		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal