Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	95194	1			T1	53		T2	9		T3	2
all_values[1]	95194	1			T1	53		T2	9		T3	2
all_values[2]	95194	1			T1	53		T2	9		T3	2
all_values[3]	95194	1			T1	53		T2	9		T3	2
all_values[4]	95194	1			T1	53		T2	9		T3	2
all_values[5]	95194	1			T1	53		T2	9		T3	2
all_values[6]	95194	1			T1	53		T2	9		T3	2
all_values[7]	95194	1			T1	53		T2	9		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

386834

1

T1

155

T2

27

T3

16

auto[1]

374718

1

T1

269

T2

45

T4

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

714225

1

T1

366

T2

62

T3

13

auto[1]

47327

1

T1

58

T2

10

T3

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27400	1			T2	1		T6	9		T7	16
all_values[0]	auto[0]	auto[1]	18878	1			T3	2		T5	2		T6	1
all_values[0]	auto[1]	auto[0]	29373	1			T2	1		T6	5		T7	34
all_values[0]	auto[1]	auto[1]	19543	1			T1	53		T2	7		T4	1
all_values[1]	auto[0]	auto[0]	47565	1			T2	8		T3	2		T4	1
all_values[1]	auto[0]	auto[1]	1214	1			T90	2		T121	4		T145	1
all_values[1]	auto[1]	auto[0]	44863	1			T1	53		T2	1		T6	8
all_values[1]	auto[1]	auto[1]	1552	1			T31	1		T25	1		T18	48
all_values[2]	auto[0]	auto[0]	45722	1			T3	1		T5	1		T6	11
all_values[2]	auto[0]	auto[1]	2224	1			T3	1		T5	1		T6	3
all_values[2]	auto[1]	auto[0]	45274	1			T1	48		T2	6		T4	1
all_values[2]	auto[1]	auto[1]	1974	1			T1	5		T2	3		T6	1
all_values[3]	auto[0]	auto[0]	44213	1			T1	49		T2	6		T3	2
all_values[3]	auto[0]	auto[1]	145	1			T11	6		T24	4		T27	2
all_values[3]	auto[1]	auto[0]	50660	1			T1	4		T2	3		T6	14
all_values[3]	auto[1]	auto[1]	176	1			T11	6		T13	1		T23	3
all_values[4]	auto[0]	auto[0]	52918	1			T2	3		T3	2		T4	1
all_values[4]	auto[0]	auto[1]	399	1			T11	3		T15	1		T13	4
all_values[4]	auto[1]	auto[0]	41583	1			T1	53		T2	6		T6	6
all_values[4]	auto[1]	auto[1]	294	1			T11	9		T15	1		T26	1
all_values[5]	auto[0]	auto[0]	49039	1			T1	49		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	106	1			T11	3		T12	1		T38	1
all_values[5]	auto[1]	auto[0]	45946	1			T1	4		T2	6		T6	9
all_values[5]	auto[1]	auto[1]	103	1			T11	10		T15	1		T12	1
all_values[6]	auto[0]	auto[0]	47769	1			T1	4		T2	5		T3	2
all_values[6]	auto[0]	auto[1]	99	1			T11	11		T13	2		T24	4
all_values[6]	auto[1]	auto[0]	47233	1			T1	49		T2	4		T6	2
all_values[6]	auto[1]	auto[1]	93	1			T11	6		T13	1		T24	2
all_values[7]	auto[0]	auto[0]	48894	1			T1	53		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	249	1			T19	4		T11	4		T117	2
all_values[7]	auto[1]	auto[0]	45773	1			T2	8		T6	2		T7	42
all_values[7]	auto[1]	auto[1]	278	1			T18	27		T11	9		T117	7