Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2072

1

T1

1

T2

1

T3

1

auto[UartRx]

2072

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3943	1			T1	2		T2	2		T3	2
values[1]	36	1			T11	1		T15	1		T12	2
values[2]	10	1			T12	2		T24	1		T78	1
values[3]	18	1			T11	1		T26	1		T24	1
values[4]	22	1			T11	2		T12	2		T39	1
values[5]	16	1			T15	1		T38	1		T24	2
values[6]	9	1			T11	1		T78	1		T113	1
values[7]	21	1			T11	2		T15	1		T39	1
values[8]	17	1			T11	1		T38	1		T41	1
values[9]	20	1			T15	1		T12	1		T40	1
values[10]	20	1			T15	2		T12	1		T40	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2013	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	12	1			T11	1		T15	1		T12	1
auto[UartTx]	values[2]	2	1			T435	1		T294	1		-	-
auto[UartTx]	values[3]	3	1			T24	1		T41	1		T436	1
auto[UartTx]	values[4]	6	1			T11	1		T12	1		T111	1
auto[UartTx]	values[5]	6	1			T24	1		T111	1		T437	1
auto[UartTx]	values[6]	3	1			T438	1		T439	1		T440	1
auto[UartTx]	values[7]	6	1			T11	1		T15	1		T24	1
auto[UartTx]	values[8]	3	1			T355	1		T441	1		T442	1
auto[UartTx]	values[9]	7	1			T15	1		T40	1		T112	1
auto[UartTx]	values[10]	8	1			T40	1		T72	1		T437	1
auto[UartRx]	values[0]	1930	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	24	1			T12	1		T26	1		T38	1
auto[UartRx]	values[2]	8	1			T12	2		T24	1		T78	1
auto[UartRx]	values[3]	15	1			T11	1		T26	1		T40	1
auto[UartRx]	values[4]	16	1			T11	1		T12	1		T39	1
auto[UartRx]	values[5]	10	1			T15	1		T38	1		T24	1
auto[UartRx]	values[6]	6	1			T11	1		T78	1		T113	1
auto[UartRx]	values[7]	15	1			T11	1		T39	1		T370	1
auto[UartRx]	values[8]	14	1			T11	1		T38	1		T41	1
auto[UartRx]	values[9]	13	1			T12	1		T58	2		T437	1
auto[UartRx]	values[10]	12	1			T15	2		T12	1		T41	1