Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1815	1			T1	1		T3	1		T4	3
auto[BaudRate115200]	1568	1			T6	1		T8	1		T90	4
auto[BaudRate230400]	1589	1			T1	2		T2	1		T4	9
auto[BaudRate128Kbps]	1571	1			T1	3		T3	1		T5	1
auto[BaudRate256Kbps]	1701	1			T2	4		T4	6		T5	1
auto[BaudRate1Mbps]	1519	1			T1	1		T2	2		T6	2
auto[BaudRate1p5Mbps]	1064	1			T1	1		T2	1		T6	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1074	1			T8	5		T160	9		T22	2
freqs[25]	1111	1			T10	6		T25	10		T30	51
freqs[48]	757	1			T2	8		T5	2		T14	6
freqs[50]	667	1			T6	5		T52	6		T119	21
freqs[100]	904	1			T31	16		T56	12		T45	5

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	184	1			T160	3		T123	5		T443	1
auto[BaudRate9600]	freqs[25]	190	1			T25	1		T30	3		T49	1
auto[BaudRate9600]	freqs[48]	147	1			T14	6		T21	1		T12	2
auto[BaudRate9600]	freqs[50]	83	1			T119	4		T216	6		T342	2
auto[BaudRate9600]	freqs[100]	194	1			T31	4		T56	1		T47	2
auto[BaudRate115200]	freqs[24]	173	1			T8	1		T160	2		T123	5
auto[BaudRate115200]	freqs[25]	196	1			T25	2		T30	24		T49	1
auto[BaudRate115200]	freqs[48]	100	1			T12	13		T349	1		T252	2
auto[BaudRate115200]	freqs[50]	93	1			T6	1		T52	1		T119	1
auto[BaudRate115200]	freqs[100]	124	1			T31	2		T45	1		T47	1
auto[BaudRate230400]	freqs[24]	151	1			T8	1		T160	1		T123	3
auto[BaudRate230400]	freqs[25]	145	1			T25	3		T30	3		T49	1
auto[BaudRate230400]	freqs[48]	100	1			T2	1		T304	1		T12	6
auto[BaudRate230400]	freqs[50]	87	1			T52	1		T216	9		T342	1
auto[BaudRate230400]	freqs[100]	112	1			T31	3		T45	1		T47	1
auto[BaudRate128Kbps]	freqs[24]	141	1			T22	2		T123	3		T403	1
auto[BaudRate128Kbps]	freqs[25]	155	1			T10	3		T25	1		T30	12
auto[BaudRate128Kbps]	freqs[48]	101	1			T5	1		T12	4		T349	3
auto[BaudRate128Kbps]	freqs[50]	88	1			T52	1		T119	1		T216	13
auto[BaudRate128Kbps]	freqs[100]	116	1			T31	2		T56	3		T45	1
auto[BaudRate256Kbps]	freqs[24]	172	1			T8	1		T160	2		T123	11
auto[BaudRate256Kbps]	freqs[25]	178	1			T10	1		T25	1		T30	3
auto[BaudRate256Kbps]	freqs[48]	97	1			T2	4		T5	1		T304	2
auto[BaudRate256Kbps]	freqs[50]	106	1			T6	1		T119	2		T216	9
auto[BaudRate256Kbps]	freqs[100]	107	1			T31	2		T56	3		T45	1
auto[BaudRate1Mbps]	freqs[24]	180	1			T8	2		T123	15		T403	1
auto[BaudRate1Mbps]	freqs[25]	165	1			T10	1		T25	1		T30	3
auto[BaudRate1Mbps]	freqs[48]	108	1			T2	2		T12	13		T349	1
auto[BaudRate1Mbps]	freqs[50]	104	1			T6	2		T52	3		T119	6
auto[BaudRate1Mbps]	freqs[100]	133	1			T31	2		T56	4		T45	1
auto[BaudRate1p5Mbps]	freqs[25]	82	1			T10	1		T25	1		T30	3
auto[BaudRate1p5Mbps]	freqs[48]	104	1			T2	1		T304	1		T12	6
auto[BaudRate1p5Mbps]	freqs[50]	106	1			T6	1		T119	7		T216	11
auto[BaudRate1p5Mbps]	freqs[100]	118	1			T31	1		T56	1		T47	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded