Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1203 1 T31 1 T121 4 T51 2
all_levels[1] 612 1 T25 6 T18 21 T11 8
all_levels[2] 292 1 T19 8 T138 8 T123 8
all_levels[3] 236 1 T90 2 T145 1 T122 5
all_levels[4] 162 1 T26 4 T168 1 T27 8
all_levels[5] 116 1 T163 13 T13 6 T39 2
all_levels[6] 70 1 T290 15 T448 7 T111 2
all_levels[7] 71 1 T449 4 T107 2 T41 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%