Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	95194	1			T1	53		T2	9		T3	2
all_pins[1]	95194	1			T1	53		T2	9		T3	2
all_pins[2]	95194	1			T1	53		T2	9		T3	2
all_pins[3]	95194	1			T1	53		T2	9		T3	2
all_pins[4]	95194	1			T1	53		T2	9		T3	2
all_pins[5]	95194	1			T1	53		T2	9		T3	2
all_pins[6]	95194	1			T1	53		T2	9		T3	2
all_pins[7]	95194	1			T1	53		T2	9		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	736797	1			T1	366		T2	62		T3	16
values[0x1]	24755	1			T1	58		T2	10		T4	1
transitions[0x0=>0x1]	23788	1			T1	58		T2	10		T4	1
transitions[0x1=>0x0]	23361	1			T1	57		T2	9		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	75590	1			T2	2		T3	2		T5	2
all_pins[0]	values[0x1]	19604	1			T1	53		T2	7		T4	1
all_pins[0]	transitions[0x0=>0x1]	19027	1			T1	53		T2	7		T4	1
all_pins[0]	transitions[0x1=>0x0]	978	1			T31	1		T25	1		T18	48
all_pins[1]	values[0x0]	93639	1			T1	53		T2	9		T3	2
all_pins[1]	values[0x1]	1555	1			T31	1		T25	1		T18	48
all_pins[1]	transitions[0x0=>0x1]	1482	1			T25	1		T18	46		T163	5
all_pins[1]	transitions[0x1=>0x0]	1952	1			T1	5		T2	3		T6	1
all_pins[2]	values[0x0]	93169	1			T1	48		T2	6		T3	2
all_pins[2]	values[0x1]	2025	1			T1	5		T2	3		T6	1
all_pins[2]	transitions[0x0=>0x1]	1980	1			T1	5		T2	3		T6	1
all_pins[2]	transitions[0x1=>0x0]	131	1			T11	4		T23	3		T24	2
all_pins[3]	values[0x0]	95018	1			T1	53		T2	9		T3	2
all_pins[3]	values[0x1]	176	1			T11	6		T13	1		T23	3
all_pins[3]	transitions[0x0=>0x1]	137	1			T11	4		T13	1		T23	3
all_pins[3]	transitions[0x1=>0x0]	255	1			T11	7		T15	1		T26	1
all_pins[4]	values[0x0]	94900	1			T1	53		T2	9		T3	2
all_pins[4]	values[0x1]	294	1			T11	9		T15	1		T26	1
all_pins[4]	transitions[0x0=>0x1]	253	1			T11	7		T15	1		T26	1
all_pins[4]	transitions[0x1=>0x0]	108	1			T11	8		T15	1		T12	1
all_pins[5]	values[0x0]	95045	1			T1	53		T2	9		T3	2
all_pins[5]	values[0x1]	149	1			T11	10		T15	1		T12	1
all_pins[5]	transitions[0x0=>0x1]	120	1			T11	8		T15	1		T12	1
all_pins[5]	transitions[0x1=>0x0]	645	1			T7	1		T90	1		T89	1
all_pins[6]	values[0x0]	94520	1			T1	53		T2	9		T3	2
all_pins[6]	values[0x1]	674	1			T7	1		T90	1		T89	1
all_pins[6]	transitions[0x0=>0x1]	641	1			T7	1		T90	1		T89	1
all_pins[6]	transitions[0x1=>0x0]	245	1			T18	27		T11	7		T117	7
all_pins[7]	values[0x0]	94916	1			T1	53		T2	9		T3	2
all_pins[7]	values[0x1]	278	1			T18	27		T11	9		T117	7
all_pins[7]	transitions[0x0=>0x1]	148	1			T18	27		T11	6		T117	6
all_pins[7]	transitions[0x1=>0x0]	19047	1			T1	52		T2	6		T7	8