Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
7 |
0 |
7 |
100.00 |
Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
7 |
0 |
7 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
7 |
0 |
7 |
100.00 |
User Defined Bins for cp_watermark_lvl
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
4071 |
1 |
|
|
T3 |
2 |
|
T5 |
2 |
|
T7 |
15 |
all_levels[1] |
3160 |
1 |
|
|
T1 |
4 |
|
T6 |
1 |
|
T89 |
2 |
all_levels[2] |
4061 |
1 |
|
|
T9 |
3 |
|
T89 |
6 |
|
T31 |
3 |
all_levels[3] |
4157 |
1 |
|
|
T7 |
2 |
|
T9 |
6 |
|
T90 |
2 |
all_levels[4] |
6285 |
1 |
|
|
T2 |
5 |
|
T7 |
8 |
|
T89 |
9 |
all_levels[5] |
6622 |
1 |
|
|
T1 |
49 |
|
T2 |
2 |
|
T4 |
1 |
all_levels[6] |
10182 |
1 |
|
|
T6 |
1 |
|
T8 |
2 |
|
T9 |
1 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |