Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	496	1			T11	32		T15	4		T12	4
all_values[1]	496	1			T11	32		T15	4		T12	4
all_values[2]	496	1			T11	32		T15	4		T12	4
all_values[3]	496	1			T11	32		T15	4		T12	4
all_values[4]	496	1			T11	32		T15	4		T12	4
all_values[5]	496	1			T11	32		T15	4		T12	4
all_values[6]	496	1			T11	32		T15	4		T12	4
all_values[7]	496	1			T11	32		T15	4		T12	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2104

1

T11

124

T15

24

T12

16

auto[1]

1864

1

T11

132

T15

8

T12

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1507

1

T11

105

T15

17

T12

16

auto[1]

2461

1

T11

151

T15

15

T12

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2406

1

T11

156

T15

24

T12

20

auto[1]

1562

1

T11

100

T15

8

T12

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	162	1			T11	10		T15	3		T12	1
all_values[0]	auto[0]	auto[1]	auto[1]	133	1			T11	7		T12	1		T13	1
all_values[0]	auto[1]	auto[0]	auto[1]	107	1			T11	9		T15	1		T12	1
all_values[0]	auto[1]	auto[1]	auto[1]	94	1			T11	6		T12	1		T38	1
all_values[1]	auto[0]	auto[0]	auto[0]	146	1			T11	9		T15	2		T12	1
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T11	9		T15	1		T12	1
all_values[1]	auto[1]	auto[0]	auto[1]	117	1			T11	8		T15	1		T12	1
all_values[1]	auto[1]	auto[1]	auto[1]	100	1			T11	6		T12	1		T13	2
all_values[2]	auto[0]	auto[0]	auto[0]	108	1			T11	11		T12	4		T13	2
all_values[2]	auto[0]	auto[0]	auto[1]	43	1			T11	1		T13	1		T41	1
all_values[2]	auto[0]	auto[1]	auto[0]	81	1			T11	8		T24	3		T368	1
all_values[2]	auto[0]	auto[1]	auto[1]	58	1			T15	2		T38	1		T24	2
all_values[2]	auto[1]	auto[0]	auto[1]	117	1			T11	8		T15	2		T38	1
all_values[2]	auto[1]	auto[1]	auto[1]	89	1			T11	4		T13	1		T38	1
all_values[3]	auto[0]	auto[0]	auto[0]	102	1			T11	8		T15	2		T13	2
all_values[3]	auto[0]	auto[0]	auto[1]	45	1			T11	4		T24	3		T368	1
all_values[3]	auto[0]	auto[1]	auto[0]	84	1			T11	7		T15	2		T12	3
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T11	2		T368	2		T41	1
all_values[3]	auto[1]	auto[0]	auto[1]	100	1			T11	3		T13	1		T24	4
all_values[3]	auto[1]	auto[1]	auto[1]	98	1			T11	8		T12	1		T13	1
all_values[4]	auto[0]	auto[0]	auto[0]	108	1			T11	6		T15	1		T12	1
all_values[4]	auto[0]	auto[0]	auto[1]	50	1			T11	3		T15	1		T24	4
all_values[4]	auto[0]	auto[1]	auto[0]	82	1			T11	9		T12	2		T13	1
all_values[4]	auto[0]	auto[1]	auto[1]	59	1			T11	4		T24	2		T368	1
all_values[4]	auto[1]	auto[0]	auto[1]	112	1			T11	3		T15	1		T12	1
all_values[4]	auto[1]	auto[1]	auto[1]	85	1			T11	7		T15	1		T24	2
all_values[5]	auto[0]	auto[0]	auto[0]	123	1			T11	6		T15	1		T13	2
all_values[5]	auto[0]	auto[0]	auto[1]	42	1			T11	1		T38	2		T24	1
all_values[5]	auto[0]	auto[1]	auto[0]	102	1			T11	7		T12	1		T13	2
all_values[5]	auto[0]	auto[1]	auto[1]	53	1			T11	3		T15	1		T24	2
all_values[5]	auto[1]	auto[0]	auto[1]	87	1			T11	3		T15	2		T12	2
all_values[5]	auto[1]	auto[1]	auto[1]	89	1			T11	12		T12	1		T38	1
all_values[6]	auto[0]	auto[0]	auto[0]	129	1			T11	5		T15	3		T12	3
all_values[6]	auto[0]	auto[0]	auto[1]	46	1			T11	4		T13	2		T24	4
all_values[6]	auto[0]	auto[1]	auto[0]	109	1			T11	6		T15	1		T38	2
all_values[6]	auto[0]	auto[1]	auto[1]	42	1			T11	4		T368	2		T41	2
all_values[6]	auto[1]	auto[0]	auto[1]	96	1			T11	7		T12	1		T24	3
all_values[6]	auto[1]	auto[1]	auto[1]	74	1			T11	6		T13	1		T38	1
all_values[7]	auto[0]	auto[0]	auto[0]	100	1			T11	6		T15	4		T13	1
all_values[7]	auto[0]	auto[0]	auto[1]	47	1			T11	4		T13	2		T24	2
all_values[7]	auto[0]	auto[1]	auto[0]	100	1			T11	8		T38	2		T368	4
all_values[7]	auto[0]	auto[1]	auto[1]	52	1			T11	4		T12	2		T38	1
all_values[7]	auto[1]	auto[0]	auto[1]	117	1			T11	5		T13	1		T368	2
all_values[7]	auto[1]	auto[1]	auto[1]	80	1			T11	5		T12	2		T38	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal