Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81605	1			T1	2		T2	2		T3	11
all_values[1]	81605	1			T1	2		T2	2		T3	11
all_values[2]	81605	1			T1	2		T2	2		T3	11
all_values[3]	81605	1			T1	2		T2	2		T3	11
all_values[4]	81605	1			T1	2		T2	2		T3	11
all_values[5]	81605	1			T1	2		T2	2		T3	11
all_values[6]	81605	1			T1	2		T2	2		T3	11
all_values[7]	81605	1			T1	2		T2	2		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329746

1

T1

10

T2

16

T3

53

auto[1]

323094

1

T1

6

T3

35

T4

100

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605037

1

T1

14

T2

13

T3

79

auto[1]

47803

1

T1

2

T2

3

T3

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	20830	1			T7	39		T11	20		T85	5
all_values[0]	auto[0]	auto[1]	18914	1			T2	2		T3	3		T5	17
all_values[0]	auto[1]	auto[0]	21808	1			T1	1		T3	3		T5	1
all_values[0]	auto[1]	auto[1]	20053	1			T1	1		T3	5		T4	20
all_values[1]	auto[0]	auto[0]	39320	1			T1	2		T2	2		T3	11
all_values[1]	auto[0]	auto[1]	1243	1			T4	13		T119	11		T21	4
all_values[1]	auto[1]	auto[0]	39868	1			T4	2		T5	4		T7	43
all_values[1]	auto[1]	auto[1]	1174	1			T117	8		T19	3		T42	4
all_values[2]	auto[0]	auto[0]	37606	1			T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	2380	1			T1	1		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	39596	1			T3	8		T4	18		T5	3
all_values[2]	auto[1]	auto[1]	2023	1			T5	1		T11	12		T115	2
all_values[3]	auto[0]	auto[0]	41055	1			T1	2		T2	2		T5	13
all_values[3]	auto[0]	auto[1]	219	1			T5	1		T11	4		T19	1
all_values[3]	auto[1]	auto[0]	40113	1			T3	11		T4	20		T5	4
all_values[3]	auto[1]	auto[1]	218	1			T11	2		T12	2		T19	1
all_values[4]	auto[0]	auto[0]	38801	1			T1	2		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	281	1			T11	2		T15	5		T22	2
all_values[4]	auto[1]	auto[0]	42222	1			T3	8		T4	20		T5	14
all_values[4]	auto[1]	auto[1]	301	1			T11	1		T15	5		T16	1
all_values[5]	auto[0]	auto[0]	43832	1			T1	2		T2	2		T3	11
all_values[5]	auto[0]	auto[1]	112	1			T11	2		T16	1		T22	2
all_values[5]	auto[1]	auto[0]	37538	1			T4	2		T5	14		T7	51
all_values[5]	auto[1]	auto[1]	123	1			T16	3		T22	4		T84	3
all_values[6]	auto[0]	auto[0]	43164	1			T2	2		T3	11		T4	2
all_values[6]	auto[0]	auto[1]	121	1			T16	1		T22	1		T84	5
all_values[6]	auto[1]	auto[0]	38181	1			T1	2		T4	18		T5	17
all_values[6]	auto[1]	auto[1]	139	1			T16	1		T22	7		T245	1
all_values[7]	auto[0]	auto[0]	41612	1			T2	2		T3	11		T4	20
all_values[7]	auto[0]	auto[1]	256	1			T10	2		T11	2		T26	1
all_values[7]	auto[1]	auto[0]	39491	1			T1	2		T5	18		T7	17
all_values[7]	auto[1]	auto[1]	246	1			T11	1		T26	4		T120	2