Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1921	1			T2	1		T3	1		T4	1
auto[BaudRate115200]	1615	1			T4	1		T5	1		T7	1
auto[BaudRate230400]	1534	1			T3	3		T5	1		T8	1
auto[BaudRate128Kbps]	1522	1			T4	1		T5	1		T7	1
auto[BaudRate256Kbps]	1735	1			T4	1		T6	1		T7	3
auto[BaudRate1Mbps]	1479	1			T1	3		T2	1		T3	2
auto[BaudRate1p5Mbps]	1019	1			T5	2		T6	1		T7	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1380	1			T7	8		T27	2		T51	6
freqs[25]	1029	1			T5	5		T8	10		T49	2
freqs[48]	610	1			T85	16		T20	6		T12	6
freqs[50]	498	1			T2	2		T9	2		T14	18
freqs[100]	996	1			T10	5		T115	5		T41	6

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	216	1			T7	2		T27	1		T47	3
auto[BaudRate9600]	freqs[25]	162	1			T168	1		T142	1		T146	1
auto[BaudRate9600]	freqs[48]	92	1			T85	4		T136	4		T267	1
auto[BaudRate9600]	freqs[50]	95	1			T2	1		T9	1		T14	18
auto[BaudRate9600]	freqs[100]	147	1			T41	1		T131	2		T287	1
auto[BaudRate115200]	freqs[24]	236	1			T7	1		T51	1		T129	3
auto[BaudRate115200]	freqs[25]	151	1			T5	1		T168	2		T142	1
auto[BaudRate115200]	freqs[48]	77	1			T85	2		T336	3		T100	2
auto[BaudRate115200]	freqs[50]	64	1			T9	1		T337	3		T247	2
auto[BaudRate115200]	freqs[100]	145	1			T115	1		T48	1		T131	3
auto[BaudRate230400]	freqs[24]	198	1			T27	1		T51	3		T47	1
auto[BaudRate230400]	freqs[25]	162	1			T5	1		T8	1		T168	2
auto[BaudRate230400]	freqs[48]	70	1			T85	3		T336	3		T136	1
auto[BaudRate230400]	freqs[50]	63	1			T262	2		T186	1		T315	1
auto[BaudRate230400]	freqs[100]	167	1			T115	3		T43	1		T48	5
auto[BaudRate128Kbps]	freqs[24]	190	1			T7	1		T47	3		T274	3
auto[BaudRate128Kbps]	freqs[25]	146	1			T5	1		T8	2		T49	2
auto[BaudRate128Kbps]	freqs[48]	102	1			T85	1		T336	6		T293	1
auto[BaudRate128Kbps]	freqs[50]	66	1			T262	2		T283	1		T247	1
auto[BaudRate128Kbps]	freqs[100]	159	1			T10	1		T41	2		T43	1
auto[BaudRate256Kbps]	freqs[24]	203	1			T7	3		T47	1		T129	2
auto[BaudRate256Kbps]	freqs[25]	145	1			T8	1		T168	1		T142	1
auto[BaudRate256Kbps]	freqs[48]	94	1			T12	2		T336	6		T136	4
auto[BaudRate256Kbps]	freqs[50]	71	1			T180	1		T262	3		T247	1
auto[BaudRate256Kbps]	freqs[100]	122	1			T43	2		T48	1		T128	1
auto[BaudRate1Mbps]	freqs[24]	236	1			T51	1		T47	1		T269	1
auto[BaudRate1Mbps]	freqs[25]	171	1			T8	4		T168	2		T146	2
auto[BaudRate1Mbps]	freqs[48]	75	1			T85	1		T20	4		T12	3
auto[BaudRate1Mbps]	freqs[50]	74	1			T2	1		T180	2		T337	3
auto[BaudRate1Mbps]	freqs[100]	141	1			T10	2		T115	1		T41	1
auto[BaudRate1p5Mbps]	freqs[25]	92	1			T5	2		T8	2		T168	3
auto[BaudRate1p5Mbps]	freqs[48]	100	1			T85	5		T20	2		T12	1
auto[BaudRate1p5Mbps]	freqs[50]	65	1			T180	2		T262	2		T247	1
auto[BaudRate1p5Mbps]	freqs[100]	115	1			T10	2		T41	2		T43	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded