Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	23840957	1			T1	10		T3	5		T4	2
all_levels[1]	184782	1			T7	2		T8	1		T11	7
all_levels[2]	2276	1			T4	1		T5	1		T7	2
all_levels[3]	975	1			T4	1		T10	1		T11	5
all_levels[4]	661	1			T11	3		T115	1		T85	1
all_levels[5]	530	1			T4	3		T11	2		T85	1
all_levels[6]	387	1			T7	1		T11	1		T19	1
all_levels[7]	299	1			T7	1		T119	2		T21	1
all_levels[8]	254	1			T3	1		T5	1		T85	1
all_levels[9]	224	1			T4	4		T19	3		T119	3
all_levels[10]	208	1			T8	1		T117	3		T19	2
all_levels[11]	151	1			T11	1		T19	1		T126	2
all_levels[12]	145	1			T119	2		T48	1		T120	1
all_levels[13]	121	1			T117	1		T119	2		T48	1
all_levels[14]	114	1			T5	1		T10	1		T11	1
all_levels[15]	88	1			T3	1		T127	1		T128	1
all_levels[16]	83	1			T12	3		T119	1		T129	1
all_levels[17]	79	1			T10	1		T19	1		T45	1
all_levels[18]	85	1			T119	1		T48	1		T130	1
all_levels[19]	61	1			T8	1		T11	2		T18	1
all_levels[20]	70	1			T119	1		T45	1		T26	2
all_levels[21]	55	1			T19	1		T48	1		T15	1
all_levels[22]	62	1			T45	1		T48	1		T131	1
all_levels[23]	60	1			T7	1		T129	1		T26	1
all_levels[24]	49	1			T21	1		T132	1		T133	1
all_levels[25]	29	1			T120	2		T134	1		T22	1
all_levels[26]	40	1			T8	1		T135	1		T136	1
all_levels[27]	35	1			T19	1		T122	3		T16	1
all_levels[28]	38	1			T137	1		T138	1		T139	1
all_levels[29]	43	1			T131	1		T140	1		T141	1
all_levels[30]	32	1			T45	1		T120	1		T140	1
all_levels[31]	28	1			T142	1		T35	1		T143	1
all_levels[32]	15	1			T19	1		T16	1		T144	1
all_levels[33]	30	1			T131	1		T15	2		T121	1
all_levels[34]	18	1			T5	1		T42	1		T141	3
all_levels[35]	22	1			T131	1		T35	2		T145	1
all_levels[36]	33	1			T131	1		T121	1		T146	1
all_levels[37]	12	1			T124	1		T141	1		T147	2
all_levels[38]	22	1			T148	1		T149	1		T150	1
all_levels[39]	25	1			T131	1		T124	3		T16	1
all_levels[40]	13	1			T21	1		T151	1		T152	3
all_levels[41]	13	1			T10	1		T142	2		T151	1
all_levels[42]	24	1			T10	1		T136	2		T133	1
all_levels[43]	7	1			T8	1		T153	1		T139	1
all_levels[44]	10	1			T120	1		T153	1		T148	2
all_levels[45]	11	1			T146	1		T151	1		T154	1
all_levels[46]	11	1			T21	1		T155	1		T151	3
all_levels[47]	15	1			T12	2		T142	3		T156	2
all_levels[48]	19	1			T137	1		T36	1		T157	1
all_levels[49]	14	1			T45	1		T151	1		T148	1
all_levels[50]	3	1			T129	1		T153	1		T158	1
all_levels[51]	5	1			T159	1		T160	1		T161	1
all_levels[52]	13	1			T21	1		T162	1		T138	1
all_levels[53]	5	1			T3	2		T148	1		T163	1
all_levels[54]	5	1			T161	1		T164	1		T165	1
all_levels[55]	5	1			T142	1		T166	1		T167	1
all_levels[56]	8	1			T168	1		T37	1		T105	1
all_levels[57]	6	1			T169	1		T154	1		T170	1
all_levels[58]	5	1			T171	1		T172	1		T173	2
all_levels[59]	11	1			T35	1		T174	1		T175	1
all_levels[60]	5	1			T176	3		T161	2		-	-
all_levels[61]	3	1			T129	1		T177	1		T178	1
all_levels[62]	8	1			T129	1		T36	1		T179	1
all_levels[63]	11	1			T5	1		T120	1		T140	3
all_levels[64]	126	1			T5	1		T129	2		T120	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24029594

1

T1

10

T3

4

T4

5

auto[1]

3960

1

T3

5

T4

6

T5

2

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[25]]	[auto[1]]	0	1	1
[all_levels[32]]	[auto[1]]	0	1	1
[all_levels[43] , all_levels[44] , all_levels[45] , all_levels[46]]	[auto[1]]	--	--	4
[all_levels[49] , all_levels[50] , all_levels[51]]	[auto[1]]	--	--	3
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[61] , all_levels[62]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	23837438	1			T1	10		T3	1		T4	1
all_levels[0]	auto[1]	3519	1			T3	4		T4	1		T5	2
all_levels[1]	auto[0]	184708	1			T7	2		T8	1		T11	7
all_levels[1]	auto[1]	74	1			T126	3		T131	2		T180	2
all_levels[2]	auto[0]	2238	1			T4	1		T5	1		T7	2
all_levels[2]	auto[1]	38	1			T181	1		T182	2		T159	2
all_levels[3]	auto[0]	957	1			T4	1		T10	1		T11	5
all_levels[3]	auto[1]	18	1			T131	1		T148	1		T183	3
all_levels[4]	auto[0]	642	1			T11	3		T115	1		T85	1
all_levels[4]	auto[1]	19	1			T152	3		T184	1		T185	2
all_levels[5]	auto[0]	505	1			T4	1		T11	2		T85	1
all_levels[5]	auto[1]	25	1			T4	2		T134	1		T35	2
all_levels[6]	auto[0]	374	1			T7	1		T11	1		T19	1
all_levels[6]	auto[1]	13	1			T136	1		T134	1		T166	2
all_levels[7]	auto[0]	288	1			T7	1		T119	2		T21	1
all_levels[7]	auto[1]	11	1			T15	2		T186	2		T187	1
all_levels[8]	auto[0]	243	1			T3	1		T5	1		T85	1
all_levels[8]	auto[1]	11	1			T141	1		T148	1		T188	2
all_levels[9]	auto[0]	212	1			T4	1		T19	2		T119	2
all_levels[9]	auto[1]	12	1			T4	3		T19	1		T119	1
all_levels[10]	auto[0]	198	1			T8	1		T117	1		T19	2
all_levels[10]	auto[1]	10	1			T117	2		T189	2		T190	1
all_levels[11]	auto[0]	137	1			T11	1		T19	1		T126	1
all_levels[11]	auto[1]	14	1			T126	1		T191	1		T114	1
all_levels[12]	auto[0]	130	1			T119	2		T48	1		T120	1
all_levels[12]	auto[1]	15	1			T122	1		T136	1		T192	1
all_levels[13]	auto[0]	108	1			T117	1		T119	1		T48	1
all_levels[13]	auto[1]	13	1			T119	1		T15	2		T124	1
all_levels[14]	auto[0]	104	1			T5	1		T10	1		T11	1
all_levels[14]	auto[1]	10	1			T117	1		T184	1		T193	1
all_levels[15]	auto[0]	83	1			T3	1		T127	1		T128	1
all_levels[15]	auto[1]	5	1			T16	1		T194	2		T195	1
all_levels[16]	auto[0]	79	1			T12	1		T119	1		T129	1
all_levels[16]	auto[1]	4	1			T12	2		T196	1		T197	1
all_levels[17]	auto[0]	74	1			T10	1		T19	1		T45	1
all_levels[17]	auto[1]	5	1			T184	1		T198	1		T199	1
all_levels[18]	auto[0]	77	1			T119	1		T48	1		T130	1
all_levels[18]	auto[1]	8	1			T200	1		T201	1		T202	1
all_levels[19]	auto[0]	58	1			T8	1		T11	1		T18	1
all_levels[19]	auto[1]	3	1			T11	1		T203	1		T204	1
all_levels[20]	auto[0]	61	1			T119	1		T45	1		T26	2
all_levels[20]	auto[1]	9	1			T142	1		T205	1		T206	2
all_levels[21]	auto[0]	51	1			T19	1		T48	1		T15	1
all_levels[21]	auto[1]	4	1			T207	1		T208	2		T209	1
all_levels[22]	auto[0]	49	1			T45	1		T48	1		T131	1
all_levels[22]	auto[1]	13	1			T152	2		T210	6		T211	1
all_levels[23]	auto[0]	49	1			T7	1		T129	1		T26	1
all_levels[23]	auto[1]	11	1			T212	4		T213	1		T214	1
all_levels[24]	auto[0]	46	1			T21	1		T132	1		T133	1
all_levels[24]	auto[1]	3	1			T154	1		T215	2		-	-
all_levels[25]	auto[0]	29	1			T120	2		T134	1		T22	1
all_levels[26]	auto[0]	37	1			T8	1		T135	1		T136	1
all_levels[26]	auto[1]	3	1			T216	1		T105	2		-	-
all_levels[27]	auto[0]	32	1			T19	1		T122	1		T16	1
all_levels[27]	auto[1]	3	1			T122	2		T217	1		-	-
all_levels[28]	auto[0]	33	1			T137	1		T138	1		T139	1
all_levels[28]	auto[1]	5	1			T218	1		T219	2		T220	1
all_levels[29]	auto[0]	38	1			T131	1		T140	1		T141	1
all_levels[29]	auto[1]	5	1			T221	1		T154	1		T222	3
all_levels[30]	auto[0]	29	1			T45	1		T120	1		T140	1
all_levels[30]	auto[1]	3	1			T143	1		T201	1		T223	1
all_levels[31]	auto[0]	25	1			T142	1		T35	1		T143	1
all_levels[31]	auto[1]	3	1			T52	1		T224	1		T225	1
all_levels[32]	auto[0]	15	1			T19	1		T16	1		T144	1
all_levels[33]	auto[0]	27	1			T131	1		T15	1		T121	1
all_levels[33]	auto[1]	3	1			T15	1		T124	1		T226	1
all_levels[34]	auto[0]	16	1			T5	1		T42	1		T141	2
all_levels[34]	auto[1]	2	1			T141	1		T227	1		-	-
all_levels[35]	auto[0]	15	1			T131	1		T35	1		T145	1
all_levels[35]	auto[1]	7	1			T35	1		T148	1		T228	1
all_levels[36]	auto[0]	28	1			T131	1		T121	1		T146	1
all_levels[36]	auto[1]	5	1			T16	1		T229	2		T230	2
all_levels[37]	auto[0]	11	1			T124	1		T141	1		T147	1
all_levels[37]	auto[1]	1	1			T147	1		-	-		-	-
all_levels[38]	auto[0]	20	1			T148	1		T149	1		T150	1
all_levels[38]	auto[1]	2	1			T156	1		T231	1		-	-
all_levels[39]	auto[0]	22	1			T131	1		T124	1		T16	1
all_levels[39]	auto[1]	3	1			T124	2		T232	1		-	-
all_levels[40]	auto[0]	10	1			T21	1		T151	1		T152	1
all_levels[40]	auto[1]	3	1			T152	2		T233	1		-	-
all_levels[41]	auto[0]	12	1			T10	1		T142	1		T151	1
all_levels[41]	auto[1]	1	1			T142	1		-	-		-	-
all_levels[42]	auto[0]	16	1			T10	1		T136	1		T133	1
all_levels[42]	auto[1]	8	1			T136	1		T188	2		T234	2
all_levels[43]	auto[0]	7	1			T8	1		T153	1		T139	1
all_levels[44]	auto[0]	10	1			T120	1		T153	1		T148	2
all_levels[45]	auto[0]	11	1			T146	1		T151	1		T154	1
all_levels[46]	auto[0]	11	1			T21	1		T155	1		T151	3
all_levels[47]	auto[0]	12	1			T12	1		T142	2		T156	2
all_levels[47]	auto[1]	3	1			T12	1		T142	1		T235	1
all_levels[48]	auto[0]	15	1			T137	1		T36	1		T157	1
all_levels[48]	auto[1]	4	1			T236	1		T237	1		T238	1
all_levels[49]	auto[0]	14	1			T45	1		T151	1		T148	1
all_levels[50]	auto[0]	3	1			T129	1		T153	1		T158	1
all_levels[51]	auto[0]	5	1			T159	1		T160	1		T161	1
all_levels[52]	auto[0]	12	1			T21	1		T162	1		T138	1
all_levels[52]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[53]	auto[0]	4	1			T3	1		T148	1		T163	1
all_levels[53]	auto[1]	1	1			T3	1		-	-		-	-
all_levels[54]	auto[0]	5	1			T161	1		T164	1		T165	1
all_levels[55]	auto[0]	5	1			T142	1		T166	1		T167	1
all_levels[56]	auto[0]	7	1			T168	1		T37	1		T105	1
all_levels[56]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[57]	auto[0]	4	1			T169	1		T154	1		T170	1
all_levels[57]	auto[1]	2	1			T241	2		-	-		-	-
all_levels[58]	auto[0]	4	1			T171	1		T172	1		T173	1
all_levels[58]	auto[1]	1	1			T173	1		-	-		-	-
all_levels[59]	auto[0]	10	1			T35	1		T174	1		T175	1
all_levels[59]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[60]	auto[0]	3	1			T176	1		T161	2		-	-
all_levels[60]	auto[1]	2	1			T176	2		-	-		-	-
all_levels[61]	auto[0]	3	1			T129	1		T177	1		T178	1
all_levels[62]	auto[0]	8	1			T129	1		T36	1		T179	1
all_levels[63]	auto[0]	7	1			T5	1		T120	1		T140	1
all_levels[63]	auto[1]	4	1			T140	2		T243	2		-	-
all_levels[64]	auto[0]	110	1			T5	1		T129	2		T120	1
all_levels[64]	auto[1]	16	1			T174	1		T244	2		T148	1