Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81605	1			T1	2		T2	2		T3	11
all_pins[1]	81605	1			T1	2		T2	2		T3	11
all_pins[2]	81605	1			T1	2		T2	2		T3	11
all_pins[3]	81605	1			T1	2		T2	2		T3	11
all_pins[4]	81605	1			T1	2		T2	2		T3	11
all_pins[5]	81605	1			T1	2		T2	2		T3	11
all_pins[6]	81605	1			T1	2		T2	2		T3	11
all_pins[7]	81605	1			T1	2		T2	2		T3	11

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	627841	1			T1	15		T2	16		T3	83
values[0x1]	24999	1			T1	1		T3	5		T4	20
transitions[0x0=>0x1]	24247	1			T1	1		T3	5		T4	20
transitions[0x1=>0x0]	23802	1			T3	5		T4	19		T5	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61509	1			T1	1		T2	2		T3	6
all_pins[0]	values[0x1]	20096	1			T1	1		T3	5		T4	20
all_pins[0]	transitions[0x0=>0x1]	19739	1			T1	1		T3	5		T4	20
all_pins[0]	transitions[0x1=>0x0]	817	1			T117	1		T19	3		T42	4
all_pins[1]	values[0x0]	80431	1			T1	2		T2	2		T3	11
all_pins[1]	values[0x1]	1174	1			T117	8		T19	3		T42	4
all_pins[1]	transitions[0x0=>0x1]	1086	1			T117	8		T19	2		T42	4
all_pins[1]	transitions[0x1=>0x0]	1966	1			T5	1		T11	12		T115	2
all_pins[2]	values[0x0]	79551	1			T1	2		T2	2		T3	11
all_pins[2]	values[0x1]	2054	1			T5	1		T11	12		T115	2
all_pins[2]	transitions[0x0=>0x1]	1998	1			T5	1		T11	12		T115	2
all_pins[2]	transitions[0x1=>0x0]	162	1			T11	2		T12	2		T19	1
all_pins[3]	values[0x0]	81387	1			T1	2		T2	2		T3	11
all_pins[3]	values[0x1]	218	1			T11	2		T12	2		T19	1
all_pins[3]	transitions[0x0=>0x1]	189	1			T11	2		T12	2		T19	1
all_pins[3]	transitions[0x1=>0x0]	272	1			T11	1		T15	5		T16	1
all_pins[4]	values[0x0]	81304	1			T1	2		T2	2		T3	11
all_pins[4]	values[0x1]	301	1			T11	1		T15	5		T16	1
all_pins[4]	transitions[0x0=>0x1]	256	1			T11	1		T15	5		T16	1
all_pins[4]	transitions[0x1=>0x0]	109	1			T16	3		T22	3		T246	1
all_pins[5]	values[0x0]	81451	1			T1	2		T2	2		T3	11
all_pins[5]	values[0x1]	154	1			T16	3		T24	2		T25	1
all_pins[5]	transitions[0x0=>0x1]	124	1			T16	3		T24	2		T25	1
all_pins[5]	transitions[0x1=>0x0]	726	1			T5	4		T10	1		T11	1
all_pins[6]	values[0x0]	80849	1			T1	2		T2	2		T3	11
all_pins[6]	values[0x1]	756	1			T5	4		T10	1		T11	1
all_pins[6]	transitions[0x0=>0x1]	721	1			T5	4		T10	1		T11	1
all_pins[6]	transitions[0x1=>0x0]	211	1			T11	1		T26	4		T120	2
all_pins[7]	values[0x0]	81359	1			T1	2		T2	2		T3	11
all_pins[7]	values[0x1]	246	1			T11	1		T26	4		T120	2
all_pins[7]	transitions[0x0=>0x1]	134	1			T26	2		T120	1		T15	3
all_pins[7]	transitions[0x1=>0x0]	19539	1			T3	5		T4	19		T7	4