Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6103705	1			T1	1		T3	8		T4	5
all_levels[1]	844796	1			T1	2		T8	1		T10	2
all_levels[2]	377427	1			T3	1		T11	11		T85	11
all_levels[3]	152028	1			T11	2		T85	17		T20	21
all_levels[4]	654807	1			T5	2		T7	2		T85	7
all_levels[5]	267655	1			T5	3		T11	2		T85	16
all_levels[6]	368062	1			T11	20		T115	1		T85	45
all_levels[7]	329680	1			T1	4		T115	3		T85	10
all_levels[8]	157846	1			T115	1		T85	5		T20	15
all_levels[9]	194238	1			T11	2		T115	2		T85	12
all_levels[10]	609314	1			T4	4		T7	1		T11	2
all_levels[11]	161021	1			T1	1		T11	10		T20	20
all_levels[12]	174222	1			T11	1		T20	24		T117	1
all_levels[13]	165628	1			T11	4		T85	1		T20	19
all_levels[14]	134414	1			T7	2		T11	9		T20	25
all_levels[15]	133253	1			T4	3		T11	1		T85	125
all_levels[16]	266263	1			T11	2		T85	19		T20	21
all_levels[17]	131987	1			T11	1		T20	17		T117	3
all_levels[18]	181757	1			T115	2		T85	1		T20	17
all_levels[19]	131677	1			T1	3		T7	2		T10	3
all_levels[20]	141296	1			T50	4		T20	22		T18	5
all_levels[21]	132046	1			T11	3		T85	3		T20	16
all_levels[22]	219171	1			T7	4		T20	23		T117	2
all_levels[23]	158410	1			T7	5		T50	3		T20	25
all_levels[24]	253647	1			T20	27		T117	2		T51	109
all_levels[25]	231339	1			T20	25		T117	1		T51	29133
all_levels[26]	140334	1			T5	2		T20	21		T117	2
all_levels[27]	222502	1			T11	7		T20	20		T117	2
all_levels[28]	143909	1			T20	19		T117	7		T19	5
all_levels[29]	174298	1			T7	1		T11	2		T20	16
all_levels[30]	121630	1			T20	19		T117	1		T51	108
all_levels[31]	362350	1			T7	3		T11	3		T20	568
all_levels[32]	10192594	1			T7	69		T10	7		T11	24

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24029594

1

T1

10

T3

4

T4

5

auto[1]

3712

1

T1

1

T3

5

T4

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6101777	1			T1	1		T3	3		T4	2
all_levels[0]	auto[1]	1928	1			T3	5		T4	3		T5	4
all_levels[1]	auto[0]	844600	1			T1	2		T8	1		T10	2
all_levels[1]	auto[1]	196	1			T11	1		T19	1		T18	1
all_levels[2]	auto[0]	377381	1			T3	1		T11	11		T85	11
all_levels[2]	auto[1]	46	1			T117	1		T131	1		T180	1
all_levels[3]	auto[0]	151931	1			T11	2		T85	17		T20	21
all_levels[3]	auto[1]	97	1			T15	2		T24	2		T339	29
all_levels[4]	auto[0]	654768	1			T5	1		T7	2		T85	7
all_levels[4]	auto[1]	39	1			T5	1		T130	1		T100	1
all_levels[5]	auto[0]	267630	1			T5	2		T11	2		T85	16
all_levels[5]	auto[1]	25	1			T5	1		T122	2		T308	1
all_levels[6]	auto[0]	368038	1			T11	20		T115	1		T85	45
all_levels[6]	auto[1]	24	1			T181	1		T298	1		T186	2
all_levels[7]	auto[0]	329588	1			T1	4		T115	3		T85	10
all_levels[7]	auto[1]	92	1			T136	1		T110	1		T306	4
all_levels[8]	auto[0]	157818	1			T115	1		T85	5		T20	15
all_levels[8]	auto[1]	28	1			T25	1		T303	2		T218	1
all_levels[9]	auto[0]	194216	1			T11	1		T115	2		T85	12
all_levels[9]	auto[1]	22	1			T11	1		T119	1		T130	1
all_levels[10]	auto[0]	609284	1			T4	2		T7	1		T11	2
all_levels[10]	auto[1]	30	1			T4	2		T261	1		T272	1
all_levels[11]	auto[0]	161000	1			T1	1		T11	10		T20	20
all_levels[11]	auto[1]	21	1			T180	1		T250	1		T340	1
all_levels[12]	auto[0]	174202	1			T11	1		T20	24		T117	1
all_levels[12]	auto[1]	20	1			T46	1		T188	3		T341	2
all_levels[13]	auto[0]	165598	1			T11	4		T85	1		T20	19
all_levels[13]	auto[1]	30	1			T261	1		T16	2		T25	1
all_levels[14]	auto[0]	134383	1			T7	2		T11	9		T20	25
all_levels[14]	auto[1]	31	1			T19	4		T45	2		T247	2
all_levels[15]	auto[0]	132930	1			T4	1		T11	1		T85	125
all_levels[15]	auto[1]	323	1			T4	2		T180	2		T15	4
all_levels[16]	auto[0]	266250	1			T11	2		T85	19		T20	21
all_levels[16]	auto[1]	13	1			T182	1		T161	1		T229	3
all_levels[17]	auto[0]	131966	1			T11	1		T20	17		T117	3
all_levels[17]	auto[1]	21	1			T142	1		T110	1		T316	1
all_levels[18]	auto[0]	181735	1			T115	2		T85	1		T20	17
all_levels[18]	auto[1]	22	1			T117	2		T102	1		T143	1
all_levels[19]	auto[0]	131658	1			T1	2		T7	2		T10	3
all_levels[19]	auto[1]	19	1			T1	1		T47	2		T162	1
all_levels[20]	auto[0]	141279	1			T50	4		T20	22		T18	4
all_levels[20]	auto[1]	17	1			T18	1		T142	1		T124	1
all_levels[21]	auto[0]	132024	1			T11	3		T85	2		T20	16
all_levels[21]	auto[1]	22	1			T85	1		T253	1		T342	1
all_levels[22]	auto[0]	219158	1			T7	4		T20	23		T117	2
all_levels[22]	auto[1]	13	1			T15	1		T130	1		T308	2
all_levels[23]	auto[0]	158383	1			T7	5		T50	2		T20	25
all_levels[23]	auto[1]	27	1			T50	1		T180	1		T318	1
all_levels[24]	auto[0]	253626	1			T20	27		T117	2		T51	109
all_levels[24]	auto[1]	21	1			T136	1		T153	1		T185	1
all_levels[25]	auto[0]	231321	1			T20	25		T117	1		T51	29132
all_levels[25]	auto[1]	18	1			T51	1		T292	1		T343	1
all_levels[26]	auto[0]	140314	1			T5	2		T20	21		T117	2
all_levels[26]	auto[1]	20	1			T135	2		T205	1		T139	1
all_levels[27]	auto[0]	222478	1			T11	7		T20	20		T117	2
all_levels[27]	auto[1]	24	1			T126	3		T44	1		T216	1
all_levels[28]	auto[0]	143894	1			T20	19		T117	7		T19	4
all_levels[28]	auto[1]	15	1			T19	1		T181	1		T100	2
all_levels[29]	auto[0]	174285	1			T7	1		T11	2		T20	16
all_levels[29]	auto[1]	13	1			T15	1		T296	1		T311	1
all_levels[30]	auto[0]	121611	1			T20	19		T117	1		T51	108
all_levels[30]	auto[1]	19	1			T185	1		T344	4		T345	1
all_levels[31]	auto[0]	362333	1			T7	3		T11	3		T20	568
all_levels[31]	auto[1]	17	1			T141	1		T259	1		T192	3
all_levels[32]	auto[0]	10192135	1			T7	69		T10	6		T11	24
all_levels[32]	auto[1]	459	1			T10	1		T20	1		T117	1