Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	502	1			T11	7		T16	7		T22	14
all_values[1]	502	1			T11	7		T16	7		T22	14
all_values[2]	502	1			T11	7		T16	7		T22	14
all_values[3]	502	1			T11	7		T16	7		T22	14
all_values[4]	502	1			T11	7		T16	7		T22	14
all_values[5]	502	1			T11	7		T16	7		T22	14
all_values[6]	502	1			T11	7		T16	7		T22	14
all_values[7]	502	1			T11	7		T16	7		T22	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2142

1

T11

29

T16

26

T22

55

auto[1]

1874

1

T11

27

T16

30

T22

57

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1497

1

T11

28

T16

19

T22

42

auto[1]

2519

1

T11

28

T16

37

T22

70

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2348

1

T11

39

T16

27

T22

64

auto[1]

1668

1

T11

17

T16

29

T22

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	159	1			T11	3		T16	1		T22	2
all_values[0]	auto[0]	auto[1]	auto[1]	136	1			T11	2		T16	2		T22	5
all_values[0]	auto[1]	auto[0]	auto[1]	122	1			T16	1		T22	4		T84	1
all_values[0]	auto[1]	auto[1]	auto[1]	85	1			T11	2		T16	3		T22	3
all_values[1]	auto[0]	auto[0]	auto[0]	140	1			T11	4		T16	1		T22	5
all_values[1]	auto[0]	auto[1]	auto[0]	149	1			T11	3		T16	3		T22	2
all_values[1]	auto[1]	auto[0]	auto[1]	116	1			T22	3		T84	2		T34	2
all_values[1]	auto[1]	auto[1]	auto[1]	97	1			T16	3		T22	4		T84	1
all_values[2]	auto[0]	auto[0]	auto[0]	103	1			T11	1		T16	1		T22	4
all_values[2]	auto[0]	auto[0]	auto[1]	47	1			T22	1		T112	1		T38	1
all_values[2]	auto[0]	auto[1]	auto[0]	87	1			T11	3		T16	2		T22	3
all_values[2]	auto[0]	auto[1]	auto[1]	50	1			T11	1		T84	1		T34	1
all_values[2]	auto[1]	auto[0]	auto[1]	109	1			T11	2		T22	4		T34	1
all_values[2]	auto[1]	auto[1]	auto[1]	106	1			T16	4		T22	2		T84	3
all_values[3]	auto[0]	auto[0]	auto[0]	135	1			T16	1		T22	1		T84	3
all_values[3]	auto[0]	auto[0]	auto[1]	38	1			T11	2		T22	3		T112	1
all_values[3]	auto[0]	auto[1]	auto[0]	92	1			T16	1		T22	1		T84	3
all_values[3]	auto[0]	auto[1]	auto[1]	44	1			T11	2		T22	2		T52	2
all_values[3]	auto[1]	auto[0]	auto[1]	109	1			T11	2		T16	5		T22	6
all_values[3]	auto[1]	auto[1]	auto[1]	84	1			T11	1		T22	1		T84	1
all_values[4]	auto[0]	auto[0]	auto[0]	129	1			T11	2		T16	1		T22	2
all_values[4]	auto[0]	auto[0]	auto[1]	36	1			T84	1		T34	1		T112	1
all_values[4]	auto[0]	auto[1]	auto[0]	89	1			T16	4		T22	4		T112	3
all_values[4]	auto[0]	auto[1]	auto[1]	50	1			T22	3		T34	1		T111	1
all_values[4]	auto[1]	auto[0]	auto[1]	91	1			T11	2		T16	1		T22	2
all_values[4]	auto[1]	auto[1]	auto[1]	107	1			T11	3		T16	1		T22	3
all_values[5]	auto[0]	auto[0]	auto[0]	86	1			T11	2		T16	2		T22	2
all_values[5]	auto[0]	auto[0]	auto[1]	49	1			T16	1		T22	1		T245	2
all_values[5]	auto[0]	auto[1]	auto[0]	96	1			T11	3		T22	3		T84	3
all_values[5]	auto[0]	auto[1]	auto[1]	54	1			T16	1		T22	2		T84	1
all_values[5]	auto[1]	auto[0]	auto[1]	129	1			T11	2		T16	1		T22	2
all_values[5]	auto[1]	auto[1]	auto[1]	88	1			T16	2		T22	4		T84	1
all_values[6]	auto[0]	auto[0]	auto[0]	99	1			T11	2		T16	2		T22	4
all_values[6]	auto[0]	auto[0]	auto[1]	54	1			T16	1		T22	1		T84	2
all_values[6]	auto[0]	auto[1]	auto[0]	81	1			T11	4		T22	2		T34	1
all_values[6]	auto[0]	auto[1]	auto[1]	51	1			T16	1		T22	1		T245	1
all_values[6]	auto[1]	auto[0]	auto[1]	122	1			T11	1		T16	2		T22	1
all_values[6]	auto[1]	auto[1]	auto[1]	95	1			T16	1		T22	5		T84	1
all_values[7]	auto[0]	auto[0]	auto[0]	110	1			T11	2		T16	1		T22	5
all_values[7]	auto[0]	auto[0]	auto[1]	41	1			T11	1		T16	1		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	101	1			T11	2		T22	4		T34	4
all_values[7]	auto[0]	auto[1]	auto[1]	42	1			T112	1		T37	1		T38	2
all_values[7]	auto[1]	auto[0]	auto[1]	118	1			T11	1		T16	3		T22	1
all_values[7]	auto[1]	auto[1]	auto[1]	90	1			T11	1		T16	2		T22	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal