Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.31 99.38 97.90 100.00 99.04 100.00 99.55


Total test records in report: 1248
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T1036 /workspace/coverage/default/33.uart_smoke.11795072 Mar 17 12:36:21 PM PDT 24 Mar 17 12:36:23 PM PDT 24 697725719 ps
T1037 /workspace/coverage/default/9.uart_rx_start_bit_filter.3220554884 Mar 17 12:34:27 PM PDT 24 Mar 17 12:34:32 PM PDT 24 2945652245 ps
T170 /workspace/coverage/default/21.uart_stress_all.2730665182 Mar 17 12:35:27 PM PDT 24 Mar 17 12:37:52 PM PDT 24 368059003016 ps
T1038 /workspace/coverage/default/9.uart_alert_test.4174619353 Mar 17 12:34:25 PM PDT 24 Mar 17 12:34:26 PM PDT 24 48811127 ps
T1039 /workspace/coverage/default/6.uart_fifo_overflow.849005055 Mar 17 12:34:10 PM PDT 24 Mar 17 12:35:07 PM PDT 24 49082465659 ps
T1040 /workspace/coverage/default/25.uart_fifo_full.4058347668 Mar 17 12:35:41 PM PDT 24 Mar 17 12:36:25 PM PDT 24 26865307071 ps
T1041 /workspace/coverage/default/46.uart_intr.1072454704 Mar 17 12:37:22 PM PDT 24 Mar 17 12:37:28 PM PDT 24 5871951173 ps
T1042 /workspace/coverage/default/113.uart_fifo_reset.1984331316 Mar 17 12:38:17 PM PDT 24 Mar 17 12:40:16 PM PDT 24 158688641122 ps
T1043 /workspace/coverage/default/144.uart_fifo_reset.2915741743 Mar 17 12:38:23 PM PDT 24 Mar 17 12:39:50 PM PDT 24 247580576776 ps
T1044 /workspace/coverage/default/8.uart_rx_oversample.2851429343 Mar 17 12:34:28 PM PDT 24 Mar 17 12:35:04 PM PDT 24 4496019774 ps
T1045 /workspace/coverage/default/7.uart_noise_filter.1635245104 Mar 17 12:34:10 PM PDT 24 Mar 17 12:35:40 PM PDT 24 46991678503 ps
T1046 /workspace/coverage/default/36.uart_rx_start_bit_filter.1507281103 Mar 17 12:36:37 PM PDT 24 Mar 17 12:36:49 PM PDT 24 30837874502 ps
T1047 /workspace/coverage/default/297.uart_fifo_reset.190592741 Mar 17 12:39:14 PM PDT 24 Mar 17 12:45:11 PM PDT 24 85383468373 ps
T1048 /workspace/coverage/default/15.uart_perf.3569927663 Mar 17 12:34:56 PM PDT 24 Mar 17 12:38:23 PM PDT 24 15605263423 ps
T1049 /workspace/coverage/default/28.uart_fifo_full.804070975 Mar 17 12:35:58 PM PDT 24 Mar 17 12:36:44 PM PDT 24 186494764455 ps
T1050 /workspace/coverage/default/1.uart_fifo_overflow.3792567802 Mar 17 12:33:56 PM PDT 24 Mar 17 12:34:15 PM PDT 24 53824197337 ps
T1051 /workspace/coverage/default/9.uart_loopback.2432803541 Mar 17 12:34:26 PM PDT 24 Mar 17 12:34:35 PM PDT 24 4442914629 ps
T1052 /workspace/coverage/default/38.uart_noise_filter.3430448205 Mar 17 12:36:52 PM PDT 24 Mar 17 12:37:16 PM PDT 24 55178114512 ps
T1053 /workspace/coverage/default/43.uart_fifo_reset.3112035063 Mar 17 12:37:11 PM PDT 24 Mar 17 12:38:00 PM PDT 24 32921027448 ps
T1054 /workspace/coverage/default/36.uart_fifo_full.1329826648 Mar 17 12:36:36 PM PDT 24 Mar 17 12:37:50 PM PDT 24 118508200266 ps
T1055 /workspace/coverage/default/12.uart_rx_oversample.703929031 Mar 17 12:34:44 PM PDT 24 Mar 17 12:35:25 PM PDT 24 6976153176 ps
T1056 /workspace/coverage/default/182.uart_fifo_reset.440678691 Mar 17 12:38:31 PM PDT 24 Mar 17 12:39:19 PM PDT 24 128677212589 ps
T230 /workspace/coverage/default/253.uart_fifo_reset.2020318238 Mar 17 12:39:07 PM PDT 24 Mar 17 12:40:38 PM PDT 24 186293359640 ps
T1057 /workspace/coverage/default/14.uart_intr.871314949 Mar 17 12:34:52 PM PDT 24 Mar 17 12:35:37 PM PDT 24 235973076725 ps
T1058 /workspace/coverage/default/46.uart_rx_parity_err.2822116314 Mar 17 12:37:21 PM PDT 24 Mar 17 12:37:40 PM PDT 24 113283474276 ps
T1059 /workspace/coverage/default/14.uart_rx_oversample.1615658373 Mar 17 12:34:51 PM PDT 24 Mar 17 12:35:00 PM PDT 24 4346274185 ps
T1060 /workspace/coverage/default/34.uart_stress_all.2341146179 Mar 17 12:36:26 PM PDT 24 Mar 17 12:56:46 PM PDT 24 209792587111 ps
T1061 /workspace/coverage/default/231.uart_fifo_reset.3420095254 Mar 17 12:38:55 PM PDT 24 Mar 17 12:39:40 PM PDT 24 126413527302 ps
T1062 /workspace/coverage/default/31.uart_fifo_full.989782793 Mar 17 12:36:15 PM PDT 24 Mar 17 12:37:08 PM PDT 24 101240988705 ps
T1063 /workspace/coverage/default/185.uart_fifo_reset.421398802 Mar 17 12:38:31 PM PDT 24 Mar 17 12:39:25 PM PDT 24 133468175519 ps
T1064 /workspace/coverage/default/16.uart_noise_filter.2737616994 Mar 17 12:35:07 PM PDT 24 Mar 17 12:36:31 PM PDT 24 33003688882 ps
T1065 /workspace/coverage/default/4.uart_stress_all.3799312773 Mar 17 12:34:06 PM PDT 24 Mar 17 12:40:51 PM PDT 24 350226955741 ps
T1066 /workspace/coverage/default/30.uart_long_xfer_wo_dly.2599178848 Mar 17 12:36:16 PM PDT 24 Mar 17 12:46:24 PM PDT 24 176549445097 ps
T1067 /workspace/coverage/default/149.uart_fifo_reset.3244029837 Mar 17 12:38:24 PM PDT 24 Mar 17 12:40:12 PM PDT 24 140813511980 ps
T1068 /workspace/coverage/default/11.uart_long_xfer_wo_dly.4002838072 Mar 17 12:34:42 PM PDT 24 Mar 17 12:42:23 PM PDT 24 154049775524 ps
T1069 /workspace/coverage/default/27.uart_rx_parity_err.1940672143 Mar 17 12:35:58 PM PDT 24 Mar 17 12:36:52 PM PDT 24 204090016597 ps
T1070 /workspace/coverage/default/273.uart_fifo_reset.674743489 Mar 17 12:39:07 PM PDT 24 Mar 17 12:39:55 PM PDT 24 26319119965 ps
T1071 /workspace/coverage/default/173.uart_fifo_reset.4101767695 Mar 17 12:38:33 PM PDT 24 Mar 17 12:38:52 PM PDT 24 24145617890 ps
T1072 /workspace/coverage/default/34.uart_rx_oversample.1930726445 Mar 17 12:36:28 PM PDT 24 Mar 17 12:36:40 PM PDT 24 3134464070 ps
T1073 /workspace/coverage/default/49.uart_tx_rx.3353456067 Mar 17 12:37:33 PM PDT 24 Mar 17 12:38:03 PM PDT 24 57306651271 ps
T1074 /workspace/coverage/default/27.uart_fifo_full.1669899020 Mar 17 12:35:59 PM PDT 24 Mar 17 12:38:42 PM PDT 24 105668313501 ps
T1075 /workspace/coverage/default/23.uart_alert_test.306058777 Mar 17 12:35:40 PM PDT 24 Mar 17 12:35:42 PM PDT 24 31962737 ps
T1076 /workspace/coverage/default/41.uart_tx_rx.3573114861 Mar 17 12:37:02 PM PDT 24 Mar 17 12:40:07 PM PDT 24 122720585237 ps
T1077 /workspace/coverage/default/114.uart_fifo_reset.4294177698 Mar 17 12:38:18 PM PDT 24 Mar 17 12:41:28 PM PDT 24 102885845444 ps
T1078 /workspace/coverage/default/16.uart_intr.1959115935 Mar 17 12:34:58 PM PDT 24 Mar 17 12:35:26 PM PDT 24 18763116096 ps
T1079 /workspace/coverage/default/43.uart_alert_test.2267015042 Mar 17 12:37:14 PM PDT 24 Mar 17 12:37:15 PM PDT 24 29123182 ps
T1080 /workspace/coverage/default/42.uart_long_xfer_wo_dly.2851426598 Mar 17 12:37:14 PM PDT 24 Mar 17 12:38:50 PM PDT 24 26347088452 ps
T1081 /workspace/coverage/default/263.uart_fifo_reset.3792635197 Mar 17 12:39:00 PM PDT 24 Mar 17 12:39:10 PM PDT 24 109760060783 ps
T1082 /workspace/coverage/default/17.uart_perf.2965633283 Mar 17 12:35:05 PM PDT 24 Mar 17 12:40:23 PM PDT 24 14707071724 ps
T1083 /workspace/coverage/default/16.uart_loopback.1466550704 Mar 17 12:35:05 PM PDT 24 Mar 17 12:35:07 PM PDT 24 2566586173 ps
T209 /workspace/coverage/default/195.uart_fifo_reset.3116506091 Mar 17 12:38:42 PM PDT 24 Mar 17 12:39:32 PM PDT 24 109065888472 ps
T1084 /workspace/coverage/default/288.uart_fifo_reset.3188287304 Mar 17 12:39:09 PM PDT 24 Mar 17 12:40:20 PM PDT 24 151236049767 ps
T204 /workspace/coverage/default/28.uart_stress_all.2708049280 Mar 17 12:36:11 PM PDT 24 Mar 17 12:50:04 PM PDT 24 229303671351 ps
T217 /workspace/coverage/default/177.uart_fifo_reset.1330835389 Mar 17 12:38:31 PM PDT 24 Mar 17 12:38:46 PM PDT 24 21562913178 ps
T1085 /workspace/coverage/default/33.uart_rx_start_bit_filter.164146077 Mar 17 12:36:28 PM PDT 24 Mar 17 12:36:30 PM PDT 24 3295496558 ps
T1086 /workspace/coverage/default/22.uart_fifo_full.370188953 Mar 17 12:35:29 PM PDT 24 Mar 17 12:35:40 PM PDT 24 18825468865 ps
T1087 /workspace/coverage/default/15.uart_fifo_full.608500278 Mar 17 12:34:58 PM PDT 24 Mar 17 12:35:25 PM PDT 24 24026017279 ps
T1088 /workspace/coverage/default/34.uart_perf.1463204873 Mar 17 12:36:28 PM PDT 24 Mar 17 12:44:11 PM PDT 24 9631031532 ps
T1089 /workspace/coverage/default/11.uart_loopback.769947561 Mar 17 12:34:42 PM PDT 24 Mar 17 12:34:50 PM PDT 24 4067490648 ps
T1090 /workspace/coverage/default/28.uart_intr.4147256189 Mar 17 12:35:59 PM PDT 24 Mar 17 12:36:09 PM PDT 24 19252402684 ps
T1091 /workspace/coverage/default/186.uart_fifo_reset.2342715675 Mar 17 12:38:31 PM PDT 24 Mar 17 12:42:56 PM PDT 24 143562200334 ps
T1092 /workspace/coverage/default/48.uart_rx_start_bit_filter.1495142222 Mar 17 12:37:32 PM PDT 24 Mar 17 12:37:48 PM PDT 24 41952669596 ps
T1093 /workspace/coverage/default/260.uart_fifo_reset.2070037525 Mar 17 12:39:03 PM PDT 24 Mar 17 12:39:23 PM PDT 24 52104565033 ps
T1094 /workspace/coverage/default/27.uart_long_xfer_wo_dly.2058672863 Mar 17 12:36:00 PM PDT 24 Mar 17 12:38:35 PM PDT 24 66682287432 ps
T1095 /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1996462099 Mar 17 12:36:35 PM PDT 24 Mar 17 12:46:14 PM PDT 24 470980840631 ps
T1096 /workspace/coverage/default/36.uart_tx_rx.621636648 Mar 17 12:36:35 PM PDT 24 Mar 17 12:38:35 PM PDT 24 57612590370 ps
T1097 /workspace/coverage/default/45.uart_loopback.1767480821 Mar 17 12:37:21 PM PDT 24 Mar 17 12:37:25 PM PDT 24 7472727426 ps
T1098 /workspace/coverage/default/16.uart_rx_parity_err.999886961 Mar 17 12:35:06 PM PDT 24 Mar 17 12:35:31 PM PDT 24 53922982661 ps
T1099 /workspace/coverage/default/30.uart_perf.282831773 Mar 17 12:36:13 PM PDT 24 Mar 17 12:38:50 PM PDT 24 5598500572 ps
T1100 /workspace/coverage/default/40.uart_rx_start_bit_filter.811523782 Mar 17 12:36:58 PM PDT 24 Mar 17 12:37:03 PM PDT 24 3660597097 ps
T1101 /workspace/coverage/default/32.uart_noise_filter.1904067977 Mar 17 12:36:25 PM PDT 24 Mar 17 12:41:17 PM PDT 24 339521578391 ps
T1102 /workspace/coverage/default/277.uart_fifo_reset.3766652725 Mar 17 12:39:07 PM PDT 24 Mar 17 12:40:46 PM PDT 24 214378553361 ps
T1103 /workspace/coverage/default/222.uart_fifo_reset.2779201628 Mar 17 12:38:45 PM PDT 24 Mar 17 12:38:59 PM PDT 24 41899407090 ps
T1104 /workspace/coverage/default/163.uart_fifo_reset.1712895243 Mar 17 12:38:30 PM PDT 24 Mar 17 12:41:40 PM PDT 24 136484215984 ps
T1105 /workspace/coverage/default/130.uart_fifo_reset.1462866422 Mar 17 12:38:22 PM PDT 24 Mar 17 12:38:37 PM PDT 24 15616019274 ps
T1106 /workspace/coverage/default/129.uart_fifo_reset.115272158 Mar 17 12:38:15 PM PDT 24 Mar 17 12:38:44 PM PDT 24 37167650271 ps
T241 /workspace/coverage/default/109.uart_fifo_reset.2074738203 Mar 17 12:38:12 PM PDT 24 Mar 17 12:38:42 PM PDT 24 68005738060 ps
T1107 /workspace/coverage/default/230.uart_fifo_reset.2149177353 Mar 17 12:38:47 PM PDT 24 Mar 17 12:39:05 PM PDT 24 40907155306 ps
T1108 /workspace/coverage/default/12.uart_fifo_overflow.3693389830 Mar 17 12:34:44 PM PDT 24 Mar 17 12:35:17 PM PDT 24 20377970572 ps
T1109 /workspace/coverage/default/45.uart_intr.3871517434 Mar 17 12:37:20 PM PDT 24 Mar 17 12:38:58 PM PDT 24 54612744538 ps
T1110 /workspace/coverage/default/57.uart_fifo_reset.2123203648 Mar 17 12:37:37 PM PDT 24 Mar 17 12:37:52 PM PDT 24 8474469802 ps
T1111 /workspace/coverage/default/34.uart_loopback.2437555196 Mar 17 12:36:26 PM PDT 24 Mar 17 12:36:30 PM PDT 24 6480071766 ps
T1112 /workspace/coverage/default/21.uart_tx_rx.2754892660 Mar 17 12:35:32 PM PDT 24 Mar 17 12:36:01 PM PDT 24 29689456884 ps
T74 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3872735216 Mar 17 12:24:49 PM PDT 24 Mar 17 12:24:50 PM PDT 24 13338812 ps
T1113 /workspace/coverage/cover_reg_top/10.uart_intr_test.1706605170 Mar 17 12:26:06 PM PDT 24 Mar 17 12:26:07 PM PDT 24 23238833 ps
T75 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2197346921 Mar 17 12:26:06 PM PDT 24 Mar 17 12:26:07 PM PDT 24 47522834 ps
T1114 /workspace/coverage/cover_reg_top/47.uart_intr_test.2634178793 Mar 17 12:25:23 PM PDT 24 Mar 17 12:25:24 PM PDT 24 52855700 ps
T76 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1324386496 Mar 17 12:26:07 PM PDT 24 Mar 17 12:26:08 PM PDT 24 84084449 ps
T77 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2912887196 Mar 17 12:22:44 PM PDT 24 Mar 17 12:22:45 PM PDT 24 18393328 ps
T1115 /workspace/coverage/cover_reg_top/13.uart_intr_test.2757112467 Mar 17 12:27:19 PM PDT 24 Mar 17 12:27:20 PM PDT 24 31911330 ps
T1116 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3579318558 Mar 17 12:27:04 PM PDT 24 Mar 17 12:27:08 PM PDT 24 422633086 ps
T1117 /workspace/coverage/cover_reg_top/15.uart_tl_errors.686369811 Mar 17 12:23:40 PM PDT 24 Mar 17 12:23:42 PM PDT 24 32591087 ps
T78 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2136676602 Mar 17 12:25:47 PM PDT 24 Mar 17 12:25:48 PM PDT 24 52912653 ps
T1118 /workspace/coverage/cover_reg_top/28.uart_intr_test.2850210284 Mar 17 12:23:46 PM PDT 24 Mar 17 12:23:47 PM PDT 24 15030769 ps
T86 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.110373554 Mar 17 12:23:20 PM PDT 24 Mar 17 12:23:21 PM PDT 24 60600208 ps
T1119 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.127185115 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:03 PM PDT 24 65424178 ps
T1120 /workspace/coverage/cover_reg_top/0.uart_intr_test.1252629146 Mar 17 12:22:44 PM PDT 24 Mar 17 12:22:44 PM PDT 24 23719675 ps
T1121 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2384833315 Mar 17 12:27:55 PM PDT 24 Mar 17 12:27:57 PM PDT 24 37666395 ps
T79 /workspace/coverage/cover_reg_top/7.uart_csr_rw.61071031 Mar 17 12:28:30 PM PDT 24 Mar 17 12:28:31 PM PDT 24 14179311 ps
T1122 /workspace/coverage/cover_reg_top/39.uart_intr_test.540558222 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:08 PM PDT 24 47376700 ps
T87 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2849214346 Mar 17 12:27:14 PM PDT 24 Mar 17 12:27:16 PM PDT 24 847705991 ps
T1123 /workspace/coverage/cover_reg_top/12.uart_tl_errors.118199707 Mar 17 12:26:22 PM PDT 24 Mar 17 12:26:23 PM PDT 24 30508788 ps
T1124 /workspace/coverage/cover_reg_top/20.uart_intr_test.3123448554 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:42 PM PDT 24 16782613 ps
T80 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1518733761 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:34 PM PDT 24 111748015 ps
T63 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.371010771 Mar 17 12:25:06 PM PDT 24 Mar 17 12:25:07 PM PDT 24 30145540 ps
T88 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.842502891 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:30 PM PDT 24 132555000 ps
T89 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1768361432 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:43 PM PDT 24 164745537 ps
T1125 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1300237081 Mar 17 12:24:58 PM PDT 24 Mar 17 12:24:59 PM PDT 24 14062009 ps
T1126 /workspace/coverage/cover_reg_top/31.uart_intr_test.2370062660 Mar 17 12:23:48 PM PDT 24 Mar 17 12:23:49 PM PDT 24 19601326 ps
T1127 /workspace/coverage/cover_reg_top/18.uart_intr_test.3334123755 Mar 17 12:24:08 PM PDT 24 Mar 17 12:24:09 PM PDT 24 16508129 ps
T1128 /workspace/coverage/cover_reg_top/7.uart_tl_errors.948057227 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:10 PM PDT 24 264465884 ps
T1129 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3324534892 Mar 17 12:27:20 PM PDT 24 Mar 17 12:27:21 PM PDT 24 27418263 ps
T81 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2102564420 Mar 17 12:27:13 PM PDT 24 Mar 17 12:27:13 PM PDT 24 19484239 ps
T1130 /workspace/coverage/cover_reg_top/48.uart_intr_test.409753747 Mar 17 12:24:30 PM PDT 24 Mar 17 12:24:30 PM PDT 24 16803943 ps
T1131 /workspace/coverage/cover_reg_top/45.uart_intr_test.3416440318 Mar 17 12:26:53 PM PDT 24 Mar 17 12:26:54 PM PDT 24 26477239 ps
T1132 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1820487994 Mar 17 12:23:23 PM PDT 24 Mar 17 12:23:24 PM PDT 24 76010214 ps
T1133 /workspace/coverage/cover_reg_top/4.uart_intr_test.1700942958 Mar 17 12:28:15 PM PDT 24 Mar 17 12:28:17 PM PDT 24 17612654 ps
T1134 /workspace/coverage/cover_reg_top/1.uart_intr_test.3839768060 Mar 17 12:22:45 PM PDT 24 Mar 17 12:22:46 PM PDT 24 41745348 ps
T82 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1363534607 Mar 17 12:27:56 PM PDT 24 Mar 17 12:27:57 PM PDT 24 35114424 ps
T1135 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1182366430 Mar 17 12:24:45 PM PDT 24 Mar 17 12:24:46 PM PDT 24 36589250 ps
T64 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2313857604 Mar 17 12:24:20 PM PDT 24 Mar 17 12:24:21 PM PDT 24 21226083 ps
T118 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1007491442 Mar 17 12:26:09 PM PDT 24 Mar 17 12:26:10 PM PDT 24 130174441 ps
T1136 /workspace/coverage/cover_reg_top/17.uart_tl_errors.80385549 Mar 17 12:24:17 PM PDT 24 Mar 17 12:24:20 PM PDT 24 516511864 ps
T83 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1450286821 Mar 17 12:27:58 PM PDT 24 Mar 17 12:28:00 PM PDT 24 74851645 ps
T1137 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3451228973 Mar 17 12:27:17 PM PDT 24 Mar 17 12:27:19 PM PDT 24 58069190 ps
T90 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.901892857 Mar 17 12:27:20 PM PDT 24 Mar 17 12:27:21 PM PDT 24 1385835637 ps
T92 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.485138386 Mar 17 12:27:55 PM PDT 24 Mar 17 12:27:56 PM PDT 24 250034027 ps
T1138 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.837097390 Mar 17 12:23:17 PM PDT 24 Mar 17 12:23:18 PM PDT 24 60165931 ps
T1139 /workspace/coverage/cover_reg_top/15.uart_intr_test.779900054 Mar 17 12:23:39 PM PDT 24 Mar 17 12:23:40 PM PDT 24 163809364 ps
T1140 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1956579234 Mar 17 12:28:14 PM PDT 24 Mar 17 12:28:16 PM PDT 24 32195685 ps
T1141 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4208093054 Mar 17 12:27:43 PM PDT 24 Mar 17 12:27:44 PM PDT 24 15064112 ps
T1142 /workspace/coverage/cover_reg_top/26.uart_intr_test.757260448 Mar 17 12:24:31 PM PDT 24 Mar 17 12:24:32 PM PDT 24 38696198 ps
T1143 /workspace/coverage/cover_reg_top/16.uart_csr_rw.341326059 Mar 17 12:24:08 PM PDT 24 Mar 17 12:24:09 PM PDT 24 86605154 ps
T1144 /workspace/coverage/cover_reg_top/2.uart_tl_errors.865480970 Mar 17 12:22:48 PM PDT 24 Mar 17 12:22:49 PM PDT 24 230197729 ps
T1145 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1823115131 Mar 17 12:26:07 PM PDT 24 Mar 17 12:26:08 PM PDT 24 33712065 ps
T65 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2044587656 Mar 17 12:23:46 PM PDT 24 Mar 17 12:23:47 PM PDT 24 53093243 ps
T1146 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1266285476 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:42 PM PDT 24 23184444 ps
T66 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3951434542 Mar 17 12:24:30 PM PDT 24 Mar 17 12:24:30 PM PDT 24 21031528 ps
T91 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1738952562 Mar 17 12:26:21 PM PDT 24 Mar 17 12:26:23 PM PDT 24 120613416 ps
T1147 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3497010679 Mar 17 12:27:20 PM PDT 24 Mar 17 12:27:21 PM PDT 24 50157242 ps
T67 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1834628045 Mar 17 12:23:43 PM PDT 24 Mar 17 12:23:43 PM PDT 24 22976575 ps
T1148 /workspace/coverage/cover_reg_top/46.uart_intr_test.2911651239 Mar 17 12:24:45 PM PDT 24 Mar 17 12:24:46 PM PDT 24 14422479 ps
T1149 /workspace/coverage/cover_reg_top/32.uart_intr_test.656365615 Mar 17 12:26:05 PM PDT 24 Mar 17 12:26:06 PM PDT 24 13043682 ps
T1150 /workspace/coverage/cover_reg_top/5.uart_tl_errors.399946371 Mar 17 12:26:16 PM PDT 24 Mar 17 12:26:17 PM PDT 24 45330287 ps
T1151 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3603141940 Mar 17 12:26:04 PM PDT 24 Mar 17 12:26:05 PM PDT 24 12553848 ps
T1152 /workspace/coverage/cover_reg_top/34.uart_intr_test.1027280998 Mar 17 12:24:01 PM PDT 24 Mar 17 12:24:02 PM PDT 24 84030351 ps
T1153 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1461974510 Mar 17 12:28:35 PM PDT 24 Mar 17 12:28:36 PM PDT 24 29632864 ps
T1154 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3079573479 Mar 17 12:22:44 PM PDT 24 Mar 17 12:22:47 PM PDT 24 303044633 ps
T1155 /workspace/coverage/cover_reg_top/43.uart_intr_test.3670212409 Mar 17 12:26:53 PM PDT 24 Mar 17 12:26:54 PM PDT 24 19828379 ps
T1156 /workspace/coverage/cover_reg_top/38.uart_intr_test.3080339857 Mar 17 12:26:53 PM PDT 24 Mar 17 12:26:54 PM PDT 24 15607137 ps
T1157 /workspace/coverage/cover_reg_top/41.uart_intr_test.446718885 Mar 17 12:25:53 PM PDT 24 Mar 17 12:25:53 PM PDT 24 18569827 ps
T1158 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1863847900 Mar 17 12:23:59 PM PDT 24 Mar 17 12:24:01 PM PDT 24 374421741 ps
T68 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3292029309 Mar 17 12:23:33 PM PDT 24 Mar 17 12:23:34 PM PDT 24 28818485 ps
T1159 /workspace/coverage/cover_reg_top/21.uart_intr_test.2363664848 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:12 PM PDT 24 22658886 ps
T1160 /workspace/coverage/cover_reg_top/25.uart_intr_test.4271788462 Mar 17 12:27:55 PM PDT 24 Mar 17 12:27:56 PM PDT 24 17113587 ps
T1161 /workspace/coverage/cover_reg_top/27.uart_intr_test.1828826225 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:11 PM PDT 24 115874373 ps
T1162 /workspace/coverage/cover_reg_top/3.uart_intr_test.3754520687 Mar 17 12:22:51 PM PDT 24 Mar 17 12:22:52 PM PDT 24 152816047 ps
T1163 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4035910061 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:01 PM PDT 24 92146381 ps
T1164 /workspace/coverage/cover_reg_top/30.uart_intr_test.942664472 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:42 PM PDT 24 40341713 ps
T1165 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2182774588 Mar 17 12:26:17 PM PDT 24 Mar 17 12:26:18 PM PDT 24 19686976 ps
T1166 /workspace/coverage/cover_reg_top/8.uart_csr_rw.479479012 Mar 17 12:27:53 PM PDT 24 Mar 17 12:27:54 PM PDT 24 45215651 ps
T1167 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.288777772 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:42 PM PDT 24 62288789 ps
T69 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2636460895 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:42 PM PDT 24 52156631 ps
T1168 /workspace/coverage/cover_reg_top/12.uart_intr_test.2450152666 Mar 17 12:27:19 PM PDT 24 Mar 17 12:27:19 PM PDT 24 39768413 ps
T1169 /workspace/coverage/cover_reg_top/29.uart_intr_test.1791180744 Mar 17 12:23:54 PM PDT 24 Mar 17 12:23:56 PM PDT 24 25576872 ps
T1170 /workspace/coverage/cover_reg_top/14.uart_intr_test.2195921703 Mar 17 12:27:13 PM PDT 24 Mar 17 12:27:13 PM PDT 24 11229222 ps
T1171 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.950557920 Mar 17 12:27:40 PM PDT 24 Mar 17 12:27:40 PM PDT 24 15828289 ps
T1172 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2863730523 Mar 17 12:24:53 PM PDT 24 Mar 17 12:24:54 PM PDT 24 195054855 ps
T1173 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1260413899 Mar 17 12:27:56 PM PDT 24 Mar 17 12:27:57 PM PDT 24 161733890 ps
T1174 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3589860224 Mar 17 12:23:46 PM PDT 24 Mar 17 12:23:48 PM PDT 24 134485605 ps
T1175 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3446682996 Mar 17 12:23:44 PM PDT 24 Mar 17 12:23:45 PM PDT 24 298717046 ps
T1176 /workspace/coverage/cover_reg_top/37.uart_intr_test.1629950823 Mar 17 12:28:48 PM PDT 24 Mar 17 12:28:49 PM PDT 24 22384320 ps
T1177 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3984196727 Mar 17 12:28:16 PM PDT 24 Mar 17 12:28:18 PM PDT 24 440950850 ps
T1178 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1123999746 Mar 17 12:22:44 PM PDT 24 Mar 17 12:22:45 PM PDT 24 91412766 ps
T1179 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1943909299 Mar 17 12:28:00 PM PDT 24 Mar 17 12:28:02 PM PDT 24 93480640 ps
T1180 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3385467537 Mar 17 12:27:55 PM PDT 24 Mar 17 12:27:56 PM PDT 24 81731027 ps
T1181 /workspace/coverage/cover_reg_top/40.uart_intr_test.387888154 Mar 17 12:26:53 PM PDT 24 Mar 17 12:26:54 PM PDT 24 22151996 ps
T1182 /workspace/coverage/cover_reg_top/49.uart_intr_test.1781351440 Mar 17 12:28:12 PM PDT 24 Mar 17 12:28:12 PM PDT 24 16747510 ps
T70 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.464631669 Mar 17 12:23:17 PM PDT 24 Mar 17 12:23:18 PM PDT 24 84474475 ps
T1183 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3970386781 Mar 17 12:26:21 PM PDT 24 Mar 17 12:26:22 PM PDT 24 473125396 ps
T1184 /workspace/coverage/cover_reg_top/33.uart_intr_test.659584631 Mar 17 12:28:00 PM PDT 24 Mar 17 12:28:02 PM PDT 24 29848975 ps
T1185 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.541720960 Mar 17 12:28:29 PM PDT 24 Mar 17 12:28:30 PM PDT 24 79900358 ps
T1186 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3769715505 Mar 17 12:23:38 PM PDT 24 Mar 17 12:23:39 PM PDT 24 55646248 ps
T1187 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2065248636 Mar 17 12:22:45 PM PDT 24 Mar 17 12:22:46 PM PDT 24 21382212 ps
T1188 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3309561605 Mar 17 12:22:44 PM PDT 24 Mar 17 12:22:45 PM PDT 24 20769933 ps
T1189 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2695652049 Mar 17 12:23:38 PM PDT 24 Mar 17 12:23:40 PM PDT 24 587340412 ps
T1190 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3238473585 Mar 17 12:26:06 PM PDT 24 Mar 17 12:26:07 PM PDT 24 154755366 ps
T1191 /workspace/coverage/cover_reg_top/19.uart_csr_rw.323645307 Mar 17 12:28:27 PM PDT 24 Mar 17 12:28:29 PM PDT 24 30311500 ps
T1192 /workspace/coverage/cover_reg_top/6.uart_intr_test.2109013707 Mar 17 12:25:32 PM PDT 24 Mar 17 12:25:33 PM PDT 24 13470652 ps
T1193 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2048877601 Mar 17 12:28:17 PM PDT 24 Mar 17 12:28:18 PM PDT 24 295292051 ps
T1194 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.637031297 Mar 17 12:27:55 PM PDT 24 Mar 17 12:27:57 PM PDT 24 69323245 ps
T1195 /workspace/coverage/cover_reg_top/44.uart_intr_test.1249750492 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:07 PM PDT 24 32855019 ps
T1196 /workspace/coverage/cover_reg_top/42.uart_intr_test.3307708672 Mar 17 12:26:21 PM PDT 24 Mar 17 12:26:21 PM PDT 24 11931626 ps
T1197 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1511201259 Mar 17 12:27:43 PM PDT 24 Mar 17 12:27:44 PM PDT 24 73047410 ps
T1198 /workspace/coverage/cover_reg_top/23.uart_intr_test.1382539592 Mar 17 12:26:10 PM PDT 24 Mar 17 12:26:11 PM PDT 24 13540215 ps
T1199 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1323869489 Mar 17 12:23:38 PM PDT 24 Mar 17 12:23:39 PM PDT 24 88466880 ps
T1200 /workspace/coverage/cover_reg_top/9.uart_intr_test.1701318352 Mar 17 12:24:35 PM PDT 24 Mar 17 12:24:36 PM PDT 24 30859727 ps
T1201 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.240443096 Mar 17 12:22:38 PM PDT 24 Mar 17 12:22:39 PM PDT 24 25948996 ps
T1202 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3454767173 Mar 17 12:23:36 PM PDT 24 Mar 17 12:23:38 PM PDT 24 150365658 ps
T1203 /workspace/coverage/cover_reg_top/18.uart_csr_rw.501053019 Mar 17 12:23:46 PM PDT 24 Mar 17 12:23:47 PM PDT 24 60266509 ps
T1204 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1904283178 Mar 17 12:26:12 PM PDT 24 Mar 17 12:26:14 PM PDT 24 25855854 ps
T1205 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3962610909 Mar 17 12:23:09 PM PDT 24 Mar 17 12:23:10 PM PDT 24 147471097 ps
T1206 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1852876693 Mar 17 12:28:12 PM PDT 24 Mar 17 12:28:14 PM PDT 24 48294930 ps
T1207 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3122013700 Mar 17 12:22:44 PM PDT 24 Mar 17 12:22:46 PM PDT 24 366362651 ps
T1208 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3739492015 Mar 17 12:27:55 PM PDT 24 Mar 17 12:27:57 PM PDT 24 23467851 ps
T71 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2738420434 Mar 17 12:23:26 PM PDT 24 Mar 17 12:23:26 PM PDT 24 21927849 ps
T1209 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2711065433 Mar 17 12:24:13 PM PDT 24 Mar 17 12:24:14 PM PDT 24 61778950 ps
T1210 /workspace/coverage/cover_reg_top/11.uart_intr_test.1512104833 Mar 17 12:27:40 PM PDT 24 Mar 17 12:27:41 PM PDT 24 28608979 ps
T72 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.725890306 Mar 17 12:22:46 PM PDT 24 Mar 17 12:22:47 PM PDT 24 37172200 ps
T1211 /workspace/coverage/cover_reg_top/6.uart_csr_rw.210905313 Mar 17 12:25:58 PM PDT 24 Mar 17 12:25:58 PM PDT 24 114500053 ps
T1212 /workspace/coverage/cover_reg_top/35.uart_intr_test.1575246859 Mar 17 12:23:45 PM PDT 24 Mar 17 12:23:46 PM PDT 24 44271037 ps
T1213 /workspace/coverage/cover_reg_top/2.uart_csr_rw.4228335730 Mar 17 12:26:22 PM PDT 24 Mar 17 12:26:22 PM PDT 24 22547158 ps
T1214 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.832435082 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:09 PM PDT 24 35374822 ps
T1215 /workspace/coverage/cover_reg_top/22.uart_intr_test.1391072335 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:12 PM PDT 24 51460940 ps
T1216 /workspace/coverage/cover_reg_top/16.uart_intr_test.3668938757 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:42 PM PDT 24 14128725 ps
T1217 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3898607933 Mar 17 12:23:09 PM PDT 24 Mar 17 12:23:10 PM PDT 24 86495436 ps
T1218 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.819176553 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:29 PM PDT 24 52586156 ps
T1219 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2129319297 Mar 17 12:26:22 PM PDT 24 Mar 17 12:26:22 PM PDT 24 27001301 ps
T1220 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2005411466 Mar 17 12:22:57 PM PDT 24 Mar 17 12:22:58 PM PDT 24 18378460 ps
T1221 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1980712576 Mar 17 12:25:41 PM PDT 24 Mar 17 12:25:44 PM PDT 24 164335827 ps
T1222 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2244137074 Mar 17 12:23:36 PM PDT 24 Mar 17 12:23:37 PM PDT 24 51700375 ps
T1223 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1960948165 Mar 17 12:25:16 PM PDT 24 Mar 17 12:25:17 PM PDT 24 48250671 ps
T73 /workspace/coverage/cover_reg_top/11.uart_csr_rw.438452592 Mar 17 12:23:36 PM PDT 24 Mar 17 12:23:37 PM PDT 24 15061799 ps
T1224 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.429741547 Mar 17 12:22:45 PM PDT 24 Mar 17 12:22:46 PM PDT 24 15210335 ps
T1225 /workspace/coverage/cover_reg_top/19.uart_intr_test.164442230 Mar 17 12:26:52 PM PDT 24 Mar 17 12:26:53 PM PDT 24 39054020 ps
T1226 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.293966521 Mar 17 12:27:06 PM PDT 24 Mar 17 12:27:08 PM PDT 24 99179644 ps
T1227 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.271260086 Mar 17 12:22:46 PM PDT 24 Mar 17 12:22:47 PM PDT 24 24551810 ps
T1228 /workspace/coverage/cover_reg_top/0.uart_tl_errors.373952139 Mar 17 12:22:43 PM PDT 24 Mar 17 12:22:46 PM PDT 24 80209176 ps
T1229 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3916274890 Mar 17 12:23:10 PM PDT 24 Mar 17 12:23:11 PM PDT 24 35422793 ps
T1230 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1805026565 Mar 17 12:25:55 PM PDT 24 Mar 17 12:25:56 PM PDT 24 14183886 ps
T1231 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1134673023 Mar 17 12:28:05 PM PDT 24 Mar 17 12:28:08 PM PDT 24 43240814 ps
T1232 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3004114281 Mar 17 12:27:52 PM PDT 24 Mar 17 12:27:54 PM PDT 24 78853258 ps
T1233 /workspace/coverage/cover_reg_top/36.uart_intr_test.2385548790 Mar 17 12:23:59 PM PDT 24 Mar 17 12:24:00 PM PDT 24 17842113 ps
T1234 /workspace/coverage/cover_reg_top/17.uart_csr_rw.4097276565 Mar 17 12:23:38 PM PDT 24 Mar 17 12:23:39 PM PDT 24 46406785 ps
T1235 /workspace/coverage/cover_reg_top/24.uart_intr_test.1393500192 Mar 17 12:28:01 PM PDT 24 Mar 17 12:28:02 PM PDT 24 14661128 ps
T1236 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1642130186 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:08 PM PDT 24 32621204 ps
T1237 /workspace/coverage/cover_reg_top/2.uart_intr_test.4205198356 Mar 17 12:23:09 PM PDT 24 Mar 17 12:23:10 PM PDT 24 21675917 ps
T1238 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4228175430 Mar 17 12:27:55 PM PDT 24 Mar 17 12:27:57 PM PDT 24 90050909 ps
T1239 /workspace/coverage/cover_reg_top/16.uart_tl_errors.442064862 Mar 17 12:24:02 PM PDT 24 Mar 17 12:24:04 PM PDT 24 349123933 ps
T1240 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3595220273 Mar 17 12:23:38 PM PDT 24 Mar 17 12:23:38 PM PDT 24 103997879 ps
T1241 /workspace/coverage/cover_reg_top/8.uart_intr_test.906591766 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:07 PM PDT 24 34643427 ps
T1242 /workspace/coverage/cover_reg_top/17.uart_intr_test.280114391 Mar 17 12:27:03 PM PDT 24 Mar 17 12:27:05 PM PDT 24 37987651 ps
T1243 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3639809396 Mar 17 12:26:33 PM PDT 24 Mar 17 12:26:35 PM PDT 24 58859169 ps
T1244 /workspace/coverage/cover_reg_top/5.uart_intr_test.974002693 Mar 17 12:23:57 PM PDT 24 Mar 17 12:23:58 PM PDT 24 17680667 ps
T1245 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.337021562 Mar 17 12:22:46 PM PDT 24 Mar 17 12:22:47 PM PDT 24 106646647 ps
T1246 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1585037285 Mar 17 12:23:37 PM PDT 24 Mar 17 12:23:38 PM PDT 24 79248431 ps
T1247 /workspace/coverage/cover_reg_top/7.uart_intr_test.2099813804 Mar 17 12:26:14 PM PDT 24 Mar 17 12:26:14 PM PDT 24 14316532 ps
T1248 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3390030751 Mar 17 12:23:38 PM PDT 24 Mar 17 12:23:39 PM PDT 24 25932720 ps

Test location /workspace/coverage/default/197.uart_fifo_reset.969503817
Short name T8
Test name
Test status
Simulation time 51921936221 ps
CPU time 26.64 seconds
Started Mar 17 12:38:39 PM PDT 24
Finished Mar 17 12:39:07 PM PDT 24
Peak memory 200036 kb
Host smart-fae52293-875d-481b-a47d-d1590d0fabcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969503817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.969503817
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1610047787
Short name T15
Test name
Test status
Simulation time 326031736159 ps
CPU time 1172.13 seconds
Started Mar 17 12:38:09 PM PDT 24
Finished Mar 17 12:57:41 PM PDT 24
Peak memory 224952 kb
Host smart-d1c91075-356d-49e8-be46-182933a2d948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610047787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1610047787
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.271770607
Short name T111
Test name
Test status
Simulation time 187017482340 ps
CPU time 717.13 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:47:18 PM PDT 24
Peak memory 199972 kb
Host smart-f10bbdb9-2c13-469c-a930-7e57eeeb241c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271770607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.271770607
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all.196660485
Short name T11
Test name
Test status
Simulation time 259761106354 ps
CPU time 124.19 seconds
Started Mar 17 12:37:16 PM PDT 24
Finished Mar 17 12:39:20 PM PDT 24
Peak memory 200056 kb
Host smart-6b9c3815-66b5-4e42-8a72-7388add77ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196660485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.196660485
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1305340113
Short name T251
Test name
Test status
Simulation time 136848561737 ps
CPU time 856.82 seconds
Started Mar 17 12:35:28 PM PDT 24
Finished Mar 17 12:49:46 PM PDT 24
Peak memory 200020 kb
Host smart-8c0858d3-3a0e-4868-8cc5-6e87566b13cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305340113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1305340113
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.142849867
Short name T35
Test name
Test status
Simulation time 150190269645 ps
CPU time 336.17 seconds
Started Mar 17 12:34:59 PM PDT 24
Finished Mar 17 12:40:36 PM PDT 24
Peak memory 224700 kb
Host smart-cb16a6c9-633f-498a-8872-cc36098500fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142849867 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.142849867
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3447719808
Short name T155
Test name
Test status
Simulation time 307584249916 ps
CPU time 233.43 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:39:20 PM PDT 24
Peak memory 199908 kb
Host smart-409de467-0182-43f8-a044-51071b67af55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447719808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3447719808
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_stress_all.3356117147
Short name T245
Test name
Test status
Simulation time 941007159711 ps
CPU time 277.23 seconds
Started Mar 17 12:34:58 PM PDT 24
Finished Mar 17 12:39:35 PM PDT 24
Peak memory 208388 kb
Host smart-a7779922-fd46-4959-83fe-f8b1053a49b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356117147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3356117147
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.522604644
Short name T31
Test name
Test status
Simulation time 58314847 ps
CPU time 0.72 seconds
Started Mar 17 12:33:54 PM PDT 24
Finished Mar 17 12:33:55 PM PDT 24
Peak memory 218424 kb
Host smart-85a48c78-654b-4ab9-81a4-a44a79376c0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522604644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.522604644
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1843347027
Short name T180
Test name
Test status
Simulation time 242711910952 ps
CPU time 313.62 seconds
Started Mar 17 12:38:28 PM PDT 24
Finished Mar 17 12:43:42 PM PDT 24
Peak memory 199920 kb
Host smart-54ff6663-9473-4a82-8b94-27517d911541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843347027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1843347027
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.1696549991
Short name T25
Test name
Test status
Simulation time 258310667393 ps
CPU time 201.31 seconds
Started Mar 17 12:35:08 PM PDT 24
Finished Mar 17 12:38:29 PM PDT 24
Peak memory 200028 kb
Host smart-4a5ea094-ec4c-4cd1-8d94-a0f357792fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696549991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1696549991
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.371010771
Short name T63
Test name
Test status
Simulation time 30145540 ps
CPU time 0.76 seconds
Started Mar 17 12:25:06 PM PDT 24
Finished Mar 17 12:25:07 PM PDT 24
Peak memory 197224 kb
Host smart-267971f6-ad45-4c34-9012-53eb36b0730f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371010771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.371010771
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3710427815
Short name T119
Test name
Test status
Simulation time 214117652621 ps
CPU time 312.58 seconds
Started Mar 17 12:38:10 PM PDT 24
Finished Mar 17 12:43:23 PM PDT 24
Peak memory 199968 kb
Host smart-ce58b9af-3993-41e2-b405-484607d6ac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710427815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3710427815
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3272549071
Short name T22
Test name
Test status
Simulation time 217146891378 ps
CPU time 415.12 seconds
Started Mar 17 12:37:40 PM PDT 24
Finished Mar 17 12:44:36 PM PDT 24
Peak memory 216464 kb
Host smart-66ee570f-bc0d-46af-a889-df639eb2284f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272549071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3272549071
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1209353314
Short name T36
Test name
Test status
Simulation time 286674468472 ps
CPU time 1014.66 seconds
Started Mar 17 12:37:15 PM PDT 24
Finished Mar 17 12:54:10 PM PDT 24
Peak memory 216432 kb
Host smart-24892b0b-a17b-4d2c-b5e1-6f76d170be2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209353314 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1209353314
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.842502891
Short name T88
Test name
Test status
Simulation time 132555000 ps
CPU time 1.33 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 199848 kb
Host smart-3493851d-67f6-4b5f-9e1a-870b5c949dce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842502891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.842502891
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1129216491
Short name T131
Test name
Test status
Simulation time 147010806686 ps
CPU time 240.5 seconds
Started Mar 17 12:38:20 PM PDT 24
Finished Mar 17 12:42:20 PM PDT 24
Peak memory 199640 kb
Host smart-96bf13fa-4021-46d0-8fb1-58c2fcfded14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129216491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1129216491
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2052540701
Short name T254
Test name
Test status
Simulation time 131091102228 ps
CPU time 90.09 seconds
Started Mar 17 12:37:52 PM PDT 24
Finished Mar 17 12:39:22 PM PDT 24
Peak memory 199904 kb
Host smart-4604a816-b407-499f-aec1-84d59e3eac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052540701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2052540701
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_alert_test.817145828
Short name T386
Test name
Test status
Simulation time 46204896 ps
CPU time 0.54 seconds
Started Mar 17 12:34:32 PM PDT 24
Finished Mar 17 12:34:33 PM PDT 24
Peak memory 195400 kb
Host smart-882d8160-8fee-4fa7-b422-a803ef953d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817145828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.817145828
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_stress_all.3193494297
Short name T84
Test name
Test status
Simulation time 238607769271 ps
CPU time 485.64 seconds
Started Mar 17 12:35:35 PM PDT 24
Finished Mar 17 12:43:41 PM PDT 24
Peak memory 200112 kb
Host smart-3431375c-0f7b-4a9d-ac03-3255dc51a77a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193494297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3193494297
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.687977688
Short name T182
Test name
Test status
Simulation time 177969646568 ps
CPU time 139.81 seconds
Started Mar 17 12:38:33 PM PDT 24
Finished Mar 17 12:40:53 PM PDT 24
Peak memory 200012 kb
Host smart-8965ddb4-086e-4a6a-b59b-f04e3fe9b3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687977688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.687977688
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2422391193
Short name T7
Test name
Test status
Simulation time 163746836870 ps
CPU time 71.09 seconds
Started Mar 17 12:35:44 PM PDT 24
Finished Mar 17 12:36:55 PM PDT 24
Peak memory 199968 kb
Host smart-b737fc47-6753-4e20-8fb3-f6bd3bb3c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422391193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2422391193
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.586503193
Short name T303
Test name
Test status
Simulation time 168045155992 ps
CPU time 154.04 seconds
Started Mar 17 12:38:41 PM PDT 24
Finished Mar 17 12:41:17 PM PDT 24
Peak memory 200020 kb
Host smart-828fd832-748e-4801-8756-4323516ce6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586503193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.586503193
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3789216974
Short name T151
Test name
Test status
Simulation time 118103358246 ps
CPU time 24.5 seconds
Started Mar 17 12:36:51 PM PDT 24
Finished Mar 17 12:37:15 PM PDT 24
Peak memory 199876 kb
Host smart-25179c51-63dc-4e99-9467-cfd3c333cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789216974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3789216974
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.4255324446
Short name T253
Test name
Test status
Simulation time 125350772972 ps
CPU time 217.67 seconds
Started Mar 17 12:37:16 PM PDT 24
Finished Mar 17 12:40:54 PM PDT 24
Peak memory 199992 kb
Host smart-b0780121-5712-41d8-b41b-57f3d303f1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255324446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4255324446
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1648184598
Short name T37
Test name
Test status
Simulation time 225895332525 ps
CPU time 857.35 seconds
Started Mar 17 12:35:06 PM PDT 24
Finished Mar 17 12:49:23 PM PDT 24
Peak memory 216548 kb
Host smart-dc7fde0a-7efb-4534-bccc-d6493763fc1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648184598 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1648184598
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.3676550335
Short name T148
Test name
Test status
Simulation time 321948958004 ps
CPU time 739.18 seconds
Started Mar 17 12:36:08 PM PDT 24
Finished Mar 17 12:48:28 PM PDT 24
Peak memory 200136 kb
Host smart-06d9ccb6-a817-458e-9e4d-304dbe5cb8a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676550335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3676550335
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2197346921
Short name T75
Test name
Test status
Simulation time 47522834 ps
CPU time 0.58 seconds
Started Mar 17 12:26:06 PM PDT 24
Finished Mar 17 12:26:07 PM PDT 24
Peak memory 195252 kb
Host smart-a6a43abf-3f88-4e75-8382-585ec4b00a29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197346921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2197346921
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2436099813
Short name T122
Test name
Test status
Simulation time 272879268316 ps
CPU time 50.34 seconds
Started Mar 17 12:38:46 PM PDT 24
Finished Mar 17 12:39:37 PM PDT 24
Peak memory 200140 kb
Host smart-b8e1265d-b6bb-4cc4-bc9b-e9502c7b73f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436099813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2436099813
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1653249526
Short name T142
Test name
Test status
Simulation time 69740635596 ps
CPU time 33.58 seconds
Started Mar 17 12:39:05 PM PDT 24
Finished Mar 17 12:39:38 PM PDT 24
Peak memory 200004 kb
Host smart-cbd8ec19-f313-4039-9e24-cb043a655f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653249526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1653249526
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1459689698
Short name T291
Test name
Test status
Simulation time 56021278641 ps
CPU time 31.92 seconds
Started Mar 17 12:35:22 PM PDT 24
Finished Mar 17 12:35:54 PM PDT 24
Peak memory 199960 kb
Host smart-ea8e60a7-a4a1-468b-a594-7f6615c2110f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459689698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1459689698
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_stress_all.2889652633
Short name T18
Test name
Test status
Simulation time 35975745724 ps
CPU time 43.69 seconds
Started Mar 17 12:36:34 PM PDT 24
Finished Mar 17 12:37:18 PM PDT 24
Peak memory 199984 kb
Host smart-8156dbfc-f3e6-470a-a9ab-9b739fca0cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889652633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2889652633
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.563593528
Short name T129
Test name
Test status
Simulation time 211001437143 ps
CPU time 151.12 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:36:35 PM PDT 24
Peak memory 199996 kb
Host smart-685cfdd5-5490-4ba4-8cb9-76315535a78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563593528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.563593528
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3415787830
Short name T138
Test name
Test status
Simulation time 23853202108 ps
CPU time 22.4 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:38:46 PM PDT 24
Peak memory 199884 kb
Host smart-2abb7d21-4a1b-4319-bc9e-7a09a06aed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415787830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3415787830
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1757823195
Short name T152
Test name
Test status
Simulation time 79777279607 ps
CPU time 37.9 seconds
Started Mar 17 12:39:01 PM PDT 24
Finished Mar 17 12:39:39 PM PDT 24
Peak memory 199956 kb
Host smart-d575abfc-85b8-4c26-850d-18c1a473a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757823195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1757823195
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.183079457
Short name T16
Test name
Test status
Simulation time 52786467121 ps
CPU time 67.92 seconds
Started Mar 17 12:35:57 PM PDT 24
Finished Mar 17 12:37:05 PM PDT 24
Peak memory 199988 kb
Host smart-6d99dda8-210b-431d-a01b-3842be180d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183079457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.183079457
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.901892857
Short name T90
Test name
Test status
Simulation time 1385835637 ps
CPU time 1.31 seconds
Started Mar 17 12:27:20 PM PDT 24
Finished Mar 17 12:27:21 PM PDT 24
Peak memory 199264 kb
Host smart-25a386d7-44a6-460e-a278-338434a1d63f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901892857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.901892857
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.909415245
Short name T161
Test name
Test status
Simulation time 591438026269 ps
CPU time 1171.43 seconds
Started Mar 17 12:34:49 PM PDT 24
Finished Mar 17 12:54:21 PM PDT 24
Peak memory 224900 kb
Host smart-597122eb-1ad1-460f-a0fc-4799c239bc59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909415245 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.909415245
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3641608773
Short name T332
Test name
Test status
Simulation time 141914217772 ps
CPU time 317.26 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:39:24 PM PDT 24
Peak memory 216284 kb
Host smart-c9be13e9-1041-44d9-bcdc-4946ce8fc743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641608773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3641608773
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4178431381
Short name T186
Test name
Test status
Simulation time 34073470207 ps
CPU time 29.71 seconds
Started Mar 17 12:38:45 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 200012 kb
Host smart-7509de1a-2984-4d7c-b20b-92e3a05edc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178431381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4178431381
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1128287537
Short name T183
Test name
Test status
Simulation time 341266010976 ps
CPU time 43.57 seconds
Started Mar 17 12:38:46 PM PDT 24
Finished Mar 17 12:39:30 PM PDT 24
Peak memory 200048 kb
Host smart-8bdcc422-7ecf-452b-b221-bcfd35ac7d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128287537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1128287537
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2419897596
Short name T136
Test name
Test status
Simulation time 129940775152 ps
CPU time 96.19 seconds
Started Mar 17 12:34:15 PM PDT 24
Finished Mar 17 12:35:52 PM PDT 24
Peak memory 199848 kb
Host smart-0134367a-f22b-48bc-bba4-66e5fc2d576e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419897596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2419897596
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3172226323
Short name T506
Test name
Test status
Simulation time 77909720836 ps
CPU time 49.86 seconds
Started Mar 17 12:35:00 PM PDT 24
Finished Mar 17 12:35:50 PM PDT 24
Peak memory 200004 kb
Host smart-443be8cd-3750-4292-a84b-0d738de211dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172226323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3172226323
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1898171447
Short name T154
Test name
Test status
Simulation time 178758873497 ps
CPU time 62.11 seconds
Started Mar 17 12:38:32 PM PDT 24
Finished Mar 17 12:39:34 PM PDT 24
Peak memory 200024 kb
Host smart-22142bc5-5e69-44f7-b9aa-96b24079cf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898171447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1898171447
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3265849904
Short name T243
Test name
Test status
Simulation time 20425199645 ps
CPU time 18.05 seconds
Started Mar 17 12:38:17 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 200044 kb
Host smart-7b980e7e-b809-401f-8aaf-b2b162c179c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265849904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3265849904
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2364260069
Short name T198
Test name
Test status
Simulation time 33269847825 ps
CPU time 56.54 seconds
Started Mar 17 12:38:20 PM PDT 24
Finished Mar 17 12:39:16 PM PDT 24
Peak memory 199620 kb
Host smart-f90f5f59-3805-4db2-989d-d5483779bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364260069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2364260069
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1584664932
Short name T126
Test name
Test status
Simulation time 209456528290 ps
CPU time 40.7 seconds
Started Mar 17 12:38:28 PM PDT 24
Finished Mar 17 12:39:08 PM PDT 24
Peak memory 199888 kb
Host smart-1d3d17a5-577f-41e6-ae5d-5be91c6c99cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584664932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1584664932
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3633727093
Short name T173
Test name
Test status
Simulation time 66141472841 ps
CPU time 108.58 seconds
Started Mar 17 12:39:00 PM PDT 24
Finished Mar 17 12:40:48 PM PDT 24
Peak memory 200080 kb
Host smart-49a09e3a-7766-4902-a3fb-8b27eacf264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633727093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3633727093
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1377389601
Short name T242
Test name
Test status
Simulation time 262530656010 ps
CPU time 68.42 seconds
Started Mar 17 12:36:41 PM PDT 24
Finished Mar 17 12:37:50 PM PDT 24
Peak memory 200008 kb
Host smart-d3c26932-0801-45eb-8228-3e8f27adcf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377389601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1377389601
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1812104526
Short name T165
Test name
Test status
Simulation time 66830110078 ps
CPU time 1116.76 seconds
Started Mar 17 12:36:50 PM PDT 24
Finished Mar 17 12:55:27 PM PDT 24
Peak memory 224720 kb
Host smart-ae63bbdd-34c5-400f-9c28-1462cdcf9843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812104526 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1812104526
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.288497660
Short name T149
Test name
Test status
Simulation time 321690088380 ps
CPU time 307.67 seconds
Started Mar 17 12:34:10 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 208480 kb
Host smart-0e043471-6983-42f6-b1cb-edbcecfa4d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288497660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.288497660
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2382094146
Short name T47
Test name
Test status
Simulation time 126446444995 ps
CPU time 68.58 seconds
Started Mar 17 12:38:20 PM PDT 24
Finished Mar 17 12:39:29 PM PDT 24
Peak memory 199492 kb
Host smart-9e2c1951-fc07-4480-af81-db2d63dc8721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382094146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2382094146
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1655517946
Short name T345
Test name
Test status
Simulation time 73776344627 ps
CPU time 128.48 seconds
Started Mar 17 12:34:51 PM PDT 24
Finished Mar 17 12:37:01 PM PDT 24
Peak memory 200172 kb
Host smart-4c197c94-bfa1-42d7-9f0f-9c6e9ea5306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655517946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1655517946
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1629940327
Short name T143
Test name
Test status
Simulation time 101519212498 ps
CPU time 258.79 seconds
Started Mar 17 12:38:47 PM PDT 24
Finished Mar 17 12:43:06 PM PDT 24
Peak memory 200044 kb
Host smart-7ad30f90-5978-4bbf-a9da-d319b6eccc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629940327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1629940327
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3142759314
Short name T200
Test name
Test status
Simulation time 32890213142 ps
CPU time 29.05 seconds
Started Mar 17 12:38:54 PM PDT 24
Finished Mar 17 12:39:23 PM PDT 24
Peak memory 199984 kb
Host smart-f2bf7de1-cb66-4850-ad0c-d326a6f0c08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142759314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3142759314
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3994475327
Short name T207
Test name
Test status
Simulation time 45007277394 ps
CPU time 37.26 seconds
Started Mar 17 12:39:01 PM PDT 24
Finished Mar 17 12:39:38 PM PDT 24
Peak memory 199992 kb
Host smart-3ddbd44d-1527-448d-8ca4-fe79fbee316b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994475327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3994475327
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3268813568
Short name T306
Test name
Test status
Simulation time 8081410914 ps
CPU time 20.7 seconds
Started Mar 17 12:39:15 PM PDT 24
Finished Mar 17 12:39:36 PM PDT 24
Peak memory 200064 kb
Host smart-3ef4582d-c0d4-43c6-87a7-844ae7268280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268813568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3268813568
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1107461611
Short name T316
Test name
Test status
Simulation time 132211697590 ps
CPU time 386.77 seconds
Started Mar 17 12:38:08 PM PDT 24
Finished Mar 17 12:44:35 PM PDT 24
Peak memory 200012 kb
Host smart-70528a5e-099f-487b-bd0d-ef41f2e07021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107461611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1107461611
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2074738203
Short name T241
Test name
Test status
Simulation time 68005738060 ps
CPU time 30.28 seconds
Started Mar 17 12:38:12 PM PDT 24
Finished Mar 17 12:38:42 PM PDT 24
Peak memory 200024 kb
Host smart-bced6587-efdd-4146-aae2-738fe3b3ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074738203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2074738203
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_perf.4236803627
Short name T46
Test name
Test status
Simulation time 7401407923 ps
CPU time 294.85 seconds
Started Mar 17 12:34:45 PM PDT 24
Finished Mar 17 12:39:40 PM PDT 24
Peak memory 199964 kb
Host smart-3c405bfc-9677-43de-834c-26f79a652a91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236803627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.4236803627
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1791756355
Short name T196
Test name
Test status
Simulation time 33338288494 ps
CPU time 12.05 seconds
Started Mar 17 12:34:43 PM PDT 24
Finished Mar 17 12:34:55 PM PDT 24
Peak memory 199944 kb
Host smart-f1ac5b57-61a6-40b2-a64b-8ad274878b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791756355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1791756355
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3784865141
Short name T238
Test name
Test status
Simulation time 79865693199 ps
CPU time 58.59 seconds
Started Mar 17 12:38:25 PM PDT 24
Finished Mar 17 12:39:23 PM PDT 24
Peak memory 200136 kb
Host smart-7739541d-c642-4a24-be3a-01f3e61a93bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784865141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3784865141
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.4093590107
Short name T218
Test name
Test status
Simulation time 45183396187 ps
CPU time 71.77 seconds
Started Mar 17 12:38:30 PM PDT 24
Finished Mar 17 12:39:42 PM PDT 24
Peak memory 199960 kb
Host smart-397faf26-0b91-4107-8bdf-2668fb84f51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093590107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.4093590107
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.923502229
Short name T227
Test name
Test status
Simulation time 29139407729 ps
CPU time 23.41 seconds
Started Mar 17 12:38:38 PM PDT 24
Finished Mar 17 12:39:03 PM PDT 24
Peak memory 199948 kb
Host smart-bf475cc0-1dad-47b8-b67b-c60a96422800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923502229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.923502229
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3210864628
Short name T176
Test name
Test status
Simulation time 24733597592 ps
CPU time 12 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:18 PM PDT 24
Peak memory 199928 kb
Host smart-62f0e9be-8ed1-4df8-a141-26fe69edcc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210864628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3210864628
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3668869871
Short name T3
Test name
Test status
Simulation time 25903132892 ps
CPU time 10.9 seconds
Started Mar 17 12:38:55 PM PDT 24
Finished Mar 17 12:39:06 PM PDT 24
Peak memory 200040 kb
Host smart-72a4a911-5038-42e3-ae51-fa9d11186567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668869871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3668869871
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4274777879
Short name T231
Test name
Test status
Simulation time 116700583151 ps
CPU time 115.28 seconds
Started Mar 17 12:39:01 PM PDT 24
Finished Mar 17 12:40:57 PM PDT 24
Peak memory 200084 kb
Host smart-c8bd30c9-c84a-4abb-add6-4c6bb7c53722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274777879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4274777879
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.273784682
Short name T216
Test name
Test status
Simulation time 82369474964 ps
CPU time 61.44 seconds
Started Mar 17 12:39:15 PM PDT 24
Finished Mar 17 12:40:17 PM PDT 24
Peak memory 199896 kb
Host smart-188f4a37-a521-4052-b2cf-d13aa8cdb33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273784682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.273784682
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.125948462
Short name T124
Test name
Test status
Simulation time 155787898601 ps
CPU time 140.44 seconds
Started Mar 17 12:36:13 PM PDT 24
Finished Mar 17 12:38:33 PM PDT 24
Peak memory 200036 kb
Host smart-8abe9cca-27b5-45e2-b350-f989b7dfa393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125948462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.125948462
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all.1651282910
Short name T147
Test name
Test status
Simulation time 63611842661 ps
CPU time 35.4 seconds
Started Mar 17 12:37:18 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 199876 kb
Host smart-1c158016-ea2c-485b-8ad0-794e7a57355a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651282910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1651282910
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1583106505
Short name T240
Test name
Test status
Simulation time 20527958247 ps
CPU time 30.67 seconds
Started Mar 17 12:37:22 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 199616 kb
Host smart-6f8e342a-3602-4ac0-b3cc-af83f125a06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583106505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1583106505
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3863890115
Short name T52
Test name
Test status
Simulation time 285460135061 ps
CPU time 859.19 seconds
Started Mar 17 12:37:42 PM PDT 24
Finished Mar 17 12:52:01 PM PDT 24
Peak memory 224892 kb
Host smart-8c376d64-4706-4352-a77b-ed8c36271278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863890115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3863890115
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2262880752
Short name T239
Test name
Test status
Simulation time 119576061356 ps
CPU time 88.41 seconds
Started Mar 17 12:38:00 PM PDT 24
Finished Mar 17 12:39:28 PM PDT 24
Peak memory 199920 kb
Host smart-b19750e8-e7ba-4f03-a33b-433393177462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262880752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2262880752
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.464631669
Short name T70
Test name
Test status
Simulation time 84474475 ps
CPU time 0.65 seconds
Started Mar 17 12:23:17 PM PDT 24
Finished Mar 17 12:23:18 PM PDT 24
Peak memory 195632 kb
Host smart-9c62c054-8b44-4a9f-b0bd-31bdab61a1ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464631669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.464631669
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3639809396
Short name T1243
Test name
Test status
Simulation time 58859169 ps
CPU time 2.23 seconds
Started Mar 17 12:26:33 PM PDT 24
Finished Mar 17 12:26:35 PM PDT 24
Peak memory 197700 kb
Host smart-d8191da7-3a01-4979-8879-13d340add839
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639809396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3639809396
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.950557920
Short name T1171
Test name
Test status
Simulation time 15828289 ps
CPU time 0.61 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:27:40 PM PDT 24
Peak memory 195600 kb
Host smart-c838b9b6-9ac1-4d8e-9ebd-5af531488700
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950557920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.950557920
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3451228973
Short name T1137
Test name
Test status
Simulation time 58069190 ps
CPU time 0.69 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:27:19 PM PDT 24
Peak memory 196636 kb
Host smart-6693ce93-2b1c-4d6d-8202-6e878889df83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451228973 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3451228973
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2738420434
Short name T71
Test name
Test status
Simulation time 21927849 ps
CPU time 0.67 seconds
Started Mar 17 12:23:26 PM PDT 24
Finished Mar 17 12:23:26 PM PDT 24
Peak memory 195728 kb
Host smart-4d4ba852-6cbf-402c-b91b-c1632edc7213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738420434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2738420434
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1252629146
Short name T1120
Test name
Test status
Simulation time 23719675 ps
CPU time 0.61 seconds
Started Mar 17 12:22:44 PM PDT 24
Finished Mar 17 12:22:44 PM PDT 24
Peak memory 194624 kb
Host smart-8c2963e0-8bec-4ca0-889b-94aa7a9efb81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252629146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1252629146
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2065248636
Short name T1187
Test name
Test status
Simulation time 21382212 ps
CPU time 0.66 seconds
Started Mar 17 12:22:45 PM PDT 24
Finished Mar 17 12:22:46 PM PDT 24
Peak memory 196092 kb
Host smart-064d5bc2-f3fc-4734-bfcc-a72105467480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065248636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2065248636
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.373952139
Short name T1228
Test name
Test status
Simulation time 80209176 ps
CPU time 2.04 seconds
Started Mar 17 12:22:43 PM PDT 24
Finished Mar 17 12:22:46 PM PDT 24
Peak memory 200340 kb
Host smart-e96536a4-80ee-4d53-b85b-91e49450b991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373952139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.373952139
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.337021562
Short name T1245
Test name
Test status
Simulation time 106646647 ps
CPU time 1.39 seconds
Started Mar 17 12:22:46 PM PDT 24
Finished Mar 17 12:22:47 PM PDT 24
Peak memory 199496 kb
Host smart-2169aaa6-ac2e-4f70-b0d3-523e24986ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337021562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.337021562
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3309561605
Short name T1188
Test name
Test status
Simulation time 20769933 ps
CPU time 0.67 seconds
Started Mar 17 12:22:44 PM PDT 24
Finished Mar 17 12:22:45 PM PDT 24
Peak memory 195644 kb
Host smart-f670d2ce-13a4-4846-a639-3226f8bdbb38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309561605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3309561605
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.725890306
Short name T72
Test name
Test status
Simulation time 37172200 ps
CPU time 1.39 seconds
Started Mar 17 12:22:46 PM PDT 24
Finished Mar 17 12:22:47 PM PDT 24
Peak memory 198272 kb
Host smart-8f02f3a4-c975-4670-8c31-ffd340d06423
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725890306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.725890306
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1834628045
Short name T67
Test name
Test status
Simulation time 22976575 ps
CPU time 0.63 seconds
Started Mar 17 12:23:43 PM PDT 24
Finished Mar 17 12:23:43 PM PDT 24
Peak memory 195628 kb
Host smart-e68bb6ad-99ec-4539-89e5-b2b500de67a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834628045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1834628045
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1823115131
Short name T1145
Test name
Test status
Simulation time 33712065 ps
CPU time 0.9 seconds
Started Mar 17 12:26:07 PM PDT 24
Finished Mar 17 12:26:08 PM PDT 24
Peak memory 200156 kb
Host smart-2ab06bc4-f271-4fe1-9069-f75f4aaa565e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823115131 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1823115131
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1642130186
Short name T1236
Test name
Test status
Simulation time 32621204 ps
CPU time 0.6 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 195596 kb
Host smart-6e0a15fb-d74a-405b-811a-e850a6237d40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642130186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1642130186
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3839768060
Short name T1134
Test name
Test status
Simulation time 41745348 ps
CPU time 0.58 seconds
Started Mar 17 12:22:45 PM PDT 24
Finished Mar 17 12:22:46 PM PDT 24
Peak memory 194648 kb
Host smart-3b41fc07-a2dd-410f-9a35-3e43bc8e9c5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839768060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3839768060
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1943909299
Short name T1179
Test name
Test status
Simulation time 93480640 ps
CPU time 0.72 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 196576 kb
Host smart-4cd5197e-6762-4069-b637-c96e593f86f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943909299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1943909299
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3079573479
Short name T1154
Test name
Test status
Simulation time 303044633 ps
CPU time 1.68 seconds
Started Mar 17 12:22:44 PM PDT 24
Finished Mar 17 12:22:47 PM PDT 24
Peak memory 200304 kb
Host smart-8c5c60ef-f0d6-4791-87f0-9373a2f5ad0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079573479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3079573479
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2849214346
Short name T87
Test name
Test status
Simulation time 847705991 ps
CPU time 1.42 seconds
Started Mar 17 12:27:14 PM PDT 24
Finished Mar 17 12:27:16 PM PDT 24
Peak memory 198404 kb
Host smart-482d2ec7-4e7c-4aa0-b684-cf2c36170e90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849214346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2849214346
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1461974510
Short name T1153
Test name
Test status
Simulation time 29632864 ps
CPU time 0.87 seconds
Started Mar 17 12:28:35 PM PDT 24
Finished Mar 17 12:28:36 PM PDT 24
Peak memory 199828 kb
Host smart-3044a74f-1db5-401d-8b58-62962b304016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461974510 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1461974510
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1706605170
Short name T1113
Test name
Test status
Simulation time 23238833 ps
CPU time 0.57 seconds
Started Mar 17 12:26:06 PM PDT 24
Finished Mar 17 12:26:07 PM PDT 24
Peak memory 193976 kb
Host smart-81018aad-c2a9-489a-a8dc-d4a3eb317d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706605170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1706605170
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1324386496
Short name T76
Test name
Test status
Simulation time 84084449 ps
CPU time 0.66 seconds
Started Mar 17 12:26:07 PM PDT 24
Finished Mar 17 12:26:08 PM PDT 24
Peak memory 194728 kb
Host smart-1000a424-2bea-47fc-b7fd-71913d0d9dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324386496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1324386496
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2048877601
Short name T1193
Test name
Test status
Simulation time 295292051 ps
CPU time 1.27 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:28:18 PM PDT 24
Peak memory 200328 kb
Host smart-81ea999e-8117-4df5-a54f-ee041649324d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048877601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2048877601
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1007491442
Short name T118
Test name
Test status
Simulation time 130174441 ps
CPU time 0.91 seconds
Started Mar 17 12:26:09 PM PDT 24
Finished Mar 17 12:26:10 PM PDT 24
Peak memory 199348 kb
Host smart-b843bd4f-c33f-46e8-98d4-1c6ce6d1c532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007491442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1007491442
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.837097390
Short name T1138
Test name
Test status
Simulation time 60165931 ps
CPU time 0.86 seconds
Started Mar 17 12:23:17 PM PDT 24
Finished Mar 17 12:23:18 PM PDT 24
Peak memory 198216 kb
Host smart-6e170f9c-2a6c-4d05-91ae-d8f3544451ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837097390 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.837097390
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.438452592
Short name T73
Test name
Test status
Simulation time 15061799 ps
CPU time 0.6 seconds
Started Mar 17 12:23:36 PM PDT 24
Finished Mar 17 12:23:37 PM PDT 24
Peak memory 195624 kb
Host smart-c5363665-200e-4ed5-85da-56451158bae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438452592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.438452592
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1512104833
Short name T1210
Test name
Test status
Simulation time 28608979 ps
CPU time 0.59 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:27:41 PM PDT 24
Peak memory 194696 kb
Host smart-bda08634-8e18-4fdb-8550-4373297db9b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512104833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1512104833
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1450286821
Short name T83
Test name
Test status
Simulation time 74851645 ps
CPU time 0.7 seconds
Started Mar 17 12:27:58 PM PDT 24
Finished Mar 17 12:28:00 PM PDT 24
Peak memory 195920 kb
Host smart-9dfe117a-0c8b-40be-8154-93686a386cd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450286821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1450286821
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1852876693
Short name T1206
Test name
Test status
Simulation time 48294930 ps
CPU time 1.2 seconds
Started Mar 17 12:28:12 PM PDT 24
Finished Mar 17 12:28:14 PM PDT 24
Peak memory 200372 kb
Host smart-1b28d395-2604-4ffe-a1af-a64ec927cb29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852876693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1852876693
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3769715505
Short name T1186
Test name
Test status
Simulation time 55646248 ps
CPU time 0.96 seconds
Started Mar 17 12:23:38 PM PDT 24
Finished Mar 17 12:23:39 PM PDT 24
Peak memory 199220 kb
Host smart-f5cf6d0e-fdde-421d-ab5d-9b85a8092e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769715505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3769715505
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3595220273
Short name T1240
Test name
Test status
Simulation time 103997879 ps
CPU time 0.75 seconds
Started Mar 17 12:23:38 PM PDT 24
Finished Mar 17 12:23:38 PM PDT 24
Peak memory 199588 kb
Host smart-9bba42c6-a28e-4b3f-86f6-4709bd9c915e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595220273 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3595220273
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1518733761
Short name T80
Test name
Test status
Simulation time 111748015 ps
CPU time 0.59 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:34 PM PDT 24
Peak memory 195652 kb
Host smart-2eb3c8e3-9425-4d5d-9e9f-baf19902bca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518733761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1518733761
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2450152666
Short name T1168
Test name
Test status
Simulation time 39768413 ps
CPU time 0.57 seconds
Started Mar 17 12:27:19 PM PDT 24
Finished Mar 17 12:27:19 PM PDT 24
Peak memory 193584 kb
Host smart-1fcf79d8-84cc-4117-bab3-913bed1477b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450152666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2450152666
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2863730523
Short name T1172
Test name
Test status
Simulation time 195054855 ps
CPU time 0.77 seconds
Started Mar 17 12:24:53 PM PDT 24
Finished Mar 17 12:24:54 PM PDT 24
Peak memory 195708 kb
Host smart-65dc2421-c57c-4979-b85d-cdee0c87622f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863730523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2863730523
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.118199707
Short name T1123
Test name
Test status
Simulation time 30508788 ps
CPU time 1.54 seconds
Started Mar 17 12:26:22 PM PDT 24
Finished Mar 17 12:26:23 PM PDT 24
Peak memory 200272 kb
Host smart-8f4e1461-12da-47f0-a11f-337eddd084e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118199707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.118199707
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.819176553
Short name T1218
Test name
Test status
Simulation time 52586156 ps
CPU time 0.74 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:29 PM PDT 24
Peak memory 199380 kb
Host smart-cad35ba2-df6e-445f-99a2-277275c63223
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819176553 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.819176553
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3292029309
Short name T68
Test name
Test status
Simulation time 28818485 ps
CPU time 0.62 seconds
Started Mar 17 12:23:33 PM PDT 24
Finished Mar 17 12:23:34 PM PDT 24
Peak memory 195700 kb
Host smart-41ff0b9e-1c0e-49a0-936a-739899ca3e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292029309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3292029309
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2757112467
Short name T1115
Test name
Test status
Simulation time 31911330 ps
CPU time 0.57 seconds
Started Mar 17 12:27:19 PM PDT 24
Finished Mar 17 12:27:20 PM PDT 24
Peak memory 194372 kb
Host smart-9cdcf54e-7b46-45cc-be6a-04d384c8bff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757112467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2757112467
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2129319297
Short name T1219
Test name
Test status
Simulation time 27001301 ps
CPU time 0.68 seconds
Started Mar 17 12:26:22 PM PDT 24
Finished Mar 17 12:26:22 PM PDT 24
Peak memory 197736 kb
Host smart-3cc000fa-ad5d-4eab-953b-bfc171d3326b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129319297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2129319297
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2695652049
Short name T1189
Test name
Test status
Simulation time 587340412 ps
CPU time 2.38 seconds
Started Mar 17 12:23:38 PM PDT 24
Finished Mar 17 12:23:40 PM PDT 24
Peak memory 200396 kb
Host smart-6bacaca0-0206-4f3f-a6f9-ce2dd65fb90a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695652049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2695652049
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1323869489
Short name T1199
Test name
Test status
Simulation time 88466880 ps
CPU time 1.32 seconds
Started Mar 17 12:23:38 PM PDT 24
Finished Mar 17 12:23:39 PM PDT 24
Peak memory 199596 kb
Host smart-e5102caa-066c-44c5-b6fe-6f3b1744b923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323869489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1323869489
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3739492015
Short name T1208
Test name
Test status
Simulation time 23467851 ps
CPU time 1.03 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:27:57 PM PDT 24
Peak memory 199948 kb
Host smart-42c38c23-1243-4ffd-9018-4b72f8c709e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739492015 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3739492015
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1266285476
Short name T1146
Test name
Test status
Simulation time 23184444 ps
CPU time 0.73 seconds
Started Mar 17 12:23:41 PM PDT 24
Finished Mar 17 12:23:42 PM PDT 24
Peak memory 194296 kb
Host smart-58b266ac-2fd3-4572-8567-bba86398b8e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266285476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1266285476
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2195921703
Short name T1170
Test name
Test status
Simulation time 11229222 ps
CPU time 0.57 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:27:13 PM PDT 24
Peak memory 194664 kb
Host smart-ead83603-5249-4d9c-ab1f-46403d7fdf81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195921703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2195921703
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1260413899
Short name T1173
Test name
Test status
Simulation time 161733890 ps
CPU time 0.8 seconds
Started Mar 17 12:27:56 PM PDT 24
Finished Mar 17 12:27:57 PM PDT 24
Peak memory 197316 kb
Host smart-ba5fc7ef-ddf8-450e-9e99-7ad5d9d48ad7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260413899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1260413899
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1980712576
Short name T1221
Test name
Test status
Simulation time 164335827 ps
CPU time 2.71 seconds
Started Mar 17 12:25:41 PM PDT 24
Finished Mar 17 12:25:44 PM PDT 24
Peak memory 200376 kb
Host smart-4130bb53-d82a-44af-8003-9144673d3825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980712576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1980712576
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.110373554
Short name T86
Test name
Test status
Simulation time 60600208 ps
CPU time 0.99 seconds
Started Mar 17 12:23:20 PM PDT 24
Finished Mar 17 12:23:21 PM PDT 24
Peak memory 199748 kb
Host smart-ef275534-bebd-48dc-94fa-8074bb3bd099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110373554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.110373554
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4228175430
Short name T1238
Test name
Test status
Simulation time 90050909 ps
CPU time 0.75 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:27:57 PM PDT 24
Peak memory 198572 kb
Host smart-ef16cde7-9015-4628-be6f-8ce83208b858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228175430 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4228175430
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3951434542
Short name T66
Test name
Test status
Simulation time 21031528 ps
CPU time 0.62 seconds
Started Mar 17 12:24:30 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 195644 kb
Host smart-690bac42-df99-4097-b397-350b8da8f5a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951434542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3951434542
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.779900054
Short name T1139
Test name
Test status
Simulation time 163809364 ps
CPU time 0.57 seconds
Started Mar 17 12:23:39 PM PDT 24
Finished Mar 17 12:23:40 PM PDT 24
Peak memory 194728 kb
Host smart-8c129d65-771a-4526-a959-54141445243f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779900054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.779900054
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1805026565
Short name T1230
Test name
Test status
Simulation time 14183886 ps
CPU time 0.65 seconds
Started Mar 17 12:25:55 PM PDT 24
Finished Mar 17 12:25:56 PM PDT 24
Peak memory 196956 kb
Host smart-f06c6b3a-0688-4ccd-b120-e37d4b759818
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805026565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1805026565
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.686369811
Short name T1117
Test name
Test status
Simulation time 32591087 ps
CPU time 1.68 seconds
Started Mar 17 12:23:40 PM PDT 24
Finished Mar 17 12:23:42 PM PDT 24
Peak memory 200340 kb
Host smart-5c2c9c88-a1f1-489e-a464-504a9a29303a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686369811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.686369811
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1768361432
Short name T89
Test name
Test status
Simulation time 164745537 ps
CPU time 1.44 seconds
Started Mar 17 12:23:41 PM PDT 24
Finished Mar 17 12:23:43 PM PDT 24
Peak memory 198000 kb
Host smart-bdb77f1d-d83a-49cc-ba1d-07a8f82dd936
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768361432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1768361432
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.288777772
Short name T1167
Test name
Test status
Simulation time 62288789 ps
CPU time 0.74 seconds
Started Mar 17 12:23:41 PM PDT 24
Finished Mar 17 12:23:42 PM PDT 24
Peak memory 198320 kb
Host smart-301fb0a5-b81e-471b-8f19-6e0a7a7a5e06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288777772 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.288777772
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.341326059
Short name T1143
Test name
Test status
Simulation time 86605154 ps
CPU time 0.58 seconds
Started Mar 17 12:24:08 PM PDT 24
Finished Mar 17 12:24:09 PM PDT 24
Peak memory 195624 kb
Host smart-e41f6617-978c-4e37-9f61-28ca703a29c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341326059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.341326059
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3668938757
Short name T1216
Test name
Test status
Simulation time 14128725 ps
CPU time 0.59 seconds
Started Mar 17 12:23:41 PM PDT 24
Finished Mar 17 12:23:42 PM PDT 24
Peak memory 194648 kb
Host smart-b856db25-22d4-43a9-a412-6a424e9a21cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668938757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3668938757
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1363534607
Short name T82
Test name
Test status
Simulation time 35114424 ps
CPU time 0.65 seconds
Started Mar 17 12:27:56 PM PDT 24
Finished Mar 17 12:27:57 PM PDT 24
Peak memory 194900 kb
Host smart-689f5330-b085-4b10-a87d-39cfabf51a67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363534607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1363534607
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.442064862
Short name T1239
Test name
Test status
Simulation time 349123933 ps
CPU time 2.16 seconds
Started Mar 17 12:24:02 PM PDT 24
Finished Mar 17 12:24:04 PM PDT 24
Peak memory 200556 kb
Host smart-6ee977df-7be7-464f-b296-5c3cead6d22c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442064862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.442064862
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.293966521
Short name T1226
Test name
Test status
Simulation time 99179644 ps
CPU time 1.22 seconds
Started Mar 17 12:27:06 PM PDT 24
Finished Mar 17 12:27:08 PM PDT 24
Peak memory 199776 kb
Host smart-3d9e3f5f-38da-4ecd-ba77-ae1b6e911282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293966521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.293966521
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3385467537
Short name T1180
Test name
Test status
Simulation time 81731027 ps
CPU time 0.74 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:27:56 PM PDT 24
Peak memory 198016 kb
Host smart-7318397c-b5c5-4580-afc9-a38ca0263c54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385467537 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3385467537
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.4097276565
Short name T1234
Test name
Test status
Simulation time 46406785 ps
CPU time 0.58 seconds
Started Mar 17 12:23:38 PM PDT 24
Finished Mar 17 12:23:39 PM PDT 24
Peak memory 195660 kb
Host smart-d3e26139-1050-446a-8b78-652b3192d54d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097276565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.4097276565
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.280114391
Short name T1242
Test name
Test status
Simulation time 37987651 ps
CPU time 0.53 seconds
Started Mar 17 12:27:03 PM PDT 24
Finished Mar 17 12:27:05 PM PDT 24
Peak memory 194676 kb
Host smart-ac499440-47d8-42bb-a67c-f36246cb865d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280114391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.280114391
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.637031297
Short name T1194
Test name
Test status
Simulation time 69323245 ps
CPU time 0.73 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:27:57 PM PDT 24
Peak memory 197900 kb
Host smart-b17ec695-f95c-4ff7-9c27-92c22fe9c11a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637031297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.637031297
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.80385549
Short name T1136
Test name
Test status
Simulation time 516511864 ps
CPU time 2.79 seconds
Started Mar 17 12:24:17 PM PDT 24
Finished Mar 17 12:24:20 PM PDT 24
Peak memory 200388 kb
Host smart-41acb5d2-3314-4ae0-97ea-201dccaa1c30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80385549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.80385549
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3454767173
Short name T1202
Test name
Test status
Simulation time 150365658 ps
CPU time 1.29 seconds
Started Mar 17 12:23:36 PM PDT 24
Finished Mar 17 12:23:38 PM PDT 24
Peak memory 199576 kb
Host smart-597a310d-cd59-4792-ad17-2fe67cef87fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454767173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3454767173
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2182774588
Short name T1165
Test name
Test status
Simulation time 19686976 ps
CPU time 0.94 seconds
Started Mar 17 12:26:17 PM PDT 24
Finished Mar 17 12:26:18 PM PDT 24
Peak memory 200120 kb
Host smart-56320ca6-8645-433c-9152-ae2e6a4f137c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182774588 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2182774588
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.501053019
Short name T1203
Test name
Test status
Simulation time 60266509 ps
CPU time 0.67 seconds
Started Mar 17 12:23:46 PM PDT 24
Finished Mar 17 12:23:47 PM PDT 24
Peak memory 194296 kb
Host smart-fc871fe4-af71-4756-bb93-0717c5ff71cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501053019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.501053019
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3334123755
Short name T1127
Test name
Test status
Simulation time 16508129 ps
CPU time 0.61 seconds
Started Mar 17 12:24:08 PM PDT 24
Finished Mar 17 12:24:09 PM PDT 24
Peak memory 194648 kb
Host smart-c53e9749-b15c-4d4d-a60f-11dc88e5d98a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334123755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3334123755
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3390030751
Short name T1248
Test name
Test status
Simulation time 25932720 ps
CPU time 0.74 seconds
Started Mar 17 12:23:38 PM PDT 24
Finished Mar 17 12:23:39 PM PDT 24
Peak memory 197456 kb
Host smart-e66a1d8a-f752-4825-bd08-e82ee398c42d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390030751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3390030751
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2384833315
Short name T1121
Test name
Test status
Simulation time 37666395 ps
CPU time 0.94 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:27:57 PM PDT 24
Peak memory 199968 kb
Host smart-c0e50aa4-923d-47b6-bd65-7d7ba9d6cf50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384833315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2384833315
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1960948165
Short name T1223
Test name
Test status
Simulation time 48250671 ps
CPU time 0.95 seconds
Started Mar 17 12:25:16 PM PDT 24
Finished Mar 17 12:25:17 PM PDT 24
Peak memory 199324 kb
Host smart-1bf380f3-a920-4458-89e3-a8cfb123956c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960948165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1960948165
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1182366430
Short name T1135
Test name
Test status
Simulation time 36589250 ps
CPU time 0.81 seconds
Started Mar 17 12:24:45 PM PDT 24
Finished Mar 17 12:24:46 PM PDT 24
Peak memory 199108 kb
Host smart-70a71b84-fd47-4ced-a0d9-a0d00d28311c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182366430 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1182366430
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.323645307
Short name T1191
Test name
Test status
Simulation time 30311500 ps
CPU time 0.59 seconds
Started Mar 17 12:28:27 PM PDT 24
Finished Mar 17 12:28:29 PM PDT 24
Peak memory 195572 kb
Host smart-aa61215a-0330-4f30-ab6a-ed2d5b08e4be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323645307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.323645307
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.164442230
Short name T1225
Test name
Test status
Simulation time 39054020 ps
CPU time 0.55 seconds
Started Mar 17 12:26:52 PM PDT 24
Finished Mar 17 12:26:53 PM PDT 24
Peak memory 194624 kb
Host smart-208adac4-bb6f-4cbc-a47c-2edde6b9b7bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164442230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.164442230
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2102564420
Short name T81
Test name
Test status
Simulation time 19484239 ps
CPU time 0.65 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:27:13 PM PDT 24
Peak memory 195108 kb
Host smart-db6904ad-103d-41fe-bdde-79a5656919d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102564420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2102564420
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3579318558
Short name T1116
Test name
Test status
Simulation time 422633086 ps
CPU time 2.22 seconds
Started Mar 17 12:27:04 PM PDT 24
Finished Mar 17 12:27:08 PM PDT 24
Peak memory 200416 kb
Host smart-164eeb57-ed9e-444c-a79b-7eb45c318484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579318558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3579318558
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.485138386
Short name T92
Test name
Test status
Simulation time 250034027 ps
CPU time 0.89 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:27:56 PM PDT 24
Peak memory 198936 kb
Host smart-f322561f-c58a-4c7d-9484-f9a45e0b8f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485138386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.485138386
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3916274890
Short name T1229
Test name
Test status
Simulation time 35422793 ps
CPU time 0.62 seconds
Started Mar 17 12:23:10 PM PDT 24
Finished Mar 17 12:23:11 PM PDT 24
Peak memory 195064 kb
Host smart-c7844294-94fa-4209-b2b2-b2ae4083cbfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916274890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3916274890
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3122013700
Short name T1207
Test name
Test status
Simulation time 366362651 ps
CPU time 1.5 seconds
Started Mar 17 12:22:44 PM PDT 24
Finished Mar 17 12:22:46 PM PDT 24
Peak memory 197968 kb
Host smart-3e2845b8-2c14-4ea0-9289-79e0c0b9ef3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122013700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3122013700
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2044587656
Short name T65
Test name
Test status
Simulation time 53093243 ps
CPU time 0.63 seconds
Started Mar 17 12:23:46 PM PDT 24
Finished Mar 17 12:23:47 PM PDT 24
Peak memory 195688 kb
Host smart-9ccb77a6-46e1-4214-97bf-9396f9513c4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044587656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2044587656
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.271260086
Short name T1227
Test name
Test status
Simulation time 24551810 ps
CPU time 0.77 seconds
Started Mar 17 12:22:46 PM PDT 24
Finished Mar 17 12:22:47 PM PDT 24
Peak memory 199556 kb
Host smart-0a71827d-bda1-4001-97a5-cee838f49b20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271260086 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.271260086
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4228335730
Short name T1213
Test name
Test status
Simulation time 22547158 ps
CPU time 0.59 seconds
Started Mar 17 12:26:22 PM PDT 24
Finished Mar 17 12:26:22 PM PDT 24
Peak memory 195712 kb
Host smart-a8c16eed-4a18-4929-892f-7966cb7874d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228335730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4228335730
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.4205198356
Short name T1237
Test name
Test status
Simulation time 21675917 ps
CPU time 0.55 seconds
Started Mar 17 12:23:09 PM PDT 24
Finished Mar 17 12:23:10 PM PDT 24
Peak memory 194660 kb
Host smart-469769cb-9193-4447-b10f-42544727c4a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205198356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.4205198356
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2912887196
Short name T77
Test name
Test status
Simulation time 18393328 ps
CPU time 0.64 seconds
Started Mar 17 12:22:44 PM PDT 24
Finished Mar 17 12:22:45 PM PDT 24
Peak memory 196028 kb
Host smart-170882bc-49da-4b0f-b2e2-97f9844506a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912887196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2912887196
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.865480970
Short name T1144
Test name
Test status
Simulation time 230197729 ps
CPU time 1.35 seconds
Started Mar 17 12:22:48 PM PDT 24
Finished Mar 17 12:22:49 PM PDT 24
Peak memory 200224 kb
Host smart-a3aa72d7-60a9-4c43-85be-3915a5465f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865480970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.865480970
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3589860224
Short name T1174
Test name
Test status
Simulation time 134485605 ps
CPU time 0.95 seconds
Started Mar 17 12:23:46 PM PDT 24
Finished Mar 17 12:23:48 PM PDT 24
Peak memory 198924 kb
Host smart-f6e5f6a7-7ace-4e08-889e-d96961a80f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589860224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3589860224
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3123448554
Short name T1124
Test name
Test status
Simulation time 16782613 ps
CPU time 0.65 seconds
Started Mar 17 12:23:41 PM PDT 24
Finished Mar 17 12:23:42 PM PDT 24
Peak memory 194764 kb
Host smart-af3fdbb6-7d66-4ef3-99a4-6d34600998ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123448554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3123448554
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2363664848
Short name T1159
Test name
Test status
Simulation time 22658886 ps
CPU time 0.57 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 194516 kb
Host smart-bcbcc097-d094-44c7-9d30-b38f5a66d3c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363664848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2363664848
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1391072335
Short name T1215
Test name
Test status
Simulation time 51460940 ps
CPU time 0.57 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 194580 kb
Host smart-33eae0f9-a1d8-4402-bc61-e73df2fc1d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391072335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1391072335
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1382539592
Short name T1198
Test name
Test status
Simulation time 13540215 ps
CPU time 0.56 seconds
Started Mar 17 12:26:10 PM PDT 24
Finished Mar 17 12:26:11 PM PDT 24
Peak memory 194664 kb
Host smart-497cf6ae-7d77-49ad-9663-cead67df56fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382539592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1382539592
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1393500192
Short name T1235
Test name
Test status
Simulation time 14661128 ps
CPU time 0.58 seconds
Started Mar 17 12:28:01 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 194596 kb
Host smart-a8d6a77b-dfcf-4a68-9c0f-a0ef7cb9d5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393500192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1393500192
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.4271788462
Short name T1160
Test name
Test status
Simulation time 17113587 ps
CPU time 0.62 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:27:56 PM PDT 24
Peak memory 193696 kb
Host smart-128c8328-b8e9-4e34-b6bc-6a1734fefe9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271788462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4271788462
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.757260448
Short name T1142
Test name
Test status
Simulation time 38696198 ps
CPU time 0.66 seconds
Started Mar 17 12:24:31 PM PDT 24
Finished Mar 17 12:24:32 PM PDT 24
Peak memory 194608 kb
Host smart-4ba589f8-1d5d-41c5-b132-dc67f5542516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757260448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.757260448
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1828826225
Short name T1161
Test name
Test status
Simulation time 115874373 ps
CPU time 0.59 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:11 PM PDT 24
Peak memory 194516 kb
Host smart-987db95f-3046-43fe-a48b-c80cb454d6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828826225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1828826225
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2850210284
Short name T1118
Test name
Test status
Simulation time 15030769 ps
CPU time 0.63 seconds
Started Mar 17 12:23:46 PM PDT 24
Finished Mar 17 12:23:47 PM PDT 24
Peak memory 193232 kb
Host smart-6bf49c39-4b68-48a7-8dc3-210de9aa6364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850210284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2850210284
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1791180744
Short name T1169
Test name
Test status
Simulation time 25576872 ps
CPU time 0.56 seconds
Started Mar 17 12:23:54 PM PDT 24
Finished Mar 17 12:23:56 PM PDT 24
Peak memory 194600 kb
Host smart-07ffb361-2f7b-4983-9b47-50fc91fb8542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791180744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1791180744
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1863847900
Short name T1158
Test name
Test status
Simulation time 374421741 ps
CPU time 1.57 seconds
Started Mar 17 12:23:59 PM PDT 24
Finished Mar 17 12:24:01 PM PDT 24
Peak memory 198192 kb
Host smart-13e9803c-7f7a-454d-986d-a70d92323901
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863847900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1863847900
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.429741547
Short name T1224
Test name
Test status
Simulation time 15210335 ps
CPU time 0.63 seconds
Started Mar 17 12:22:45 PM PDT 24
Finished Mar 17 12:22:46 PM PDT 24
Peak memory 195644 kb
Host smart-9743daeb-f4db-4bf9-bd1d-3e4175f9b3ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429741547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.429741547
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1820487994
Short name T1132
Test name
Test status
Simulation time 76010214 ps
CPU time 0.76 seconds
Started Mar 17 12:23:23 PM PDT 24
Finished Mar 17 12:23:24 PM PDT 24
Peak memory 197844 kb
Host smart-1b702b2c-572c-45ff-a2b8-c53d5ab0b4f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820487994 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1820487994
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2005411466
Short name T1220
Test name
Test status
Simulation time 18378460 ps
CPU time 0.58 seconds
Started Mar 17 12:22:57 PM PDT 24
Finished Mar 17 12:22:58 PM PDT 24
Peak memory 195660 kb
Host smart-b57f3055-f692-4d09-bee8-3f7e54efb3f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005411466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2005411466
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3754520687
Short name T1162
Test name
Test status
Simulation time 152816047 ps
CPU time 0.59 seconds
Started Mar 17 12:22:51 PM PDT 24
Finished Mar 17 12:22:52 PM PDT 24
Peak memory 194644 kb
Host smart-070771e0-87a2-4590-b120-71d6a8da495a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754520687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3754520687
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.240443096
Short name T1201
Test name
Test status
Simulation time 25948996 ps
CPU time 0.85 seconds
Started Mar 17 12:22:38 PM PDT 24
Finished Mar 17 12:22:39 PM PDT 24
Peak memory 196496 kb
Host smart-b5f2495c-d866-4988-9e9f-3d4af96267b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240443096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.240443096
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1123999746
Short name T1178
Test name
Test status
Simulation time 91412766 ps
CPU time 1.23 seconds
Started Mar 17 12:22:44 PM PDT 24
Finished Mar 17 12:22:45 PM PDT 24
Peak memory 200200 kb
Host smart-acee9986-7c40-449c-a8e1-7fe313703e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123999746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1123999746
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3898607933
Short name T1217
Test name
Test status
Simulation time 86495436 ps
CPU time 0.9 seconds
Started Mar 17 12:23:09 PM PDT 24
Finished Mar 17 12:23:10 PM PDT 24
Peak memory 198924 kb
Host smart-b80d202b-ea9f-4b5a-a2dd-03a09aa3fd35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898607933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3898607933
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.942664472
Short name T1164
Test name
Test status
Simulation time 40341713 ps
CPU time 0.62 seconds
Started Mar 17 12:23:41 PM PDT 24
Finished Mar 17 12:23:42 PM PDT 24
Peak memory 194764 kb
Host smart-f0779ada-83f1-40f2-810f-2dc3dc74902f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942664472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.942664472
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2370062660
Short name T1126
Test name
Test status
Simulation time 19601326 ps
CPU time 0.56 seconds
Started Mar 17 12:23:48 PM PDT 24
Finished Mar 17 12:23:49 PM PDT 24
Peak memory 194644 kb
Host smart-8e6cca73-7047-443e-9dba-5a022e72c1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370062660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2370062660
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.656365615
Short name T1149
Test name
Test status
Simulation time 13043682 ps
CPU time 0.62 seconds
Started Mar 17 12:26:05 PM PDT 24
Finished Mar 17 12:26:06 PM PDT 24
Peak memory 194824 kb
Host smart-083a13b7-6535-4b07-8afb-71d33a6e2acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656365615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.656365615
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.659584631
Short name T1184
Test name
Test status
Simulation time 29848975 ps
CPU time 0.57 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 194596 kb
Host smart-c0196f99-ae24-484f-9179-6b4ab0a9a3e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659584631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.659584631
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1027280998
Short name T1152
Test name
Test status
Simulation time 84030351 ps
CPU time 0.6 seconds
Started Mar 17 12:24:01 PM PDT 24
Finished Mar 17 12:24:02 PM PDT 24
Peak memory 194668 kb
Host smart-6bf8cde5-e8c5-4606-a99c-2517a37db4db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027280998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1027280998
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1575246859
Short name T1212
Test name
Test status
Simulation time 44271037 ps
CPU time 0.61 seconds
Started Mar 17 12:23:45 PM PDT 24
Finished Mar 17 12:23:46 PM PDT 24
Peak memory 194668 kb
Host smart-3ae5db07-07cf-4d65-ae18-6d432adb7150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575246859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1575246859
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2385548790
Short name T1233
Test name
Test status
Simulation time 17842113 ps
CPU time 0.56 seconds
Started Mar 17 12:23:59 PM PDT 24
Finished Mar 17 12:24:00 PM PDT 24
Peak memory 194600 kb
Host smart-74221da5-5255-42a5-b265-faeab927914f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385548790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2385548790
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1629950823
Short name T1176
Test name
Test status
Simulation time 22384320 ps
CPU time 0.62 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:28:49 PM PDT 24
Peak memory 194656 kb
Host smart-a8eb45d7-2c65-48f8-9487-3a8eac5dd9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629950823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1629950823
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3080339857
Short name T1156
Test name
Test status
Simulation time 15607137 ps
CPU time 0.55 seconds
Started Mar 17 12:26:53 PM PDT 24
Finished Mar 17 12:26:54 PM PDT 24
Peak memory 193760 kb
Host smart-ca64ce53-5f62-4619-bbac-d011cec8697f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080339857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3080339857
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.540558222
Short name T1122
Test name
Test status
Simulation time 47376700 ps
CPU time 0.56 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 194692 kb
Host smart-7b052311-2072-4301-adad-0c8fd84b2de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540558222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.540558222
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2636460895
Short name T69
Test name
Test status
Simulation time 52156631 ps
CPU time 0.93 seconds
Started Mar 17 12:23:41 PM PDT 24
Finished Mar 17 12:23:42 PM PDT 24
Peak memory 195120 kb
Host smart-59bde49f-47d3-4b09-a365-5a97f5c6ccd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636460895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2636460895
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.127185115
Short name T1119
Test name
Test status
Simulation time 65424178 ps
CPU time 1.54 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:03 PM PDT 24
Peak memory 196444 kb
Host smart-29c826d3-0184-45a7-9cd9-9bb0428a803e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127185115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.127185115
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2313857604
Short name T64
Test name
Test status
Simulation time 21226083 ps
CPU time 0.6 seconds
Started Mar 17 12:24:20 PM PDT 24
Finished Mar 17 12:24:21 PM PDT 24
Peak memory 195688 kb
Host smart-1693f743-c32d-4967-9798-04b6ec4a2d8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313857604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2313857604
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1585037285
Short name T1246
Test name
Test status
Simulation time 79248431 ps
CPU time 0.66 seconds
Started Mar 17 12:23:37 PM PDT 24
Finished Mar 17 12:23:38 PM PDT 24
Peak memory 197608 kb
Host smart-b7cc10bd-08b7-4793-9e46-e5f22aebc424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585037285 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1585037285
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3603141940
Short name T1151
Test name
Test status
Simulation time 12553848 ps
CPU time 0.6 seconds
Started Mar 17 12:26:04 PM PDT 24
Finished Mar 17 12:26:05 PM PDT 24
Peak memory 195812 kb
Host smart-a28eeb3f-823a-4d00-b1e0-544120494bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603141940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3603141940
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1700942958
Short name T1133
Test name
Test status
Simulation time 17612654 ps
CPU time 0.6 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:28:17 PM PDT 24
Peak memory 193768 kb
Host smart-79d23032-5f51-482e-b3d4-ed3bffd71b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700942958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1700942958
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2136676602
Short name T78
Test name
Test status
Simulation time 52912653 ps
CPU time 0.71 seconds
Started Mar 17 12:25:47 PM PDT 24
Finished Mar 17 12:25:48 PM PDT 24
Peak memory 196080 kb
Host smart-47cfb8a5-5cb0-4ab3-80cb-d4dc2535f75a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136676602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2136676602
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3962610909
Short name T1205
Test name
Test status
Simulation time 147471097 ps
CPU time 1.32 seconds
Started Mar 17 12:23:09 PM PDT 24
Finished Mar 17 12:23:10 PM PDT 24
Peak memory 200428 kb
Host smart-7f5d4467-bb82-42fb-87c0-f4ca7934fb63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962610909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3962610909
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2244137074
Short name T1222
Test name
Test status
Simulation time 51700375 ps
CPU time 0.97 seconds
Started Mar 17 12:23:36 PM PDT 24
Finished Mar 17 12:23:37 PM PDT 24
Peak memory 199276 kb
Host smart-3d28c06a-c674-4e82-aad5-449b016319b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244137074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2244137074
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.387888154
Short name T1181
Test name
Test status
Simulation time 22151996 ps
CPU time 0.58 seconds
Started Mar 17 12:26:53 PM PDT 24
Finished Mar 17 12:26:54 PM PDT 24
Peak memory 193328 kb
Host smart-cfe1913f-f415-4990-8c81-b9d902092a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387888154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.387888154
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.446718885
Short name T1157
Test name
Test status
Simulation time 18569827 ps
CPU time 0.65 seconds
Started Mar 17 12:25:53 PM PDT 24
Finished Mar 17 12:25:53 PM PDT 24
Peak memory 194656 kb
Host smart-b606286f-499a-4c15-b9f2-d9b20a401891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446718885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.446718885
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3307708672
Short name T1196
Test name
Test status
Simulation time 11931626 ps
CPU time 0.55 seconds
Started Mar 17 12:26:21 PM PDT 24
Finished Mar 17 12:26:21 PM PDT 24
Peak memory 194608 kb
Host smart-dbcde5a6-9545-4b56-b967-af5177033027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307708672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3307708672
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3670212409
Short name T1155
Test name
Test status
Simulation time 19828379 ps
CPU time 0.6 seconds
Started Mar 17 12:26:53 PM PDT 24
Finished Mar 17 12:26:54 PM PDT 24
Peak memory 193184 kb
Host smart-062a4082-cd04-494b-a1a7-66e400c7bf8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670212409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3670212409
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1249750492
Short name T1195
Test name
Test status
Simulation time 32855019 ps
CPU time 0.54 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:07 PM PDT 24
Peak memory 194640 kb
Host smart-f436b079-0337-428f-aeda-b2e458f621ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249750492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1249750492
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3416440318
Short name T1131
Test name
Test status
Simulation time 26477239 ps
CPU time 0.56 seconds
Started Mar 17 12:26:53 PM PDT 24
Finished Mar 17 12:26:54 PM PDT 24
Peak memory 194436 kb
Host smart-5c25a271-393e-4449-b6d8-3b5504ecc0c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416440318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3416440318
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2911651239
Short name T1148
Test name
Test status
Simulation time 14422479 ps
CPU time 0.55 seconds
Started Mar 17 12:24:45 PM PDT 24
Finished Mar 17 12:24:46 PM PDT 24
Peak memory 194608 kb
Host smart-52a8a57f-c040-484a-8841-576379df69b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911651239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2911651239
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2634178793
Short name T1114
Test name
Test status
Simulation time 52855700 ps
CPU time 0.59 seconds
Started Mar 17 12:25:23 PM PDT 24
Finished Mar 17 12:25:24 PM PDT 24
Peak memory 194708 kb
Host smart-88ea96f4-ca49-4e13-af07-780fb862b3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634178793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2634178793
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.409753747
Short name T1130
Test name
Test status
Simulation time 16803943 ps
CPU time 0.59 seconds
Started Mar 17 12:24:30 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 194640 kb
Host smart-5fb0c111-66be-469d-ade8-971e0aed8752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409753747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.409753747
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1781351440
Short name T1182
Test name
Test status
Simulation time 16747510 ps
CPU time 0.63 seconds
Started Mar 17 12:28:12 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 194476 kb
Host smart-3f7fd34e-6b6c-4861-8320-83dfaa748940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781351440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1781351440
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3446682996
Short name T1175
Test name
Test status
Simulation time 298717046 ps
CPU time 0.89 seconds
Started Mar 17 12:23:44 PM PDT 24
Finished Mar 17 12:23:45 PM PDT 24
Peak memory 200048 kb
Host smart-a7c287e8-0800-4244-8229-bc8ce38bc824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446682996 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3446682996
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3872735216
Short name T74
Test name
Test status
Simulation time 13338812 ps
CPU time 0.59 seconds
Started Mar 17 12:24:49 PM PDT 24
Finished Mar 17 12:24:50 PM PDT 24
Peak memory 195764 kb
Host smart-0575cea3-2442-48b1-820b-c327bac3b587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872735216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3872735216
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.974002693
Short name T1244
Test name
Test status
Simulation time 17680667 ps
CPU time 0.59 seconds
Started Mar 17 12:23:57 PM PDT 24
Finished Mar 17 12:23:58 PM PDT 24
Peak memory 194524 kb
Host smart-9bcd9f45-1ccb-4c7c-9372-ce0d8864b2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974002693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.974002693
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4035910061
Short name T1163
Test name
Test status
Simulation time 92146381 ps
CPU time 0.63 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:01 PM PDT 24
Peak memory 196048 kb
Host smart-46e0ac14-84d2-4630-9990-8a4f2a63788d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035910061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4035910061
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.399946371
Short name T1150
Test name
Test status
Simulation time 45330287 ps
CPU time 1.04 seconds
Started Mar 17 12:26:16 PM PDT 24
Finished Mar 17 12:26:17 PM PDT 24
Peak memory 200064 kb
Host smart-663d95fd-67cf-4fe7-a228-80d8c56bc9a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399946371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.399946371
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3004114281
Short name T1232
Test name
Test status
Simulation time 78853258 ps
CPU time 0.96 seconds
Started Mar 17 12:27:52 PM PDT 24
Finished Mar 17 12:27:54 PM PDT 24
Peak memory 198188 kb
Host smart-9591bca9-6dcb-4385-8798-6e080a89362e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004114281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3004114281
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.832435082
Short name T1214
Test name
Test status
Simulation time 35374822 ps
CPU time 0.87 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:09 PM PDT 24
Peak memory 200056 kb
Host smart-dec107b4-5093-499f-8ab7-3439116b2802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832435082 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.832435082
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.210905313
Short name T1211
Test name
Test status
Simulation time 114500053 ps
CPU time 0.61 seconds
Started Mar 17 12:25:58 PM PDT 24
Finished Mar 17 12:25:58 PM PDT 24
Peak memory 195788 kb
Host smart-eb13f456-3088-4811-bce1-ad970aaa24ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210905313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.210905313
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2109013707
Short name T1192
Test name
Test status
Simulation time 13470652 ps
CPU time 0.56 seconds
Started Mar 17 12:25:32 PM PDT 24
Finished Mar 17 12:25:33 PM PDT 24
Peak memory 194668 kb
Host smart-428c8cfe-a69c-4a7a-87c4-aee8fb53f00f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109013707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2109013707
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4208093054
Short name T1141
Test name
Test status
Simulation time 15064112 ps
CPU time 0.66 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:44 PM PDT 24
Peak memory 194896 kb
Host smart-e736880a-6f59-4af0-ab4c-85cac3a1c74b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208093054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.4208093054
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1904283178
Short name T1204
Test name
Test status
Simulation time 25855854 ps
CPU time 1.18 seconds
Started Mar 17 12:26:12 PM PDT 24
Finished Mar 17 12:26:14 PM PDT 24
Peak memory 200364 kb
Host smart-260a1557-5b3a-4bcf-99ca-bc1f246033a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904283178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1904283178
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1511201259
Short name T1197
Test name
Test status
Simulation time 73047410 ps
CPU time 0.97 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:44 PM PDT 24
Peak memory 199148 kb
Host smart-2f565d79-3b2f-4df2-88ee-3ed0db626e05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511201259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1511201259
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1300237081
Short name T1125
Test name
Test status
Simulation time 14062009 ps
CPU time 0.65 seconds
Started Mar 17 12:24:58 PM PDT 24
Finished Mar 17 12:24:59 PM PDT 24
Peak memory 197444 kb
Host smart-abcd1376-c75d-46fd-9c51-ad814b306afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300237081 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1300237081
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.61071031
Short name T79
Test name
Test status
Simulation time 14179311 ps
CPU time 0.6 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:28:31 PM PDT 24
Peak memory 195596 kb
Host smart-b4d19d5c-5d40-4292-9ea7-f9d33ac9ab97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61071031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.61071031
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2099813804
Short name T1247
Test name
Test status
Simulation time 14316532 ps
CPU time 0.58 seconds
Started Mar 17 12:26:14 PM PDT 24
Finished Mar 17 12:26:14 PM PDT 24
Peak memory 194804 kb
Host smart-ab923b58-0c53-4927-8565-f1f648a99bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099813804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2099813804
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2711065433
Short name T1209
Test name
Test status
Simulation time 61778950 ps
CPU time 0.77 seconds
Started Mar 17 12:24:13 PM PDT 24
Finished Mar 17 12:24:14 PM PDT 24
Peak memory 197760 kb
Host smart-7d403533-849f-4b7b-b8ed-cca0bbc26e95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711065433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2711065433
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.948057227
Short name T1128
Test name
Test status
Simulation time 264465884 ps
CPU time 1.41 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 200292 kb
Host smart-749c5329-445b-4a6d-93e2-65c372b61f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948057227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.948057227
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1738952562
Short name T91
Test name
Test status
Simulation time 120613416 ps
CPU time 1.29 seconds
Started Mar 17 12:26:21 PM PDT 24
Finished Mar 17 12:26:23 PM PDT 24
Peak memory 199380 kb
Host smart-2e171769-4a8d-46b6-868b-bece116ba112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738952562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1738952562
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3497010679
Short name T1147
Test name
Test status
Simulation time 50157242 ps
CPU time 1.08 seconds
Started Mar 17 12:27:20 PM PDT 24
Finished Mar 17 12:27:21 PM PDT 24
Peak memory 199988 kb
Host smart-f5ca75c1-5230-4374-a730-bba9609670ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497010679 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3497010679
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.479479012
Short name T1166
Test name
Test status
Simulation time 45215651 ps
CPU time 0.64 seconds
Started Mar 17 12:27:53 PM PDT 24
Finished Mar 17 12:27:54 PM PDT 24
Peak memory 195308 kb
Host smart-3bc30aa2-296c-4863-a71d-a07ea6a598f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479479012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.479479012
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.906591766
Short name T1241
Test name
Test status
Simulation time 34643427 ps
CPU time 0.57 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:07 PM PDT 24
Peak memory 194316 kb
Host smart-a3d07494-91fd-4067-a2a8-2d618949f635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906591766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.906591766
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1956579234
Short name T1140
Test name
Test status
Simulation time 32195685 ps
CPU time 0.78 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:16 PM PDT 24
Peak memory 196248 kb
Host smart-758c6cdb-7986-4b31-814d-be51136410c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956579234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1956579234
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1134673023
Short name T1231
Test name
Test status
Simulation time 43240814 ps
CPU time 2.05 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 200076 kb
Host smart-0ba9fc2f-7905-4995-b0b5-51847eb9db47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134673023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1134673023
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.541720960
Short name T1185
Test name
Test status
Simulation time 79900358 ps
CPU time 0.97 seconds
Started Mar 17 12:28:29 PM PDT 24
Finished Mar 17 12:28:30 PM PDT 24
Peak memory 199036 kb
Host smart-37704516-546a-4b4e-9559-4546efcb3fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541720960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.541720960
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3970386781
Short name T1183
Test name
Test status
Simulation time 473125396 ps
CPU time 0.85 seconds
Started Mar 17 12:26:21 PM PDT 24
Finished Mar 17 12:26:22 PM PDT 24
Peak memory 200252 kb
Host smart-d70e3fa7-a10a-4199-8ad3-96668353fd56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970386781 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3970386781
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3324534892
Short name T1129
Test name
Test status
Simulation time 27418263 ps
CPU time 0.58 seconds
Started Mar 17 12:27:20 PM PDT 24
Finished Mar 17 12:27:21 PM PDT 24
Peak memory 195204 kb
Host smart-952b1cdb-e9f5-4fdd-aa9e-a6f1120310e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324534892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3324534892
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1701318352
Short name T1200
Test name
Test status
Simulation time 30859727 ps
CPU time 0.57 seconds
Started Mar 17 12:24:35 PM PDT 24
Finished Mar 17 12:24:36 PM PDT 24
Peak memory 194640 kb
Host smart-936558d3-f36e-4c37-8d2a-de956627fdff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701318352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1701318352
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3238473585
Short name T1190
Test name
Test status
Simulation time 154755366 ps
CPU time 0.74 seconds
Started Mar 17 12:26:06 PM PDT 24
Finished Mar 17 12:26:07 PM PDT 24
Peak memory 194656 kb
Host smart-9d090f0a-5f4d-4c7a-80c7-3cd561445872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238473585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3238473585
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3984196727
Short name T1177
Test name
Test status
Simulation time 440950850 ps
CPU time 1.83 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:28:18 PM PDT 24
Peak memory 200084 kb
Host smart-850caa80-8451-4775-93eb-08342c5de70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984196727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3984196727
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_alert_test.2092574012
Short name T892
Test name
Test status
Simulation time 16530705 ps
CPU time 0.53 seconds
Started Mar 17 12:33:54 PM PDT 24
Finished Mar 17 12:33:55 PM PDT 24
Peak memory 195484 kb
Host smart-2b987987-0f82-44e1-9491-9a240bf979d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092574012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2092574012
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3180860695
Short name T1014
Test name
Test status
Simulation time 36639078999 ps
CPU time 60.86 seconds
Started Mar 17 12:23:09 PM PDT 24
Finished Mar 17 12:24:10 PM PDT 24
Peak memory 200020 kb
Host smart-7227b867-3f06-4920-b0a6-6f71479fd12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180860695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3180860695
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1252002275
Short name T822
Test name
Test status
Simulation time 72021051145 ps
CPU time 99.65 seconds
Started Mar 17 12:24:45 PM PDT 24
Finished Mar 17 12:26:25 PM PDT 24
Peak memory 198416 kb
Host smart-9a021f96-d6e9-4eb4-9523-eb28432ba866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252002275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1252002275
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2961735834
Short name T924
Test name
Test status
Simulation time 31077664553 ps
CPU time 46.49 seconds
Started Mar 17 12:28:11 PM PDT 24
Finished Mar 17 12:28:58 PM PDT 24
Peak memory 199876 kb
Host smart-ef96e7f2-03f1-4754-9a58-f360a38147f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961735834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2961735834
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.4266479626
Short name T280
Test name
Test status
Simulation time 277307542176 ps
CPU time 480.97 seconds
Started Mar 17 12:33:41 PM PDT 24
Finished Mar 17 12:41:42 PM PDT 24
Peak memory 199960 kb
Host smart-fe93e129-c419-4b76-b72b-b8b6ecc83f69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266479626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.4266479626
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.858178616
Short name T428
Test name
Test status
Simulation time 137108834923 ps
CPU time 1330.93 seconds
Started Mar 17 12:33:57 PM PDT 24
Finished Mar 17 12:56:08 PM PDT 24
Peak memory 200008 kb
Host smart-6a85439e-17f3-443a-9aba-d0a87c886841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=858178616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.858178616
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2640817649
Short name T383
Test name
Test status
Simulation time 2619487323 ps
CPU time 5.44 seconds
Started Mar 17 12:33:54 PM PDT 24
Finished Mar 17 12:34:00 PM PDT 24
Peak memory 197804 kb
Host smart-e2206c3b-a22f-4ac7-ba4d-92c40fdf23d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640817649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2640817649
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.482687732
Short name T625
Test name
Test status
Simulation time 110053511524 ps
CPU time 218.55 seconds
Started Mar 17 12:33:41 PM PDT 24
Finished Mar 17 12:37:20 PM PDT 24
Peak memory 198808 kb
Host smart-052a1f89-b86e-4b0d-840c-334bd07fc3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482687732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.482687732
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.420848086
Short name T419
Test name
Test status
Simulation time 1452035242 ps
CPU time 43.1 seconds
Started Mar 17 12:33:55 PM PDT 24
Finished Mar 17 12:34:38 PM PDT 24
Peak memory 199916 kb
Host smart-9e7c2dd0-1710-44d5-92c4-e6d08cb0cca8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=420848086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.420848086
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3940110352
Short name T384
Test name
Test status
Simulation time 4216413223 ps
CPU time 17 seconds
Started Mar 17 12:26:04 PM PDT 24
Finished Mar 17 12:26:22 PM PDT 24
Peak memory 198408 kb
Host smart-bd753211-7758-46f1-8414-2096f0212296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940110352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3940110352
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.849009529
Short name T493
Test name
Test status
Simulation time 100336844811 ps
CPU time 47.11 seconds
Started Mar 17 12:33:39 PM PDT 24
Finished Mar 17 12:34:27 PM PDT 24
Peak memory 199200 kb
Host smart-a7e5a4b2-d148-4086-8635-59f984cbc0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849009529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.849009529
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.592149867
Short name T714
Test name
Test status
Simulation time 45863204044 ps
CPU time 15.13 seconds
Started Mar 17 12:33:41 PM PDT 24
Finished Mar 17 12:33:56 PM PDT 24
Peak memory 196016 kb
Host smart-8d3f7681-e75a-4337-b2eb-13bb197752cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592149867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.592149867
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.4235522209
Short name T418
Test name
Test status
Simulation time 465997662 ps
CPU time 1.43 seconds
Started Mar 17 12:27:53 PM PDT 24
Finished Mar 17 12:27:55 PM PDT 24
Peak memory 198484 kb
Host smart-8072d961-4f41-4f35-b743-0ad34b3d2167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235522209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4235522209
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2201861005
Short name T396
Test name
Test status
Simulation time 139209193472 ps
CPU time 65.02 seconds
Started Mar 17 12:33:55 PM PDT 24
Finished Mar 17 12:35:01 PM PDT 24
Peak memory 215728 kb
Host smart-64477b9d-4aca-457d-a999-db10f50fa592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201861005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2201861005
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.105119505
Short name T106
Test name
Test status
Simulation time 197912687295 ps
CPU time 721.21 seconds
Started Mar 17 12:33:55 PM PDT 24
Finished Mar 17 12:45:56 PM PDT 24
Peak memory 216412 kb
Host smart-cd14d268-a365-444d-9206-5826fe5f56cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105119505 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.105119505
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.743457145
Short name T547
Test name
Test status
Simulation time 750442086 ps
CPU time 2.37 seconds
Started Mar 17 12:33:54 PM PDT 24
Finished Mar 17 12:33:56 PM PDT 24
Peak memory 198996 kb
Host smart-8baceaab-828d-4925-b8b0-d6479fdb42f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743457145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.743457145
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.4225906819
Short name T287
Test name
Test status
Simulation time 18855325319 ps
CPU time 31.16 seconds
Started Mar 17 12:26:04 PM PDT 24
Finished Mar 17 12:26:35 PM PDT 24
Peak memory 198176 kb
Host smart-d991282e-c3f2-4950-9981-e3b63ceb01d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225906819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.4225906819
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3297467547
Short name T738
Test name
Test status
Simulation time 35172425 ps
CPU time 0.55 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:07 PM PDT 24
Peak memory 195560 kb
Host smart-7cc4f247-73f9-4714-9e24-64c2d48e00a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297467547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3297467547
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3628879308
Short name T899
Test name
Test status
Simulation time 42570417401 ps
CPU time 65.18 seconds
Started Mar 17 12:33:59 PM PDT 24
Finished Mar 17 12:35:04 PM PDT 24
Peak memory 200052 kb
Host smart-4d907b85-c601-47a5-95d9-8d3982950c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628879308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3628879308
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3792567802
Short name T1050
Test name
Test status
Simulation time 53824197337 ps
CPU time 18.92 seconds
Started Mar 17 12:33:56 PM PDT 24
Finished Mar 17 12:34:15 PM PDT 24
Peak memory 199696 kb
Host smart-499156ea-4eec-4426-b068-0ec60134172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792567802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3792567802
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2267649335
Short name T510
Test name
Test status
Simulation time 74022596761 ps
CPU time 53 seconds
Started Mar 17 12:33:55 PM PDT 24
Finished Mar 17 12:34:48 PM PDT 24
Peak memory 199744 kb
Host smart-0ef796da-6abb-40b2-9a72-255370af1e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267649335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2267649335
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3149377153
Short name T465
Test name
Test status
Simulation time 26495926102 ps
CPU time 21.27 seconds
Started Mar 17 12:34:00 PM PDT 24
Finished Mar 17 12:34:21 PM PDT 24
Peak memory 197716 kb
Host smart-b17ac8b3-3807-4908-bcd3-e5a92bbe2db4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149377153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3149377153
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2489495470
Short name T410
Test name
Test status
Simulation time 37920284430 ps
CPU time 340.2 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:39:45 PM PDT 24
Peak memory 200052 kb
Host smart-1ee63e18-3148-4fb3-b682-3bdcf0c78cc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489495470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2489495470
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.657012652
Short name T726
Test name
Test status
Simulation time 8440626042 ps
CPU time 9.51 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:16 PM PDT 24
Peak memory 200084 kb
Host smart-54b56764-f2ae-4d94-96c2-597ad01b8aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657012652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.657012652
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.4055630286
Short name T61
Test name
Test status
Simulation time 3175528611 ps
CPU time 6.13 seconds
Started Mar 17 12:33:54 PM PDT 24
Finished Mar 17 12:34:00 PM PDT 24
Peak memory 195796 kb
Host smart-7ac998a9-9658-46f3-85f9-2b8e539de914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055630286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4055630286
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.179428958
Short name T604
Test name
Test status
Simulation time 9682489917 ps
CPU time 227.44 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 199960 kb
Host smart-4bfee471-0190-40d5-9797-df4f5c0e5b03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179428958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.179428958
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1287282542
Short name T743
Test name
Test status
Simulation time 1289945025 ps
CPU time 1.9 seconds
Started Mar 17 12:33:55 PM PDT 24
Finished Mar 17 12:33:57 PM PDT 24
Peak memory 198032 kb
Host smart-d94e95a0-c99c-40f3-8ee3-be8f30f5e383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287282542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1287282542
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2049962289
Short name T632
Test name
Test status
Simulation time 56782158106 ps
CPU time 102.91 seconds
Started Mar 17 12:33:57 PM PDT 24
Finished Mar 17 12:35:41 PM PDT 24
Peak memory 200076 kb
Host smart-6e3eb58d-84eb-4ad6-bb45-297f3b6ccaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049962289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2049962289
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3708052061
Short name T362
Test name
Test status
Simulation time 2417390789 ps
CPU time 0.98 seconds
Started Mar 17 12:33:54 PM PDT 24
Finished Mar 17 12:33:55 PM PDT 24
Peak memory 195568 kb
Host smart-40333ba1-525b-4f7f-b40c-c0754f60cb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708052061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3708052061
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3068919620
Short name T93
Test name
Test status
Simulation time 144701061 ps
CPU time 0.77 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:34:08 PM PDT 24
Peak memory 218320 kb
Host smart-aeae07f9-2b40-4a30-a93e-cecf92678526
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068919620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3068919620
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3326486864
Short name T304
Test name
Test status
Simulation time 447287076 ps
CPU time 1.71 seconds
Started Mar 17 12:33:56 PM PDT 24
Finished Mar 17 12:33:58 PM PDT 24
Peak memory 198448 kb
Host smart-a9e78e12-1478-4f94-9669-57cefa41cb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326486864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3326486864
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2245340226
Short name T853
Test name
Test status
Simulation time 160346979979 ps
CPU time 1036.93 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:51:24 PM PDT 24
Peak memory 199996 kb
Host smart-8cec8a03-6268-4aa5-b0c7-5f6d5d9f5692
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245340226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2245340226
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1818776020
Short name T265
Test name
Test status
Simulation time 1611117178 ps
CPU time 2.15 seconds
Started Mar 17 12:33:55 PM PDT 24
Finished Mar 17 12:33:57 PM PDT 24
Peak memory 199596 kb
Host smart-deca4a18-16a0-4ee4-afb4-27d1418adac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818776020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1818776020
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3612740071
Short name T825
Test name
Test status
Simulation time 12695132680 ps
CPU time 17.24 seconds
Started Mar 17 12:33:58 PM PDT 24
Finished Mar 17 12:34:15 PM PDT 24
Peak memory 200056 kb
Host smart-72592c7c-4fd4-455a-be87-a7297d1b6d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612740071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3612740071
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.4062984949
Short name T819
Test name
Test status
Simulation time 32585345531 ps
CPU time 15.98 seconds
Started Mar 17 12:34:29 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 200028 kb
Host smart-be44fe8e-dbce-409c-893a-12247cd21ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062984949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.4062984949
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3200996600
Short name T666
Test name
Test status
Simulation time 59711284718 ps
CPU time 34.56 seconds
Started Mar 17 12:34:25 PM PDT 24
Finished Mar 17 12:35:00 PM PDT 24
Peak memory 200012 kb
Host smart-49b93b61-9836-4160-816d-f588ec29d7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200996600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3200996600
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.4025570029
Short name T474
Test name
Test status
Simulation time 17812277987 ps
CPU time 16.78 seconds
Started Mar 17 12:34:28 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 199892 kb
Host smart-5c1779ff-5293-4a6f-85e5-15e84a3b69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025570029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.4025570029
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.4057610043
Short name T433
Test name
Test status
Simulation time 8752301955 ps
CPU time 3.96 seconds
Started Mar 17 12:34:26 PM PDT 24
Finished Mar 17 12:34:30 PM PDT 24
Peak memory 200004 kb
Host smart-76315f3a-e4b2-4eab-b67a-b47e22ab0b6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057610043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.4057610043
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3070545617
Short name T655
Test name
Test status
Simulation time 147724318046 ps
CPU time 310.89 seconds
Started Mar 17 12:34:33 PM PDT 24
Finished Mar 17 12:39:45 PM PDT 24
Peak memory 200124 kb
Host smart-a1e40a9d-ecff-4e4a-ae9c-e1f65c16b4ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070545617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3070545617
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.343817535
Short name T370
Test name
Test status
Simulation time 2639811154 ps
CPU time 5.29 seconds
Started Mar 17 12:34:34 PM PDT 24
Finished Mar 17 12:34:40 PM PDT 24
Peak memory 199808 kb
Host smart-12d3be97-f446-40ee-97aa-77a3c353c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343817535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.343817535
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3045613509
Short name T695
Test name
Test status
Simulation time 58819603837 ps
CPU time 54.03 seconds
Started Mar 17 12:34:26 PM PDT 24
Finished Mar 17 12:35:20 PM PDT 24
Peak memory 198072 kb
Host smart-50373d08-e99c-4303-92af-3b4c75f7c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045613509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3045613509
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3008409473
Short name T747
Test name
Test status
Simulation time 24270752883 ps
CPU time 121.86 seconds
Started Mar 17 12:34:32 PM PDT 24
Finished Mar 17 12:36:35 PM PDT 24
Peak memory 200008 kb
Host smart-52d02d9a-8214-4f1d-8d71-ba0b9c653777
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008409473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3008409473
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.127125185
Short name T824
Test name
Test status
Simulation time 2301528540 ps
CPU time 8.59 seconds
Started Mar 17 12:34:27 PM PDT 24
Finished Mar 17 12:34:35 PM PDT 24
Peak memory 199236 kb
Host smart-1d635cb5-23e0-4d94-ae9d-2fef926a4a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=127125185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.127125185
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2287356944
Short name T660
Test name
Test status
Simulation time 70850008694 ps
CPU time 56.51 seconds
Started Mar 17 12:34:26 PM PDT 24
Finished Mar 17 12:35:22 PM PDT 24
Peak memory 199928 kb
Host smart-8a5961c0-cb9c-4acf-8df9-9ad2dbea0fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287356944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2287356944
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3861611760
Short name T729
Test name
Test status
Simulation time 3435200306 ps
CPU time 4.55 seconds
Started Mar 17 12:34:26 PM PDT 24
Finished Mar 17 12:34:31 PM PDT 24
Peak memory 196272 kb
Host smart-a1dd2c60-5754-4b05-9af9-1b5090b1d4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861611760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3861611760
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2644394348
Short name T736
Test name
Test status
Simulation time 264932389 ps
CPU time 1.57 seconds
Started Mar 17 12:34:25 PM PDT 24
Finished Mar 17 12:34:27 PM PDT 24
Peak memory 198396 kb
Host smart-928ebb92-7444-407d-a459-8fa449c64ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644394348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2644394348
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.4101900689
Short name T1010
Test name
Test status
Simulation time 81360362483 ps
CPU time 109.55 seconds
Started Mar 17 12:34:34 PM PDT 24
Finished Mar 17 12:36:24 PM PDT 24
Peak memory 199952 kb
Host smart-da0f3b63-3040-4867-8aa7-a780b3930a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101900689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4101900689
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4102909291
Short name T409
Test name
Test status
Simulation time 773377486 ps
CPU time 1.62 seconds
Started Mar 17 12:34:33 PM PDT 24
Finished Mar 17 12:34:35 PM PDT 24
Peak memory 198588 kb
Host smart-664352fd-55c9-4d42-a16e-4fde1fad5c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102909291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4102909291
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3300476754
Short name T387
Test name
Test status
Simulation time 27672718596 ps
CPU time 21.83 seconds
Started Mar 17 12:34:29 PM PDT 24
Finished Mar 17 12:34:51 PM PDT 24
Peak memory 198136 kb
Host smart-9101c0e8-2f76-450d-b141-de997150564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300476754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3300476754
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2053057668
Short name T722
Test name
Test status
Simulation time 108780968034 ps
CPU time 559.88 seconds
Started Mar 17 12:38:10 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 199952 kb
Host smart-2676a8c2-2a84-4da5-b245-0568d62ac520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053057668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2053057668
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.865371226
Short name T791
Test name
Test status
Simulation time 47341496295 ps
CPU time 24.02 seconds
Started Mar 17 12:38:09 PM PDT 24
Finished Mar 17 12:38:34 PM PDT 24
Peak memory 199848 kb
Host smart-5faeca1c-6ead-4225-91d5-4f634f62f094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865371226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.865371226
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3787298893
Short name T417
Test name
Test status
Simulation time 21173680297 ps
CPU time 35.34 seconds
Started Mar 17 12:38:07 PM PDT 24
Finished Mar 17 12:38:43 PM PDT 24
Peak memory 199996 kb
Host smart-0b5471d5-150f-4810-9051-b749200076b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787298893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3787298893
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3276012150
Short name T972
Test name
Test status
Simulation time 116243009578 ps
CPU time 174.29 seconds
Started Mar 17 12:38:11 PM PDT 24
Finished Mar 17 12:41:06 PM PDT 24
Peak memory 199964 kb
Host smart-74deefdb-5c9a-4917-8062-c0aef0f2da17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276012150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3276012150
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.183570911
Short name T915
Test name
Test status
Simulation time 22832467387 ps
CPU time 34.64 seconds
Started Mar 17 12:38:10 PM PDT 24
Finished Mar 17 12:38:44 PM PDT 24
Peak memory 200000 kb
Host smart-1d23201b-2585-42b8-acf7-216c134a0c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183570911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.183570911
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1902934075
Short name T222
Test name
Test status
Simulation time 86156292088 ps
CPU time 74.16 seconds
Started Mar 17 12:38:09 PM PDT 24
Finished Mar 17 12:39:24 PM PDT 24
Peak memory 199976 kb
Host smart-e9920dd9-9b26-4cbf-b0a0-da402d02d98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902934075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1902934075
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2866652592
Short name T135
Test name
Test status
Simulation time 54113742453 ps
CPU time 79.21 seconds
Started Mar 17 12:38:11 PM PDT 24
Finished Mar 17 12:39:31 PM PDT 24
Peak memory 199996 kb
Host smart-3ee67d4a-a918-496f-96ae-5ab06de86dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866652592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2866652592
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2744273842
Short name T956
Test name
Test status
Simulation time 26858260365 ps
CPU time 29.62 seconds
Started Mar 17 12:38:09 PM PDT 24
Finished Mar 17 12:38:39 PM PDT 24
Peak memory 199944 kb
Host smart-ee33e193-1728-48f5-91e5-fb622c49a2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744273842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2744273842
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3191413349
Short name T550
Test name
Test status
Simulation time 48633985 ps
CPU time 0.55 seconds
Started Mar 17 12:34:46 PM PDT 24
Finished Mar 17 12:34:47 PM PDT 24
Peak memory 195500 kb
Host smart-20ed3def-3162-4839-aed0-f1c28e167406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191413349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3191413349
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.4182129474
Short name T41
Test name
Test status
Simulation time 34741607843 ps
CPU time 51.97 seconds
Started Mar 17 12:34:34 PM PDT 24
Finished Mar 17 12:35:26 PM PDT 24
Peak memory 199972 kb
Host smart-86907f05-e6be-4d8f-9053-1a5e889c26dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182129474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4182129474
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2522780141
Short name T597
Test name
Test status
Simulation time 50342849446 ps
CPU time 81.13 seconds
Started Mar 17 12:34:33 PM PDT 24
Finished Mar 17 12:35:55 PM PDT 24
Peak memory 199924 kb
Host smart-415f0082-9eeb-4715-92cd-aa3f65a6cc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522780141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2522780141
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.4216335732
Short name T194
Test name
Test status
Simulation time 20875338692 ps
CPU time 35.34 seconds
Started Mar 17 12:34:34 PM PDT 24
Finished Mar 17 12:35:10 PM PDT 24
Peak memory 200036 kb
Host smart-cf94af23-9e9d-48ce-bd5a-b91c32471880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216335732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.4216335732
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2093132646
Short name T365
Test name
Test status
Simulation time 14396369367 ps
CPU time 10.96 seconds
Started Mar 17 12:34:37 PM PDT 24
Finished Mar 17 12:34:48 PM PDT 24
Peak memory 200004 kb
Host smart-c9a06094-a770-4032-93e2-131bc0b4046f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093132646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2093132646
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4002838072
Short name T1068
Test name
Test status
Simulation time 154049775524 ps
CPU time 461.26 seconds
Started Mar 17 12:34:42 PM PDT 24
Finished Mar 17 12:42:23 PM PDT 24
Peak memory 200008 kb
Host smart-36295c15-0d43-4546-9709-204a3c6acd65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002838072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4002838072
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.769947561
Short name T1089
Test name
Test status
Simulation time 4067490648 ps
CPU time 7.45 seconds
Started Mar 17 12:34:42 PM PDT 24
Finished Mar 17 12:34:50 PM PDT 24
Peak memory 198356 kb
Host smart-f981aa7e-ad1c-4e76-9903-f97ef3a2c820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769947561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.769947561
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2789084959
Short name T376
Test name
Test status
Simulation time 149098977417 ps
CPU time 62.33 seconds
Started Mar 17 12:34:37 PM PDT 24
Finished Mar 17 12:35:39 PM PDT 24
Peak memory 199000 kb
Host smart-2a3162b8-a497-444c-a937-8a8e1fa48444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789084959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2789084959
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.4058613192
Short name T379
Test name
Test status
Simulation time 4177385854 ps
CPU time 9.83 seconds
Started Mar 17 12:34:33 PM PDT 24
Finished Mar 17 12:34:43 PM PDT 24
Peak memory 198864 kb
Host smart-2888b36e-0f6c-4abf-ac5b-09151e2b17a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058613192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4058613192
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1723793855
Short name T179
Test name
Test status
Simulation time 166825230789 ps
CPU time 94.5 seconds
Started Mar 17 12:34:45 PM PDT 24
Finished Mar 17 12:36:20 PM PDT 24
Peak memory 200240 kb
Host smart-ec47c19b-1ea6-4b8a-90e5-a745ec1b45de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723793855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1723793855
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2390259955
Short name T450
Test name
Test status
Simulation time 2390978428 ps
CPU time 4.04 seconds
Started Mar 17 12:34:40 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 196088 kb
Host smart-c52ddc96-3ee2-48f7-a11a-cf18861851b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390259955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2390259955
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.318468058
Short name T817
Test name
Test status
Simulation time 579801119 ps
CPU time 2 seconds
Started Mar 17 12:34:33 PM PDT 24
Finished Mar 17 12:34:35 PM PDT 24
Peak memory 198816 kb
Host smart-a0a282cc-80a6-4e04-bd34-8fa2d9eb2b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318468058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.318468058
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.327169800
Short name T959
Test name
Test status
Simulation time 400631260483 ps
CPU time 179.67 seconds
Started Mar 17 12:34:44 PM PDT 24
Finished Mar 17 12:37:43 PM PDT 24
Peak memory 200008 kb
Host smart-b0bee13c-eb6b-4c5c-b563-27b6e88104b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327169800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.327169800
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.4285469570
Short name T276
Test name
Test status
Simulation time 11529346099 ps
CPU time 4.21 seconds
Started Mar 17 12:34:43 PM PDT 24
Finished Mar 17 12:34:48 PM PDT 24
Peak memory 199820 kb
Host smart-65626427-9217-4673-bf9e-8b2ecd697d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285469570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4285469570
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2883685952
Short name T951
Test name
Test status
Simulation time 184106827738 ps
CPU time 69.42 seconds
Started Mar 17 12:34:34 PM PDT 24
Finished Mar 17 12:35:44 PM PDT 24
Peak memory 200052 kb
Host smart-6a9fe6ee-eea8-4869-85fb-94e2319f9d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883685952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2883685952
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3284793019
Short name T415
Test name
Test status
Simulation time 31489786529 ps
CPU time 58.71 seconds
Started Mar 17 12:38:16 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 200144 kb
Host smart-1ed76bac-b9cc-4d56-927a-1d79ab6ba528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284793019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3284793019
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3179431683
Short name T199
Test name
Test status
Simulation time 135851088386 ps
CPU time 21.25 seconds
Started Mar 17 12:38:20 PM PDT 24
Finished Mar 17 12:38:42 PM PDT 24
Peak memory 200004 kb
Host smart-7db8d652-3fab-4ba3-be80-17592cb116ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179431683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3179431683
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2460368133
Short name T325
Test name
Test status
Simulation time 48444497561 ps
CPU time 87.16 seconds
Started Mar 17 12:38:19 PM PDT 24
Finished Mar 17 12:39:46 PM PDT 24
Peak memory 199968 kb
Host smart-df9ba30f-c3fd-4c73-a4d1-1cc468bb6098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460368133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2460368133
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1984331316
Short name T1042
Test name
Test status
Simulation time 158688641122 ps
CPU time 118.89 seconds
Started Mar 17 12:38:17 PM PDT 24
Finished Mar 17 12:40:16 PM PDT 24
Peak memory 200020 kb
Host smart-219aa154-1c40-4672-9212-619b5269a15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984331316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1984331316
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.4294177698
Short name T1077
Test name
Test status
Simulation time 102885845444 ps
CPU time 189.38 seconds
Started Mar 17 12:38:18 PM PDT 24
Finished Mar 17 12:41:28 PM PDT 24
Peak memory 199956 kb
Host smart-46e12586-4d99-446c-99a2-48d244dd723b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294177698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.4294177698
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.4020095517
Short name T212
Test name
Test status
Simulation time 108340365976 ps
CPU time 48.56 seconds
Started Mar 17 12:38:17 PM PDT 24
Finished Mar 17 12:39:06 PM PDT 24
Peak memory 199912 kb
Host smart-de3cb9cc-dce9-4503-8298-4aa5a6235448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020095517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.4020095517
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1699553809
Short name T572
Test name
Test status
Simulation time 83086355990 ps
CPU time 75.93 seconds
Started Mar 17 12:38:16 PM PDT 24
Finished Mar 17 12:39:32 PM PDT 24
Peak memory 199960 kb
Host smart-076987b5-c636-41f0-85fc-26d45cf01234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699553809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1699553809
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4054562457
Short name T920
Test name
Test status
Simulation time 68549383089 ps
CPU time 81.1 seconds
Started Mar 17 12:38:19 PM PDT 24
Finished Mar 17 12:39:40 PM PDT 24
Peak memory 199880 kb
Host smart-07badf97-67fb-4af9-ba89-645a3fcc5dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054562457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4054562457
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1643890943
Short name T462
Test name
Test status
Simulation time 24664330232 ps
CPU time 13.85 seconds
Started Mar 17 12:38:19 PM PDT 24
Finished Mar 17 12:38:33 PM PDT 24
Peak memory 199944 kb
Host smart-55f36579-eeae-49d1-979c-480b6ca06a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643890943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1643890943
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1670076653
Short name T703
Test name
Test status
Simulation time 13269429 ps
CPU time 0.55 seconds
Started Mar 17 12:34:47 PM PDT 24
Finished Mar 17 12:34:48 PM PDT 24
Peak memory 195524 kb
Host smart-602a2570-6403-4062-9828-2d9b063f50cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670076653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1670076653
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2153087029
Short name T167
Test name
Test status
Simulation time 92648850573 ps
CPU time 89.83 seconds
Started Mar 17 12:34:42 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 199992 kb
Host smart-625a728a-782f-4c20-b90c-9c99dbedc40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153087029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2153087029
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3693389830
Short name T1108
Test name
Test status
Simulation time 20377970572 ps
CPU time 33.64 seconds
Started Mar 17 12:34:44 PM PDT 24
Finished Mar 17 12:35:17 PM PDT 24
Peak memory 199856 kb
Host smart-3c492367-e7a5-4b1e-8eee-f16ec24454f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693389830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3693389830
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.485501721
Short name T782
Test name
Test status
Simulation time 23841972243 ps
CPU time 41.47 seconds
Started Mar 17 12:34:46 PM PDT 24
Finished Mar 17 12:35:27 PM PDT 24
Peak memory 197696 kb
Host smart-f0c03bc3-af40-42e6-8606-4e737f317397
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485501721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.485501721
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1378238771
Short name T993
Test name
Test status
Simulation time 145715856549 ps
CPU time 133.27 seconds
Started Mar 17 12:34:50 PM PDT 24
Finished Mar 17 12:37:03 PM PDT 24
Peak memory 200036 kb
Host smart-31bf9006-2c05-4911-9b24-e5204d66b399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378238771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1378238771
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2085192423
Short name T838
Test name
Test status
Simulation time 8858857574 ps
CPU time 9.23 seconds
Started Mar 17 12:34:51 PM PDT 24
Finished Mar 17 12:35:01 PM PDT 24
Peak memory 199388 kb
Host smart-ed533425-def9-4c2b-ba09-9eda26b1e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085192423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2085192423
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2230179160
Short name T343
Test name
Test status
Simulation time 67783129221 ps
CPU time 47.97 seconds
Started Mar 17 12:34:41 PM PDT 24
Finished Mar 17 12:35:29 PM PDT 24
Peak memory 200044 kb
Host smart-6e6f71ba-181f-4d37-855f-5d3598fec06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230179160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2230179160
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2347915092
Short name T512
Test name
Test status
Simulation time 20846871051 ps
CPU time 314.24 seconds
Started Mar 17 12:34:49 PM PDT 24
Finished Mar 17 12:40:03 PM PDT 24
Peak memory 200020 kb
Host smart-1f959a4a-075d-4a0a-b9ca-ca9fb3d15e9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347915092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2347915092
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.703929031
Short name T1055
Test name
Test status
Simulation time 6976153176 ps
CPU time 41.58 seconds
Started Mar 17 12:34:44 PM PDT 24
Finished Mar 17 12:35:25 PM PDT 24
Peak memory 198280 kb
Host smart-32f14db2-ea15-45db-b5b8-7a32159e0e38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703929031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.703929031
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3759694082
Short name T873
Test name
Test status
Simulation time 46108141389 ps
CPU time 23.41 seconds
Started Mar 17 12:34:45 PM PDT 24
Finished Mar 17 12:35:08 PM PDT 24
Peak memory 200032 kb
Host smart-397d7a39-64c4-435e-a541-6d4c1b020059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759694082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3759694082
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1813181516
Short name T487
Test name
Test status
Simulation time 3038590185 ps
CPU time 2.97 seconds
Started Mar 17 12:34:44 PM PDT 24
Finished Mar 17 12:34:48 PM PDT 24
Peak memory 196036 kb
Host smart-8d99d9ee-851d-4b28-b0d4-079fba211e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813181516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1813181516
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1990693573
Short name T926
Test name
Test status
Simulation time 5813718340 ps
CPU time 21.01 seconds
Started Mar 17 12:34:44 PM PDT 24
Finished Mar 17 12:35:05 PM PDT 24
Peak memory 199708 kb
Host smart-3c11d5b9-4014-4b37-9754-5efed12751d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990693573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1990693573
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.575079220
Short name T584
Test name
Test status
Simulation time 267001019661 ps
CPU time 116.89 seconds
Started Mar 17 12:34:52 PM PDT 24
Finished Mar 17 12:36:49 PM PDT 24
Peak memory 208232 kb
Host smart-37396a28-eaff-41f8-90b8-03d276b267a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575079220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.575079220
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3621759728
Short name T310
Test name
Test status
Simulation time 747847603 ps
CPU time 2.31 seconds
Started Mar 17 12:34:41 PM PDT 24
Finished Mar 17 12:34:44 PM PDT 24
Peak memory 198380 kb
Host smart-108e33df-bf49-411f-8d64-557002625c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621759728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3621759728
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4030552374
Short name T836
Test name
Test status
Simulation time 67063214919 ps
CPU time 119.31 seconds
Started Mar 17 12:34:43 PM PDT 24
Finished Mar 17 12:36:42 PM PDT 24
Peak memory 199944 kb
Host smart-18ba81ce-e52a-469b-acd4-b5eaae7519f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030552374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4030552374
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1362687219
Short name T706
Test name
Test status
Simulation time 105695405552 ps
CPU time 48.23 seconds
Started Mar 17 12:38:20 PM PDT 24
Finished Mar 17 12:39:08 PM PDT 24
Peak memory 199896 kb
Host smart-e659e1cf-d00f-4313-aa06-2ef50a594fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362687219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1362687219
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3310498735
Short name T686
Test name
Test status
Simulation time 65114933986 ps
CPU time 57.79 seconds
Started Mar 17 12:38:16 PM PDT 24
Finished Mar 17 12:39:14 PM PDT 24
Peak memory 200060 kb
Host smart-67430e7b-11f2-433d-9c3c-8d2005bc4f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310498735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3310498735
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1894930722
Short name T602
Test name
Test status
Simulation time 7961446743 ps
CPU time 15.65 seconds
Started Mar 17 12:38:18 PM PDT 24
Finished Mar 17 12:38:34 PM PDT 24
Peak memory 199892 kb
Host smart-529aea6b-e0ab-4f9b-8488-a13155097e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894930722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1894930722
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2808232363
Short name T454
Test name
Test status
Simulation time 41945849831 ps
CPU time 18.95 seconds
Started Mar 17 12:38:16 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 199880 kb
Host smart-499643f5-156e-4d9f-9708-747a68423705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808232363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2808232363
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.864057534
Short name T511
Test name
Test status
Simulation time 185074680111 ps
CPU time 83.46 seconds
Started Mar 17 12:38:20 PM PDT 24
Finished Mar 17 12:39:44 PM PDT 24
Peak memory 199380 kb
Host smart-b7662199-68db-417a-b531-46ada0995e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864057534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.864057534
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.4195829147
Short name T928
Test name
Test status
Simulation time 76257367958 ps
CPU time 21.01 seconds
Started Mar 17 12:38:15 PM PDT 24
Finished Mar 17 12:38:36 PM PDT 24
Peak memory 200008 kb
Host smart-a621d597-75c5-4de6-9a51-e64f26229676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195829147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4195829147
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2673332712
Short name T839
Test name
Test status
Simulation time 24574326221 ps
CPU time 42.81 seconds
Started Mar 17 12:38:17 PM PDT 24
Finished Mar 17 12:39:00 PM PDT 24
Peak memory 200004 kb
Host smart-4b615974-c31c-4469-a6f3-04537522a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673332712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2673332712
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.764879245
Short name T531
Test name
Test status
Simulation time 52477977354 ps
CPU time 16.43 seconds
Started Mar 17 12:38:14 PM PDT 24
Finished Mar 17 12:38:31 PM PDT 24
Peak memory 200040 kb
Host smart-542b833e-e326-44d1-93fb-e3a478dc8586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764879245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.764879245
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.115272158
Short name T1106
Test name
Test status
Simulation time 37167650271 ps
CPU time 28.77 seconds
Started Mar 17 12:38:15 PM PDT 24
Finished Mar 17 12:38:44 PM PDT 24
Peak memory 199856 kb
Host smart-a0c054c4-b56e-41c7-9920-1457364a60e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115272158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.115272158
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1261836197
Short name T548
Test name
Test status
Simulation time 49121678 ps
CPU time 0.54 seconds
Started Mar 17 12:34:49 PM PDT 24
Finished Mar 17 12:34:49 PM PDT 24
Peak memory 195440 kb
Host smart-ddef0aee-f55c-4e5b-9938-7e95c801cf9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261836197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1261836197
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3327846862
Short name T175
Test name
Test status
Simulation time 30964843820 ps
CPU time 22.72 seconds
Started Mar 17 12:34:56 PM PDT 24
Finished Mar 17 12:35:18 PM PDT 24
Peak memory 199944 kb
Host smart-d1ecfa65-a2f8-4d7f-a97f-0e67a04ef6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327846862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3327846862
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2328650242
Short name T300
Test name
Test status
Simulation time 60095076495 ps
CPU time 27.37 seconds
Started Mar 17 12:34:54 PM PDT 24
Finished Mar 17 12:35:21 PM PDT 24
Peak memory 200132 kb
Host smart-5e615f73-685e-4e5a-82b1-5174d583f092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328650242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2328650242
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.499181253
Short name T166
Test name
Test status
Simulation time 140716734497 ps
CPU time 41.76 seconds
Started Mar 17 12:34:52 PM PDT 24
Finished Mar 17 12:35:34 PM PDT 24
Peak memory 199860 kb
Host smart-f9efb805-0a67-4934-be7e-0ea410f148f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499181253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.499181253
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1430383816
Short name T863
Test name
Test status
Simulation time 27941246936 ps
CPU time 45.72 seconds
Started Mar 17 12:34:51 PM PDT 24
Finished Mar 17 12:35:38 PM PDT 24
Peak memory 199032 kb
Host smart-74cba6e4-aad0-4372-9a81-1c1c41fed281
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430383816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1430383816
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3206554838
Short name T719
Test name
Test status
Simulation time 56412594269 ps
CPU time 83.35 seconds
Started Mar 17 12:34:49 PM PDT 24
Finished Mar 17 12:36:13 PM PDT 24
Peak memory 199964 kb
Host smart-4422ea44-caa2-496e-b378-ef6f89ea4811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3206554838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3206554838
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.669324057
Short name T732
Test name
Test status
Simulation time 3398107683 ps
CPU time 5.35 seconds
Started Mar 17 12:34:53 PM PDT 24
Finished Mar 17 12:34:58 PM PDT 24
Peak memory 199176 kb
Host smart-77be74dd-7de3-440f-a03d-9a80a5c7b672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669324057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.669324057
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.1606096566
Short name T877
Test name
Test status
Simulation time 13279490830 ps
CPU time 742.16 seconds
Started Mar 17 12:34:54 PM PDT 24
Finished Mar 17 12:47:17 PM PDT 24
Peak memory 199988 kb
Host smart-36134922-10c4-4c61-9c45-16ccf7700883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606096566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1606096566
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2820481494
Short name T14
Test name
Test status
Simulation time 7317774744 ps
CPU time 31.35 seconds
Started Mar 17 12:34:49 PM PDT 24
Finished Mar 17 12:35:20 PM PDT 24
Peak memory 199956 kb
Host smart-be58ff76-c7cd-4fc6-8359-3e7c308c0a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2820481494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2820481494
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1773792852
Short name T814
Test name
Test status
Simulation time 222351853044 ps
CPU time 101.04 seconds
Started Mar 17 12:34:54 PM PDT 24
Finished Mar 17 12:36:36 PM PDT 24
Peak memory 199568 kb
Host smart-ab6ce195-7a99-4cd0-b64a-75140997f485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773792852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1773792852
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3120211511
Short name T519
Test name
Test status
Simulation time 5505664527 ps
CPU time 1.97 seconds
Started Mar 17 12:34:50 PM PDT 24
Finished Mar 17 12:34:54 PM PDT 24
Peak memory 196040 kb
Host smart-29773081-dd4d-4f2c-8e35-e1df0b8fc8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120211511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3120211511
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2065904644
Short name T770
Test name
Test status
Simulation time 690554015 ps
CPU time 2.64 seconds
Started Mar 17 12:34:50 PM PDT 24
Finished Mar 17 12:34:55 PM PDT 24
Peak memory 198268 kb
Host smart-3d196786-df62-47fe-9c90-4b5b912509fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065904644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2065904644
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.816378503
Short name T374
Test name
Test status
Simulation time 210739760229 ps
CPU time 247.71 seconds
Started Mar 17 12:34:49 PM PDT 24
Finished Mar 17 12:38:57 PM PDT 24
Peak memory 200012 kb
Host smart-bd87092b-325d-4b59-87b9-d6a5b7b480bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816378503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.816378503
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1693709057
Short name T631
Test name
Test status
Simulation time 495915126 ps
CPU time 1.79 seconds
Started Mar 17 12:34:49 PM PDT 24
Finished Mar 17 12:34:51 PM PDT 24
Peak memory 198392 kb
Host smart-26b11e8c-4429-424e-8ed3-a2c740feec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693709057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1693709057
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.967479376
Short name T658
Test name
Test status
Simulation time 10114425059 ps
CPU time 17.42 seconds
Started Mar 17 12:34:55 PM PDT 24
Finished Mar 17 12:35:13 PM PDT 24
Peak memory 199944 kb
Host smart-999b5567-dccd-44fe-9d81-e5f900dd0a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967479376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.967479376
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1462866422
Short name T1105
Test name
Test status
Simulation time 15616019274 ps
CPU time 14.59 seconds
Started Mar 17 12:38:22 PM PDT 24
Finished Mar 17 12:38:37 PM PDT 24
Peak memory 199952 kb
Host smart-06cac925-2aa7-4568-90b0-c7b256a0e957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462866422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1462866422
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2170722331
Short name T515
Test name
Test status
Simulation time 75094073409 ps
CPU time 29.5 seconds
Started Mar 17 12:38:19 PM PDT 24
Finished Mar 17 12:38:49 PM PDT 24
Peak memory 199852 kb
Host smart-f414d866-78a0-4b81-8092-517de4f47ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170722331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2170722331
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.454073396
Short name T1022
Test name
Test status
Simulation time 30410701555 ps
CPU time 64.82 seconds
Started Mar 17 12:38:15 PM PDT 24
Finished Mar 17 12:39:20 PM PDT 24
Peak memory 200044 kb
Host smart-56a460ed-afde-45e4-95ad-48200fb25f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454073396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.454073396
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.4037372251
Short name T391
Test name
Test status
Simulation time 19006710331 ps
CPU time 16.86 seconds
Started Mar 17 12:38:18 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 199776 kb
Host smart-d4ca7968-91cd-4d1c-9fd6-149857f4e9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037372251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.4037372251
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.850402559
Short name T5
Test name
Test status
Simulation time 47504137524 ps
CPU time 23.03 seconds
Started Mar 17 12:38:15 PM PDT 24
Finished Mar 17 12:38:38 PM PDT 24
Peak memory 199884 kb
Host smart-9f52ba06-3844-460c-b577-be81fb16d28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850402559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.850402559
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1996254553
Short name T944
Test name
Test status
Simulation time 87404899565 ps
CPU time 26.52 seconds
Started Mar 17 12:38:17 PM PDT 24
Finished Mar 17 12:38:44 PM PDT 24
Peak memory 200248 kb
Host smart-9ed42f3f-e238-4454-8ed1-03413573d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996254553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1996254553
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4236106356
Short name T769
Test name
Test status
Simulation time 31421664277 ps
CPU time 12.42 seconds
Started Mar 17 12:38:19 PM PDT 24
Finished Mar 17 12:38:32 PM PDT 24
Peak memory 199980 kb
Host smart-2503b477-fcfb-4317-9b95-e753189f90f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236106356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4236106356
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2324079687
Short name T737
Test name
Test status
Simulation time 92390317854 ps
CPU time 37.15 seconds
Started Mar 17 12:38:16 PM PDT 24
Finished Mar 17 12:38:54 PM PDT 24
Peak memory 200008 kb
Host smart-122dd08c-f76e-44ec-8cb5-9e566aed7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324079687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2324079687
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1767558670
Short name T566
Test name
Test status
Simulation time 20433124 ps
CPU time 0.55 seconds
Started Mar 17 12:34:55 PM PDT 24
Finished Mar 17 12:34:56 PM PDT 24
Peak memory 194464 kb
Host smart-969c10c6-6ed6-4e12-ae20-b0f1392b6f18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767558670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1767558670
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1207167884
Short name T250
Test name
Test status
Simulation time 99438541151 ps
CPU time 28.19 seconds
Started Mar 17 12:34:49 PM PDT 24
Finished Mar 17 12:35:17 PM PDT 24
Peak memory 200036 kb
Host smart-dd435c57-44ff-495f-86f8-c6f2575ff4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207167884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1207167884
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3813825525
Short name T823
Test name
Test status
Simulation time 135590804235 ps
CPU time 35.66 seconds
Started Mar 17 12:34:55 PM PDT 24
Finished Mar 17 12:35:31 PM PDT 24
Peak memory 199784 kb
Host smart-faaf8923-6c55-4c0c-87d2-39f092e0d2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813825525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3813825525
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4210861857
Short name T906
Test name
Test status
Simulation time 14908556808 ps
CPU time 32.1 seconds
Started Mar 17 12:34:54 PM PDT 24
Finished Mar 17 12:35:26 PM PDT 24
Peak memory 199936 kb
Host smart-e2bd5f1a-be68-4103-856e-ff238c66d290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210861857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4210861857
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.871314949
Short name T1057
Test name
Test status
Simulation time 235973076725 ps
CPU time 44.77 seconds
Started Mar 17 12:34:52 PM PDT 24
Finished Mar 17 12:35:37 PM PDT 24
Peak memory 199948 kb
Host smart-825989f8-26fc-4374-ad9e-a7b02aa7b177
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871314949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.871314949
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.999079107
Short name T797
Test name
Test status
Simulation time 94238841608 ps
CPU time 202.48 seconds
Started Mar 17 12:34:55 PM PDT 24
Finished Mar 17 12:38:18 PM PDT 24
Peak memory 199996 kb
Host smart-07953821-3f77-4b3f-80ba-d418c2b351a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999079107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.999079107
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2492682661
Short name T352
Test name
Test status
Simulation time 2320190575 ps
CPU time 2.78 seconds
Started Mar 17 12:34:52 PM PDT 24
Finished Mar 17 12:34:55 PM PDT 24
Peak memory 196188 kb
Host smart-16d744b8-49ea-4d53-8439-3fff78722365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492682661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2492682661
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2816971575
Short name T907
Test name
Test status
Simulation time 325233262657 ps
CPU time 99.36 seconds
Started Mar 17 12:34:53 PM PDT 24
Finished Mar 17 12:36:32 PM PDT 24
Peak memory 200200 kb
Host smart-9e5a32d8-1e4d-44e4-84a7-6e0a0c665472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816971575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2816971575
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1510727889
Short name T437
Test name
Test status
Simulation time 14860212039 ps
CPU time 204.07 seconds
Started Mar 17 12:34:52 PM PDT 24
Finished Mar 17 12:38:16 PM PDT 24
Peak memory 199928 kb
Host smart-60d37d29-eb64-45bc-8fdf-c9df69a19df8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510727889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1510727889
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1615658373
Short name T1059
Test name
Test status
Simulation time 4346274185 ps
CPU time 8.1 seconds
Started Mar 17 12:34:51 PM PDT 24
Finished Mar 17 12:35:00 PM PDT 24
Peak memory 198568 kb
Host smart-5be0d5bb-ab93-42bf-82b9-ee94d29ab13b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615658373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1615658373
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1296806071
Short name T490
Test name
Test status
Simulation time 37046374880 ps
CPU time 57.83 seconds
Started Mar 17 12:34:54 PM PDT 24
Finished Mar 17 12:35:52 PM PDT 24
Peak memory 199952 kb
Host smart-fd95925e-8134-425f-b8b7-6dfea26b5745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296806071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1296806071
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3339047243
Short name T821
Test name
Test status
Simulation time 51196618618 ps
CPU time 84.17 seconds
Started Mar 17 12:34:50 PM PDT 24
Finished Mar 17 12:36:16 PM PDT 24
Peak memory 195804 kb
Host smart-4fa52403-1676-4424-a725-366c6d42dc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339047243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3339047243
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.872405865
Short name T558
Test name
Test status
Simulation time 6267975344 ps
CPU time 23.01 seconds
Started Mar 17 12:34:50 PM PDT 24
Finished Mar 17 12:35:15 PM PDT 24
Peak memory 199128 kb
Host smart-eb2bd9f8-8ae4-46a9-ab3a-e70c65cf148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872405865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.872405865
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2898482784
Short name T650
Test name
Test status
Simulation time 28448028128 ps
CPU time 467.38 seconds
Started Mar 17 12:34:53 PM PDT 24
Finished Mar 17 12:42:41 PM PDT 24
Peak memory 199444 kb
Host smart-1f48da2b-5142-4bcf-a656-1af9281a8682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898482784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2898482784
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1388198622
Short name T317
Test name
Test status
Simulation time 766009616 ps
CPU time 2.2 seconds
Started Mar 17 12:34:50 PM PDT 24
Finished Mar 17 12:34:54 PM PDT 24
Peak memory 198744 kb
Host smart-723dcd6b-c16f-4674-b154-f0157d124326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388198622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1388198622
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4239121991
Short name T955
Test name
Test status
Simulation time 114510344441 ps
CPU time 58.4 seconds
Started Mar 17 12:34:50 PM PDT 24
Finished Mar 17 12:35:50 PM PDT 24
Peak memory 199984 kb
Host smart-07a4b8ce-0c53-4d01-ac71-b90a22b0ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239121991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4239121991
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2393965036
Short name T727
Test name
Test status
Simulation time 99262326639 ps
CPU time 35.45 seconds
Started Mar 17 12:38:22 PM PDT 24
Finished Mar 17 12:38:58 PM PDT 24
Peak memory 200168 kb
Host smart-baf834fb-8bc4-4b6a-afd1-878b5e478c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393965036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2393965036
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3664425140
Short name T910
Test name
Test status
Simulation time 41990317079 ps
CPU time 66.53 seconds
Started Mar 17 12:38:23 PM PDT 24
Finished Mar 17 12:39:29 PM PDT 24
Peak memory 200048 kb
Host smart-5639ce42-bfcb-4aae-91a1-2262689aea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664425140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3664425140
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2915741743
Short name T1043
Test name
Test status
Simulation time 247580576776 ps
CPU time 86.62 seconds
Started Mar 17 12:38:23 PM PDT 24
Finished Mar 17 12:39:50 PM PDT 24
Peak memory 199828 kb
Host smart-35b0ab89-c261-44b9-9c65-0e4e7a706c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915741743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2915741743
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4126170992
Short name T518
Test name
Test status
Simulation time 92899223064 ps
CPU time 245.22 seconds
Started Mar 17 12:38:23 PM PDT 24
Finished Mar 17 12:42:28 PM PDT 24
Peak memory 200000 kb
Host smart-6c135dbe-8971-4d22-ab52-06cdea34461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126170992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4126170992
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.953591000
Short name T553
Test name
Test status
Simulation time 32006322059 ps
CPU time 50.83 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 200032 kb
Host smart-c630c9ba-144e-4902-9209-4b44602191a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953591000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.953591000
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1385646785
Short name T12
Test name
Test status
Simulation time 39577172750 ps
CPU time 32.44 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:38:57 PM PDT 24
Peak memory 200012 kb
Host smart-9623744b-e627-44b4-abe3-fd12f27d6b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385646785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1385646785
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3244029837
Short name T1067
Test name
Test status
Simulation time 140813511980 ps
CPU time 107.84 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:40:12 PM PDT 24
Peak memory 199980 kb
Host smart-db47fc1a-9e25-4f79-8afa-2000b8969dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244029837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3244029837
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1350169604
Short name T514
Test name
Test status
Simulation time 11455988 ps
CPU time 0.55 seconds
Started Mar 17 12:34:57 PM PDT 24
Finished Mar 17 12:34:58 PM PDT 24
Peak memory 195448 kb
Host smart-7c9fc1b0-eef6-4844-82bc-269a9bf376d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350169604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1350169604
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.608500278
Short name T1087
Test name
Test status
Simulation time 24026017279 ps
CPU time 27.6 seconds
Started Mar 17 12:34:58 PM PDT 24
Finished Mar 17 12:35:25 PM PDT 24
Peak memory 200024 kb
Host smart-f36f35a2-607d-42c8-b0a1-36e121bbb751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608500278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.608500278
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.947887072
Short name T888
Test name
Test status
Simulation time 33121076818 ps
CPU time 60.55 seconds
Started Mar 17 12:34:57 PM PDT 24
Finished Mar 17 12:35:57 PM PDT 24
Peak memory 199984 kb
Host smart-1aba70bd-2dcc-4013-99d4-97f0ce82102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947887072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.947887072
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.171759758
Short name T557
Test name
Test status
Simulation time 210397665342 ps
CPU time 150.52 seconds
Started Mar 17 12:34:56 PM PDT 24
Finished Mar 17 12:37:26 PM PDT 24
Peak memory 199972 kb
Host smart-a6751e21-57cd-42f5-b987-0b213984d548
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171759758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.171759758
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2884801775
Short name T609
Test name
Test status
Simulation time 158801321151 ps
CPU time 316.67 seconds
Started Mar 17 12:34:57 PM PDT 24
Finished Mar 17 12:40:13 PM PDT 24
Peak memory 200012 kb
Host smart-6d811be4-8d06-4cce-af5e-dd43b1fc96c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884801775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2884801775
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3486901374
Short name T521
Test name
Test status
Simulation time 6065766107 ps
CPU time 3.76 seconds
Started Mar 17 12:35:00 PM PDT 24
Finished Mar 17 12:35:04 PM PDT 24
Peak memory 198244 kb
Host smart-78aa11e1-864e-4ff8-9cdd-1eafb27a7eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486901374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3486901374
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.635864905
Short name T612
Test name
Test status
Simulation time 67408243354 ps
CPU time 117.68 seconds
Started Mar 17 12:34:56 PM PDT 24
Finished Mar 17 12:36:54 PM PDT 24
Peak memory 199704 kb
Host smart-824df69a-f317-44db-81a0-b5f23f4f7281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635864905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.635864905
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3569927663
Short name T1048
Test name
Test status
Simulation time 15605263423 ps
CPU time 206.75 seconds
Started Mar 17 12:34:56 PM PDT 24
Finished Mar 17 12:38:23 PM PDT 24
Peak memory 200044 kb
Host smart-92795add-4088-4aa3-9c36-b0abcf3e09d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569927663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3569927663
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2266590313
Short name T804
Test name
Test status
Simulation time 6730354434 ps
CPU time 15.96 seconds
Started Mar 17 12:35:00 PM PDT 24
Finished Mar 17 12:35:16 PM PDT 24
Peak memory 198080 kb
Host smart-07773f56-613e-4bcd-84a7-b2e4e546f02e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266590313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2266590313
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1067920567
Short name T832
Test name
Test status
Simulation time 51462110381 ps
CPU time 80.67 seconds
Started Mar 17 12:34:58 PM PDT 24
Finished Mar 17 12:36:19 PM PDT 24
Peak memory 200152 kb
Host smart-04b5c128-7749-4301-a499-63a7c829b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067920567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1067920567
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.297555331
Short name T567
Test name
Test status
Simulation time 3291129688 ps
CPU time 1.22 seconds
Started Mar 17 12:34:56 PM PDT 24
Finished Mar 17 12:34:57 PM PDT 24
Peak memory 196080 kb
Host smart-77ab6910-7c0c-408a-b9a9-df6ef5ca3bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297555331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.297555331
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.4069109935
Short name T1000
Test name
Test status
Simulation time 675714445 ps
CPU time 2.19 seconds
Started Mar 17 12:34:48 PM PDT 24
Finished Mar 17 12:34:50 PM PDT 24
Peak memory 199784 kb
Host smart-8968782b-45b2-40b0-92af-1c0a9b10ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069109935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4069109935
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2343330391
Short name T912
Test name
Test status
Simulation time 7231692046 ps
CPU time 5.41 seconds
Started Mar 17 12:34:59 PM PDT 24
Finished Mar 17 12:35:04 PM PDT 24
Peak memory 199784 kb
Host smart-4b047714-266e-4191-b2de-0372c0531faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343330391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2343330391
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.4088571789
Short name T683
Test name
Test status
Simulation time 107458957158 ps
CPU time 84.51 seconds
Started Mar 17 12:34:54 PM PDT 24
Finished Mar 17 12:36:19 PM PDT 24
Peak memory 200120 kb
Host smart-03fb4c2c-9da5-4669-8f0e-1c7fd24a5c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088571789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.4088571789
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.974370800
Short name T1019
Test name
Test status
Simulation time 98587693391 ps
CPU time 109.09 seconds
Started Mar 17 12:38:25 PM PDT 24
Finished Mar 17 12:40:15 PM PDT 24
Peak memory 199896 kb
Host smart-b29a3ff5-e6cc-4771-8e70-a2daefb42216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974370800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.974370800
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3156476926
Short name T938
Test name
Test status
Simulation time 95642457409 ps
CPU time 39.44 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:39:04 PM PDT 24
Peak memory 200012 kb
Host smart-25424b62-85e8-4633-992a-524991d3cd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156476926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3156476926
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3534716351
Short name T235
Test name
Test status
Simulation time 68470576660 ps
CPU time 20.73 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:38:44 PM PDT 24
Peak memory 199944 kb
Host smart-8be47ddb-f798-4251-8f2b-907e13c2ee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534716351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3534716351
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.19383930
Short name T852
Test name
Test status
Simulation time 63995822658 ps
CPU time 26.47 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:38:50 PM PDT 24
Peak memory 200024 kb
Host smart-e032c550-1b48-48f3-9462-77557abb37c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19383930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.19383930
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2455788536
Short name T446
Test name
Test status
Simulation time 98303664350 ps
CPU time 72.3 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:39:36 PM PDT 24
Peak memory 199924 kb
Host smart-cb7a77b9-daea-4110-a56d-51ffec76a4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455788536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2455788536
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3144026976
Short name T1027
Test name
Test status
Simulation time 23788758771 ps
CPU time 10.9 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 200136 kb
Host smart-b53811be-9118-4ecd-ad51-b4c528b16708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144026976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3144026976
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2828133456
Short name T918
Test name
Test status
Simulation time 95295031674 ps
CPU time 174.32 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:41:19 PM PDT 24
Peak memory 200012 kb
Host smart-2f5ab0fe-c2d4-4d99-8c22-6d444dded2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828133456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2828133456
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.658273482
Short name T213
Test name
Test status
Simulation time 32350470391 ps
CPU time 27.5 seconds
Started Mar 17 12:38:23 PM PDT 24
Finished Mar 17 12:38:51 PM PDT 24
Peak memory 199960 kb
Host smart-d9a2c580-61eb-4c8b-ac20-9961beeb4ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658273482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.658273482
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2728207002
Short name T978
Test name
Test status
Simulation time 113239405794 ps
CPU time 206.82 seconds
Started Mar 17 12:38:22 PM PDT 24
Finished Mar 17 12:41:49 PM PDT 24
Peak memory 199864 kb
Host smart-667b16ea-6808-4cff-8b8e-ea11c5eec53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728207002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2728207002
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.348144921
Short name T571
Test name
Test status
Simulation time 16792147039 ps
CPU time 37.68 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:39:02 PM PDT 24
Peak memory 199960 kb
Host smart-4110b452-0935-46dd-ab05-9437094bca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348144921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.348144921
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2299695731
Short name T905
Test name
Test status
Simulation time 20481560 ps
CPU time 0.57 seconds
Started Mar 17 12:35:04 PM PDT 24
Finished Mar 17 12:35:05 PM PDT 24
Peak memory 195460 kb
Host smart-fba695b4-97f9-47a5-a2e3-e45f316dfc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299695731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2299695731
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1559696892
Short name T427
Test name
Test status
Simulation time 90443366367 ps
CPU time 42.93 seconds
Started Mar 17 12:34:56 PM PDT 24
Finished Mar 17 12:35:39 PM PDT 24
Peak memory 200028 kb
Host smart-c1d7d110-09bd-422f-adc3-39bfd5a2d033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559696892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1559696892
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1200523546
Short name T689
Test name
Test status
Simulation time 106984582242 ps
CPU time 19.77 seconds
Started Mar 17 12:35:00 PM PDT 24
Finished Mar 17 12:35:20 PM PDT 24
Peak memory 199972 kb
Host smart-9d37fbce-2bf5-4a3b-8891-be0ecf3b3dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200523546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1200523546
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.21174877
Short name T495
Test name
Test status
Simulation time 8193763938 ps
CPU time 15.49 seconds
Started Mar 17 12:34:58 PM PDT 24
Finished Mar 17 12:35:13 PM PDT 24
Peak memory 199836 kb
Host smart-19adb592-fa4d-48e8-a12d-640fb82f6858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21174877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.21174877
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1959115935
Short name T1078
Test name
Test status
Simulation time 18763116096 ps
CPU time 28.43 seconds
Started Mar 17 12:34:58 PM PDT 24
Finished Mar 17 12:35:26 PM PDT 24
Peak memory 197208 kb
Host smart-7cf64d6f-9222-4156-acd3-84d15e348fa3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959115935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1959115935
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.688140965
Short name T523
Test name
Test status
Simulation time 117870591953 ps
CPU time 119.92 seconds
Started Mar 17 12:35:04 PM PDT 24
Finished Mar 17 12:37:04 PM PDT 24
Peak memory 199924 kb
Host smart-b2239a8c-87b5-43ef-a996-bfe30792e005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688140965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.688140965
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1466550704
Short name T1083
Test name
Test status
Simulation time 2566586173 ps
CPU time 1.91 seconds
Started Mar 17 12:35:05 PM PDT 24
Finished Mar 17 12:35:07 PM PDT 24
Peak memory 197464 kb
Host smart-fefec568-41b0-48ed-b255-926af5608958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466550704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1466550704
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2737616994
Short name T1064
Test name
Test status
Simulation time 33003688882 ps
CPU time 84.75 seconds
Started Mar 17 12:35:07 PM PDT 24
Finished Mar 17 12:36:31 PM PDT 24
Peak memory 200068 kb
Host smart-f908e27f-75be-41b5-8d35-4ad2008c94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737616994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2737616994
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.943713878
Short name T764
Test name
Test status
Simulation time 18078348298 ps
CPU time 524.98 seconds
Started Mar 17 12:35:10 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 200072 kb
Host smart-7510a179-c94f-4d06-897f-c70fd70bcd35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943713878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.943713878
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3202299556
Short name T980
Test name
Test status
Simulation time 2208757948 ps
CPU time 15.63 seconds
Started Mar 17 12:34:55 PM PDT 24
Finished Mar 17 12:35:11 PM PDT 24
Peak memory 198164 kb
Host smart-0984736f-3ff6-4569-84a6-f3a68bf1ed65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202299556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3202299556
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.999886961
Short name T1098
Test name
Test status
Simulation time 53922982661 ps
CPU time 25.11 seconds
Started Mar 17 12:35:06 PM PDT 24
Finished Mar 17 12:35:31 PM PDT 24
Peak memory 200060 kb
Host smart-25bdbebc-a39f-4971-8450-657178024cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999886961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.999886961
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.855546666
Short name T60
Test name
Test status
Simulation time 5435490135 ps
CPU time 4.99 seconds
Started Mar 17 12:35:07 PM PDT 24
Finished Mar 17 12:35:12 PM PDT 24
Peak memory 196328 kb
Host smart-1c6f4f7d-8646-4464-b354-f69addf969f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855546666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.855546666
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4132606850
Short name T634
Test name
Test status
Simulation time 901745662 ps
CPU time 2.34 seconds
Started Mar 17 12:34:58 PM PDT 24
Finished Mar 17 12:35:00 PM PDT 24
Peak memory 198420 kb
Host smart-2fc386ac-8bbb-4d7f-aa70-f6274931e5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132606850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4132606850
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1879710628
Short name T778
Test name
Test status
Simulation time 6201830108 ps
CPU time 22.91 seconds
Started Mar 17 12:35:06 PM PDT 24
Finished Mar 17 12:35:29 PM PDT 24
Peak memory 199944 kb
Host smart-fce430d3-dfbd-4c9a-a39e-8fd6e6154cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879710628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1879710628
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.829646663
Short name T538
Test name
Test status
Simulation time 28972270013 ps
CPU time 23.85 seconds
Started Mar 17 12:34:57 PM PDT 24
Finished Mar 17 12:35:21 PM PDT 24
Peak memory 199936 kb
Host smart-71c08514-f04e-4ec4-9822-4915f78c0e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829646663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.829646663
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.841691075
Short name T228
Test name
Test status
Simulation time 82537973586 ps
CPU time 40.36 seconds
Started Mar 17 12:38:24 PM PDT 24
Finished Mar 17 12:39:04 PM PDT 24
Peak memory 199948 kb
Host smart-61ee1f5d-d50f-41e9-8bd6-18882cf78c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841691075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.841691075
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3346694660
Short name T679
Test name
Test status
Simulation time 42827770634 ps
CPU time 16.45 seconds
Started Mar 17 12:38:32 PM PDT 24
Finished Mar 17 12:38:49 PM PDT 24
Peak memory 199884 kb
Host smart-73e6ff81-6f32-4892-abef-47f04560b18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346694660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3346694660
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3051113752
Short name T563
Test name
Test status
Simulation time 104651091169 ps
CPU time 163.12 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:41:14 PM PDT 24
Peak memory 199540 kb
Host smart-97bf868a-ff43-4815-b79e-7c59d2e13644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051113752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3051113752
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1712895243
Short name T1104
Test name
Test status
Simulation time 136484215984 ps
CPU time 190.01 seconds
Started Mar 17 12:38:30 PM PDT 24
Finished Mar 17 12:41:40 PM PDT 24
Peak memory 199960 kb
Host smart-4f2e37c7-85e1-4e97-95a1-4572ddcf7972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712895243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1712895243
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.54927332
Short name T296
Test name
Test status
Simulation time 128832646055 ps
CPU time 116.85 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:40:29 PM PDT 24
Peak memory 199932 kb
Host smart-e4f0cad0-6a45-414b-8b95-472af6ded53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54927332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.54927332
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3683463599
Short name T45
Test name
Test status
Simulation time 127409551061 ps
CPU time 55.47 seconds
Started Mar 17 12:38:32 PM PDT 24
Finished Mar 17 12:39:28 PM PDT 24
Peak memory 199988 kb
Host smart-5f95da2f-1d79-475f-b387-bf1bca82049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683463599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3683463599
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2288311859
Short name T500
Test name
Test status
Simulation time 31961745649 ps
CPU time 12.88 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:38:44 PM PDT 24
Peak memory 199928 kb
Host smart-4edbed05-5dda-4186-bcd3-5fce1a0a9691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288311859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2288311859
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2781154112
Short name T208
Test name
Test status
Simulation time 20370044851 ps
CPU time 44.26 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 199968 kb
Host smart-60ca378f-232f-4484-aab7-ffd189c2eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781154112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2781154112
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.930966888
Short name T422
Test name
Test status
Simulation time 24575740039 ps
CPU time 41.46 seconds
Started Mar 17 12:38:30 PM PDT 24
Finished Mar 17 12:39:11 PM PDT 24
Peak memory 199952 kb
Host smart-c64bb836-5265-490a-bdb6-2ba897ed38c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930966888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.930966888
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2706759740
Short name T184
Test name
Test status
Simulation time 55263340350 ps
CPU time 52.78 seconds
Started Mar 17 12:38:33 PM PDT 24
Finished Mar 17 12:39:26 PM PDT 24
Peak memory 199964 kb
Host smart-621e933f-609f-4b1c-9840-8bb5bcbb052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706759740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2706759740
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.735380186
Short name T400
Test name
Test status
Simulation time 41962904 ps
CPU time 0.53 seconds
Started Mar 17 12:35:09 PM PDT 24
Finished Mar 17 12:35:10 PM PDT 24
Peak memory 195488 kb
Host smart-e8750705-b760-43fe-9f34-ad1a5b8774d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735380186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.735380186
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.649737606
Short name T744
Test name
Test status
Simulation time 27270442486 ps
CPU time 12.39 seconds
Started Mar 17 12:35:07 PM PDT 24
Finished Mar 17 12:35:19 PM PDT 24
Peak memory 200004 kb
Host smart-210fe413-0df7-4c81-95a8-a5a7ba0497bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649737606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.649737606
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1615235348
Short name T97
Test name
Test status
Simulation time 244173095695 ps
CPU time 110.15 seconds
Started Mar 17 12:35:06 PM PDT 24
Finished Mar 17 12:36:56 PM PDT 24
Peak memory 199984 kb
Host smart-f2243a20-31f1-40f8-8ddc-5d9ce37a5eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615235348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1615235348
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3097575321
Short name T610
Test name
Test status
Simulation time 25701510223 ps
CPU time 47.71 seconds
Started Mar 17 12:35:06 PM PDT 24
Finished Mar 17 12:35:54 PM PDT 24
Peak memory 200040 kb
Host smart-744a0e89-8e3c-4a79-9491-befe427e9773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097575321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3097575321
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1785745247
Short name T868
Test name
Test status
Simulation time 71949008730 ps
CPU time 16.56 seconds
Started Mar 17 12:35:05 PM PDT 24
Finished Mar 17 12:35:22 PM PDT 24
Peak memory 199952 kb
Host smart-5486ce15-9ac2-46f1-85d8-cf907d59251e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785745247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1785745247
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2907775992
Short name T54
Test name
Test status
Simulation time 271634312338 ps
CPU time 993.74 seconds
Started Mar 17 12:35:07 PM PDT 24
Finished Mar 17 12:51:41 PM PDT 24
Peak memory 199976 kb
Host smart-858f14bb-fdc4-43bf-8842-ca2cbb72f70c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907775992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2907775992
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3046539601
Short name T353
Test name
Test status
Simulation time 3307096278 ps
CPU time 6.05 seconds
Started Mar 17 12:35:08 PM PDT 24
Finished Mar 17 12:35:14 PM PDT 24
Peak memory 196160 kb
Host smart-159afef2-1d7c-4b7e-8e34-1a0dfecb7962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046539601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3046539601
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1842943941
Short name T871
Test name
Test status
Simulation time 211880489089 ps
CPU time 232.79 seconds
Started Mar 17 12:35:06 PM PDT 24
Finished Mar 17 12:38:59 PM PDT 24
Peak memory 200000 kb
Host smart-f0fb2263-50a4-4e8b-a77e-2f8cf3f2df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842943941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1842943941
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2965633283
Short name T1082
Test name
Test status
Simulation time 14707071724 ps
CPU time 318.19 seconds
Started Mar 17 12:35:05 PM PDT 24
Finished Mar 17 12:40:23 PM PDT 24
Peak memory 200064 kb
Host smart-2774065c-9193-4e04-81be-e0b3dee75d26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965633283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2965633283
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2499690945
Short name T411
Test name
Test status
Simulation time 3965341868 ps
CPU time 24.72 seconds
Started Mar 17 12:35:05 PM PDT 24
Finished Mar 17 12:35:30 PM PDT 24
Peak memory 198920 kb
Host smart-f0222a8c-f806-4e43-8ea8-5da4b8922740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499690945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2499690945
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2160644569
Short name T292
Test name
Test status
Simulation time 43223107640 ps
CPU time 83.74 seconds
Started Mar 17 12:35:07 PM PDT 24
Finished Mar 17 12:36:31 PM PDT 24
Peak memory 200008 kb
Host smart-8a33c01e-4ee1-42d5-b2ef-82dc49287f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160644569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2160644569
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1413254473
Short name T368
Test name
Test status
Simulation time 3438454119 ps
CPU time 2.91 seconds
Started Mar 17 12:35:08 PM PDT 24
Finished Mar 17 12:35:11 PM PDT 24
Peak memory 196036 kb
Host smart-49b4a026-3a3c-4c15-95e9-7569e3b1e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413254473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1413254473
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.4022386205
Short name T268
Test name
Test status
Simulation time 5292141345 ps
CPU time 22.39 seconds
Started Mar 17 12:35:10 PM PDT 24
Finished Mar 17 12:35:32 PM PDT 24
Peak memory 199776 kb
Host smart-7feccb2f-e591-4a1f-9ceb-45e7223cab82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022386205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4022386205
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1394070321
Short name T661
Test name
Test status
Simulation time 251360289875 ps
CPU time 92.4 seconds
Started Mar 17 12:35:07 PM PDT 24
Finished Mar 17 12:36:39 PM PDT 24
Peak memory 200240 kb
Host smart-5f7935fb-7323-4f05-9d09-b343e369f098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394070321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1394070321
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1234044132
Short name T21
Test name
Test status
Simulation time 45329351556 ps
CPU time 245.63 seconds
Started Mar 17 12:35:10 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 213792 kb
Host smart-f218b3f4-644b-4bc1-9669-e1161176ffb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234044132 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1234044132
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2600030093
Short name T998
Test name
Test status
Simulation time 6643254833 ps
CPU time 35.87 seconds
Started Mar 17 12:35:07 PM PDT 24
Finished Mar 17 12:35:43 PM PDT 24
Peak memory 200036 kb
Host smart-44d60f62-6f44-4ac9-9141-2b244fff0ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600030093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2600030093
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1101396500
Short name T363
Test name
Test status
Simulation time 9526952996 ps
CPU time 9.23 seconds
Started Mar 17 12:35:05 PM PDT 24
Finished Mar 17 12:35:15 PM PDT 24
Peak memory 198520 kb
Host smart-7ddd293f-e36a-4def-8da7-9260d875673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101396500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1101396500
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.744642138
Short name T214
Test name
Test status
Simulation time 38305234684 ps
CPU time 31.04 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:39:02 PM PDT 24
Peak memory 199496 kb
Host smart-86474eef-e3ad-4937-a43a-9540c3630536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744642138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.744642138
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.572103762
Short name T312
Test name
Test status
Simulation time 190055330747 ps
CPU time 88.93 seconds
Started Mar 17 12:38:32 PM PDT 24
Finished Mar 17 12:40:01 PM PDT 24
Peak memory 200024 kb
Host smart-978ebaf2-02db-4f10-ad6b-ec111557adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572103762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.572103762
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.4101767695
Short name T1071
Test name
Test status
Simulation time 24145617890 ps
CPU time 19.1 seconds
Started Mar 17 12:38:33 PM PDT 24
Finished Mar 17 12:38:52 PM PDT 24
Peak memory 199984 kb
Host smart-f4ae7073-755a-4186-b5bc-968ffd33ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101767695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.4101767695
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2407629964
Short name T313
Test name
Test status
Simulation time 36795682093 ps
CPU time 28 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:38:59 PM PDT 24
Peak memory 199940 kb
Host smart-25438cd4-dbd3-44f3-8675-2e63c5eaf404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407629964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2407629964
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3172371285
Short name T486
Test name
Test status
Simulation time 98510719707 ps
CPU time 11.78 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:38:43 PM PDT 24
Peak memory 199996 kb
Host smart-2db6db18-37e6-4a94-92ad-e9bf45b25a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172371285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3172371285
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2191504651
Short name T219
Test name
Test status
Simulation time 126181957931 ps
CPU time 204.84 seconds
Started Mar 17 12:38:32 PM PDT 24
Finished Mar 17 12:41:57 PM PDT 24
Peak memory 200032 kb
Host smart-4c39f5c6-e593-4676-98ed-15ac2c3307c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191504651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2191504651
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1330835389
Short name T217
Test name
Test status
Simulation time 21562913178 ps
CPU time 14.88 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:38:46 PM PDT 24
Peak memory 198868 kb
Host smart-cb15e015-c6c8-42c0-af1b-9425588ceba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330835389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1330835389
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2142061483
Short name T202
Test name
Test status
Simulation time 108899706350 ps
CPU time 92.57 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:40:04 PM PDT 24
Peak memory 199980 kb
Host smart-75cfcbd7-38bc-46d2-9f23-fee19934ac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142061483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2142061483
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2605440309
Short name T794
Test name
Test status
Simulation time 110024023755 ps
CPU time 63.29 seconds
Started Mar 17 12:38:33 PM PDT 24
Finished Mar 17 12:39:37 PM PDT 24
Peak memory 200028 kb
Host smart-2020eac2-4ece-4ca0-8d4a-814c981afde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605440309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2605440309
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3824659579
Short name T520
Test name
Test status
Simulation time 26663365 ps
CPU time 0.55 seconds
Started Mar 17 12:35:15 PM PDT 24
Finished Mar 17 12:35:16 PM PDT 24
Peak memory 195404 kb
Host smart-1f15ade6-dc3b-47be-bb69-cb4e3759b24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824659579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3824659579
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1256812054
Short name T806
Test name
Test status
Simulation time 194963453821 ps
CPU time 116.02 seconds
Started Mar 17 12:35:13 PM PDT 24
Finished Mar 17 12:37:09 PM PDT 24
Peak memory 200040 kb
Host smart-88dd7811-3bfa-41ed-afea-b9c1214005e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256812054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1256812054
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.767128842
Short name T763
Test name
Test status
Simulation time 165200606313 ps
CPU time 324.13 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:40:36 PM PDT 24
Peak memory 199952 kb
Host smart-17918b03-50cb-4ffb-b98c-cb77d7060d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767128842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.767128842
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1362636875
Short name T187
Test name
Test status
Simulation time 19017794604 ps
CPU time 10.55 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:35:22 PM PDT 24
Peak memory 200028 kb
Host smart-9cbe1565-f24e-49d7-a8a6-8a5a80ee8e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362636875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1362636875
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1994507449
Short name T125
Test name
Test status
Simulation time 42793905789 ps
CPU time 73.56 seconds
Started Mar 17 12:35:11 PM PDT 24
Finished Mar 17 12:36:25 PM PDT 24
Peak memory 200032 kb
Host smart-715d4002-9684-438f-a60d-b32ef6c27f2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994507449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1994507449
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2205330079
Short name T587
Test name
Test status
Simulation time 48355515604 ps
CPU time 119.5 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:37:13 PM PDT 24
Peak memory 199948 kb
Host smart-b8cafef4-c8a3-42be-b6c3-0b6f1c154abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205330079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2205330079
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.353306572
Short name T983
Test name
Test status
Simulation time 8243636657 ps
CPU time 6.09 seconds
Started Mar 17 12:35:11 PM PDT 24
Finished Mar 17 12:35:17 PM PDT 24
Peak memory 198384 kb
Host smart-bb5e32e4-feb7-47f6-a8a8-70c031e8a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353306572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.353306572
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2752372512
Short name T456
Test name
Test status
Simulation time 225621611392 ps
CPU time 90.94 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:36:43 PM PDT 24
Peak memory 200468 kb
Host smart-d8278ff0-09de-447c-bb6b-9be269488abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752372512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2752372512
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1646063788
Short name T728
Test name
Test status
Simulation time 25530267136 ps
CPU time 962.11 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:51:15 PM PDT 24
Peak memory 199944 kb
Host smart-17c9826b-a3db-4acc-84aa-d4418ef62c2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646063788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1646063788
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3178442339
Short name T753
Test name
Test status
Simulation time 2661135790 ps
CPU time 19.46 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:35:49 PM PDT 24
Peak memory 199036 kb
Host smart-20673081-4338-4bfb-b8d9-f4a6f59bf8ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178442339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3178442339
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.761412164
Short name T408
Test name
Test status
Simulation time 18543930205 ps
CPU time 29.71 seconds
Started Mar 17 12:35:10 PM PDT 24
Finished Mar 17 12:35:40 PM PDT 24
Peak memory 200080 kb
Host smart-33c30225-a81b-4e52-ba6c-4f2cf540d309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761412164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.761412164
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2495721995
Short name T264
Test name
Test status
Simulation time 5612773291 ps
CPU time 2.78 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:35:16 PM PDT 24
Peak memory 196104 kb
Host smart-03c21fb1-36d5-4569-b2f8-145cc8a1ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495721995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2495721995
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3806628325
Short name T285
Test name
Test status
Simulation time 291344074 ps
CPU time 1.37 seconds
Started Mar 17 12:35:08 PM PDT 24
Finished Mar 17 12:35:10 PM PDT 24
Peak memory 198296 kb
Host smart-1b98e385-e160-4a7b-9fb1-41800afc49bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806628325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3806628325
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2719059254
Short name T849
Test name
Test status
Simulation time 189321153599 ps
CPU time 73.32 seconds
Started Mar 17 12:35:10 PM PDT 24
Finished Mar 17 12:36:24 PM PDT 24
Peak memory 200136 kb
Host smart-4c9e01a5-ce96-4c9f-9955-9151bb62c8af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719059254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2719059254
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3120531863
Short name T966
Test name
Test status
Simulation time 1669640465 ps
CPU time 2.66 seconds
Started Mar 17 12:35:13 PM PDT 24
Finished Mar 17 12:35:16 PM PDT 24
Peak memory 198312 kb
Host smart-5738d503-9800-4a90-bdf4-ea9be053dcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120531863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3120531863
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1776881963
Short name T579
Test name
Test status
Simulation time 13535646354 ps
CPU time 23.73 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:35:36 PM PDT 24
Peak memory 199964 kb
Host smart-788a2ba2-e790-4143-8e00-808469513d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776881963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1776881963
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3569057987
Short name T898
Test name
Test status
Simulation time 41220099094 ps
CPU time 86.03 seconds
Started Mar 17 12:38:30 PM PDT 24
Finished Mar 17 12:39:56 PM PDT 24
Peak memory 199984 kb
Host smart-701c3966-48c9-4f12-9544-4128179eaae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569057987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3569057987
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.595016176
Short name T708
Test name
Test status
Simulation time 11395593409 ps
CPU time 20.06 seconds
Started Mar 17 12:38:32 PM PDT 24
Finished Mar 17 12:38:52 PM PDT 24
Peak memory 200040 kb
Host smart-74b44097-13ae-487c-ab9f-2523662e460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595016176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.595016176
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.440678691
Short name T1056
Test name
Test status
Simulation time 128677212589 ps
CPU time 48.29 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:39:19 PM PDT 24
Peak memory 200132 kb
Host smart-9c657968-c359-4317-978e-bc47ea436874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440678691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.440678691
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.672641203
Short name T995
Test name
Test status
Simulation time 136955478886 ps
CPU time 222.58 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:42:14 PM PDT 24
Peak memory 200020 kb
Host smart-c43333d5-3605-4697-9d54-7c05f107c7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672641203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.672641203
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.421398802
Short name T1063
Test name
Test status
Simulation time 133468175519 ps
CPU time 53.79 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:39:25 PM PDT 24
Peak memory 199972 kb
Host smart-a4d91c53-3f95-4a0f-a5aa-039fa04f3aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421398802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.421398802
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2342715675
Short name T1091
Test name
Test status
Simulation time 143562200334 ps
CPU time 265.13 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 199920 kb
Host smart-19ad39d1-44fe-4de8-9eae-720cd48189cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342715675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2342715675
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3842364862
Short name T1003
Test name
Test status
Simulation time 38764928713 ps
CPU time 48.23 seconds
Started Mar 17 12:38:31 PM PDT 24
Finished Mar 17 12:39:19 PM PDT 24
Peak memory 199996 kb
Host smart-be2e6307-5579-45b1-9c19-457d14bd3559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842364862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3842364862
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1692917675
Short name T997
Test name
Test status
Simulation time 13977438 ps
CPU time 0.55 seconds
Started Mar 17 12:35:22 PM PDT 24
Finished Mar 17 12:35:23 PM PDT 24
Peak memory 195564 kb
Host smart-35ba7311-802e-4e27-828f-3df1b0e034e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692917675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1692917675
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4274690750
Short name T390
Test name
Test status
Simulation time 32006672352 ps
CPU time 71.39 seconds
Started Mar 17 12:35:13 PM PDT 24
Finished Mar 17 12:36:24 PM PDT 24
Peak memory 199856 kb
Host smart-eced258e-9e7a-489a-8e28-7a443e00d5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274690750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4274690750
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1899152784
Short name T748
Test name
Test status
Simulation time 42329229867 ps
CPU time 16.56 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:35:43 PM PDT 24
Peak memory 199668 kb
Host smart-e623945d-3725-4c63-95f7-71dbf30f198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899152784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1899152784
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3595926766
Short name T95
Test name
Test status
Simulation time 18081955649 ps
CPU time 30.91 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:35:58 PM PDT 24
Peak memory 197048 kb
Host smart-a79ba6b3-d983-49f9-9f8e-c4bf03261fbe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595926766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3595926766
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1467021998
Short name T996
Test name
Test status
Simulation time 85013673930 ps
CPU time 622.78 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:45:44 PM PDT 24
Peak memory 199976 kb
Host smart-9e78c210-bbef-491b-9667-c8fa9e76fce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467021998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1467021998
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1326873275
Short name T575
Test name
Test status
Simulation time 6143624381 ps
CPU time 11.12 seconds
Started Mar 17 12:35:22 PM PDT 24
Finished Mar 17 12:35:33 PM PDT 24
Peak memory 198376 kb
Host smart-acbba268-5884-460e-a191-5c4c4517dc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326873275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1326873275
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2923264558
Short name T277
Test name
Test status
Simulation time 58090663288 ps
CPU time 40.56 seconds
Started Mar 17 12:35:11 PM PDT 24
Finished Mar 17 12:35:52 PM PDT 24
Peak memory 198044 kb
Host smart-d82ff333-cce2-4812-ab4a-c8153e3a22d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923264558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2923264558
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3655307882
Short name T773
Test name
Test status
Simulation time 18078755529 ps
CPU time 229.82 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:39:11 PM PDT 24
Peak memory 200048 kb
Host smart-8cbfb74b-5f1d-4509-91a8-1c2eefbb6a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655307882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3655307882
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1431069946
Short name T870
Test name
Test status
Simulation time 7289463741 ps
CPU time 63.15 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:36:15 PM PDT 24
Peak memory 199264 kb
Host smart-8f18621a-aa80-4993-ac9f-ff6be8d72e86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1431069946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1431069946
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1826274880
Short name T971
Test name
Test status
Simulation time 98772236796 ps
CPU time 136.35 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:37:43 PM PDT 24
Peak memory 199728 kb
Host smart-41a6a9a4-8566-4473-a22c-518f83de6cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826274880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1826274880
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2015669109
Short name T586
Test name
Test status
Simulation time 47552804482 ps
CPU time 17.46 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:35:44 PM PDT 24
Peak memory 195956 kb
Host smart-21f59b1e-d855-4bf7-9480-fdec4d6a8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015669109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2015669109
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.579814468
Short name T529
Test name
Test status
Simulation time 96106282 ps
CPU time 0.74 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:35:28 PM PDT 24
Peak memory 196524 kb
Host smart-9e4d5eb6-2f0b-4aec-984d-841c2ed5ff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579814468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.579814468
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2016987799
Short name T589
Test name
Test status
Simulation time 251635276259 ps
CPU time 340.13 seconds
Started Mar 17 12:35:25 PM PDT 24
Finished Mar 17 12:41:05 PM PDT 24
Peak memory 200136 kb
Host smart-c70610e0-d5a9-4349-b6d8-d41d2b41e2e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016987799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2016987799
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.858665446
Short name T705
Test name
Test status
Simulation time 931108854 ps
CPU time 1.92 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:35:23 PM PDT 24
Peak memory 198564 kb
Host smart-d0e74bf0-b7fc-4f2b-806e-4649577f197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858665446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.858665446
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.354376685
Short name T546
Test name
Test status
Simulation time 26622228749 ps
CPU time 46.91 seconds
Started Mar 17 12:35:12 PM PDT 24
Finished Mar 17 12:35:59 PM PDT 24
Peak memory 200024 kb
Host smart-5c2ab8bb-b737-41f7-863b-cfc6ac5c9b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354376685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.354376685
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2226146267
Short name T862
Test name
Test status
Simulation time 18109020361 ps
CPU time 31.02 seconds
Started Mar 17 12:38:39 PM PDT 24
Finished Mar 17 12:39:12 PM PDT 24
Peak memory 200088 kb
Host smart-9e167d13-9ad3-4cf2-951b-2ac7d2346829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226146267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2226146267
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.4214958853
Short name T582
Test name
Test status
Simulation time 60878938179 ps
CPU time 35.8 seconds
Started Mar 17 12:38:41 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 200000 kb
Host smart-12641a94-ddcf-4866-ac05-029fa4a64266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214958853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4214958853
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1787131866
Short name T215
Test name
Test status
Simulation time 94224645395 ps
CPU time 126.89 seconds
Started Mar 17 12:38:40 PM PDT 24
Finished Mar 17 12:40:48 PM PDT 24
Peak memory 200080 kb
Host smart-2635ae2a-6cf4-40bb-9aad-b573562ab07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787131866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1787131866
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.4064457913
Short name T932
Test name
Test status
Simulation time 129594629091 ps
CPU time 129.28 seconds
Started Mar 17 12:38:41 PM PDT 24
Finished Mar 17 12:40:51 PM PDT 24
Peak memory 199912 kb
Host smart-0fd543a0-b8e6-4587-9701-5e783bda9416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064457913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.4064457913
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3116506091
Short name T209
Test name
Test status
Simulation time 109065888472 ps
CPU time 49.35 seconds
Started Mar 17 12:38:42 PM PDT 24
Finished Mar 17 12:39:32 PM PDT 24
Peak memory 199944 kb
Host smart-693ce239-f4a7-4349-99da-45706b1b0c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116506091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3116506091
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2136584716
Short name T4
Test name
Test status
Simulation time 9409821478 ps
CPU time 8.42 seconds
Started Mar 17 12:38:40 PM PDT 24
Finished Mar 17 12:38:49 PM PDT 24
Peak memory 200020 kb
Host smart-4039775d-6681-4ec3-9964-00e8eac12d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136584716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2136584716
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2438422475
Short name T96
Test name
Test status
Simulation time 19275192439 ps
CPU time 9.37 seconds
Started Mar 17 12:38:42 PM PDT 24
Finished Mar 17 12:38:52 PM PDT 24
Peak memory 200040 kb
Host smart-36b4b628-0b83-49a2-8004-d1100b17cc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438422475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2438422475
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3958846598
Short name T358
Test name
Test status
Simulation time 77065962 ps
CPU time 0.55 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:07 PM PDT 24
Peak memory 195384 kb
Host smart-f9d6aabb-7377-4906-a367-da7232c2e2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958846598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3958846598
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.940575558
Short name T530
Test name
Test status
Simulation time 98548361783 ps
CPU time 104.78 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:35:49 PM PDT 24
Peak memory 200000 kb
Host smart-fb6422c3-0ef9-4576-a6bf-e2030f21a67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940575558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.940575558
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3090406217
Short name T851
Test name
Test status
Simulation time 36989893927 ps
CPU time 40.94 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:47 PM PDT 24
Peak memory 200108 kb
Host smart-7a73cfa5-5f2e-40f0-b4d1-a6ac0c80b1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090406217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3090406217
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.1602763777
Short name T499
Test name
Test status
Simulation time 58491063800 ps
CPU time 46.3 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:34:51 PM PDT 24
Peak memory 200008 kb
Host smart-fa428e2a-f4da-48cf-b4bc-71a4944735c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602763777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1602763777
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2099634846
Short name T861
Test name
Test status
Simulation time 109346972018 ps
CPU time 805.49 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:47:33 PM PDT 24
Peak memory 199860 kb
Host smart-b82b221f-84c6-40a5-88c6-de0db2969679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099634846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2099634846
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2514994258
Short name T347
Test name
Test status
Simulation time 3064207837 ps
CPU time 4.11 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:34:08 PM PDT 24
Peak memory 198464 kb
Host smart-046ee64e-62b3-4ad8-a443-e81c57ce79d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514994258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2514994258
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2291010013
Short name T260
Test name
Test status
Simulation time 85689830365 ps
CPU time 131.17 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:36:18 PM PDT 24
Peak memory 199448 kb
Host smart-1534d5ec-8555-4fbd-92b2-ad0710eb4bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291010013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2291010013
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.207716262
Short name T878
Test name
Test status
Simulation time 16026338219 ps
CPU time 108.21 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:35:52 PM PDT 24
Peak memory 199984 kb
Host smart-2c82bed7-4de0-41b3-a889-fbf4259e08c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=207716262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.207716262
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.823613896
Short name T781
Test name
Test status
Simulation time 5612050033 ps
CPU time 53.98 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:35:00 PM PDT 24
Peak memory 198168 kb
Host smart-9ece4979-a32b-41df-b02c-2b28a92ab626
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823613896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.823613896
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.70289088
Short name T894
Test name
Test status
Simulation time 14815462620 ps
CPU time 26.18 seconds
Started Mar 17 12:34:03 PM PDT 24
Finished Mar 17 12:34:30 PM PDT 24
Peak memory 200032 kb
Host smart-19a3af6e-f87c-4de7-996d-9e8d5aa436b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70289088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.70289088
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2215486506
Short name T757
Test name
Test status
Simulation time 4363776138 ps
CPU time 3.34 seconds
Started Mar 17 12:34:08 PM PDT 24
Finished Mar 17 12:34:11 PM PDT 24
Peak memory 196076 kb
Host smart-6ccbd775-831c-4cf0-93b3-aae105523184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215486506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2215486506
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3075079933
Short name T32
Test name
Test status
Simulation time 144939211 ps
CPU time 0.77 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:07 PM PDT 24
Peak memory 218044 kb
Host smart-14711838-9d78-4d5c-bebf-6e17b4fca317
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075079933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3075079933
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3655529336
Short name T815
Test name
Test status
Simulation time 246542593 ps
CPU time 1.29 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:06 PM PDT 24
Peak memory 198488 kb
Host smart-8765ff8d-ddb3-43f7-a2e5-62f3c0ff2ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655529336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3655529336
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2198563844
Short name T581
Test name
Test status
Simulation time 126211933611 ps
CPU time 66 seconds
Started Mar 17 12:34:03 PM PDT 24
Finished Mar 17 12:35:09 PM PDT 24
Peak memory 199992 kb
Host smart-a64f9973-6fa7-4e64-9aba-940129f6aeed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198563844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2198563844
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1508949115
Short name T564
Test name
Test status
Simulation time 22332246992 ps
CPU time 367.22 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:40:12 PM PDT 24
Peak memory 216356 kb
Host smart-2cb813db-0a95-4e7c-9ac8-0251182568c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508949115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1508949115
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3130944734
Short name T452
Test name
Test status
Simulation time 8278595107 ps
CPU time 7.45 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:34:12 PM PDT 24
Peak memory 199552 kb
Host smart-42adb57d-935d-4c87-878f-9fe69623c93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130944734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3130944734
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1345975957
Short name T50
Test name
Test status
Simulation time 34180051973 ps
CPU time 13.53 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:19 PM PDT 24
Peak memory 199180 kb
Host smart-fe9ee0f4-366a-4c42-8c95-028de1f4fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345975957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1345975957
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.393629192
Short name T29
Test name
Test status
Simulation time 14769703 ps
CPU time 0.57 seconds
Started Mar 17 12:35:30 PM PDT 24
Finished Mar 17 12:35:30 PM PDT 24
Peak memory 195496 kb
Host smart-8bc754eb-7919-4a22-abc6-102b0206b15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393629192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.393629192
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3328845123
Short name T882
Test name
Test status
Simulation time 65710644061 ps
CPU time 52.13 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:36:13 PM PDT 24
Peak memory 199876 kb
Host smart-cb605108-39a4-4f22-89b0-f6902e3a3015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328845123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3328845123
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.4133312352
Short name T664
Test name
Test status
Simulation time 58443070832 ps
CPU time 29.71 seconds
Started Mar 17 12:35:20 PM PDT 24
Finished Mar 17 12:35:50 PM PDT 24
Peak memory 200020 kb
Host smart-a7501a0e-8dc7-4544-94b8-7f38c9d8e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133312352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.4133312352
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1839952844
Short name T256
Test name
Test status
Simulation time 57768788491 ps
CPU time 158.85 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:38:00 PM PDT 24
Peak memory 199940 kb
Host smart-4bc380d6-f9f7-4496-b455-d9115d31afa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839952844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1839952844
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2941185339
Short name T565
Test name
Test status
Simulation time 5840980875 ps
CPU time 2.5 seconds
Started Mar 17 12:35:20 PM PDT 24
Finished Mar 17 12:35:23 PM PDT 24
Peak memory 198780 kb
Host smart-7252b96b-b954-4f8c-ae9d-1485ff1ba0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941185339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2941185339
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1511691794
Short name T830
Test name
Test status
Simulation time 68589315526 ps
CPU time 117.68 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:37:19 PM PDT 24
Peak memory 198912 kb
Host smart-1ce5a6dc-3d4b-4925-9396-e2f6a054d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511691794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1511691794
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.473748772
Short name T699
Test name
Test status
Simulation time 15783023829 ps
CPU time 181.32 seconds
Started Mar 17 12:35:19 PM PDT 24
Finished Mar 17 12:38:21 PM PDT 24
Peak memory 199920 kb
Host smart-d7fa0a13-3cf7-4220-845c-d0403c6660f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473748772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.473748772
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3293182455
Short name T562
Test name
Test status
Simulation time 6375563236 ps
CPU time 29.5 seconds
Started Mar 17 12:35:25 PM PDT 24
Finished Mar 17 12:35:55 PM PDT 24
Peak memory 198904 kb
Host smart-055b0e13-d815-49e6-9497-30fc9e3dee07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3293182455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3293182455
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2651718948
Short name T262
Test name
Test status
Simulation time 90727883184 ps
CPU time 71.34 seconds
Started Mar 17 12:35:25 PM PDT 24
Finished Mar 17 12:36:36 PM PDT 24
Peak memory 199848 kb
Host smart-9f8b22cf-e34c-4ac0-9e0b-1e771a6a37a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651718948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2651718948
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3449376501
Short name T950
Test name
Test status
Simulation time 60955316343 ps
CPU time 49.54 seconds
Started Mar 17 12:35:20 PM PDT 24
Finished Mar 17 12:36:10 PM PDT 24
Peak memory 196328 kb
Host smart-21ff40e6-c2d0-48d2-bf21-bc73d16b4297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449376501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3449376501
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1966049245
Short name T691
Test name
Test status
Simulation time 308658466 ps
CPU time 1.07 seconds
Started Mar 17 12:35:30 PM PDT 24
Finished Mar 17 12:35:31 PM PDT 24
Peak memory 199352 kb
Host smart-2641ff12-d7ee-4774-b490-a544b85b0c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966049245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1966049245
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3685914207
Short name T286
Test name
Test status
Simulation time 695306332 ps
CPU time 2.57 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:35:24 PM PDT 24
Peak memory 199468 kb
Host smart-b4e5b149-b034-4dce-b060-07694d633801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685914207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3685914207
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2253145301
Short name T889
Test name
Test status
Simulation time 43136507627 ps
CPU time 20.12 seconds
Started Mar 17 12:35:21 PM PDT 24
Finished Mar 17 12:35:41 PM PDT 24
Peak memory 199948 kb
Host smart-a5585231-7516-4ae5-b85d-e11a1860ddd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253145301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2253145301
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3201133521
Short name T223
Test name
Test status
Simulation time 106743002043 ps
CPU time 190.92 seconds
Started Mar 17 12:38:40 PM PDT 24
Finished Mar 17 12:41:53 PM PDT 24
Peak memory 199976 kb
Host smart-39006e7a-2508-4197-949c-73aab555aac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201133521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3201133521
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.4221972347
Short name T189
Test name
Test status
Simulation time 53782897358 ps
CPU time 60.75 seconds
Started Mar 17 12:38:39 PM PDT 24
Finished Mar 17 12:39:41 PM PDT 24
Peak memory 199968 kb
Host smart-84796aed-33e9-43a3-801c-206324a42412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221972347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4221972347
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2235158167
Short name T580
Test name
Test status
Simulation time 30780584648 ps
CPU time 13.34 seconds
Started Mar 17 12:38:39 PM PDT 24
Finished Mar 17 12:38:54 PM PDT 24
Peak memory 200008 kb
Host smart-439ddd07-5402-4ae6-9f3f-d9d48e5ea2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235158167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2235158167
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.4139553242
Short name T745
Test name
Test status
Simulation time 59873671610 ps
CPU time 34.18 seconds
Started Mar 17 12:38:42 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 199960 kb
Host smart-84dbaefc-e1df-41bf-9e85-625157f3055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139553242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.4139553242
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.788640485
Short name T342
Test name
Test status
Simulation time 53343289782 ps
CPU time 32.37 seconds
Started Mar 17 12:38:39 PM PDT 24
Finished Mar 17 12:39:13 PM PDT 24
Peak memory 199996 kb
Host smart-dd647a96-84ab-47d7-a00a-2cbb98dff2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788640485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.788640485
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1347402882
Short name T947
Test name
Test status
Simulation time 66535144873 ps
CPU time 19.27 seconds
Started Mar 17 12:38:39 PM PDT 24
Finished Mar 17 12:38:58 PM PDT 24
Peak memory 199892 kb
Host smart-4402cd7a-27f0-457a-be80-15d5ca33a2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347402882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1347402882
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1845058846
Short name T1017
Test name
Test status
Simulation time 13782681712 ps
CPU time 26.02 seconds
Started Mar 17 12:38:38 PM PDT 24
Finished Mar 17 12:39:05 PM PDT 24
Peak memory 200048 kb
Host smart-ec0a251e-d291-4b3b-98a9-285f1316f564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845058846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1845058846
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2783028021
Short name T327
Test name
Test status
Simulation time 83711534430 ps
CPU time 29.03 seconds
Started Mar 17 12:38:40 PM PDT 24
Finished Mar 17 12:39:10 PM PDT 24
Peak memory 199752 kb
Host smart-4be3056d-119b-4a84-8355-c77c9239eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783028021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2783028021
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.846577136
Short name T434
Test name
Test status
Simulation time 106344667000 ps
CPU time 85.24 seconds
Started Mar 17 12:38:39 PM PDT 24
Finished Mar 17 12:40:06 PM PDT 24
Peak memory 199996 kb
Host smart-87926179-93e0-4798-9c20-18ab605c8145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846577136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.846577136
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.968863748
Short name T153
Test name
Test status
Simulation time 119836981226 ps
CPU time 48.87 seconds
Started Mar 17 12:38:39 PM PDT 24
Finished Mar 17 12:39:29 PM PDT 24
Peak memory 199992 kb
Host smart-313c1f20-348c-463a-b300-d88d6a0c23f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968863748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.968863748
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1322071977
Short name T1015
Test name
Test status
Simulation time 24368501 ps
CPU time 0.53 seconds
Started Mar 17 12:35:37 PM PDT 24
Finished Mar 17 12:35:37 PM PDT 24
Peak memory 195416 kb
Host smart-59ad0d5d-5fbf-4cfe-bcbc-839292a312e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322071977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1322071977
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4130143864
Short name T909
Test name
Test status
Simulation time 257153549436 ps
CPU time 357.36 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:41:27 PM PDT 24
Peak memory 199952 kb
Host smart-5ee44a9b-c38e-4e9e-a64f-94add580c866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130143864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4130143864
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1072127552
Short name T157
Test name
Test status
Simulation time 120643642186 ps
CPU time 89.17 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:36:58 PM PDT 24
Peak memory 199988 kb
Host smart-e8022159-9232-4afc-af8b-925ca9938254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072127552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1072127552
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3085124830
Short name T1030
Test name
Test status
Simulation time 128156047145 ps
CPU time 103.35 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:37:10 PM PDT 24
Peak memory 200096 kb
Host smart-953cc7e6-c767-4cb4-a2ae-461a60bbfd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085124830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3085124830
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1289301458
Short name T847
Test name
Test status
Simulation time 16103439222 ps
CPU time 18.12 seconds
Started Mar 17 12:35:37 PM PDT 24
Finished Mar 17 12:35:55 PM PDT 24
Peak memory 199924 kb
Host smart-f4a596e9-6bc1-47d0-8f36-b61abd4655fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289301458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1289301458
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_loopback.821229523
Short name T788
Test name
Test status
Simulation time 4635274446 ps
CPU time 9.21 seconds
Started Mar 17 12:35:36 PM PDT 24
Finished Mar 17 12:35:45 PM PDT 24
Peak memory 198884 kb
Host smart-866db40a-7ac6-4a5c-9e0b-0c8854feeac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821229523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.821229523
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3862715878
Short name T644
Test name
Test status
Simulation time 99428931543 ps
CPU time 153.26 seconds
Started Mar 17 12:35:28 PM PDT 24
Finished Mar 17 12:38:02 PM PDT 24
Peak memory 199692 kb
Host smart-81c90c8d-5c24-40f7-b8a9-ca8bb0acae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862715878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3862715878
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2651171388
Short name T1004
Test name
Test status
Simulation time 7407550321 ps
CPU time 211.24 seconds
Started Mar 17 12:35:28 PM PDT 24
Finished Mar 17 12:39:00 PM PDT 24
Peak memory 200164 kb
Host smart-15d05423-f462-42c7-86ea-65f3f31b85d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651171388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2651171388
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.296644496
Short name T508
Test name
Test status
Simulation time 6205684617 ps
CPU time 9.78 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:35:37 PM PDT 24
Peak memory 199132 kb
Host smart-ab3de256-6fc9-4f13-9e9b-d3c617a0f102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296644496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.296644496
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1621739444
Short name T984
Test name
Test status
Simulation time 110393639495 ps
CPU time 209.86 seconds
Started Mar 17 12:35:36 PM PDT 24
Finished Mar 17 12:39:06 PM PDT 24
Peak memory 199952 kb
Host smart-b48589d2-6f32-48c2-bba7-ea70ea4f2f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621739444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1621739444
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1360264498
Short name T713
Test name
Test status
Simulation time 1892259715 ps
CPU time 1.48 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:35:28 PM PDT 24
Peak memory 195424 kb
Host smart-54ee00f9-9b03-4077-831b-39093afea170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360264498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1360264498
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2558359842
Short name T545
Test name
Test status
Simulation time 473011439 ps
CPU time 1.28 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:35:28 PM PDT 24
Peak memory 198872 kb
Host smart-91b3a322-1bb3-42c1-8953-b27f7a6783dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558359842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2558359842
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2730665182
Short name T170
Test name
Test status
Simulation time 368059003016 ps
CPU time 144.97 seconds
Started Mar 17 12:35:27 PM PDT 24
Finished Mar 17 12:37:52 PM PDT 24
Peak memory 200028 kb
Host smart-1deb9908-0078-4bf8-bc2f-18c093c0ae26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730665182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2730665182
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.430807755
Short name T294
Test name
Test status
Simulation time 7020394805 ps
CPU time 19.56 seconds
Started Mar 17 12:35:32 PM PDT 24
Finished Mar 17 12:35:53 PM PDT 24
Peak memory 199872 kb
Host smart-9867abc9-e4c8-4b99-a535-ae18e77afdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430807755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.430807755
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2754892660
Short name T1112
Test name
Test status
Simulation time 29689456884 ps
CPU time 27.66 seconds
Started Mar 17 12:35:32 PM PDT 24
Finished Mar 17 12:36:01 PM PDT 24
Peak memory 200020 kb
Host smart-86242f7a-f155-4bd1-8458-ce3cac95ba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754892660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2754892660
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3820765168
Short name T403
Test name
Test status
Simulation time 132557541045 ps
CPU time 36.1 seconds
Started Mar 17 12:38:40 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 200016 kb
Host smart-360e905f-c3cc-46d0-b1c4-f3e026b4c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820765168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3820765168
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.4093422742
Short name T55
Test name
Test status
Simulation time 58623354175 ps
CPU time 92.56 seconds
Started Mar 17 12:38:46 PM PDT 24
Finished Mar 17 12:40:19 PM PDT 24
Peak memory 200128 kb
Host smart-0d98aa86-7787-419c-9e7e-24b8fe812c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093422742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4093422742
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4215742117
Short name T756
Test name
Test status
Simulation time 171493718189 ps
CPU time 185.03 seconds
Started Mar 17 12:38:45 PM PDT 24
Finished Mar 17 12:41:50 PM PDT 24
Peak memory 200144 kb
Host smart-c8d81e66-a278-46a6-92d1-889905b6be4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215742117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4215742117
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3869655371
Short name T592
Test name
Test status
Simulation time 261682773405 ps
CPU time 774.67 seconds
Started Mar 17 12:38:48 PM PDT 24
Finished Mar 17 12:51:43 PM PDT 24
Peak memory 199980 kb
Host smart-f2dac570-7517-4f73-a18b-986e43177be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869655371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3869655371
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2043828956
Short name T626
Test name
Test status
Simulation time 57780770626 ps
CPU time 15.09 seconds
Started Mar 17 12:38:47 PM PDT 24
Finished Mar 17 12:39:02 PM PDT 24
Peak memory 200052 kb
Host smart-c1204468-b8fe-40a7-86e8-d2b2d7aebee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043828956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2043828956
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3785009331
Short name T220
Test name
Test status
Simulation time 172661341189 ps
CPU time 17.06 seconds
Started Mar 17 12:38:47 PM PDT 24
Finished Mar 17 12:39:04 PM PDT 24
Peak memory 199992 kb
Host smart-85dcb9b1-e722-4df5-bbdd-0a58982ad62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785009331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3785009331
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4250904171
Short name T1012
Test name
Test status
Simulation time 36368219687 ps
CPU time 30.38 seconds
Started Mar 17 12:38:45 PM PDT 24
Finished Mar 17 12:39:16 PM PDT 24
Peak memory 199988 kb
Host smart-fa7a6dc8-a029-4dff-885d-c7eb8035891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250904171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4250904171
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1240340952
Short name T181
Test name
Test status
Simulation time 9060502826 ps
CPU time 16.9 seconds
Started Mar 17 12:38:47 PM PDT 24
Finished Mar 17 12:39:04 PM PDT 24
Peak memory 199884 kb
Host smart-0ec2e290-272d-4c6e-a17e-fd5b5ebb4e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240340952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1240340952
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2151481596
Short name T560
Test name
Test status
Simulation time 44658568 ps
CPU time 0.56 seconds
Started Mar 17 12:35:35 PM PDT 24
Finished Mar 17 12:35:36 PM PDT 24
Peak memory 195440 kb
Host smart-a0da1642-20be-45d7-a5f6-510335954864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151481596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2151481596
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.370188953
Short name T1086
Test name
Test status
Simulation time 18825468865 ps
CPU time 10.59 seconds
Started Mar 17 12:35:29 PM PDT 24
Finished Mar 17 12:35:40 PM PDT 24
Peak memory 199988 kb
Host smart-6bff2569-cd9a-42b1-9225-6c7aa263ef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370188953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.370188953
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2203873593
Short name T139
Test name
Test status
Simulation time 102866953494 ps
CPU time 125.59 seconds
Started Mar 17 12:35:30 PM PDT 24
Finished Mar 17 12:37:36 PM PDT 24
Peak memory 200020 kb
Host smart-829303bf-a689-4457-aba9-ec31689ca16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203873593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2203873593
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.698542596
Short name T715
Test name
Test status
Simulation time 101452882358 ps
CPU time 100.73 seconds
Started Mar 17 12:35:28 PM PDT 24
Finished Mar 17 12:37:10 PM PDT 24
Peak memory 200128 kb
Host smart-bb0e410b-fa08-42fa-869a-b1b3803e0653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698542596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.698542596
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.5524111
Short name T943
Test name
Test status
Simulation time 118564070546 ps
CPU time 526.55 seconds
Started Mar 17 12:35:36 PM PDT 24
Finished Mar 17 12:44:23 PM PDT 24
Peak memory 200076 kb
Host smart-e85d9501-28c2-4c07-ac1f-72c26dc1d30a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5524111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.5524111
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.909016902
Short name T994
Test name
Test status
Simulation time 11693975269 ps
CPU time 11.86 seconds
Started Mar 17 12:35:40 PM PDT 24
Finished Mar 17 12:35:53 PM PDT 24
Peak memory 199060 kb
Host smart-12ac1cce-b6f3-4a52-95c4-d14d94660ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909016902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.909016902
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2445751752
Short name T642
Test name
Test status
Simulation time 36447808269 ps
CPU time 16.49 seconds
Started Mar 17 12:35:34 PM PDT 24
Finished Mar 17 12:35:52 PM PDT 24
Peak memory 199952 kb
Host smart-f236d9a5-7d16-446f-9503-eb08ac4fd57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445751752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2445751752
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.4022622209
Short name T908
Test name
Test status
Simulation time 21320255207 ps
CPU time 982.47 seconds
Started Mar 17 12:35:40 PM PDT 24
Finished Mar 17 12:52:04 PM PDT 24
Peak memory 199980 kb
Host smart-84af3bd6-c196-4f76-9d78-6134047a2562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022622209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4022622209
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1481437397
Short name T696
Test name
Test status
Simulation time 4104950075 ps
CPU time 32.17 seconds
Started Mar 17 12:35:33 PM PDT 24
Finished Mar 17 12:36:06 PM PDT 24
Peak memory 198808 kb
Host smart-f15de798-fbd0-4903-b4e2-6b9c6fc76418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481437397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1481437397
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.504540589
Short name T172
Test name
Test status
Simulation time 150116418019 ps
CPU time 33 seconds
Started Mar 17 12:35:29 PM PDT 24
Finished Mar 17 12:36:02 PM PDT 24
Peak memory 200064 kb
Host smart-cbf990d3-c9bc-458e-afec-7fd3b2a76c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504540589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.504540589
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2246049752
Short name T269
Test name
Test status
Simulation time 4043382859 ps
CPU time 2.26 seconds
Started Mar 17 12:35:32 PM PDT 24
Finished Mar 17 12:35:36 PM PDT 24
Peak memory 196084 kb
Host smart-9f31e8c4-36b0-4f4e-88b7-935188606a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246049752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2246049752
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3446152580
Short name T831
Test name
Test status
Simulation time 668613625 ps
CPU time 1.56 seconds
Started Mar 17 12:35:26 PM PDT 24
Finished Mar 17 12:35:28 PM PDT 24
Peak memory 198216 kb
Host smart-e40db53a-080a-4cb3-971f-d3dc55088daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446152580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3446152580
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2396295264
Short name T168
Test name
Test status
Simulation time 42478053890 ps
CPU time 26.79 seconds
Started Mar 17 12:35:36 PM PDT 24
Finished Mar 17 12:36:03 PM PDT 24
Peak memory 200064 kb
Host smart-8d9c48b6-dc09-4a74-be5e-37179c40a298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396295264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2396295264
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2634564420
Short name T17
Test name
Test status
Simulation time 7103164133 ps
CPU time 10.55 seconds
Started Mar 17 12:35:30 PM PDT 24
Finished Mar 17 12:35:41 PM PDT 24
Peak memory 199928 kb
Host smart-ea49ae7c-ff70-4e16-8ff1-76a6224b91a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634564420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2634564420
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2252507248
Short name T739
Test name
Test status
Simulation time 8964562322 ps
CPU time 15.79 seconds
Started Mar 17 12:35:26 PM PDT 24
Finished Mar 17 12:35:42 PM PDT 24
Peak memory 198292 kb
Host smart-c18ed7fb-107b-474d-8c78-be2d1eb8783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252507248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2252507248
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3880444819
Short name T234
Test name
Test status
Simulation time 106964070796 ps
CPU time 52.14 seconds
Started Mar 17 12:38:47 PM PDT 24
Finished Mar 17 12:39:39 PM PDT 24
Peak memory 200072 kb
Host smart-a81e11ec-c22f-4689-80ee-586e8e23a705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880444819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3880444819
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3595966384
Short name T191
Test name
Test status
Simulation time 230870581949 ps
CPU time 40.06 seconds
Started Mar 17 12:38:47 PM PDT 24
Finished Mar 17 12:39:27 PM PDT 24
Peak memory 200024 kb
Host smart-801f983b-66e4-48fb-ac82-77cbb888ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595966384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3595966384
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2779201628
Short name T1103
Test name
Test status
Simulation time 41899407090 ps
CPU time 14.08 seconds
Started Mar 17 12:38:45 PM PDT 24
Finished Mar 17 12:38:59 PM PDT 24
Peak memory 200064 kb
Host smart-fe5a64ad-52b0-4aee-9a08-c2ec5a900596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779201628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2779201628
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3671044224
Short name T99
Test name
Test status
Simulation time 91596497186 ps
CPU time 29.32 seconds
Started Mar 17 12:38:47 PM PDT 24
Finished Mar 17 12:39:16 PM PDT 24
Peak memory 200092 kb
Host smart-9e4bbce2-9d8a-4ab9-8dc1-8084de56cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671044224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3671044224
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3833822030
Short name T948
Test name
Test status
Simulation time 213887082794 ps
CPU time 74.69 seconds
Started Mar 17 12:38:46 PM PDT 24
Finished Mar 17 12:40:01 PM PDT 24
Peak memory 199988 kb
Host smart-12caa33d-eadb-462a-83a4-b3b100249bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833822030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3833822030
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.394818040
Short name T110
Test name
Test status
Simulation time 40246774982 ps
CPU time 19.19 seconds
Started Mar 17 12:38:46 PM PDT 24
Finished Mar 17 12:39:05 PM PDT 24
Peak memory 199796 kb
Host smart-3251d3dd-3885-4f63-8759-347f6acdd8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394818040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.394818040
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.231743509
Short name T991
Test name
Test status
Simulation time 57662900319 ps
CPU time 91.08 seconds
Started Mar 17 12:38:46 PM PDT 24
Finished Mar 17 12:40:18 PM PDT 24
Peak memory 199868 kb
Host smart-d8ec9cbb-9d7a-48cf-94f3-93742662702d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231743509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.231743509
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3304516639
Short name T858
Test name
Test status
Simulation time 146957269921 ps
CPU time 40.83 seconds
Started Mar 17 12:38:45 PM PDT 24
Finished Mar 17 12:39:26 PM PDT 24
Peak memory 200016 kb
Host smart-03525717-7d77-40b0-a5b8-3b5d0e09143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304516639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3304516639
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.306058777
Short name T1075
Test name
Test status
Simulation time 31962737 ps
CPU time 0.54 seconds
Started Mar 17 12:35:40 PM PDT 24
Finished Mar 17 12:35:42 PM PDT 24
Peak memory 195448 kb
Host smart-629b8902-630e-4363-8b70-71916adf82fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306058777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.306058777
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.862704738
Short name T761
Test name
Test status
Simulation time 55527551883 ps
CPU time 24.96 seconds
Started Mar 17 12:35:33 PM PDT 24
Finished Mar 17 12:35:58 PM PDT 24
Peak memory 199684 kb
Host smart-a55c71cc-a177-4241-b0ae-f462b8dadb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862704738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.862704738
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.498404687
Short name T177
Test name
Test status
Simulation time 238171856500 ps
CPU time 99.74 seconds
Started Mar 17 12:35:34 PM PDT 24
Finished Mar 17 12:37:15 PM PDT 24
Peak memory 199908 kb
Host smart-c27dd811-84ae-4d0a-b5fa-992e4f2ed3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498404687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.498404687
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1829598681
Short name T685
Test name
Test status
Simulation time 22417632735 ps
CPU time 35 seconds
Started Mar 17 12:35:37 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 200012 kb
Host smart-29b2bc21-e380-4319-a554-49aef2446ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829598681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1829598681
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2904639315
Short name T964
Test name
Test status
Simulation time 2194564810 ps
CPU time 0.94 seconds
Started Mar 17 12:35:34 PM PDT 24
Finished Mar 17 12:35:36 PM PDT 24
Peak memory 195720 kb
Host smart-9211cf9f-2025-4be7-8c4f-76262186655f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904639315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2904639315
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.669760200
Short name T931
Test name
Test status
Simulation time 139200520427 ps
CPU time 459.79 seconds
Started Mar 17 12:35:35 PM PDT 24
Finished Mar 17 12:43:15 PM PDT 24
Peak memory 199952 kb
Host smart-c51b5211-5eaa-4054-b7de-f3d44da34e20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669760200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.669760200
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.4085353401
Short name T774
Test name
Test status
Simulation time 1126554091 ps
CPU time 1.83 seconds
Started Mar 17 12:35:34 PM PDT 24
Finished Mar 17 12:35:36 PM PDT 24
Peak memory 198292 kb
Host smart-ab3641f1-69bc-4e33-83d7-f3a796b22c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085353401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4085353401
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2552997419
Short name T471
Test name
Test status
Simulation time 52325068729 ps
CPU time 86.04 seconds
Started Mar 17 12:35:35 PM PDT 24
Finished Mar 17 12:37:02 PM PDT 24
Peak memory 200116 kb
Host smart-5a627dff-6dc1-4e73-9e67-057ac35275e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552997419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2552997419
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2136405743
Short name T733
Test name
Test status
Simulation time 9108565606 ps
CPU time 558.51 seconds
Started Mar 17 12:35:38 PM PDT 24
Finished Mar 17 12:44:57 PM PDT 24
Peak memory 200148 kb
Host smart-17b9a176-b9c6-4b97-bd1a-1d739d66a616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136405743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2136405743
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.879016264
Short name T544
Test name
Test status
Simulation time 6554070984 ps
CPU time 59.26 seconds
Started Mar 17 12:35:37 PM PDT 24
Finished Mar 17 12:36:36 PM PDT 24
Peak memory 198200 kb
Host smart-2926b8fd-9094-4ca9-a0f6-97c3e25d6840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879016264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.879016264
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2199166741
Short name T133
Test name
Test status
Simulation time 19816096115 ps
CPU time 31.25 seconds
Started Mar 17 12:35:34 PM PDT 24
Finished Mar 17 12:36:05 PM PDT 24
Peak memory 200064 kb
Host smart-7e41f9cf-7f6d-43a5-a159-4b16e9310c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199166741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2199166741
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1794854486
Short name T990
Test name
Test status
Simulation time 40605232109 ps
CPU time 61.7 seconds
Started Mar 17 12:35:35 PM PDT 24
Finished Mar 17 12:36:37 PM PDT 24
Peak memory 196344 kb
Host smart-98b3354b-0def-4e77-8b57-e3f0bf001d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794854486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1794854486
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.263705645
Short name T1021
Test name
Test status
Simulation time 6071022594 ps
CPU time 12.95 seconds
Started Mar 17 12:35:38 PM PDT 24
Finished Mar 17 12:35:51 PM PDT 24
Peak memory 199948 kb
Host smart-621e3d7e-758a-4ccb-8624-0e1f65db7050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263705645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.263705645
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1603836990
Short name T478
Test name
Test status
Simulation time 6019065295 ps
CPU time 18 seconds
Started Mar 17 12:35:33 PM PDT 24
Finished Mar 17 12:35:51 PM PDT 24
Peak memory 199256 kb
Host smart-6fc7bda9-f65f-46c2-bf26-ca3080f5491b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603836990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1603836990
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1176096879
Short name T290
Test name
Test status
Simulation time 36607741552 ps
CPU time 17.37 seconds
Started Mar 17 12:35:33 PM PDT 24
Finished Mar 17 12:35:51 PM PDT 24
Peak memory 199584 kb
Host smart-b60748f5-f3e4-4d05-807f-cd7e5babca89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176096879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1176096879
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2149177353
Short name T1107
Test name
Test status
Simulation time 40907155306 ps
CPU time 18.35 seconds
Started Mar 17 12:38:47 PM PDT 24
Finished Mar 17 12:39:05 PM PDT 24
Peak memory 200080 kb
Host smart-be834e73-4fdf-4bc1-8bca-8fbac6c14a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149177353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2149177353
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3420095254
Short name T1061
Test name
Test status
Simulation time 126413527302 ps
CPU time 45.21 seconds
Started Mar 17 12:38:55 PM PDT 24
Finished Mar 17 12:39:40 PM PDT 24
Peak memory 199924 kb
Host smart-21657382-b969-480a-809a-5355db0f4758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420095254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3420095254
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.910425953
Short name T987
Test name
Test status
Simulation time 20261985167 ps
CPU time 5.11 seconds
Started Mar 17 12:38:55 PM PDT 24
Finished Mar 17 12:39:00 PM PDT 24
Peak memory 199768 kb
Host smart-572bc9ec-0329-44c1-91f5-b5263bbdde80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910425953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.910425953
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3298849850
Short name T134
Test name
Test status
Simulation time 52880440985 ps
CPU time 86.36 seconds
Started Mar 17 12:38:54 PM PDT 24
Finished Mar 17 12:40:21 PM PDT 24
Peak memory 199972 kb
Host smart-14f30aae-efe9-45fe-8f03-0de022cc48e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298849850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3298849850
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.881691085
Short name T247
Test name
Test status
Simulation time 22451587773 ps
CPU time 25.97 seconds
Started Mar 17 12:38:54 PM PDT 24
Finished Mar 17 12:39:21 PM PDT 24
Peak memory 199952 kb
Host smart-f3951c10-58ac-4768-a1b4-4fbf4f46f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881691085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.881691085
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1130628893
Short name T324
Test name
Test status
Simulation time 49790987826 ps
CPU time 67.31 seconds
Started Mar 17 12:38:54 PM PDT 24
Finished Mar 17 12:40:02 PM PDT 24
Peak memory 200044 kb
Host smart-28711052-58a4-48be-95f1-1a66ba7ef8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130628893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1130628893
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.993529649
Short name T618
Test name
Test status
Simulation time 110954739449 ps
CPU time 56.86 seconds
Started Mar 17 12:38:55 PM PDT 24
Finished Mar 17 12:39:52 PM PDT 24
Peak memory 200024 kb
Host smart-5ce2363b-9a02-45b4-8e41-b4c840cbe40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993529649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.993529649
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3657863632
Short name T952
Test name
Test status
Simulation time 116437276419 ps
CPU time 25.62 seconds
Started Mar 17 12:38:54 PM PDT 24
Finished Mar 17 12:39:20 PM PDT 24
Peak memory 199960 kb
Host smart-94834c58-d5d3-4a19-86fa-498c808ed3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657863632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3657863632
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3779171014
Short name T762
Test name
Test status
Simulation time 51793196462 ps
CPU time 12.32 seconds
Started Mar 17 12:38:53 PM PDT 24
Finished Mar 17 12:39:06 PM PDT 24
Peak memory 200116 kb
Host smart-79e3b8d3-9714-4313-b069-45ae4eeee623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779171014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3779171014
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2542640061
Short name T367
Test name
Test status
Simulation time 13505627 ps
CPU time 0.54 seconds
Started Mar 17 12:35:43 PM PDT 24
Finished Mar 17 12:35:44 PM PDT 24
Peak memory 194472 kb
Host smart-dd9d6dea-5892-4b6f-85d6-1762e175b489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542640061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2542640061
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3479396355
Short name T598
Test name
Test status
Simulation time 52415713583 ps
CPU time 40.72 seconds
Started Mar 17 12:35:44 PM PDT 24
Finished Mar 17 12:36:24 PM PDT 24
Peak memory 199968 kb
Host smart-591312f1-de21-4722-bd34-966afa4cadcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479396355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3479396355
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.765941753
Short name T48
Test name
Test status
Simulation time 19813382295 ps
CPU time 34.07 seconds
Started Mar 17 12:35:42 PM PDT 24
Finished Mar 17 12:36:17 PM PDT 24
Peak memory 199900 kb
Host smart-9cbf3d22-0f4b-4d14-b825-6c79dc60055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765941753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.765941753
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1420960856
Short name T1028
Test name
Test status
Simulation time 106152033360 ps
CPU time 53.33 seconds
Started Mar 17 12:35:44 PM PDT 24
Finished Mar 17 12:36:38 PM PDT 24
Peak memory 199960 kb
Host smart-20cde1af-10e8-4f28-9a0a-11f2937b1840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420960856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1420960856
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1176039513
Short name T790
Test name
Test status
Simulation time 31384847716 ps
CPU time 5.42 seconds
Started Mar 17 12:35:42 PM PDT 24
Finished Mar 17 12:35:48 PM PDT 24
Peak memory 199628 kb
Host smart-22b771c1-290f-45bf-a4a8-d252a2f79e03
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176039513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1176039513
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.750361699
Short name T533
Test name
Test status
Simulation time 120259490697 ps
CPU time 291.59 seconds
Started Mar 17 12:35:43 PM PDT 24
Finished Mar 17 12:40:35 PM PDT 24
Peak memory 200056 kb
Host smart-ba6d8099-e38b-4a68-8d6f-a5ff98df58e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750361699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.750361699
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.817726846
Short name T895
Test name
Test status
Simulation time 11220474875 ps
CPU time 21.72 seconds
Started Mar 17 12:35:43 PM PDT 24
Finished Mar 17 12:36:05 PM PDT 24
Peak memory 199960 kb
Host smart-a77557b1-c9a8-4505-87c2-20909f61ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817726846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.817726846
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1979214391
Short name T965
Test name
Test status
Simulation time 47884265973 ps
CPU time 70.87 seconds
Started Mar 17 12:35:44 PM PDT 24
Finished Mar 17 12:36:54 PM PDT 24
Peak memory 200216 kb
Host smart-d7533703-4527-45fe-b40e-e8df685eb0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979214391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1979214391
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1729514998
Short name T962
Test name
Test status
Simulation time 17157833315 ps
CPU time 87.92 seconds
Started Mar 17 12:35:44 PM PDT 24
Finished Mar 17 12:37:13 PM PDT 24
Peak memory 200000 kb
Host smart-784f447c-ee5b-4358-aa8b-4b3b6843b8ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729514998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1729514998
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.988115830
Short name T913
Test name
Test status
Simulation time 2843000574 ps
CPU time 8 seconds
Started Mar 17 12:35:43 PM PDT 24
Finished Mar 17 12:35:51 PM PDT 24
Peak memory 198788 kb
Host smart-2e1dc226-8e9c-4e49-9d21-f4e05c760bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988115830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.988115830
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1950657246
Short name T438
Test name
Test status
Simulation time 128723116583 ps
CPU time 149.44 seconds
Started Mar 17 12:35:43 PM PDT 24
Finished Mar 17 12:38:13 PM PDT 24
Peak memory 199964 kb
Host smart-a4654b7e-8612-422f-9cf7-5335685a269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950657246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1950657246
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.622770163
Short name T561
Test name
Test status
Simulation time 4087256665 ps
CPU time 2.31 seconds
Started Mar 17 12:35:42 PM PDT 24
Finished Mar 17 12:35:45 PM PDT 24
Peak memory 196000 kb
Host smart-5db97544-86e3-4241-8962-c2a1d2b81377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622770163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.622770163
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1589178314
Short name T1007
Test name
Test status
Simulation time 679452400 ps
CPU time 1.42 seconds
Started Mar 17 12:35:35 PM PDT 24
Finished Mar 17 12:35:37 PM PDT 24
Peak memory 198208 kb
Host smart-bcbff176-66f6-4c66-b5b4-6abc2ef88f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589178314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1589178314
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1605699601
Short name T113
Test name
Test status
Simulation time 153949079830 ps
CPU time 185.45 seconds
Started Mar 17 12:35:43 PM PDT 24
Finished Mar 17 12:38:49 PM PDT 24
Peak memory 199956 kb
Host smart-e82a127d-3e3a-40e9-a2e1-be9bd340464e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605699601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1605699601
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.907473850
Short name T413
Test name
Test status
Simulation time 6552046994 ps
CPU time 30.46 seconds
Started Mar 17 12:35:43 PM PDT 24
Finished Mar 17 12:36:13 PM PDT 24
Peak memory 199820 kb
Host smart-1ae852ed-ec66-4249-ba19-37412597e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907473850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.907473850
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.597391495
Short name T275
Test name
Test status
Simulation time 29251686221 ps
CPU time 16.28 seconds
Started Mar 17 12:35:35 PM PDT 24
Finished Mar 17 12:35:52 PM PDT 24
Peak memory 199832 kb
Host smart-afb2d383-f83e-47ec-bb36-56c4c7f234e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597391495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.597391495
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2274129200
Short name T620
Test name
Test status
Simulation time 145925766779 ps
CPU time 224.99 seconds
Started Mar 17 12:38:55 PM PDT 24
Finished Mar 17 12:42:40 PM PDT 24
Peak memory 200012 kb
Host smart-9e2483b3-060c-4dc7-9f39-047317973a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274129200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2274129200
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3916110651
Short name T999
Test name
Test status
Simulation time 34163296738 ps
CPU time 62.53 seconds
Started Mar 17 12:38:56 PM PDT 24
Finished Mar 17 12:39:59 PM PDT 24
Peak memory 200056 kb
Host smart-51357f0b-a300-4514-a8b8-42ca6845c284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916110651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3916110651
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3014175493
Short name T412
Test name
Test status
Simulation time 72913426121 ps
CPU time 30.56 seconds
Started Mar 17 12:38:54 PM PDT 24
Finished Mar 17 12:39:25 PM PDT 24
Peak memory 200088 kb
Host smart-99fbfe98-283c-4e4a-b71a-4862aa4b4d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014175493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3014175493
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3535503369
Short name T867
Test name
Test status
Simulation time 51584610799 ps
CPU time 24.88 seconds
Started Mar 17 12:38:56 PM PDT 24
Finished Mar 17 12:39:21 PM PDT 24
Peak memory 200000 kb
Host smart-88137c38-8ad3-406f-8680-77ad35390429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535503369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3535503369
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1108378615
Short name T921
Test name
Test status
Simulation time 174292816934 ps
CPU time 28.88 seconds
Started Mar 17 12:38:55 PM PDT 24
Finished Mar 17 12:39:24 PM PDT 24
Peak memory 199956 kb
Host smart-b46d1e62-73ba-4e54-968f-af0a379972c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108378615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1108378615
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2012183351
Short name T315
Test name
Test status
Simulation time 147910314891 ps
CPU time 121.54 seconds
Started Mar 17 12:38:54 PM PDT 24
Finished Mar 17 12:40:55 PM PDT 24
Peak memory 199988 kb
Host smart-fc39d526-11eb-4edc-a75a-79467e855d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012183351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2012183351
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3228188749
Short name T837
Test name
Test status
Simulation time 191560837930 ps
CPU time 31.52 seconds
Started Mar 17 12:38:54 PM PDT 24
Finished Mar 17 12:39:26 PM PDT 24
Peak memory 199984 kb
Host smart-d19d4e55-d906-4c44-8540-bb2538dc196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228188749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3228188749
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.950036901
Short name T919
Test name
Test status
Simulation time 38390535114 ps
CPU time 25.8 seconds
Started Mar 17 12:39:02 PM PDT 24
Finished Mar 17 12:39:28 PM PDT 24
Peak memory 199964 kb
Host smart-bdbdd2e3-92ed-4552-a256-1822a0c9bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950036901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.950036901
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2334041966
Short name T425
Test name
Test status
Simulation time 11857878 ps
CPU time 0.54 seconds
Started Mar 17 12:35:49 PM PDT 24
Finished Mar 17 12:35:49 PM PDT 24
Peak memory 195556 kb
Host smart-62614912-1387-4242-83a1-794b8b25ffe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334041966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2334041966
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4058347668
Short name T1040
Test name
Test status
Simulation time 26865307071 ps
CPU time 43.65 seconds
Started Mar 17 12:35:41 PM PDT 24
Finished Mar 17 12:36:25 PM PDT 24
Peak memory 200112 kb
Host smart-4499fdc4-62f9-451a-bb51-88cfebcd767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058347668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4058347668
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2457539521
Short name T489
Test name
Test status
Simulation time 88420000689 ps
CPU time 66.04 seconds
Started Mar 17 12:35:40 PM PDT 24
Finished Mar 17 12:36:46 PM PDT 24
Peak memory 199936 kb
Host smart-a26a3a51-f2ec-46b9-808e-40d469b4946c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457539521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2457539521
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.4081211719
Short name T246
Test name
Test status
Simulation time 180445743174 ps
CPU time 119.94 seconds
Started Mar 17 12:35:42 PM PDT 24
Finished Mar 17 12:37:42 PM PDT 24
Peak memory 199984 kb
Host smart-9056007e-9cf2-46cf-a974-fbb0fa9f8201
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081211719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4081211719
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2352686475
Short name T954
Test name
Test status
Simulation time 54553814516 ps
CPU time 240.12 seconds
Started Mar 17 12:35:48 PM PDT 24
Finished Mar 17 12:39:49 PM PDT 24
Peak memory 200028 kb
Host smart-fbedb061-9a10-4ca5-8276-26af2225e931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352686475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2352686475
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3829376529
Short name T986
Test name
Test status
Simulation time 3383504766 ps
CPU time 2.27 seconds
Started Mar 17 12:35:49 PM PDT 24
Finished Mar 17 12:35:52 PM PDT 24
Peak memory 197596 kb
Host smart-d25288aa-d06b-413c-8180-534c219ef3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829376529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3829376529
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3283108714
Short name T843
Test name
Test status
Simulation time 35277982294 ps
CPU time 59.89 seconds
Started Mar 17 12:35:48 PM PDT 24
Finished Mar 17 12:36:49 PM PDT 24
Peak memory 200020 kb
Host smart-157cf3d7-cb15-47e1-b19c-f94cc569b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283108714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3283108714
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1402720835
Short name T321
Test name
Test status
Simulation time 7347601109 ps
CPU time 193.42 seconds
Started Mar 17 12:35:49 PM PDT 24
Finished Mar 17 12:39:03 PM PDT 24
Peak memory 199956 kb
Host smart-17404f4d-c91d-40af-9661-98ea0f7edc07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402720835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1402720835
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3193315871
Short name T718
Test name
Test status
Simulation time 4389531381 ps
CPU time 32.9 seconds
Started Mar 17 12:35:40 PM PDT 24
Finished Mar 17 12:36:14 PM PDT 24
Peak memory 199776 kb
Host smart-817cab8b-36eb-4547-9153-e645c3e2a5d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193315871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3193315871
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2237107692
Short name T436
Test name
Test status
Simulation time 386468596097 ps
CPU time 66.66 seconds
Started Mar 17 12:35:48 PM PDT 24
Finished Mar 17 12:36:55 PM PDT 24
Peak memory 199952 kb
Host smart-4e9a10b5-3187-495e-98bc-eabb2f027b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237107692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2237107692
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.968738914
Short name T880
Test name
Test status
Simulation time 4089631577 ps
CPU time 6.26 seconds
Started Mar 17 12:35:49 PM PDT 24
Finished Mar 17 12:35:55 PM PDT 24
Peak memory 196040 kb
Host smart-f395f45f-191b-40d5-80ae-bb820dbab059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968738914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.968738914
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.915241833
Short name T278
Test name
Test status
Simulation time 6285998195 ps
CPU time 16.46 seconds
Started Mar 17 12:35:42 PM PDT 24
Finished Mar 17 12:35:59 PM PDT 24
Peak memory 199672 kb
Host smart-12648202-cbda-4eb6-acd3-e115f9219f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915241833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.915241833
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1199673055
Short name T600
Test name
Test status
Simulation time 173903545813 ps
CPU time 193.18 seconds
Started Mar 17 12:35:53 PM PDT 24
Finished Mar 17 12:39:06 PM PDT 24
Peak memory 200012 kb
Host smart-f53132d2-b738-4b96-b2fb-bc08ce9ff921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199673055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1199673055
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3980946623
Short name T509
Test name
Test status
Simulation time 8951165440 ps
CPU time 9.57 seconds
Started Mar 17 12:35:48 PM PDT 24
Finished Mar 17 12:35:58 PM PDT 24
Peak memory 199836 kb
Host smart-3b8cf773-c84c-48be-8157-0a4520317c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980946623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3980946623
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3884500672
Short name T284
Test name
Test status
Simulation time 24359379501 ps
CPU time 6.74 seconds
Started Mar 17 12:35:42 PM PDT 24
Finished Mar 17 12:35:49 PM PDT 24
Peak memory 199956 kb
Host smart-fe967a72-29d4-49cb-809e-c10e83a18833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884500672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3884500672
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3998811426
Short name T388
Test name
Test status
Simulation time 30615323047 ps
CPU time 47.57 seconds
Started Mar 17 12:39:00 PM PDT 24
Finished Mar 17 12:39:48 PM PDT 24
Peak memory 199832 kb
Host smart-37ddbf15-51f7-4e5d-b72d-ff69e64f5a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998811426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3998811426
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3131275852
Short name T808
Test name
Test status
Simulation time 104848282831 ps
CPU time 178.99 seconds
Started Mar 17 12:39:02 PM PDT 24
Finished Mar 17 12:42:01 PM PDT 24
Peak memory 199976 kb
Host smart-437b9275-d728-4bce-b082-b65e3a505890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131275852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3131275852
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2521120651
Short name T833
Test name
Test status
Simulation time 44213489331 ps
CPU time 33.33 seconds
Started Mar 17 12:39:01 PM PDT 24
Finished Mar 17 12:39:35 PM PDT 24
Peak memory 199992 kb
Host smart-a3a32146-f039-4aed-87ef-80207602f9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521120651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2521120651
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2020318238
Short name T230
Test name
Test status
Simulation time 186293359640 ps
CPU time 90.73 seconds
Started Mar 17 12:39:07 PM PDT 24
Finished Mar 17 12:40:38 PM PDT 24
Peak memory 199968 kb
Host smart-8b996d42-b28e-4a76-8139-033c238c4e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020318238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2020318238
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3292840687
Short name T827
Test name
Test status
Simulation time 196661717318 ps
CPU time 170.39 seconds
Started Mar 17 12:39:00 PM PDT 24
Finished Mar 17 12:41:50 PM PDT 24
Peak memory 199884 kb
Host smart-04eb3d81-555d-4ed9-8864-f9ffa92e7a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292840687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3292840687
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2704329617
Short name T197
Test name
Test status
Simulation time 39811616666 ps
CPU time 75.58 seconds
Started Mar 17 12:39:00 PM PDT 24
Finished Mar 17 12:40:16 PM PDT 24
Peak memory 200024 kb
Host smart-953eb81c-be8e-4253-a53b-84aa5326666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704329617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2704329617
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3202470233
Short name T249
Test name
Test status
Simulation time 177551893390 ps
CPU time 59.59 seconds
Started Mar 17 12:39:01 PM PDT 24
Finished Mar 17 12:40:01 PM PDT 24
Peak memory 200016 kb
Host smart-719f32e8-6d01-41b7-b49d-bfbb15055803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202470233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3202470233
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3678678472
Short name T601
Test name
Test status
Simulation time 9712093876 ps
CPU time 11.32 seconds
Started Mar 17 12:38:59 PM PDT 24
Finished Mar 17 12:39:11 PM PDT 24
Peak memory 199980 kb
Host smart-7434fde4-6677-427f-bd25-81ee67e44b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678678472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3678678472
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2963594370
Short name T346
Test name
Test status
Simulation time 16866448 ps
CPU time 0.54 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:35:59 PM PDT 24
Peak memory 194864 kb
Host smart-d3e7e652-656c-49aa-bfc8-9a5529cb508c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963594370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2963594370
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1453389555
Short name T735
Test name
Test status
Simulation time 42706717486 ps
CPU time 21.8 seconds
Started Mar 17 12:35:49 PM PDT 24
Finished Mar 17 12:36:11 PM PDT 24
Peak memory 200024 kb
Host smart-2976a9d6-cecb-42ae-9110-03108f871ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453389555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1453389555
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3010008238
Short name T653
Test name
Test status
Simulation time 71936288081 ps
CPU time 50.15 seconds
Started Mar 17 12:35:48 PM PDT 24
Finished Mar 17 12:36:38 PM PDT 24
Peak memory 200080 kb
Host smart-fa20f8cc-20f4-4789-9181-4ac8524fc77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010008238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3010008238
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3651293715
Short name T850
Test name
Test status
Simulation time 143356062130 ps
CPU time 217.39 seconds
Started Mar 17 12:35:47 PM PDT 24
Finished Mar 17 12:39:25 PM PDT 24
Peak memory 199940 kb
Host smart-c3da3cb5-35d3-4a1e-b169-4124c17b4854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651293715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3651293715
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3432520394
Short name T339
Test name
Test status
Simulation time 52094258938 ps
CPU time 38.64 seconds
Started Mar 17 12:35:48 PM PDT 24
Finished Mar 17 12:36:27 PM PDT 24
Peak memory 200120 kb
Host smart-2bb6e693-82b9-4474-906f-8f1b4464a8db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432520394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3432520394
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.642154644
Short name T504
Test name
Test status
Simulation time 97799508107 ps
CPU time 100.26 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:37:39 PM PDT 24
Peak memory 199944 kb
Host smart-cb02b22f-c137-47bd-b3d4-629272bd619e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642154644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.642154644
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1124051209
Short name T854
Test name
Test status
Simulation time 4461546484 ps
CPU time 6.64 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:36:04 PM PDT 24
Peak memory 199524 kb
Host smart-5c9f1519-a51c-4c5a-bfd0-b995ea6429f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124051209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1124051209
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3718978509
Short name T845
Test name
Test status
Simulation time 49964009895 ps
CPU time 25.82 seconds
Started Mar 17 12:35:47 PM PDT 24
Finished Mar 17 12:36:13 PM PDT 24
Peak memory 200132 kb
Host smart-cbb8df4e-a021-4d19-a42f-8df6f14e6569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718978509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3718978509
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.614300290
Short name T299
Test name
Test status
Simulation time 2007901181 ps
CPU time 116.11 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 199888 kb
Host smart-e8f71577-fd4f-46c5-af96-800a4658d378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614300290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.614300290
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1557661463
Short name T372
Test name
Test status
Simulation time 6204748534 ps
CPU time 9.15 seconds
Started Mar 17 12:35:48 PM PDT 24
Finished Mar 17 12:35:57 PM PDT 24
Peak memory 198932 kb
Host smart-0922a1ce-04dc-4362-a206-b030d910126c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557661463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1557661463
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3657268533
Short name T323
Test name
Test status
Simulation time 80170285784 ps
CPU time 75.51 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:37:15 PM PDT 24
Peak memory 199948 kb
Host smart-c3bcb078-fb03-44e8-90f7-6e2f68ed58cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657268533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3657268533
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.740802272
Short name T542
Test name
Test status
Simulation time 25621946112 ps
CPU time 34.67 seconds
Started Mar 17 12:35:52 PM PDT 24
Finished Mar 17 12:36:27 PM PDT 24
Peak memory 196084 kb
Host smart-8b1fa680-d738-41fb-b797-ff26bfa7555c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740802272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.740802272
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1478629145
Short name T116
Test name
Test status
Simulation time 305803620 ps
CPU time 0.96 seconds
Started Mar 17 12:35:49 PM PDT 24
Finished Mar 17 12:35:51 PM PDT 24
Peak memory 198528 kb
Host smart-212ba5cf-f65a-4a9f-b928-720a929b8fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478629145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1478629145
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3979235095
Short name T752
Test name
Test status
Simulation time 2690459104 ps
CPU time 1.87 seconds
Started Mar 17 12:35:57 PM PDT 24
Finished Mar 17 12:35:59 PM PDT 24
Peak memory 198580 kb
Host smart-71a1956d-2a7e-450c-a028-e8fb0b01d260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979235095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3979235095
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3057580060
Short name T704
Test name
Test status
Simulation time 106945328260 ps
CPU time 71.52 seconds
Started Mar 17 12:35:47 PM PDT 24
Finished Mar 17 12:36:59 PM PDT 24
Peak memory 200024 kb
Host smart-406e733e-7ac4-4d8c-ac9d-8ec3aded7ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057580060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3057580060
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2070037525
Short name T1093
Test name
Test status
Simulation time 52104565033 ps
CPU time 20.41 seconds
Started Mar 17 12:39:03 PM PDT 24
Finished Mar 17 12:39:23 PM PDT 24
Peak memory 199992 kb
Host smart-4b92dbe3-3e76-4200-a315-9fb8a1400f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070037525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2070037525
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1397803092
Short name T192
Test name
Test status
Simulation time 175387565880 ps
CPU time 257.74 seconds
Started Mar 17 12:39:00 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 200088 kb
Host smart-a255cc5b-d570-4efc-b4ee-2748d12b7e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397803092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1397803092
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2069745880
Short name T201
Test name
Test status
Simulation time 19726309112 ps
CPU time 34.4 seconds
Started Mar 17 12:39:00 PM PDT 24
Finished Mar 17 12:39:35 PM PDT 24
Peak memory 200052 kb
Host smart-7abe5d6f-fdc1-4c70-999f-f6eb5625b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069745880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2069745880
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3792635197
Short name T1081
Test name
Test status
Simulation time 109760060783 ps
CPU time 9.97 seconds
Started Mar 17 12:39:00 PM PDT 24
Finished Mar 17 12:39:10 PM PDT 24
Peak memory 199724 kb
Host smart-bb8aca40-3613-4aba-b9a5-296c8d97c7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792635197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3792635197
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.907961181
Short name T803
Test name
Test status
Simulation time 56930428184 ps
CPU time 70.81 seconds
Started Mar 17 12:39:02 PM PDT 24
Finished Mar 17 12:40:13 PM PDT 24
Peak memory 200024 kb
Host smart-e7312a55-879b-497a-a251-52d7be733391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907961181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.907961181
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.4160952026
Short name T298
Test name
Test status
Simulation time 25896947460 ps
CPU time 39.24 seconds
Started Mar 17 12:39:02 PM PDT 24
Finished Mar 17 12:39:41 PM PDT 24
Peak memory 200084 kb
Host smart-975da9b0-5263-4838-b02e-450795be4500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160952026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4160952026
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.492509745
Short name T130
Test name
Test status
Simulation time 98987864126 ps
CPU time 183.96 seconds
Started Mar 17 12:38:59 PM PDT 24
Finished Mar 17 12:42:03 PM PDT 24
Peak memory 199928 kb
Host smart-1ad86681-bf4d-4ee7-a11d-713d6bc12211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492509745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.492509745
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.108639650
Short name T606
Test name
Test status
Simulation time 5304595841 ps
CPU time 7.96 seconds
Started Mar 17 12:39:03 PM PDT 24
Finished Mar 17 12:39:12 PM PDT 24
Peak memory 199292 kb
Host smart-4e5f0834-4f5e-4a80-8c43-bc95f23111ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108639650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.108639650
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2578976757
Short name T958
Test name
Test status
Simulation time 33861222036 ps
CPU time 15.49 seconds
Started Mar 17 12:39:00 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 199936 kb
Host smart-99a95627-b4b9-4c4e-b034-5c69603178da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578976757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2578976757
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1923613097
Short name T28
Test name
Test status
Simulation time 11821684 ps
CPU time 0.54 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:35:59 PM PDT 24
Peak memory 195452 kb
Host smart-486d41de-5da3-487b-9e23-5385de191fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923613097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1923613097
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1669899020
Short name T1074
Test name
Test status
Simulation time 105668313501 ps
CPU time 162.82 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:38:42 PM PDT 24
Peak memory 200020 kb
Host smart-53a00a6c-61ac-4170-a62e-f08235d866a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669899020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1669899020
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1712285135
Short name T673
Test name
Test status
Simulation time 57017413448 ps
CPU time 19.33 seconds
Started Mar 17 12:35:57 PM PDT 24
Finished Mar 17 12:36:17 PM PDT 24
Peak memory 199516 kb
Host smart-e2833bed-e142-4630-b754-86b405fa1e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712285135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1712285135
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.583932341
Short name T555
Test name
Test status
Simulation time 154640236012 ps
CPU time 333.61 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:41:31 PM PDT 24
Peak memory 200092 kb
Host smart-c539816d-6dd9-4be1-8a5b-b065e972a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583932341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.583932341
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.949277918
Short name T690
Test name
Test status
Simulation time 179601084686 ps
CPU time 281.28 seconds
Started Mar 17 12:36:00 PM PDT 24
Finished Mar 17 12:40:41 PM PDT 24
Peak memory 199928 kb
Host smart-9d5e37e0-e34e-401d-9f3d-ba36877313a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949277918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.949277918
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2058672863
Short name T1094
Test name
Test status
Simulation time 66682287432 ps
CPU time 154.12 seconds
Started Mar 17 12:36:00 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 200004 kb
Host smart-c327a878-9af1-40dc-bc8b-47f5cbe7cef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058672863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2058672863
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1000229608
Short name T914
Test name
Test status
Simulation time 5285260868 ps
CPU time 11.9 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:36:10 PM PDT 24
Peak memory 200180 kb
Host smart-56f5c7e7-db02-4612-80b7-f3c6acfcae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000229608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1000229608
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.23121030
Short name T475
Test name
Test status
Simulation time 76313317203 ps
CPU time 190.29 seconds
Started Mar 17 12:36:01 PM PDT 24
Finished Mar 17 12:39:11 PM PDT 24
Peak memory 200032 kb
Host smart-4e6fb28f-e0cc-4617-86ed-8cfe521c5fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23121030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.23121030
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2937630136
Short name T607
Test name
Test status
Simulation time 5741152722 ps
CPU time 150.64 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:38:30 PM PDT 24
Peak memory 200000 kb
Host smart-11ec8eda-3586-459b-9bfa-ea24cbd77869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937630136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2937630136
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1679128999
Short name T846
Test name
Test status
Simulation time 5669653811 ps
CPU time 11.32 seconds
Started Mar 17 12:36:00 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 199188 kb
Host smart-5f90599b-6230-4a8a-9788-11f340080b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679128999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1679128999
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1940672143
Short name T1069
Test name
Test status
Simulation time 204090016597 ps
CPU time 54.59 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:36:52 PM PDT 24
Peak memory 199912 kb
Host smart-c4103705-b485-4b44-855e-24afd0dea6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940672143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1940672143
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.319563940
Short name T896
Test name
Test status
Simulation time 524196925 ps
CPU time 1.54 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:36:01 PM PDT 24
Peak memory 195644 kb
Host smart-d446055f-6cb1-4708-8459-dbe1f346b689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319563940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.319563940
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1588000084
Short name T585
Test name
Test status
Simulation time 643103277 ps
CPU time 1.42 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:35:59 PM PDT 24
Peak memory 198320 kb
Host smart-6a7a330a-f395-4988-beb0-afe675af5a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588000084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1588000084
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3983177602
Short name T540
Test name
Test status
Simulation time 78770995687 ps
CPU time 1265.91 seconds
Started Mar 17 12:35:57 PM PDT 24
Finished Mar 17 12:57:03 PM PDT 24
Peak memory 200124 kb
Host smart-20080404-f1ba-4fd3-9605-9cd11fae7e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983177602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3983177602
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3126935156
Short name T104
Test name
Test status
Simulation time 25167697396 ps
CPU time 230.61 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:39:50 PM PDT 24
Peak memory 216476 kb
Host smart-3f9f2759-d811-4f4f-a1dc-a6856296f88e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126935156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3126935156
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1594367895
Short name T283
Test name
Test status
Simulation time 1235310287 ps
CPU time 2.11 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:36:01 PM PDT 24
Peak memory 198644 kb
Host smart-d90ef660-3ca8-47f2-bd1b-1a5ed498597d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594367895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1594367895
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3202383617
Short name T468
Test name
Test status
Simulation time 11617234293 ps
CPU time 5.47 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:36:05 PM PDT 24
Peak memory 198392 kb
Host smart-dc8142ab-e35b-4fb8-b7b5-e49f4c108b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202383617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3202383617
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.478182733
Short name T884
Test name
Test status
Simulation time 119358923165 ps
CPU time 210.85 seconds
Started Mar 17 12:39:01 PM PDT 24
Finished Mar 17 12:42:32 PM PDT 24
Peak memory 199932 kb
Host smart-3203f1c7-2262-4bb1-b255-3aac1d61a23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478182733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.478182733
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2533499637
Short name T923
Test name
Test status
Simulation time 65405625137 ps
CPU time 111.39 seconds
Started Mar 17 12:39:01 PM PDT 24
Finished Mar 17 12:40:53 PM PDT 24
Peak memory 199964 kb
Host smart-1332ed56-b470-442e-a9ec-8fe462661e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533499637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2533499637
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.674743489
Short name T1070
Test name
Test status
Simulation time 26319119965 ps
CPU time 47.3 seconds
Started Mar 17 12:39:07 PM PDT 24
Finished Mar 17 12:39:55 PM PDT 24
Peak memory 199940 kb
Host smart-2917d622-df80-4e0d-ace2-d507a9b72bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674743489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.674743489
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2869421336
Short name T811
Test name
Test status
Simulation time 86092532371 ps
CPU time 146.43 seconds
Started Mar 17 12:39:08 PM PDT 24
Finished Mar 17 12:41:35 PM PDT 24
Peak memory 200060 kb
Host smart-66f1ca3d-8bf1-412c-bffc-c683dbbde1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869421336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2869421336
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3055055008
Short name T185
Test name
Test status
Simulation time 71145445531 ps
CPU time 105.54 seconds
Started Mar 17 12:39:08 PM PDT 24
Finished Mar 17 12:40:54 PM PDT 24
Peak memory 200012 kb
Host smart-a4cfbba4-1969-4200-a6de-ed51500e8b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055055008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3055055008
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1481230767
Short name T205
Test name
Test status
Simulation time 75439866268 ps
CPU time 105.79 seconds
Started Mar 17 12:39:09 PM PDT 24
Finished Mar 17 12:40:55 PM PDT 24
Peak memory 199980 kb
Host smart-6c9ed485-e2d2-4810-a5e5-c2a505341b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481230767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1481230767
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3766652725
Short name T1102
Test name
Test status
Simulation time 214378553361 ps
CPU time 98.28 seconds
Started Mar 17 12:39:07 PM PDT 24
Finished Mar 17 12:40:46 PM PDT 24
Peak memory 200128 kb
Host smart-650170ab-0ce4-479c-a063-b724fb8dcc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766652725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3766652725
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1941830969
Short name T188
Test name
Test status
Simulation time 147283246333 ps
CPU time 23.67 seconds
Started Mar 17 12:39:08 PM PDT 24
Finished Mar 17 12:39:32 PM PDT 24
Peak memory 199968 kb
Host smart-7913c836-4ae8-4491-909d-e1934771084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941830969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1941830969
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2025195770
Short name T559
Test name
Test status
Simulation time 21104806256 ps
CPU time 32.03 seconds
Started Mar 17 12:39:10 PM PDT 24
Finished Mar 17 12:39:42 PM PDT 24
Peak memory 199992 kb
Host smart-c18057e1-913d-4823-a182-cbd006f7db8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025195770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2025195770
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2677908266
Short name T638
Test name
Test status
Simulation time 37217495 ps
CPU time 0.56 seconds
Started Mar 17 12:36:07 PM PDT 24
Finished Mar 17 12:36:08 PM PDT 24
Peak memory 195440 kb
Host smart-ab738874-587e-4192-b6b5-0a6caa6af293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677908266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2677908266
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.804070975
Short name T1049
Test name
Test status
Simulation time 186494764455 ps
CPU time 46.09 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:36:44 PM PDT 24
Peak memory 199908 kb
Host smart-18fc2902-bcd6-4005-ac5a-6136135fa0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804070975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.804070975
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3212812883
Short name T712
Test name
Test status
Simulation time 94361590204 ps
CPU time 79.29 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:37:17 PM PDT 24
Peak memory 199904 kb
Host smart-fdea8c0b-2a14-4380-85f0-ddf9ae0b540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212812883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3212812883
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.182130757
Short name T785
Test name
Test status
Simulation time 56214153707 ps
CPU time 51.44 seconds
Started Mar 17 12:35:56 PM PDT 24
Finished Mar 17 12:36:48 PM PDT 24
Peak memory 199988 kb
Host smart-4a0c1a49-8946-4a59-832a-bfef9ac4afb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182130757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.182130757
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4147256189
Short name T1090
Test name
Test status
Simulation time 19252402684 ps
CPU time 10.04 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:36:09 PM PDT 24
Peak memory 200116 kb
Host smart-89b48ce6-9662-4e0f-8f98-7e3de92141e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147256189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4147256189
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2268065106
Short name T800
Test name
Test status
Simulation time 340026838713 ps
CPU time 129.77 seconds
Started Mar 17 12:36:06 PM PDT 24
Finished Mar 17 12:38:16 PM PDT 24
Peak memory 200040 kb
Host smart-ce2a0e16-efcc-48ea-80d3-515027aab06a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2268065106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2268065106
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1460835801
Short name T480
Test name
Test status
Simulation time 10726524999 ps
CPU time 7.85 seconds
Started Mar 17 12:36:07 PM PDT 24
Finished Mar 17 12:36:16 PM PDT 24
Peak memory 198416 kb
Host smart-790a73b5-8bb5-41f7-99e8-b2f80aba7d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460835801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1460835801
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1633098937
Short name T874
Test name
Test status
Simulation time 41584118420 ps
CPU time 37.21 seconds
Started Mar 17 12:36:05 PM PDT 24
Finished Mar 17 12:36:42 PM PDT 24
Peak memory 200080 kb
Host smart-3705d49f-b05b-4103-8cfb-562ec0700b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633098937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1633098937
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.443590082
Short name T51
Test name
Test status
Simulation time 7782604054 ps
CPU time 107.81 seconds
Started Mar 17 12:36:05 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 200020 kb
Host smart-3540e2e0-65aa-42ea-927d-5b0d84a31a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443590082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.443590082
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.95151427
Short name T13
Test name
Test status
Simulation time 3136824417 ps
CPU time 21.84 seconds
Started Mar 17 12:35:59 PM PDT 24
Finished Mar 17 12:36:21 PM PDT 24
Peak memory 198180 kb
Host smart-7eb48cd5-e5e1-4005-bd4b-6bcbd970eec3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95151427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.95151427
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2110679198
Short name T724
Test name
Test status
Simulation time 118485847985 ps
CPU time 48.91 seconds
Started Mar 17 12:36:06 PM PDT 24
Finished Mar 17 12:36:55 PM PDT 24
Peak memory 199960 kb
Host smart-a8f34d12-a566-4993-8dcc-03783e57a0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110679198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2110679198
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2450681268
Short name T828
Test name
Test status
Simulation time 39837005772 ps
CPU time 31.71 seconds
Started Mar 17 12:36:06 PM PDT 24
Finished Mar 17 12:36:38 PM PDT 24
Peak memory 195888 kb
Host smart-5074e884-2d3d-456b-97e1-d32cae63c171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450681268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2450681268
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.510830972
Short name T1002
Test name
Test status
Simulation time 553034891 ps
CPU time 2.39 seconds
Started Mar 17 12:36:00 PM PDT 24
Finished Mar 17 12:36:02 PM PDT 24
Peak memory 198256 kb
Host smart-cc1f4023-c4bd-443c-ba96-bd4b6856a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510830972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.510830972
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2708049280
Short name T204
Test name
Test status
Simulation time 229303671351 ps
CPU time 832.34 seconds
Started Mar 17 12:36:11 PM PDT 24
Finished Mar 17 12:50:04 PM PDT 24
Peak memory 200048 kb
Host smart-d1157175-2f30-46fd-9931-b1cd806d21d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708049280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2708049280
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2467320808
Short name T605
Test name
Test status
Simulation time 244372620707 ps
CPU time 614.46 seconds
Started Mar 17 12:36:04 PM PDT 24
Finished Mar 17 12:46:19 PM PDT 24
Peak memory 216344 kb
Host smart-e091c8c8-785a-49d1-a6df-8c30e146e306
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467320808 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2467320808
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2532222184
Short name T375
Test name
Test status
Simulation time 1189929305 ps
CPU time 1.28 seconds
Started Mar 17 12:36:09 PM PDT 24
Finished Mar 17 12:36:11 PM PDT 24
Peak memory 197184 kb
Host smart-f5346290-26ad-48ed-8de8-4ba89a04785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532222184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2532222184
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1813998707
Short name T590
Test name
Test status
Simulation time 20664447907 ps
CPU time 36.71 seconds
Started Mar 17 12:35:58 PM PDT 24
Finished Mar 17 12:36:35 PM PDT 24
Peak memory 199928 kb
Host smart-9728e2b9-92cb-4f7f-92b2-29da40d86b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813998707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1813998707
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3563510007
Short name T574
Test name
Test status
Simulation time 178374921735 ps
CPU time 75.51 seconds
Started Mar 17 12:39:07 PM PDT 24
Finished Mar 17 12:40:23 PM PDT 24
Peak memory 199900 kb
Host smart-fd65cf03-8255-4fb8-96f4-741e98cc40b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563510007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3563510007
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3348133590
Short name T578
Test name
Test status
Simulation time 132384726849 ps
CPU time 238.16 seconds
Started Mar 17 12:39:10 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 199956 kb
Host smart-f7354d14-f517-4a61-935f-eb0ff792f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348133590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3348133590
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.394408624
Short name T807
Test name
Test status
Simulation time 167741247991 ps
CPU time 300.5 seconds
Started Mar 17 12:39:10 PM PDT 24
Finished Mar 17 12:44:11 PM PDT 24
Peak memory 199952 kb
Host smart-d621ca37-333a-4fe7-866a-e0cecef7d314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394408624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.394408624
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.231206272
Short name T159
Test name
Test status
Simulation time 6919861376 ps
CPU time 12.1 seconds
Started Mar 17 12:39:09 PM PDT 24
Finished Mar 17 12:39:22 PM PDT 24
Peak memory 199868 kb
Host smart-3115c357-f031-4f4d-b2e9-2159b4712b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231206272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.231206272
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.25145000
Short name T233
Test name
Test status
Simulation time 29720200441 ps
CPU time 50.2 seconds
Started Mar 17 12:39:11 PM PDT 24
Finished Mar 17 12:40:02 PM PDT 24
Peak memory 199940 kb
Host smart-a5942d3b-2d43-4132-a18a-3f873b24f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25145000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.25145000
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2971371575
Short name T976
Test name
Test status
Simulation time 107239404898 ps
CPU time 161.62 seconds
Started Mar 17 12:39:07 PM PDT 24
Finished Mar 17 12:41:49 PM PDT 24
Peak memory 199928 kb
Host smart-6dafd277-4c69-4b5b-ad0d-a6699feae836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971371575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2971371575
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3215882687
Short name T308
Test name
Test status
Simulation time 51824903115 ps
CPU time 16.99 seconds
Started Mar 17 12:39:11 PM PDT 24
Finished Mar 17 12:39:28 PM PDT 24
Peak memory 199940 kb
Host smart-3a5293c4-52de-43cf-afa3-c943c23d60c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215882687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3215882687
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3645825420
Short name T117
Test name
Test status
Simulation time 244595089309 ps
CPU time 343.4 seconds
Started Mar 17 12:39:07 PM PDT 24
Finished Mar 17 12:44:51 PM PDT 24
Peak memory 200052 kb
Host smart-33e8b3c0-77de-4cb8-afc3-6862b2809e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645825420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3645825420
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3188287304
Short name T1084
Test name
Test status
Simulation time 151236049767 ps
CPU time 70.26 seconds
Started Mar 17 12:39:09 PM PDT 24
Finished Mar 17 12:40:20 PM PDT 24
Peak memory 200016 kb
Host smart-704d3a31-a5f4-4d7a-be17-470ba7e6b9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188287304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3188287304
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3879289634
Short name T360
Test name
Test status
Simulation time 17067107629 ps
CPU time 30.47 seconds
Started Mar 17 12:39:17 PM PDT 24
Finished Mar 17 12:39:48 PM PDT 24
Peak memory 199984 kb
Host smart-c14fe09c-4902-4666-97a3-39f76d811042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879289634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3879289634
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3681395245
Short name T779
Test name
Test status
Simulation time 20472003 ps
CPU time 0.55 seconds
Started Mar 17 12:36:12 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 195496 kb
Host smart-fc35d236-b817-407d-9054-43ea323258e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681395245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3681395245
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3137100741
Short name T178
Test name
Test status
Simulation time 69450680557 ps
CPU time 32.59 seconds
Started Mar 17 12:36:07 PM PDT 24
Finished Mar 17 12:36:40 PM PDT 24
Peak memory 200008 kb
Host smart-9152739f-05aa-40bd-b08a-f6f81705a3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137100741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3137100741
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2571476039
Short name T169
Test name
Test status
Simulation time 255738942704 ps
CPU time 25.87 seconds
Started Mar 17 12:36:08 PM PDT 24
Finished Mar 17 12:36:34 PM PDT 24
Peak memory 199676 kb
Host smart-84ee98cd-1e64-4dc1-bc3d-8eb7100136ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571476039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2571476039
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.738283902
Short name T681
Test name
Test status
Simulation time 55233909019 ps
CPU time 97.61 seconds
Started Mar 17 12:36:08 PM PDT 24
Finished Mar 17 12:37:46 PM PDT 24
Peak memory 199856 kb
Host smart-e553f9b5-f29f-4393-9684-22c750307cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738283902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.738283902
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3828322825
Short name T534
Test name
Test status
Simulation time 129565877172 ps
CPU time 124.55 seconds
Started Mar 17 12:36:06 PM PDT 24
Finished Mar 17 12:38:10 PM PDT 24
Peak memory 199324 kb
Host smart-bf517f0c-1b7f-404e-922a-d0c5c7189ae1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828322825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3828322825
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1926423635
Short name T934
Test name
Test status
Simulation time 85001590719 ps
CPU time 238.92 seconds
Started Mar 17 12:36:08 PM PDT 24
Finished Mar 17 12:40:07 PM PDT 24
Peak memory 200032 kb
Host smart-eea54bce-faaf-42fb-93d6-e994bd6f205c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926423635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1926423635
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1933690020
Short name T805
Test name
Test status
Simulation time 4875068508 ps
CPU time 4.91 seconds
Started Mar 17 12:36:07 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 199288 kb
Host smart-3846ea34-271b-4b11-a9ca-0713cc355448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933690020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1933690020
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3085962214
Short name T734
Test name
Test status
Simulation time 30125065552 ps
CPU time 46.93 seconds
Started Mar 17 12:36:09 PM PDT 24
Finished Mar 17 12:36:56 PM PDT 24
Peak memory 198392 kb
Host smart-5d96c189-6cc0-4adb-bfe6-406381f2906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085962214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3085962214
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.458710934
Short name T872
Test name
Test status
Simulation time 10270534635 ps
CPU time 593.54 seconds
Started Mar 17 12:36:07 PM PDT 24
Finished Mar 17 12:46:01 PM PDT 24
Peak memory 200064 kb
Host smart-23e391a7-3cde-4c19-a076-831d5347049d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458710934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.458710934
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2391119261
Short name T380
Test name
Test status
Simulation time 1458981012 ps
CPU time 1.01 seconds
Started Mar 17 12:36:04 PM PDT 24
Finished Mar 17 12:36:05 PM PDT 24
Peak memory 198160 kb
Host smart-b822a77f-73bb-46af-b5e1-6286ca1b3005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391119261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2391119261
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2360711442
Short name T596
Test name
Test status
Simulation time 37610949239 ps
CPU time 23.16 seconds
Started Mar 17 12:36:05 PM PDT 24
Finished Mar 17 12:36:28 PM PDT 24
Peak memory 199844 kb
Host smart-e485ba6f-6d2a-4497-818d-edd31f219392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360711442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2360711442
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4021487548
Short name T935
Test name
Test status
Simulation time 1805672395 ps
CPU time 2.84 seconds
Started Mar 17 12:36:02 PM PDT 24
Finished Mar 17 12:36:05 PM PDT 24
Peak memory 195688 kb
Host smart-d15ade3f-1b46-47a6-9d5d-866412d870d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021487548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4021487548
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2948020831
Short name T766
Test name
Test status
Simulation time 5845777215 ps
CPU time 6.56 seconds
Started Mar 17 12:36:07 PM PDT 24
Finished Mar 17 12:36:14 PM PDT 24
Peak memory 199888 kb
Host smart-a5bb3a85-5a00-4b65-9c97-bc38f2166ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948020831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2948020831
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2127668241
Short name T397
Test name
Test status
Simulation time 544691061 ps
CPU time 1.53 seconds
Started Mar 17 12:36:05 PM PDT 24
Finished Mar 17 12:36:06 PM PDT 24
Peak memory 197824 kb
Host smart-dda29ad7-0365-4f33-b509-2dfd05976654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127668241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2127668241
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1981541466
Short name T945
Test name
Test status
Simulation time 1033450326 ps
CPU time 1.01 seconds
Started Mar 17 12:36:08 PM PDT 24
Finished Mar 17 12:36:10 PM PDT 24
Peak memory 197556 kb
Host smart-5dc707fb-0af4-403a-9628-b7cf4f605374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981541466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1981541466
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1514753951
Short name T401
Test name
Test status
Simulation time 49848072849 ps
CPU time 25.82 seconds
Started Mar 17 12:39:15 PM PDT 24
Finished Mar 17 12:39:41 PM PDT 24
Peak memory 200016 kb
Host smart-bb1544e6-300b-4853-badd-9630c7507f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514753951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1514753951
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.4153544884
Short name T373
Test name
Test status
Simulation time 15257285938 ps
CPU time 15.62 seconds
Started Mar 17 12:39:15 PM PDT 24
Finished Mar 17 12:39:31 PM PDT 24
Peak memory 200000 kb
Host smart-068fee6c-a9d4-4d53-bdf1-d6ee4f8133b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153544884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4153544884
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1765007246
Short name T174
Test name
Test status
Simulation time 172360986349 ps
CPU time 77.58 seconds
Started Mar 17 12:39:16 PM PDT 24
Finished Mar 17 12:40:34 PM PDT 24
Peak memory 200028 kb
Host smart-4c0e42aa-98f7-48b8-9bb1-321e34d5fec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765007246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1765007246
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3318776456
Short name T891
Test name
Test status
Simulation time 9526519674 ps
CPU time 16.29 seconds
Started Mar 17 12:39:19 PM PDT 24
Finished Mar 17 12:39:35 PM PDT 24
Peak memory 199880 kb
Host smart-396d4d0d-e963-4770-ab8b-22b722ea792e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318776456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3318776456
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2976169077
Short name T1009
Test name
Test status
Simulation time 346172242474 ps
CPU time 199.89 seconds
Started Mar 17 12:39:17 PM PDT 24
Finished Mar 17 12:42:37 PM PDT 24
Peak memory 199948 kb
Host smart-07413ec3-278e-4629-a187-bebb72f7d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976169077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2976169077
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1770252297
Short name T442
Test name
Test status
Simulation time 40341008179 ps
CPU time 42.65 seconds
Started Mar 17 12:39:18 PM PDT 24
Finished Mar 17 12:40:01 PM PDT 24
Peak memory 200016 kb
Host smart-2c48f349-5f85-4b6b-9300-d035cd97dd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770252297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1770252297
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.190592741
Short name T1047
Test name
Test status
Simulation time 85383468373 ps
CPU time 356.1 seconds
Started Mar 17 12:39:14 PM PDT 24
Finished Mar 17 12:45:11 PM PDT 24
Peak memory 199944 kb
Host smart-975ef1f7-7b59-4ee2-aa3a-7805884a3e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190592741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.190592741
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2715826856
Short name T933
Test name
Test status
Simulation time 15652318524 ps
CPU time 26.05 seconds
Started Mar 17 12:39:16 PM PDT 24
Finished Mar 17 12:39:42 PM PDT 24
Peak memory 200080 kb
Host smart-5145d3e0-1240-460f-8cc1-3a42968d98b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715826856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2715826856
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3891752715
Short name T940
Test name
Test status
Simulation time 228764742 ps
CPU time 0.59 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:34:08 PM PDT 24
Peak memory 195472 kb
Host smart-ae480023-b6dc-4c06-98d6-b1849073fd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891752715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3891752715
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1921424487
Short name T171
Test name
Test status
Simulation time 224766328606 ps
CPU time 90.41 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:35:35 PM PDT 24
Peak memory 200000 kb
Host smart-c0317e2b-bc18-4d7c-97f1-18b64f38e555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921424487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1921424487
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3459559426
Short name T649
Test name
Test status
Simulation time 226945849775 ps
CPU time 141.38 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:36:27 PM PDT 24
Peak memory 200000 kb
Host smart-76b2ee17-2652-4dc1-865e-e2c30e63768a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459559426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3459559426
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.603021655
Short name T646
Test name
Test status
Simulation time 46459912704 ps
CPU time 47.57 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:54 PM PDT 24
Peak memory 200032 kb
Host smart-5a7aaa95-30c2-4ac7-ad5b-38aa75df7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603021655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.603021655
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3158525939
Short name T674
Test name
Test status
Simulation time 44001010689 ps
CPU time 60.14 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:35:07 PM PDT 24
Peak memory 198748 kb
Host smart-4e8aeb83-1079-4393-beed-10a5cef16692
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158525939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3158525939
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.462099384
Short name T440
Test name
Test status
Simulation time 102356737940 ps
CPU time 493.22 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:42:18 PM PDT 24
Peak memory 199932 kb
Host smart-44802c4a-85dc-4ce0-9f66-5ef26314885c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462099384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.462099384
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2732165035
Short name T925
Test name
Test status
Simulation time 9196344565 ps
CPU time 6.42 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:34:10 PM PDT 24
Peak memory 199812 kb
Host smart-8d5abd2d-d5cc-43fe-bf9e-be03aec52367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732165035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2732165035
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.787299232
Short name T693
Test name
Test status
Simulation time 96716137219 ps
CPU time 58.82 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:35:05 PM PDT 24
Peak memory 200084 kb
Host smart-fac7a52c-fa82-4657-9899-704894648112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787299232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.787299232
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2603744884
Short name T502
Test name
Test status
Simulation time 32158667703 ps
CPU time 518.74 seconds
Started Mar 17 12:34:08 PM PDT 24
Finished Mar 17 12:42:47 PM PDT 24
Peak memory 200064 kb
Host smart-161dc356-20c3-439c-a685-26c6c6d3576f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603744884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2603744884
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.4093865895
Short name T820
Test name
Test status
Simulation time 6316863387 ps
CPU time 13.56 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:18 PM PDT 24
Peak memory 199076 kb
Host smart-d41e55e3-9661-4933-bf35-aa88dad02c3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093865895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.4093865895
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4040759114
Short name T267
Test name
Test status
Simulation time 59083947020 ps
CPU time 54.29 seconds
Started Mar 17 12:34:03 PM PDT 24
Finished Mar 17 12:34:58 PM PDT 24
Peak memory 200152 kb
Host smart-769bbfe7-5aea-43e2-bd46-f0c6e4238ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040759114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4040759114
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.680575866
Short name T570
Test name
Test status
Simulation time 4289563993 ps
CPU time 2.26 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:34:07 PM PDT 24
Peak memory 196304 kb
Host smart-aea1cda0-27dc-4fbb-8692-269da0f69ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680575866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.680575866
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3706980945
Short name T94
Test name
Test status
Simulation time 222196711 ps
CPU time 0.82 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:06 PM PDT 24
Peak memory 218492 kb
Host smart-3aad37b8-eacb-41c1-bfd1-1a7799bf6d07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706980945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3706980945
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.335422353
Short name T49
Test name
Test status
Simulation time 865402112 ps
CPU time 2.25 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:34:09 PM PDT 24
Peak memory 198824 kb
Host smart-fcfce2fa-43de-4126-846f-d98db252905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335422353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.335422353
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3192626838
Short name T633
Test name
Test status
Simulation time 384581366421 ps
CPU time 467.96 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:41:54 PM PDT 24
Peak memory 200028 kb
Host smart-c0e1286b-1966-46cb-9352-153d35219402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192626838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3192626838
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3091484451
Short name T331
Test name
Test status
Simulation time 44455862770 ps
CPU time 154.56 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:36:39 PM PDT 24
Peak memory 208240 kb
Host smart-26d12e82-04ab-4017-a072-783447d197df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091484451 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3091484451
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3263524774
Short name T961
Test name
Test status
Simulation time 7087714689 ps
CPU time 24.38 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:34:28 PM PDT 24
Peak memory 199700 kb
Host smart-01fd4c2c-6ecb-4709-b410-de9d3d61f7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263524774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3263524774
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2012236125
Short name T1006
Test name
Test status
Simulation time 55782233509 ps
CPU time 10.86 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:16 PM PDT 24
Peak memory 200084 kb
Host smart-1f632017-5c73-420e-b019-dfd5b956ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012236125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2012236125
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2031124435
Short name T694
Test name
Test status
Simulation time 21364228 ps
CPU time 0.51 seconds
Started Mar 17 12:36:11 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 195428 kb
Host smart-d9206dd9-bb69-4cb6-978d-c41d53aa96d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031124435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2031124435
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.4244243274
Short name T455
Test name
Test status
Simulation time 75507340422 ps
CPU time 36.45 seconds
Started Mar 17 12:36:14 PM PDT 24
Finished Mar 17 12:36:50 PM PDT 24
Peak memory 199944 kb
Host smart-8aa3e036-f55c-4963-8f13-e26f028fd5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244243274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4244243274
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3136533643
Short name T613
Test name
Test status
Simulation time 43307947443 ps
CPU time 19.8 seconds
Started Mar 17 12:36:16 PM PDT 24
Finished Mar 17 12:36:36 PM PDT 24
Peak memory 199880 kb
Host smart-a4347e8b-1e10-4cc8-b0a9-d423c5c35a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136533643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3136533643
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.405721165
Short name T476
Test name
Test status
Simulation time 232282197666 ps
CPU time 28.36 seconds
Started Mar 17 12:36:13 PM PDT 24
Finished Mar 17 12:36:42 PM PDT 24
Peak memory 200000 kb
Host smart-57e5c94d-5694-4c6d-a316-29605a56f210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405721165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.405721165
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2599178848
Short name T1066
Test name
Test status
Simulation time 176549445097 ps
CPU time 607.73 seconds
Started Mar 17 12:36:16 PM PDT 24
Finished Mar 17 12:46:24 PM PDT 24
Peak memory 199988 kb
Host smart-e42f2c72-8d37-474b-8f29-b0b2eaa13b5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599178848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2599178848
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.622174311
Short name T809
Test name
Test status
Simulation time 4257527304 ps
CPU time 4.63 seconds
Started Mar 17 12:36:14 PM PDT 24
Finished Mar 17 12:36:19 PM PDT 24
Peak memory 198776 kb
Host smart-55fa1cc5-c2e6-41e0-acb1-358aca1711e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622174311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.622174311
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2067188234
Short name T320
Test name
Test status
Simulation time 103854762089 ps
CPU time 185.92 seconds
Started Mar 17 12:36:15 PM PDT 24
Finished Mar 17 12:39:21 PM PDT 24
Peak memory 199024 kb
Host smart-d2879503-672b-4e84-b0ba-6320d3b85104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067188234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2067188234
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.282831773
Short name T1099
Test name
Test status
Simulation time 5598500572 ps
CPU time 157.48 seconds
Started Mar 17 12:36:13 PM PDT 24
Finished Mar 17 12:38:50 PM PDT 24
Peak memory 199936 kb
Host smart-0b3bb5fc-1640-431d-8388-60286bcb6b7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282831773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.282831773
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1162585685
Short name T960
Test name
Test status
Simulation time 6247980082 ps
CPU time 4.76 seconds
Started Mar 17 12:36:13 PM PDT 24
Finished Mar 17 12:36:18 PM PDT 24
Peak memory 198620 kb
Host smart-dab5b98f-2625-44c8-81bb-396735ef08c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162585685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1162585685
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1989906221
Short name T798
Test name
Test status
Simulation time 91306890820 ps
CPU time 72.84 seconds
Started Mar 17 12:36:11 PM PDT 24
Finished Mar 17 12:37:24 PM PDT 24
Peak memory 199988 kb
Host smart-9fe78236-6b77-4a1c-bd5d-22034a45c94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989906221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1989906221
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.502153033
Short name T302
Test name
Test status
Simulation time 7262152207 ps
CPU time 10.72 seconds
Started Mar 17 12:36:14 PM PDT 24
Finished Mar 17 12:36:25 PM PDT 24
Peak memory 196100 kb
Host smart-e36b2f3f-075e-4fb9-ac47-a5e1854c9fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502153033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.502153033
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3729865256
Short name T6
Test name
Test status
Simulation time 258932715 ps
CPU time 1.16 seconds
Started Mar 17 12:36:12 PM PDT 24
Finished Mar 17 12:36:13 PM PDT 24
Peak memory 198404 kb
Host smart-627a6aed-7582-45e0-8b6f-0f8bf6220dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729865256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3729865256
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3696971679
Short name T112
Test name
Test status
Simulation time 58934200494 ps
CPU time 156.62 seconds
Started Mar 17 12:36:17 PM PDT 24
Finished Mar 17 12:38:53 PM PDT 24
Peak memory 200056 kb
Host smart-2bca484f-9472-4163-a1e9-22f9ecf300fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696971679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3696971679
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1753425473
Short name T927
Test name
Test status
Simulation time 6925150343 ps
CPU time 5.33 seconds
Started Mar 17 12:36:14 PM PDT 24
Finished Mar 17 12:36:20 PM PDT 24
Peak memory 199856 kb
Host smart-75780cbe-dc5d-4354-8d0a-f235cdd0b10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753425473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1753425473
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1168635255
Short name T622
Test name
Test status
Simulation time 103340072508 ps
CPU time 57.97 seconds
Started Mar 17 12:36:12 PM PDT 24
Finished Mar 17 12:37:10 PM PDT 24
Peak memory 200016 kb
Host smart-5a447bd8-5532-43aa-9c75-ce7bd51aa142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168635255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1168635255
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3018423708
Short name T599
Test name
Test status
Simulation time 16938655 ps
CPU time 0.52 seconds
Started Mar 17 12:36:21 PM PDT 24
Finished Mar 17 12:36:22 PM PDT 24
Peak memory 195444 kb
Host smart-417bea2f-e6c8-4c20-a5b9-c8219add87ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018423708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3018423708
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.989782793
Short name T1062
Test name
Test status
Simulation time 101240988705 ps
CPU time 52.83 seconds
Started Mar 17 12:36:15 PM PDT 24
Finished Mar 17 12:37:08 PM PDT 24
Peak memory 199928 kb
Host smart-c5c9d76b-55ef-4eaf-9dec-9569d3977640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989782793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.989782793
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1961254744
Short name T641
Test name
Test status
Simulation time 63530148112 ps
CPU time 38.18 seconds
Started Mar 17 12:36:13 PM PDT 24
Finished Mar 17 12:36:52 PM PDT 24
Peak memory 199964 kb
Host smart-24cda69a-da7d-4877-b1fb-4623d091a7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961254744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1961254744
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.1502756051
Short name T554
Test name
Test status
Simulation time 41456422962 ps
CPU time 24.33 seconds
Started Mar 17 12:36:15 PM PDT 24
Finished Mar 17 12:36:39 PM PDT 24
Peak memory 198224 kb
Host smart-4775c913-316b-4741-9569-b2ce4c25dc24
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502756051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1502756051
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2986175415
Short name T615
Test name
Test status
Simulation time 161018111974 ps
CPU time 1147.78 seconds
Started Mar 17 12:36:22 PM PDT 24
Finished Mar 17 12:55:30 PM PDT 24
Peak memory 200048 kb
Host smart-7a03b75e-66d7-4f48-aa9f-d0d94a7dccf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986175415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2986175415
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.173792143
Short name T760
Test name
Test status
Simulation time 7648673130 ps
CPU time 13.26 seconds
Started Mar 17 12:36:14 PM PDT 24
Finished Mar 17 12:36:28 PM PDT 24
Peak memory 199392 kb
Host smart-11e3ae9f-17f8-44b1-b388-d7196794a10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173792143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.173792143
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3747300065
Short name T942
Test name
Test status
Simulation time 70470342715 ps
CPU time 91.8 seconds
Started Mar 17 12:36:14 PM PDT 24
Finished Mar 17 12:37:46 PM PDT 24
Peak memory 198396 kb
Host smart-a6bc6899-98c2-4667-bc40-39ded4a1f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747300065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3747300065
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2346744373
Short name T749
Test name
Test status
Simulation time 13831432981 ps
CPU time 188.92 seconds
Started Mar 17 12:36:21 PM PDT 24
Finished Mar 17 12:39:31 PM PDT 24
Peak memory 200000 kb
Host smart-1c7d8fd6-dedb-4a22-bfae-2b455dee4920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346744373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2346744373
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2477832825
Short name T716
Test name
Test status
Simulation time 1903864416 ps
CPU time 4.7 seconds
Started Mar 17 12:36:12 PM PDT 24
Finished Mar 17 12:36:17 PM PDT 24
Peak memory 197920 kb
Host smart-fa7dcd98-f4a2-4065-b528-c41b73218524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477832825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2477832825
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3918782808
Short name T132
Test name
Test status
Simulation time 224580293160 ps
CPU time 93.31 seconds
Started Mar 17 12:36:15 PM PDT 24
Finished Mar 17 12:37:49 PM PDT 24
Peak memory 199932 kb
Host smart-2f306fc4-6ae2-4970-be75-0b9a103ef382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918782808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3918782808
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1455449833
Short name T319
Test name
Test status
Simulation time 70143540314 ps
CPU time 62.13 seconds
Started Mar 17 12:36:14 PM PDT 24
Finished Mar 17 12:37:16 PM PDT 24
Peak memory 195796 kb
Host smart-951c3424-bb3e-4638-8e11-9126f5eff073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455449833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1455449833
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1598023142
Short name T258
Test name
Test status
Simulation time 839877370 ps
CPU time 2.99 seconds
Started Mar 17 12:36:14 PM PDT 24
Finished Mar 17 12:36:17 PM PDT 24
Peak memory 198216 kb
Host smart-53fcdf1e-9c23-42ce-a336-78208badf0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598023142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1598023142
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3199935777
Short name T537
Test name
Test status
Simulation time 99781534931 ps
CPU time 173.8 seconds
Started Mar 17 12:36:20 PM PDT 24
Finished Mar 17 12:39:14 PM PDT 24
Peak memory 200232 kb
Host smart-c8d324d9-7ba4-407b-9ad1-d501926304fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199935777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3199935777
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1004114385
Short name T930
Test name
Test status
Simulation time 5364643610 ps
CPU time 1.63 seconds
Started Mar 17 12:36:13 PM PDT 24
Finished Mar 17 12:36:14 PM PDT 24
Peak memory 199344 kb
Host smart-14ada313-ebb4-43c8-8657-fa8988d0ae11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004114385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1004114385
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3662077278
Short name T802
Test name
Test status
Simulation time 75448789036 ps
CPU time 34.89 seconds
Started Mar 17 12:36:13 PM PDT 24
Finished Mar 17 12:36:48 PM PDT 24
Peak memory 200024 kb
Host smart-198b9f3d-aabf-46bf-a03d-16fafbb2633c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662077278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3662077278
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2691064999
Short name T30
Test name
Test status
Simulation time 36022221 ps
CPU time 0.54 seconds
Started Mar 17 12:36:22 PM PDT 24
Finished Mar 17 12:36:22 PM PDT 24
Peak memory 195456 kb
Host smart-969c9f4e-6b6d-482c-a90b-5973f6577c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691064999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2691064999
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2427103473
Short name T305
Test name
Test status
Simulation time 141337721182 ps
CPU time 35.25 seconds
Started Mar 17 12:36:21 PM PDT 24
Finished Mar 17 12:36:56 PM PDT 24
Peak memory 199928 kb
Host smart-d66dc804-70d6-4ca1-8a2a-6dac39293c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427103473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2427103473
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2044415352
Short name T635
Test name
Test status
Simulation time 39171910983 ps
CPU time 16.37 seconds
Started Mar 17 12:36:23 PM PDT 24
Finished Mar 17 12:36:39 PM PDT 24
Peak memory 199256 kb
Host smart-32ff0d0e-1710-4c0d-bb14-aa456b077f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044415352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2044415352
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2396493447
Short name T505
Test name
Test status
Simulation time 147045655033 ps
CPU time 20.44 seconds
Started Mar 17 12:36:20 PM PDT 24
Finished Mar 17 12:36:41 PM PDT 24
Peak memory 200128 kb
Host smart-4dfd59e6-a78c-41a1-a4f6-39c546310b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396493447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2396493447
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3883144749
Short name T900
Test name
Test status
Simulation time 55950365426 ps
CPU time 49.92 seconds
Started Mar 17 12:36:20 PM PDT 24
Finished Mar 17 12:37:10 PM PDT 24
Peak memory 200052 kb
Host smart-efb52e5b-5e57-4bec-976f-4639b4a9db3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883144749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3883144749
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.416473408
Short name T765
Test name
Test status
Simulation time 528191916512 ps
CPU time 124.54 seconds
Started Mar 17 12:36:22 PM PDT 24
Finished Mar 17 12:38:27 PM PDT 24
Peak memory 200044 kb
Host smart-1327d1e9-6a34-4b97-b5e8-1c49642f2f4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416473408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.416473408
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2700183454
Short name T356
Test name
Test status
Simulation time 8985678787 ps
CPU time 18.88 seconds
Started Mar 17 12:36:20 PM PDT 24
Finished Mar 17 12:36:39 PM PDT 24
Peak memory 200008 kb
Host smart-4339727a-3e61-4d91-8ac3-5ece1806289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700183454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2700183454
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1904067977
Short name T1101
Test name
Test status
Simulation time 339521578391 ps
CPU time 291.44 seconds
Started Mar 17 12:36:25 PM PDT 24
Finished Mar 17 12:41:17 PM PDT 24
Peak memory 199636 kb
Host smart-20d64792-c117-4f95-b735-179f65300430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904067977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1904067977
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.89325999
Short name T488
Test name
Test status
Simulation time 13615632420 ps
CPU time 615.59 seconds
Started Mar 17 12:36:19 PM PDT 24
Finished Mar 17 12:46:35 PM PDT 24
Peak memory 199940 kb
Host smart-1aba1712-adf6-4856-abe3-9b55aa650c2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89325999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.89325999
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1485937089
Short name T549
Test name
Test status
Simulation time 4924779421 ps
CPU time 9.9 seconds
Started Mar 17 12:36:24 PM PDT 24
Finished Mar 17 12:36:34 PM PDT 24
Peak memory 199220 kb
Host smart-9327fdc5-9810-414b-a802-b787d5dea1ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485937089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1485937089
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.741198075
Short name T595
Test name
Test status
Simulation time 119196154179 ps
CPU time 167.92 seconds
Started Mar 17 12:36:21 PM PDT 24
Finished Mar 17 12:39:09 PM PDT 24
Peak memory 200084 kb
Host smart-b3df34a2-8663-420b-a711-d8a6079e64a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741198075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.741198075
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2353384277
Short name T357
Test name
Test status
Simulation time 869686405 ps
CPU time 1.97 seconds
Started Mar 17 12:36:22 PM PDT 24
Finished Mar 17 12:36:25 PM PDT 24
Peak memory 195428 kb
Host smart-d6d825c1-f2c4-43f9-a477-c6da6615bbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353384277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2353384277
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2911375545
Short name T432
Test name
Test status
Simulation time 275352542 ps
CPU time 1.17 seconds
Started Mar 17 12:36:23 PM PDT 24
Finished Mar 17 12:36:24 PM PDT 24
Peak memory 199904 kb
Host smart-2cc794b4-b7b1-4ace-a52e-8ecfd7aee99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911375545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2911375545
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1615414433
Short name T318
Test name
Test status
Simulation time 152080232094 ps
CPU time 194.59 seconds
Started Mar 17 12:36:20 PM PDT 24
Finished Mar 17 12:39:35 PM PDT 24
Peak memory 200000 kb
Host smart-7c20659c-211c-49d3-b8b5-b8f5cd030e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615414433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1615414433
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3655127874
Short name T879
Test name
Test status
Simulation time 6585981129 ps
CPU time 19.57 seconds
Started Mar 17 12:36:22 PM PDT 24
Finished Mar 17 12:36:42 PM PDT 24
Peak memory 199408 kb
Host smart-48c50a1d-bc21-414e-93da-c55ea6eba701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655127874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3655127874
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2869265217
Short name T651
Test name
Test status
Simulation time 43560170489 ps
CPU time 11.7 seconds
Started Mar 17 12:36:21 PM PDT 24
Finished Mar 17 12:36:33 PM PDT 24
Peak memory 200112 kb
Host smart-f9e30790-4d63-4292-b37f-c16e665d86ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869265217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2869265217
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1444871267
Short name T457
Test name
Test status
Simulation time 73531475 ps
CPU time 0.54 seconds
Started Mar 17 12:36:33 PM PDT 24
Finished Mar 17 12:36:33 PM PDT 24
Peak memory 195460 kb
Host smart-d78b6a73-1ad5-418f-b6ed-4ad1f24bcc5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444871267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1444871267
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2603817016
Short name T127
Test name
Test status
Simulation time 91439170697 ps
CPU time 179.29 seconds
Started Mar 17 12:36:23 PM PDT 24
Finished Mar 17 12:39:22 PM PDT 24
Peak memory 199908 kb
Host smart-7e932765-b5f0-4497-82ac-bdbeb787252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603817016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2603817016
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3200542656
Short name T1020
Test name
Test status
Simulation time 76431253448 ps
CPU time 72.58 seconds
Started Mar 17 12:36:20 PM PDT 24
Finished Mar 17 12:37:33 PM PDT 24
Peak memory 199948 kb
Host smart-c9e5081b-cb93-429d-a0e6-6b8d6f0588a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200542656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3200542656
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.4015883159
Short name T1011
Test name
Test status
Simulation time 33559077070 ps
CPU time 51.77 seconds
Started Mar 17 12:36:33 PM PDT 24
Finished Mar 17 12:37:24 PM PDT 24
Peak memory 199992 kb
Host smart-d5a223cd-4883-4086-ac14-ed83aa8aab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015883159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.4015883159
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2231941548
Short name T758
Test name
Test status
Simulation time 169609920859 ps
CPU time 260.88 seconds
Started Mar 17 12:36:29 PM PDT 24
Finished Mar 17 12:40:50 PM PDT 24
Peak memory 198204 kb
Host smart-ca34a685-81c2-416b-8ea7-2704843969ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231941548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2231941548
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.347061722
Short name T684
Test name
Test status
Simulation time 86630766178 ps
CPU time 379.35 seconds
Started Mar 17 12:36:32 PM PDT 24
Finished Mar 17 12:42:52 PM PDT 24
Peak memory 200004 kb
Host smart-d335f0b8-2310-4fa3-8779-246f85d77e5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347061722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.347061722
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2534653714
Short name T101
Test name
Test status
Simulation time 7041928414 ps
CPU time 7.36 seconds
Started Mar 17 12:36:33 PM PDT 24
Finished Mar 17 12:36:40 PM PDT 24
Peak memory 199600 kb
Host smart-f80d9ef7-42fb-4399-8a8f-d86ce3ad3660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534653714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2534653714
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.426822558
Short name T1025
Test name
Test status
Simulation time 82742739621 ps
CPU time 35.47 seconds
Started Mar 17 12:36:33 PM PDT 24
Finished Mar 17 12:37:08 PM PDT 24
Peak memory 199012 kb
Host smart-314fe052-5951-40aa-9b82-5060540ae19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426822558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.426822558
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2087795816
Short name T44
Test name
Test status
Simulation time 13262610434 ps
CPU time 177.51 seconds
Started Mar 17 12:36:27 PM PDT 24
Finished Mar 17 12:39:25 PM PDT 24
Peak memory 199940 kb
Host smart-c015f14d-92f5-46f4-9684-e7ba66b94c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087795816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2087795816
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.762427581
Short name T472
Test name
Test status
Simulation time 5299961218 ps
CPU time 41.15 seconds
Started Mar 17 12:36:27 PM PDT 24
Finished Mar 17 12:37:09 PM PDT 24
Peak memory 198640 kb
Host smart-bc9dc1d6-6471-4f12-b1ce-70ce125c4d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762427581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.762427581
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1268786619
Short name T835
Test name
Test status
Simulation time 4353442338 ps
CPU time 7.65 seconds
Started Mar 17 12:36:28 PM PDT 24
Finished Mar 17 12:36:36 PM PDT 24
Peak memory 200008 kb
Host smart-e6ce51ad-4c0a-4ad8-88a2-499a802526cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268786619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1268786619
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.164146077
Short name T1085
Test name
Test status
Simulation time 3295496558 ps
CPU time 2.06 seconds
Started Mar 17 12:36:28 PM PDT 24
Finished Mar 17 12:36:30 PM PDT 24
Peak memory 196116 kb
Host smart-d362d817-d29c-46d1-8f4e-8afb0abffb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164146077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.164146077
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.11795072
Short name T1036
Test name
Test status
Simulation time 697725719 ps
CPU time 1.85 seconds
Started Mar 17 12:36:21 PM PDT 24
Finished Mar 17 12:36:23 PM PDT 24
Peak memory 198328 kb
Host smart-812b814f-3b2f-4043-b7e4-9e2d24ce6eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11795072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.11795072
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.4273954796
Short name T1001
Test name
Test status
Simulation time 212489827744 ps
CPU time 381.59 seconds
Started Mar 17 12:36:30 PM PDT 24
Finished Mar 17 12:42:52 PM PDT 24
Peak memory 200008 kb
Host smart-55118e15-f4a5-4cf6-937f-d962fc56357f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273954796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4273954796
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.987673656
Short name T656
Test name
Test status
Simulation time 8733926376 ps
CPU time 14.34 seconds
Started Mar 17 12:36:30 PM PDT 24
Finished Mar 17 12:36:45 PM PDT 24
Peak memory 199992 kb
Host smart-e2c04f96-f963-43b6-8ff0-ea3c98152cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987673656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.987673656
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2165124644
Short name T385
Test name
Test status
Simulation time 38545682338 ps
CPU time 64.77 seconds
Started Mar 17 12:36:20 PM PDT 24
Finished Mar 17 12:37:25 PM PDT 24
Peak memory 199900 kb
Host smart-2b0c689c-4b29-4da8-a3e6-8e08ceec7cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165124644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2165124644
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3972412710
Short name T903
Test name
Test status
Simulation time 10547601 ps
CPU time 0.57 seconds
Started Mar 17 12:36:31 PM PDT 24
Finished Mar 17 12:36:31 PM PDT 24
Peak memory 194916 kb
Host smart-faae5dbb-02cc-4184-b0b5-789b25f064d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972412710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3972412710
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1044706657
Short name T115
Test name
Test status
Simulation time 11538463642 ps
CPU time 19.67 seconds
Started Mar 17 12:36:33 PM PDT 24
Finished Mar 17 12:36:52 PM PDT 24
Peak memory 199356 kb
Host smart-fbcac68c-711c-4c99-9572-deed538f5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044706657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1044706657
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3525327003
Short name T755
Test name
Test status
Simulation time 19579919178 ps
CPU time 15.45 seconds
Started Mar 17 12:36:27 PM PDT 24
Finished Mar 17 12:36:43 PM PDT 24
Peak memory 199948 kb
Host smart-85bda5e0-5ba8-4f73-9a54-5fbb2cfa0787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525327003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3525327003
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3227914268
Short name T640
Test name
Test status
Simulation time 60223720638 ps
CPU time 60.01 seconds
Started Mar 17 12:36:30 PM PDT 24
Finished Mar 17 12:37:30 PM PDT 24
Peak memory 199768 kb
Host smart-2ae03619-f00f-45c3-8b29-7016d596774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227914268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3227914268
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1896242086
Short name T902
Test name
Test status
Simulation time 7825632574 ps
CPU time 9.63 seconds
Started Mar 17 12:36:29 PM PDT 24
Finished Mar 17 12:36:38 PM PDT 24
Peak memory 196072 kb
Host smart-6f0fcd3c-3091-4227-b3a6-fac7b54d1b62
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896242086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1896242086
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2301120322
Short name T583
Test name
Test status
Simulation time 124112793305 ps
CPU time 1095.4 seconds
Started Mar 17 12:36:32 PM PDT 24
Finished Mar 17 12:54:48 PM PDT 24
Peak memory 199948 kb
Host smart-fcaa65b7-8525-41cd-9e91-77341d125b89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301120322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2301120322
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2437555196
Short name T1111
Test name
Test status
Simulation time 6480071766 ps
CPU time 3.62 seconds
Started Mar 17 12:36:26 PM PDT 24
Finished Mar 17 12:36:30 PM PDT 24
Peak memory 199104 kb
Host smart-c832b3be-a88d-4cab-b00a-5e68eb73a5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437555196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2437555196
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1328702135
Short name T522
Test name
Test status
Simulation time 58327934802 ps
CPU time 99.79 seconds
Started Mar 17 12:36:30 PM PDT 24
Finished Mar 17 12:38:10 PM PDT 24
Peak memory 200080 kb
Host smart-5b021c5c-8a5e-4f8c-a19b-31b263ec82a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328702135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1328702135
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1463204873
Short name T1088
Test name
Test status
Simulation time 9631031532 ps
CPU time 463.25 seconds
Started Mar 17 12:36:28 PM PDT 24
Finished Mar 17 12:44:11 PM PDT 24
Peak memory 200120 kb
Host smart-7d61b73e-ea4e-4837-82ec-bfc6fe20825d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463204873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1463204873
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1930726445
Short name T1072
Test name
Test status
Simulation time 3134464070 ps
CPU time 12.45 seconds
Started Mar 17 12:36:28 PM PDT 24
Finished Mar 17 12:36:40 PM PDT 24
Peak memory 199004 kb
Host smart-9ef775db-c688-4d7d-964c-d67c6922deca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930726445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1930726445
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1924500035
Short name T274
Test name
Test status
Simulation time 37231935079 ps
CPU time 15.67 seconds
Started Mar 17 12:36:28 PM PDT 24
Finished Mar 17 12:36:44 PM PDT 24
Peak memory 199860 kb
Host smart-079d5eb0-4260-461b-aa18-7df3a932d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924500035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1924500035
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3285249801
Short name T23
Test name
Test status
Simulation time 2098947435 ps
CPU time 4.02 seconds
Started Mar 17 12:36:33 PM PDT 24
Finished Mar 17 12:36:37 PM PDT 24
Peak memory 195696 kb
Host smart-d7368915-ed3f-49c7-8569-497d151da9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285249801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3285249801
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3578438543
Short name T443
Test name
Test status
Simulation time 690083719 ps
CPU time 1.27 seconds
Started Mar 17 12:36:30 PM PDT 24
Finished Mar 17 12:36:31 PM PDT 24
Peak memory 198680 kb
Host smart-0b20aeb6-92c6-436e-90bd-8118f7322759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578438543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3578438543
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2341146179
Short name T1060
Test name
Test status
Simulation time 209792587111 ps
CPU time 1219.45 seconds
Started Mar 17 12:36:26 PM PDT 24
Finished Mar 17 12:56:46 PM PDT 24
Peak memory 215716 kb
Host smart-1da92f40-73f1-4b87-8e4c-178584d8e84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341146179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2341146179
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1089211509
Short name T637
Test name
Test status
Simulation time 19842685837 ps
CPU time 108.09 seconds
Started Mar 17 12:36:29 PM PDT 24
Finished Mar 17 12:38:17 PM PDT 24
Peak memory 208532 kb
Host smart-c22676a8-29c4-416a-bd2e-f499391949d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089211509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1089211509
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1196273117
Short name T423
Test name
Test status
Simulation time 689139969 ps
CPU time 2.25 seconds
Started Mar 17 12:36:30 PM PDT 24
Finished Mar 17 12:36:32 PM PDT 24
Peak memory 198768 kb
Host smart-3ed056e9-a116-4a56-9ba2-fe2a07fe5aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196273117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1196273117
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2001679502
Short name T663
Test name
Test status
Simulation time 77891366084 ps
CPU time 46.52 seconds
Started Mar 17 12:36:31 PM PDT 24
Finished Mar 17 12:37:18 PM PDT 24
Peak memory 199944 kb
Host smart-9eb6c2e8-eceb-49bf-9d87-c58bf0eb1b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001679502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2001679502
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3005041882
Short name T771
Test name
Test status
Simulation time 35156507 ps
CPU time 0.58 seconds
Started Mar 17 12:36:38 PM PDT 24
Finished Mar 17 12:36:39 PM PDT 24
Peak memory 195460 kb
Host smart-00ff48ad-e55e-4d29-a434-0bbdec2de893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005041882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3005041882
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.342786097
Short name T464
Test name
Test status
Simulation time 220409590430 ps
CPU time 396.82 seconds
Started Mar 17 12:36:31 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 199892 kb
Host smart-275bba4e-d3b1-494a-9a77-3581b9eee296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342786097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.342786097
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.957444573
Short name T426
Test name
Test status
Simulation time 105238593001 ps
CPU time 249.27 seconds
Started Mar 17 12:36:29 PM PDT 24
Finished Mar 17 12:40:38 PM PDT 24
Peak memory 200060 kb
Host smart-dff49e8d-2d83-4024-9de4-2be017ff8c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957444573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.957444573
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2808942012
Short name T193
Test name
Test status
Simulation time 223243649994 ps
CPU time 143.46 seconds
Started Mar 17 12:36:27 PM PDT 24
Finished Mar 17 12:38:51 PM PDT 24
Peak memory 199988 kb
Host smart-7e747db6-1577-49af-b267-603c9d1fca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808942012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2808942012
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1542725866
Short name T591
Test name
Test status
Simulation time 23894499401 ps
CPU time 18.1 seconds
Started Mar 17 12:36:34 PM PDT 24
Finished Mar 17 12:36:52 PM PDT 24
Peak memory 198428 kb
Host smart-d9d63c15-d9a0-4d19-a5de-838dda20d888
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542725866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1542725866
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3751639886
Short name T420
Test name
Test status
Simulation time 414264361374 ps
CPU time 333.64 seconds
Started Mar 17 12:36:34 PM PDT 24
Finished Mar 17 12:42:08 PM PDT 24
Peak memory 199952 kb
Host smart-ee7421ed-700a-4172-a342-ce6832bcbafc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751639886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3751639886
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.30244765
Short name T337
Test name
Test status
Simulation time 553487120 ps
CPU time 1.06 seconds
Started Mar 17 12:36:34 PM PDT 24
Finished Mar 17 12:36:35 PM PDT 24
Peak memory 195984 kb
Host smart-35ed39a5-9370-41dd-a1e7-3c42f5e32ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30244765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.30244765
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.888787394
Short name T742
Test name
Test status
Simulation time 80448181148 ps
CPU time 134.29 seconds
Started Mar 17 12:36:41 PM PDT 24
Finished Mar 17 12:38:56 PM PDT 24
Peak memory 199992 kb
Host smart-ec5cef09-8b57-4f87-9bdc-f7f47240528a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888787394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.888787394
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.438635699
Short name T573
Test name
Test status
Simulation time 15812544207 ps
CPU time 193.14 seconds
Started Mar 17 12:36:37 PM PDT 24
Finished Mar 17 12:39:50 PM PDT 24
Peak memory 200044 kb
Host smart-36f4fc05-7cc8-4e13-ade1-2099a06671f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438635699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.438635699
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.761080031
Short name T469
Test name
Test status
Simulation time 1375791320 ps
CPU time 2.84 seconds
Started Mar 17 12:36:35 PM PDT 24
Finished Mar 17 12:36:38 PM PDT 24
Peak memory 197880 kb
Host smart-371e201f-54c1-4a1a-b695-8ed96a484adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761080031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.761080031
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1314689864
Short name T775
Test name
Test status
Simulation time 81166910091 ps
CPU time 161.01 seconds
Started Mar 17 12:36:38 PM PDT 24
Finished Mar 17 12:39:19 PM PDT 24
Peak memory 199940 kb
Host smart-6b0b1c1f-2168-4b0d-8d17-aadf68921e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314689864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1314689864
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3222178830
Short name T897
Test name
Test status
Simulation time 7166212597 ps
CPU time 3.39 seconds
Started Mar 17 12:36:42 PM PDT 24
Finished Mar 17 12:36:46 PM PDT 24
Peak memory 196100 kb
Host smart-fbac0e18-cc6a-4ce0-bec5-9a47084d3c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222178830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3222178830
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1794571022
Short name T492
Test name
Test status
Simulation time 280672157 ps
CPU time 1.58 seconds
Started Mar 17 12:36:27 PM PDT 24
Finished Mar 17 12:36:29 PM PDT 24
Peak memory 198688 kb
Host smart-1f7036bc-6bdc-4e22-98e5-113bb7c69b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794571022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1794571022
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.488737192
Short name T57
Test name
Test status
Simulation time 1157667529 ps
CPU time 2.7 seconds
Started Mar 17 12:36:35 PM PDT 24
Finished Mar 17 12:36:38 PM PDT 24
Peak memory 198440 kb
Host smart-3aed1db6-8624-46b2-b29f-0dcf7c9e25e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488737192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.488737192
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2433586797
Short name T485
Test name
Test status
Simulation time 26413631330 ps
CPU time 12.49 seconds
Started Mar 17 12:36:28 PM PDT 24
Finished Mar 17 12:36:41 PM PDT 24
Peak memory 199864 kb
Host smart-4e332136-1794-4f70-af5b-df16683d64cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433586797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2433586797
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2767215612
Short name T393
Test name
Test status
Simulation time 39453414 ps
CPU time 0.55 seconds
Started Mar 17 12:36:45 PM PDT 24
Finished Mar 17 12:36:47 PM PDT 24
Peak memory 195444 kb
Host smart-91743e34-9c57-4554-889c-3221e556cda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767215612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2767215612
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1329826648
Short name T1054
Test name
Test status
Simulation time 118508200266 ps
CPU time 73.79 seconds
Started Mar 17 12:36:36 PM PDT 24
Finished Mar 17 12:37:50 PM PDT 24
Peak memory 199944 kb
Host smart-04bc5a20-d614-4937-922c-9acaba3cf24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329826648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1329826648
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.613879803
Short name T145
Test name
Test status
Simulation time 30984943096 ps
CPU time 48.79 seconds
Started Mar 17 12:36:42 PM PDT 24
Finished Mar 17 12:37:31 PM PDT 24
Peak memory 199964 kb
Host smart-c52bb88e-5cbe-4868-a535-e7d9e6c1d777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613879803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.613879803
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.806023661
Short name T682
Test name
Test status
Simulation time 183487116226 ps
CPU time 60.58 seconds
Started Mar 17 12:36:33 PM PDT 24
Finished Mar 17 12:37:34 PM PDT 24
Peak memory 199840 kb
Host smart-bf39ff6f-f5f9-47e1-a65d-e25ce8cc00ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806023661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.806023661
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1479756158
Short name T494
Test name
Test status
Simulation time 125304038169 ps
CPU time 718.59 seconds
Started Mar 17 12:36:35 PM PDT 24
Finished Mar 17 12:48:34 PM PDT 24
Peak memory 199884 kb
Host smart-2b5b2b80-cfac-4cf6-8a6c-987473b11d70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479756158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1479756158
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2581991201
Short name T992
Test name
Test status
Simulation time 4137819482 ps
CPU time 3.07 seconds
Started Mar 17 12:36:35 PM PDT 24
Finished Mar 17 12:36:38 PM PDT 24
Peak memory 199964 kb
Host smart-6b8ece6f-80c7-4d3c-a123-183f981e12c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581991201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2581991201
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3275121316
Short name T1024
Test name
Test status
Simulation time 63829641020 ps
CPU time 49.82 seconds
Started Mar 17 12:36:34 PM PDT 24
Finished Mar 17 12:37:23 PM PDT 24
Peak memory 199300 kb
Host smart-8dc42ee9-1f55-47ea-81d2-3f0f1b17e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275121316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3275121316
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1076667614
Short name T255
Test name
Test status
Simulation time 15011637020 ps
CPU time 759.81 seconds
Started Mar 17 12:36:35 PM PDT 24
Finished Mar 17 12:49:15 PM PDT 24
Peak memory 199984 kb
Host smart-1b118000-1a8d-460f-bf3b-8cbcf6e03a22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076667614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1076667614
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3939804691
Short name T404
Test name
Test status
Simulation time 1602636157 ps
CPU time 2.4 seconds
Started Mar 17 12:36:38 PM PDT 24
Finished Mar 17 12:36:40 PM PDT 24
Peak memory 198424 kb
Host smart-f9825ed0-e635-48fd-ba13-51cab2240210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939804691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3939804691
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2180467377
Short name T901
Test name
Test status
Simulation time 26267107532 ps
CPU time 54.89 seconds
Started Mar 17 12:36:34 PM PDT 24
Finished Mar 17 12:37:29 PM PDT 24
Peak memory 199932 kb
Host smart-e551e978-d7a5-4084-96ec-7b1492e61186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180467377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2180467377
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1507281103
Short name T1046
Test name
Test status
Simulation time 30837874502 ps
CPU time 12.7 seconds
Started Mar 17 12:36:37 PM PDT 24
Finished Mar 17 12:36:49 PM PDT 24
Peak memory 196024 kb
Host smart-28391dc4-ad88-46a9-9899-283fd7ff21a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507281103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1507281103
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2967782313
Short name T424
Test name
Test status
Simulation time 538022950 ps
CPU time 2.4 seconds
Started Mar 17 12:36:36 PM PDT 24
Finished Mar 17 12:36:39 PM PDT 24
Peak memory 198184 kb
Host smart-4494e69b-5581-4483-aa25-0bcf20f38a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967782313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2967782313
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2394469197
Short name T507
Test name
Test status
Simulation time 251494785709 ps
CPU time 241.53 seconds
Started Mar 17 12:36:33 PM PDT 24
Finished Mar 17 12:40:35 PM PDT 24
Peak memory 200104 kb
Host smart-830a4e01-ca9d-4da2-87d1-e11b6fafc068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394469197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2394469197
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1996462099
Short name T1095
Test name
Test status
Simulation time 470980840631 ps
CPU time 578.42 seconds
Started Mar 17 12:36:35 PM PDT 24
Finished Mar 17 12:46:14 PM PDT 24
Peak memory 216516 kb
Host smart-a0477203-a8a6-4feb-9c71-789013c329f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996462099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1996462099
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.876343908
Short name T496
Test name
Test status
Simulation time 5897598314 ps
CPU time 17.77 seconds
Started Mar 17 12:36:36 PM PDT 24
Finished Mar 17 12:36:54 PM PDT 24
Peak memory 199992 kb
Host smart-e46c56e9-cc69-444b-9339-fb3b8b93c4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876343908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.876343908
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.621636648
Short name T1096
Test name
Test status
Simulation time 57612590370 ps
CPU time 119.56 seconds
Started Mar 17 12:36:35 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 200104 kb
Host smart-11b244f3-9604-49f2-afe9-a61764eef6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621636648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.621636648
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.752544964
Short name T967
Test name
Test status
Simulation time 16141670 ps
CPU time 0.53 seconds
Started Mar 17 12:36:41 PM PDT 24
Finished Mar 17 12:36:42 PM PDT 24
Peak memory 195488 kb
Host smart-2fd4fa73-e7c4-4395-b2fd-edfeb83e10bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752544964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.752544964
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.139394318
Short name T941
Test name
Test status
Simulation time 13717085369 ps
CPU time 2.45 seconds
Started Mar 17 12:36:44 PM PDT 24
Finished Mar 17 12:36:47 PM PDT 24
Peak memory 198108 kb
Host smart-6c2d7639-ed8d-4ada-b063-7bbfa14b7f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139394318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.139394318
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.987857858
Short name T678
Test name
Test status
Simulation time 30490722190 ps
CPU time 14.43 seconds
Started Mar 17 12:36:42 PM PDT 24
Finished Mar 17 12:36:57 PM PDT 24
Peak memory 200096 kb
Host smart-8f5c45f0-58fe-4f83-93a9-3ca539dbae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987857858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.987857858
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3408520052
Short name T244
Test name
Test status
Simulation time 21516226085 ps
CPU time 12.77 seconds
Started Mar 17 12:36:44 PM PDT 24
Finished Mar 17 12:36:57 PM PDT 24
Peak memory 200032 kb
Host smart-509d3467-24b8-4f8e-8123-c8b7d4fdfa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408520052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3408520052
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.4040580440
Short name T988
Test name
Test status
Simulation time 59114593207 ps
CPU time 50.22 seconds
Started Mar 17 12:36:43 PM PDT 24
Finished Mar 17 12:37:33 PM PDT 24
Peak memory 199992 kb
Host smart-94b4b462-ca49-42ad-90d2-6ec37c3afc70
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040580440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4040580440
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3341751442
Short name T936
Test name
Test status
Simulation time 92301656423 ps
CPU time 947.86 seconds
Started Mar 17 12:36:44 PM PDT 24
Finished Mar 17 12:52:32 PM PDT 24
Peak memory 199972 kb
Host smart-6965c8c9-2e45-4cd3-b40f-2c9e8897c106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341751442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3341751442
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2546247224
Short name T336
Test name
Test status
Simulation time 3600979569 ps
CPU time 3.45 seconds
Started Mar 17 12:36:43 PM PDT 24
Finished Mar 17 12:36:47 PM PDT 24
Peak memory 198332 kb
Host smart-b2e815eb-a7c1-48ee-b78e-e2af71f11dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546247224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2546247224
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.543408918
Short name T102
Test name
Test status
Simulation time 59992010514 ps
CPU time 115.4 seconds
Started Mar 17 12:36:46 PM PDT 24
Finished Mar 17 12:38:42 PM PDT 24
Peak memory 200100 kb
Host smart-35ee88b2-edd3-47e4-9f96-a2fde0a50859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543408918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.543408918
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3551816843
Short name T594
Test name
Test status
Simulation time 9744137126 ps
CPU time 124.85 seconds
Started Mar 17 12:36:44 PM PDT 24
Finished Mar 17 12:38:49 PM PDT 24
Peak memory 199888 kb
Host smart-dce99d51-b15f-4efd-9c5d-8803c0c82e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551816843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3551816843
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.4203353735
Short name T647
Test name
Test status
Simulation time 6967142070 ps
CPU time 30.11 seconds
Started Mar 17 12:36:44 PM PDT 24
Finished Mar 17 12:37:15 PM PDT 24
Peak memory 198512 kb
Host smart-653e514e-9857-446f-91bb-cefea632c2ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203353735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.4203353735
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2246596277
Short name T150
Test name
Test status
Simulation time 125915371777 ps
CPU time 144.74 seconds
Started Mar 17 12:36:42 PM PDT 24
Finished Mar 17 12:39:07 PM PDT 24
Peak memory 200040 kb
Host smart-3544c692-0399-41bc-8d6c-009a870dfc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246596277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2246596277
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3630862846
Short name T309
Test name
Test status
Simulation time 39794167024 ps
CPU time 29.44 seconds
Started Mar 17 12:36:43 PM PDT 24
Finished Mar 17 12:37:13 PM PDT 24
Peak memory 196036 kb
Host smart-c594a1e5-2107-4238-9c56-9556624c2288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630862846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3630862846
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3854517804
Short name T364
Test name
Test status
Simulation time 526690153 ps
CPU time 1.35 seconds
Started Mar 17 12:36:41 PM PDT 24
Finished Mar 17 12:36:43 PM PDT 24
Peak memory 198840 kb
Host smart-26cc1cb8-2b84-4487-9a4a-49671fb55857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854517804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3854517804
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1348584299
Short name T855
Test name
Test status
Simulation time 119563364252 ps
CPU time 54.11 seconds
Started Mar 17 12:36:44 PM PDT 24
Finished Mar 17 12:37:38 PM PDT 24
Peak memory 199884 kb
Host smart-641d4348-edda-4631-a735-93ee088d61da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348584299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1348584299
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.527308719
Short name T754
Test name
Test status
Simulation time 1212798400 ps
CPU time 3.41 seconds
Started Mar 17 12:36:43 PM PDT 24
Finished Mar 17 12:36:47 PM PDT 24
Peak memory 198184 kb
Host smart-c74d115d-0270-4667-a49d-0603b3212b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527308719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.527308719
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.452628393
Short name T569
Test name
Test status
Simulation time 21829196371 ps
CPU time 38.93 seconds
Started Mar 17 12:36:44 PM PDT 24
Finished Mar 17 12:37:23 PM PDT 24
Peak memory 199928 kb
Host smart-1d6ca93e-c463-4018-a6e8-c1a66859c6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452628393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.452628393
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2983843590
Short name T354
Test name
Test status
Simulation time 11460440 ps
CPU time 0.52 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:36:53 PM PDT 24
Peak memory 194476 kb
Host smart-8635ef8d-344b-48b9-bb06-55691a873e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983843590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2983843590
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1748586266
Short name T700
Test name
Test status
Simulation time 71985610572 ps
CPU time 132.76 seconds
Started Mar 17 12:36:53 PM PDT 24
Finished Mar 17 12:39:06 PM PDT 24
Peak memory 199972 kb
Host smart-d0bc12cc-2dfa-4378-aec4-d033ea3e92db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748586266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1748586266
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2862781384
Short name T252
Test name
Test status
Simulation time 138941874474 ps
CPU time 90.2 seconds
Started Mar 17 12:36:49 PM PDT 24
Finished Mar 17 12:38:19 PM PDT 24
Peak memory 199892 kb
Host smart-374528fe-ca00-452f-88c7-c334173837a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862781384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2862781384
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2439707500
Short name T552
Test name
Test status
Simulation time 75611847662 ps
CPU time 118.71 seconds
Started Mar 17 12:36:53 PM PDT 24
Finished Mar 17 12:38:51 PM PDT 24
Peak memory 200136 kb
Host smart-af0ece51-048a-4e1b-bab5-8c5639e36ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439707500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2439707500
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.4261260337
Short name T541
Test name
Test status
Simulation time 20852941010 ps
CPU time 11.12 seconds
Started Mar 17 12:36:51 PM PDT 24
Finished Mar 17 12:37:02 PM PDT 24
Peak memory 199840 kb
Host smart-21b04b93-d8b4-4c57-bd00-b8d6c8299b53
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261260337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.4261260337
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1887140313
Short name T953
Test name
Test status
Simulation time 339221326931 ps
CPU time 137.76 seconds
Started Mar 17 12:36:49 PM PDT 24
Finished Mar 17 12:39:07 PM PDT 24
Peak memory 200092 kb
Host smart-8f780a8a-69a3-4307-8f3e-c56bf6da54f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887140313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1887140313
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1952913104
Short name T885
Test name
Test status
Simulation time 8019673009 ps
CPU time 5.19 seconds
Started Mar 17 12:36:49 PM PDT 24
Finished Mar 17 12:36:55 PM PDT 24
Peak memory 200220 kb
Host smart-e9a9f62f-172d-42e7-bef8-013a26369a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952913104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1952913104
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3430448205
Short name T1052
Test name
Test status
Simulation time 55178114512 ps
CPU time 24.26 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:37:16 PM PDT 24
Peak memory 200188 kb
Host smart-2e5781f6-23d0-43d0-ae91-483cda87ab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430448205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3430448205
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1837420126
Short name T973
Test name
Test status
Simulation time 13005130493 ps
CPU time 775.62 seconds
Started Mar 17 12:36:53 PM PDT 24
Finished Mar 17 12:49:48 PM PDT 24
Peak memory 199988 kb
Host smart-f2bcccc6-7a96-44ea-a1b0-d238f5a76ae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1837420126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1837420126
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2031090997
Short name T361
Test name
Test status
Simulation time 6795518273 ps
CPU time 30.15 seconds
Started Mar 17 12:36:53 PM PDT 24
Finished Mar 17 12:37:23 PM PDT 24
Peak memory 199400 kb
Host smart-e9ebd644-317c-4c15-aec9-af0223113680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031090997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2031090997
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.955674115
Short name T810
Test name
Test status
Simulation time 110286616574 ps
CPU time 57.52 seconds
Started Mar 17 12:36:50 PM PDT 24
Finished Mar 17 12:37:47 PM PDT 24
Peak memory 199952 kb
Host smart-9a2e27dc-7c63-4fe7-92d3-21be9327cf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955674115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.955674115
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1511463342
Short name T1018
Test name
Test status
Simulation time 665873827 ps
CPU time 0.87 seconds
Started Mar 17 12:36:50 PM PDT 24
Finished Mar 17 12:36:51 PM PDT 24
Peak memory 195740 kb
Host smart-6ac79d4e-f57b-4364-8f2d-9cb62791fee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511463342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1511463342
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3307261121
Short name T776
Test name
Test status
Simulation time 449238901 ps
CPU time 1.69 seconds
Started Mar 17 12:36:45 PM PDT 24
Finished Mar 17 12:36:48 PM PDT 24
Peak memory 198328 kb
Host smart-9a8763df-8f48-46a7-b7cb-82ef6c5cd4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307261121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3307261121
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2472264627
Short name T698
Test name
Test status
Simulation time 68016715451 ps
CPU time 103.75 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:38:36 PM PDT 24
Peak memory 199924 kb
Host smart-8575f444-dd9c-4033-b9c4-38f209bdebe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472264627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2472264627
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.250129476
Short name T439
Test name
Test status
Simulation time 993444588 ps
CPU time 2.83 seconds
Started Mar 17 12:36:49 PM PDT 24
Finished Mar 17 12:36:52 PM PDT 24
Peak memory 198308 kb
Host smart-4e3d0d28-0f97-42f3-85a7-c5e4665c45d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250129476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.250129476
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.711762725
Short name T989
Test name
Test status
Simulation time 34197876679 ps
CPU time 9.12 seconds
Started Mar 17 12:36:49 PM PDT 24
Finished Mar 17 12:36:58 PM PDT 24
Peak memory 197612 kb
Host smart-1b49e216-a9a9-4e9e-9468-105c30c24d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711762725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.711762725
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.458749463
Short name T860
Test name
Test status
Simulation time 22816159 ps
CPU time 0.54 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:36:53 PM PDT 24
Peak memory 195460 kb
Host smart-a1b4cab6-2e63-4a8e-ae59-199ae4da7dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458749463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.458749463
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1586047140
Short name T829
Test name
Test status
Simulation time 27746494231 ps
CPU time 16.07 seconds
Started Mar 17 12:36:47 PM PDT 24
Finished Mar 17 12:37:05 PM PDT 24
Peak memory 199972 kb
Host smart-2a43af94-410f-4ef9-a57b-3fb09e6704f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586047140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1586047140
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.249350589
Short name T866
Test name
Test status
Simulation time 31284617798 ps
CPU time 25.15 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:37:18 PM PDT 24
Peak memory 199972 kb
Host smart-303139f1-fa74-4d30-8983-9f80a70a5be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249350589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.249350589
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3025722847
Short name T517
Test name
Test status
Simulation time 115706237227 ps
CPU time 952.18 seconds
Started Mar 17 12:36:50 PM PDT 24
Finished Mar 17 12:52:43 PM PDT 24
Peak memory 199924 kb
Host smart-5881a942-c0a2-40d2-b5a9-2952cb2d4fe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025722847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3025722847
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1755598048
Short name T968
Test name
Test status
Simulation time 6759562213 ps
CPU time 6.34 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:36:59 PM PDT 24
Peak memory 199596 kb
Host smart-2d2fa6bd-8a9a-4967-8214-febc0a239bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755598048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1755598048
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2911833520
Short name T272
Test name
Test status
Simulation time 221050833461 ps
CPU time 100.78 seconds
Started Mar 17 12:36:54 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 199300 kb
Host smart-f5927c02-1191-4600-8ebb-f467e835aac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911833520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2911833520
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3014005479
Short name T248
Test name
Test status
Simulation time 23360361156 ps
CPU time 1005.91 seconds
Started Mar 17 12:36:49 PM PDT 24
Finished Mar 17 12:53:35 PM PDT 24
Peak memory 200028 kb
Host smart-089a0cd2-e55e-414f-b7c5-c0fbb83d9047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014005479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3014005479
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2225488586
Short name T799
Test name
Test status
Simulation time 7472769605 ps
CPU time 12.61 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:37:05 PM PDT 24
Peak memory 199016 kb
Host smart-31e3f6a7-c534-4cec-890e-675f9ddf7603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225488586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2225488586
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.504007598
Short name T789
Test name
Test status
Simulation time 109530501580 ps
CPU time 31 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:37:23 PM PDT 24
Peak memory 200008 kb
Host smart-7727d72e-49fc-45bf-8a60-fe4bc453ead3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504007598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.504007598
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1948189798
Short name T818
Test name
Test status
Simulation time 4288070794 ps
CPU time 2.32 seconds
Started Mar 17 12:36:51 PM PDT 24
Finished Mar 17 12:36:54 PM PDT 24
Peak memory 196096 kb
Host smart-0d49a574-465e-4d54-8d6e-263a36720742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948189798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1948189798
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.162122076
Short name T9
Test name
Test status
Simulation time 5752703038 ps
CPU time 12.76 seconds
Started Mar 17 12:36:51 PM PDT 24
Finished Mar 17 12:37:04 PM PDT 24
Peak memory 199868 kb
Host smart-c449ea35-3f7b-4d52-81bc-92a807a63091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162122076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.162122076
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3341276625
Short name T883
Test name
Test status
Simulation time 203922238959 ps
CPU time 543.27 seconds
Started Mar 17 12:36:48 PM PDT 24
Finished Mar 17 12:45:52 PM PDT 24
Peak memory 200052 kb
Host smart-8f302f14-b74d-4ea4-a103-51d674977285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341276625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3341276625
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2628011650
Short name T645
Test name
Test status
Simulation time 754213745 ps
CPU time 2.06 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:36:54 PM PDT 24
Peak memory 198840 kb
Host smart-1d8f095c-e6a2-4b9c-9ad1-c3fd9530f2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628011650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2628011650
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2145447644
Short name T841
Test name
Test status
Simulation time 62950207765 ps
CPU time 109.3 seconds
Started Mar 17 12:36:52 PM PDT 24
Finished Mar 17 12:38:41 PM PDT 24
Peak memory 200044 kb
Host smart-767b1810-a1b0-47f0-82aa-63a29591840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145447644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2145447644
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1224842723
Short name T741
Test name
Test status
Simulation time 65909506 ps
CPU time 0.52 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:34:05 PM PDT 24
Peak memory 195432 kb
Host smart-54d85ee3-0165-4ad7-92cb-6cd64d3505ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224842723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1224842723
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.4223913309
Short name T348
Test name
Test status
Simulation time 19253362683 ps
CPU time 16.04 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:22 PM PDT 24
Peak memory 198980 kb
Host smart-a932ab77-cdf4-47f8-81c9-876239dff4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223913309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.4223913309
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2845934092
Short name T447
Test name
Test status
Simulation time 139053823185 ps
CPU time 52.93 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:35:00 PM PDT 24
Peak memory 200140 kb
Host smart-cb04bba6-f7d4-4481-b447-9a5d09fa1a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845934092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2845934092
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2267937086
Short name T911
Test name
Test status
Simulation time 58994190802 ps
CPU time 251.99 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:38:19 PM PDT 24
Peak memory 200100 kb
Host smart-831b5639-c8b5-4fdb-9757-c3a046dc29f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267937086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2267937086
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4084295331
Short name T58
Test name
Test status
Simulation time 9774956003 ps
CPU time 20.16 seconds
Started Mar 17 12:34:08 PM PDT 24
Finished Mar 17 12:34:28 PM PDT 24
Peak memory 199944 kb
Host smart-0fd40001-d7df-4a4b-b5f5-b3283288130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084295331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4084295331
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.570664234
Short name T503
Test name
Test status
Simulation time 65462142453 ps
CPU time 29.02 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:34 PM PDT 24
Peak memory 197896 kb
Host smart-cc19e58e-048c-455d-a4cd-646c6f180d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570664234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.570664234
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3441460353
Short name T937
Test name
Test status
Simulation time 19347095714 ps
CPU time 297.36 seconds
Started Mar 17 12:34:11 PM PDT 24
Finished Mar 17 12:39:09 PM PDT 24
Peak memory 200020 kb
Host smart-5b8fbaa7-a263-44a5-9afb-876ccca3f8c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441460353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3441460353
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1490619522
Short name T481
Test name
Test status
Simulation time 6893067968 ps
CPU time 63.8 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:35:10 PM PDT 24
Peak memory 198616 kb
Host smart-849551e5-69a7-4842-950b-0910ffa953f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490619522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1490619522
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2367384370
Short name T146
Test name
Test status
Simulation time 110691523567 ps
CPU time 110.29 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:35:54 PM PDT 24
Peak memory 200008 kb
Host smart-e2cbf3ef-a2ed-4984-bd5e-7d1177bc2fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367384370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2367384370
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.516976387
Short name T844
Test name
Test status
Simulation time 43732299935 ps
CPU time 71.97 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:35:17 PM PDT 24
Peak memory 195804 kb
Host smart-707c8e09-2ef1-4182-81b0-69b8a0d3c122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516976387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.516976387
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.848572806
Short name T33
Test name
Test status
Simulation time 63065224 ps
CPU time 0.83 seconds
Started Mar 17 12:34:03 PM PDT 24
Finished Mar 17 12:34:04 PM PDT 24
Peak memory 218352 kb
Host smart-cdbfa43b-debd-4e2d-9990-1751ea1adee0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848572806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.848572806
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1896654608
Short name T864
Test name
Test status
Simulation time 719865278 ps
CPU time 1.48 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:07 PM PDT 24
Peak memory 199836 kb
Host smart-19c77218-c72e-449d-b127-0195755a3a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896654608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1896654608
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3799312773
Short name T1065
Test name
Test status
Simulation time 350226955741 ps
CPU time 405.39 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:40:51 PM PDT 24
Peak memory 200040 kb
Host smart-a947736c-de47-4cfe-86bc-769e122a7599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799312773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3799312773
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1356208700
Short name T662
Test name
Test status
Simulation time 6726913984 ps
CPU time 12.17 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:18 PM PDT 24
Peak memory 199224 kb
Host smart-c5fb4954-23a4-4f34-b9ba-a82b0c4dac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356208700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1356208700
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2508572130
Short name T445
Test name
Test status
Simulation time 101394286317 ps
CPU time 25.38 seconds
Started Mar 17 12:34:07 PM PDT 24
Finished Mar 17 12:34:32 PM PDT 24
Peak memory 199048 kb
Host smart-3fb3be90-186a-4834-9e76-8d7b9b5cb9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508572130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2508572130
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2576565172
Short name T350
Test name
Test status
Simulation time 156033842 ps
CPU time 0.59 seconds
Started Mar 17 12:36:59 PM PDT 24
Finished Mar 17 12:37:01 PM PDT 24
Peak memory 195676 kb
Host smart-103b28d1-efe5-4d94-91cb-7faa56ef0df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576565172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2576565172
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1443567217
Short name T859
Test name
Test status
Simulation time 109686495271 ps
CPU time 145.39 seconds
Started Mar 17 12:36:51 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 199996 kb
Host smart-d9ad104a-a25f-4b90-8cb1-5fc7a7df4618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443567217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1443567217
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3243380150
Short name T42
Test name
Test status
Simulation time 44784683661 ps
CPU time 71.59 seconds
Started Mar 17 12:36:57 PM PDT 24
Finished Mar 17 12:38:12 PM PDT 24
Peak memory 199836 kb
Host smart-9325bc16-8e71-40fd-bb9f-5aa793a0da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243380150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3243380150
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2993700142
Short name T730
Test name
Test status
Simulation time 97160302953 ps
CPU time 77.21 seconds
Started Mar 17 12:36:55 PM PDT 24
Finished Mar 17 12:38:12 PM PDT 24
Peak memory 199956 kb
Host smart-596b8e72-3e75-4d75-909b-02803b858994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993700142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2993700142
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.437800865
Short name T697
Test name
Test status
Simulation time 51403772397 ps
CPU time 7.63 seconds
Started Mar 17 12:37:00 PM PDT 24
Finished Mar 17 12:37:08 PM PDT 24
Peak memory 199780 kb
Host smart-8e96b30d-cb5d-499a-a774-8dcf32baec3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437800865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.437800865
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.885005142
Short name T949
Test name
Test status
Simulation time 119127366356 ps
CPU time 656 seconds
Started Mar 17 12:36:55 PM PDT 24
Finished Mar 17 12:47:51 PM PDT 24
Peak memory 199872 kb
Host smart-2b501111-898d-4502-9174-2d0c6c1bd9ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885005142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.885005142
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.4032069703
Short name T399
Test name
Test status
Simulation time 6140449794 ps
CPU time 5.69 seconds
Started Mar 17 12:37:00 PM PDT 24
Finished Mar 17 12:37:06 PM PDT 24
Peak memory 200176 kb
Host smart-bc3daa9f-b4c4-46f2-8c25-552a3a787e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032069703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4032069703
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3087064091
Short name T282
Test name
Test status
Simulation time 136478125329 ps
CPU time 129.61 seconds
Started Mar 17 12:37:02 PM PDT 24
Finished Mar 17 12:39:12 PM PDT 24
Peak memory 208316 kb
Host smart-f0bcafc2-711f-4003-96df-bdc528baaa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087064091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3087064091
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3402609334
Short name T295
Test name
Test status
Simulation time 16825321786 ps
CPU time 248.31 seconds
Started Mar 17 12:36:57 PM PDT 24
Finished Mar 17 12:41:09 PM PDT 24
Peak memory 200100 kb
Host smart-62bb4b49-4baa-444c-807d-3adf6f4298bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402609334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3402609334
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1437868244
Short name T648
Test name
Test status
Simulation time 3711907141 ps
CPU time 8.06 seconds
Started Mar 17 12:36:58 PM PDT 24
Finished Mar 17 12:37:08 PM PDT 24
Peak memory 198756 kb
Host smart-b5381dc7-e5f9-4ed2-b0f2-98b08a2ddb7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437868244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1437868244
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1181714003
Short name T257
Test name
Test status
Simulation time 70467521041 ps
CPU time 55.55 seconds
Started Mar 17 12:37:00 PM PDT 24
Finished Mar 17 12:37:56 PM PDT 24
Peak memory 199920 kb
Host smart-c356267d-7f45-48a1-801f-d15436247fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181714003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1181714003
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.811523782
Short name T1100
Test name
Test status
Simulation time 3660597097 ps
CPU time 2.51 seconds
Started Mar 17 12:36:58 PM PDT 24
Finished Mar 17 12:37:03 PM PDT 24
Peak memory 196044 kb
Host smart-df4c231c-ef09-48b9-8d2b-2ad6df56c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811523782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.811523782
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2038144419
Short name T314
Test name
Test status
Simulation time 6079417341 ps
CPU time 16.43 seconds
Started Mar 17 12:36:49 PM PDT 24
Finished Mar 17 12:37:06 PM PDT 24
Peak memory 199696 kb
Host smart-41aee41d-a2ce-488d-a37e-a7a18148ca72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038144419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2038144419
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3652382347
Short name T449
Test name
Test status
Simulation time 157059334830 ps
CPU time 262.98 seconds
Started Mar 17 12:37:00 PM PDT 24
Finished Mar 17 12:41:23 PM PDT 24
Peak memory 199856 kb
Host smart-750457ca-1317-4f7e-bda6-51eca01c19c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652382347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3652382347
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2077770616
Short name T659
Test name
Test status
Simulation time 1827508949 ps
CPU time 2.46 seconds
Started Mar 17 12:36:58 PM PDT 24
Finished Mar 17 12:37:03 PM PDT 24
Peak memory 198332 kb
Host smart-e8e2da7f-dd72-46ab-9908-6bb4c85d6eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077770616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2077770616
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.24210571
Short name T281
Test name
Test status
Simulation time 26503926528 ps
CPU time 48.07 seconds
Started Mar 17 12:36:50 PM PDT 24
Finished Mar 17 12:37:38 PM PDT 24
Peak memory 200096 kb
Host smart-1fa186b4-68e3-40e1-91ea-7ca0c93f6af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24210571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.24210571
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.815863722
Short name T916
Test name
Test status
Simulation time 31845356 ps
CPU time 0.54 seconds
Started Mar 17 12:37:04 PM PDT 24
Finished Mar 17 12:37:05 PM PDT 24
Peak memory 195488 kb
Host smart-b0aa3799-fa85-4715-9179-32a971429878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815863722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.815863722
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2538035724
Short name T792
Test name
Test status
Simulation time 37250560555 ps
CPU time 66.21 seconds
Started Mar 17 12:36:58 PM PDT 24
Finished Mar 17 12:38:05 PM PDT 24
Peak memory 200008 kb
Host smart-cf97a592-1204-4319-b2f3-02864737f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538035724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2538035724
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3124076681
Short name T483
Test name
Test status
Simulation time 42279761195 ps
CPU time 68.36 seconds
Started Mar 17 12:36:58 PM PDT 24
Finished Mar 17 12:38:07 PM PDT 24
Peak memory 200124 kb
Host smart-0868c077-16da-4d79-bb45-a3696105bbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124076681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3124076681
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2619020212
Short name T875
Test name
Test status
Simulation time 33017764961 ps
CPU time 15.11 seconds
Started Mar 17 12:36:57 PM PDT 24
Finished Mar 17 12:37:15 PM PDT 24
Peak memory 199944 kb
Host smart-a78af6fe-a238-4320-a528-eca3f43f0166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619020212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2619020212
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.345051584
Short name T692
Test name
Test status
Simulation time 44873379477 ps
CPU time 14.63 seconds
Started Mar 17 12:37:07 PM PDT 24
Finished Mar 17 12:37:22 PM PDT 24
Peak memory 200112 kb
Host smart-4f56ce65-fcbb-4468-92c8-e29b9c45434a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345051584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.345051584
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3575283936
Short name T526
Test name
Test status
Simulation time 115240991407 ps
CPU time 329.17 seconds
Started Mar 17 12:37:05 PM PDT 24
Finished Mar 17 12:42:35 PM PDT 24
Peak memory 199948 kb
Host smart-bb9afcef-8248-4500-948e-be7801dd711a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575283936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3575283936
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.817268241
Short name T772
Test name
Test status
Simulation time 2033907136 ps
CPU time 1.51 seconds
Started Mar 17 12:37:04 PM PDT 24
Finished Mar 17 12:37:06 PM PDT 24
Peak memory 195892 kb
Host smart-83cfb008-118a-4be0-a0d5-8a479e2bebcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817268241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.817268241
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1500104484
Short name T886
Test name
Test status
Simulation time 44146527621 ps
CPU time 76.13 seconds
Started Mar 17 12:37:05 PM PDT 24
Finished Mar 17 12:38:22 PM PDT 24
Peak memory 200128 kb
Host smart-5ace55d9-6247-4e0d-9eea-0e80747623e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500104484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1500104484
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3443301547
Short name T501
Test name
Test status
Simulation time 11199063876 ps
CPU time 225.02 seconds
Started Mar 17 12:37:04 PM PDT 24
Finished Mar 17 12:40:50 PM PDT 24
Peak memory 200016 kb
Host smart-3ed1b7a3-1383-4b47-8753-5cee74f93684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443301547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3443301547
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2073631903
Short name T351
Test name
Test status
Simulation time 1207143092 ps
CPU time 0.78 seconds
Started Mar 17 12:36:57 PM PDT 24
Finished Mar 17 12:37:01 PM PDT 24
Peak memory 195592 kb
Host smart-7bf190a3-a4f1-428f-b3c6-39ad3ef6a3b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073631903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2073631903
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2178917500
Short name T667
Test name
Test status
Simulation time 182659047238 ps
CPU time 67.38 seconds
Started Mar 17 12:37:05 PM PDT 24
Finished Mar 17 12:38:13 PM PDT 24
Peak memory 199788 kb
Host smart-fe437535-c8b6-49e1-b632-117e9de23527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178917500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2178917500
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1469362942
Short name T1026
Test name
Test status
Simulation time 5071750311 ps
CPU time 1.44 seconds
Started Mar 17 12:37:04 PM PDT 24
Finished Mar 17 12:37:06 PM PDT 24
Peak memory 196376 kb
Host smart-54519fb3-2eb5-4a44-bdda-fa06d61761e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469362942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1469362942
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.164913387
Short name T416
Test name
Test status
Simulation time 5735986861 ps
CPU time 8.6 seconds
Started Mar 17 12:36:57 PM PDT 24
Finished Mar 17 12:37:09 PM PDT 24
Peak memory 199992 kb
Host smart-fb7e2678-319c-4caa-a0f8-b1f4306bca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164913387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.164913387
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.4008966835
Short name T206
Test name
Test status
Simulation time 917265871145 ps
CPU time 899.6 seconds
Started Mar 17 12:37:09 PM PDT 24
Finished Mar 17 12:52:09 PM PDT 24
Peak memory 208372 kb
Host smart-c19d23e3-b126-4c57-8cf0-eb1fd57cbc58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008966835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4008966835
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.122027077
Short name T453
Test name
Test status
Simulation time 849997023 ps
CPU time 2.98 seconds
Started Mar 17 12:37:05 PM PDT 24
Finished Mar 17 12:37:09 PM PDT 24
Peak memory 199924 kb
Host smart-63134153-3227-492f-a15b-3ff81e90ebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122027077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.122027077
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3573114861
Short name T1076
Test name
Test status
Simulation time 122720585237 ps
CPU time 185.02 seconds
Started Mar 17 12:37:02 PM PDT 24
Finished Mar 17 12:40:07 PM PDT 24
Peak memory 200000 kb
Host smart-a7fbfbc6-6445-47ca-9e5b-1b168e1d0265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573114861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3573114861
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3677433230
Short name T349
Test name
Test status
Simulation time 40494025 ps
CPU time 0.54 seconds
Started Mar 17 12:37:13 PM PDT 24
Finished Mar 17 12:37:14 PM PDT 24
Peak memory 195448 kb
Host smart-9471d653-f1dc-4e77-ab42-8d2f2a120e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677433230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3677433230
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2911953224
Short name T652
Test name
Test status
Simulation time 30019361640 ps
CPU time 15.49 seconds
Started Mar 17 12:37:07 PM PDT 24
Finished Mar 17 12:37:23 PM PDT 24
Peak memory 199960 kb
Host smart-39b6f1db-d946-4af4-b4cd-7fe6796efc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911953224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2911953224
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1675329109
Short name T707
Test name
Test status
Simulation time 94795325658 ps
CPU time 146.98 seconds
Started Mar 17 12:37:09 PM PDT 24
Finished Mar 17 12:39:36 PM PDT 24
Peak memory 199868 kb
Host smart-0a0fffc2-acb5-4b71-af0a-95310bb77ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675329109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1675329109
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2047899687
Short name T430
Test name
Test status
Simulation time 58666944241 ps
CPU time 216.81 seconds
Started Mar 17 12:37:07 PM PDT 24
Finished Mar 17 12:40:44 PM PDT 24
Peak memory 200028 kb
Host smart-76a84102-808d-4145-b59d-a9fdc24a7832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047899687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2047899687
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1139404491
Short name T1029
Test name
Test status
Simulation time 8485569421 ps
CPU time 15.63 seconds
Started Mar 17 12:37:06 PM PDT 24
Finished Mar 17 12:37:22 PM PDT 24
Peak memory 197720 kb
Host smart-def2cae2-b0f9-4b06-bf2f-228b7a881b01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139404491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1139404491
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2851426598
Short name T1080
Test name
Test status
Simulation time 26347088452 ps
CPU time 95.28 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:38:50 PM PDT 24
Peak memory 200140 kb
Host smart-5003afa1-92e6-4312-8990-744c1d3dd92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851426598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2851426598
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2431678290
Short name T893
Test name
Test status
Simulation time 8347586555 ps
CPU time 7.45 seconds
Started Mar 17 12:37:04 PM PDT 24
Finished Mar 17 12:37:12 PM PDT 24
Peak memory 198876 kb
Host smart-d3f0c603-37d1-47f7-b216-341acd4c50e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431678290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2431678290
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3920623073
Short name T720
Test name
Test status
Simulation time 84234965901 ps
CPU time 68.1 seconds
Started Mar 17 12:37:08 PM PDT 24
Finished Mar 17 12:38:17 PM PDT 24
Peak memory 200344 kb
Host smart-fef1d0e1-914a-40b9-9a8b-06e8142df3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920623073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3920623073
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2341606831
Short name T326
Test name
Test status
Simulation time 16650781452 ps
CPU time 994.32 seconds
Started Mar 17 12:37:08 PM PDT 24
Finished Mar 17 12:53:43 PM PDT 24
Peak memory 200032 kb
Host smart-deaabfcd-8a4a-4b82-befc-2c57cd0b391e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341606831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2341606831
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3946432592
Short name T750
Test name
Test status
Simulation time 6942181644 ps
CPU time 32.48 seconds
Started Mar 17 12:37:07 PM PDT 24
Finished Mar 17 12:37:40 PM PDT 24
Peak memory 198264 kb
Host smart-6d300b34-6076-47ad-8efb-42866bdbc721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946432592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3946432592
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3415427261
Short name T10
Test name
Test status
Simulation time 4415029376 ps
CPU time 7.57 seconds
Started Mar 17 12:37:06 PM PDT 24
Finished Mar 17 12:37:14 PM PDT 24
Peak memory 198732 kb
Host smart-55af2c84-4fc2-4399-81df-7c4e5c9c242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415427261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3415427261
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3910129795
Short name T783
Test name
Test status
Simulation time 47175161225 ps
CPU time 37.88 seconds
Started Mar 17 12:37:08 PM PDT 24
Finished Mar 17 12:37:46 PM PDT 24
Peak memory 196080 kb
Host smart-fc1cb6a0-d2cc-4d91-9f57-6530f13f715c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910129795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3910129795
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2768813308
Short name T289
Test name
Test status
Simulation time 5490760127 ps
CPU time 16.23 seconds
Started Mar 17 12:37:06 PM PDT 24
Finished Mar 17 12:37:23 PM PDT 24
Peak memory 199964 kb
Host smart-1af7dbd7-33e7-48d3-85e4-14d448a2621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768813308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2768813308
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.710016266
Short name T701
Test name
Test status
Simulation time 575034736368 ps
CPU time 278.12 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:41:53 PM PDT 24
Peak memory 208316 kb
Host smart-4fd50bab-e1fa-4ef5-86f6-1510bce9a0cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710016266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.710016266
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.124850733
Short name T2
Test name
Test status
Simulation time 6331335151 ps
CPU time 15.4 seconds
Started Mar 17 12:37:06 PM PDT 24
Finished Mar 17 12:37:22 PM PDT 24
Peak memory 199860 kb
Host smart-e95dc673-a2db-4596-82ec-5245a46fe5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124850733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.124850733
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3283030746
Short name T414
Test name
Test status
Simulation time 59320665121 ps
CPU time 48.49 seconds
Started Mar 17 12:37:07 PM PDT 24
Finished Mar 17 12:37:55 PM PDT 24
Peak memory 199952 kb
Host smart-bd790399-47a2-4efe-ae68-e473b4e16280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283030746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3283030746
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2267015042
Short name T1079
Test name
Test status
Simulation time 29123182 ps
CPU time 0.52 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:37:15 PM PDT 24
Peak memory 195040 kb
Host smart-7284445d-0b1a-475a-84e4-5546ef1ad72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267015042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2267015042
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1303828140
Short name T551
Test name
Test status
Simulation time 73376434060 ps
CPU time 32.37 seconds
Started Mar 17 12:37:18 PM PDT 24
Finished Mar 17 12:37:51 PM PDT 24
Peak memory 200020 kb
Host smart-e1f79f17-b943-4392-8894-1933c1d8a858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303828140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1303828140
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.939947448
Short name T657
Test name
Test status
Simulation time 103050161827 ps
CPU time 107.92 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:39:03 PM PDT 24
Peak memory 200064 kb
Host smart-2960696d-0830-4b4d-a76e-2a5dd8ba58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939947448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.939947448
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3112035063
Short name T1053
Test name
Test status
Simulation time 32921027448 ps
CPU time 49.18 seconds
Started Mar 17 12:37:11 PM PDT 24
Finished Mar 17 12:38:00 PM PDT 24
Peak memory 200020 kb
Host smart-b1f76fe1-bd12-497f-88a7-7750042e1730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112035063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3112035063
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1862027709
Short name T467
Test name
Test status
Simulation time 437720458135 ps
CPU time 201.58 seconds
Started Mar 17 12:37:13 PM PDT 24
Finished Mar 17 12:40:35 PM PDT 24
Peak memory 199640 kb
Host smart-0373e707-89a1-483b-b173-e302ac049271
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862027709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1862027709
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1574956566
Short name T617
Test name
Test status
Simulation time 62616790657 ps
CPU time 48.87 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:38:03 PM PDT 24
Peak memory 199964 kb
Host smart-9fb1e9a9-0a85-41e6-a84c-f00f4420a8c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574956566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1574956566
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.424013277
Short name T355
Test name
Test status
Simulation time 4183960838 ps
CPU time 2.79 seconds
Started Mar 17 12:37:15 PM PDT 24
Finished Mar 17 12:37:18 PM PDT 24
Peak memory 196604 kb
Host smart-1029c744-ad17-4ad0-8d07-1bf3b96f4c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424013277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.424013277
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3637551267
Short name T777
Test name
Test status
Simulation time 39214873044 ps
CPU time 73.13 seconds
Started Mar 17 12:37:17 PM PDT 24
Finished Mar 17 12:38:31 PM PDT 24
Peak memory 200036 kb
Host smart-b763ba14-1e3d-48e7-8e77-d261ccd741fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637551267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3637551267
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3671931251
Short name T369
Test name
Test status
Simulation time 3275916372 ps
CPU time 42.04 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:37:57 PM PDT 24
Peak memory 199952 kb
Host smart-73ab2585-761a-455b-ac77-509893b5c8f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671931251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3671931251
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1071190707
Short name T543
Test name
Test status
Simulation time 6720245301 ps
CPU time 4.78 seconds
Started Mar 17 12:37:19 PM PDT 24
Finished Mar 17 12:37:24 PM PDT 24
Peak memory 199308 kb
Host smart-6044685d-3a29-42c6-8e10-d45142cc26c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071190707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1071190707
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2234172556
Short name T120
Test name
Test status
Simulation time 57446574570 ps
CPU time 47.67 seconds
Started Mar 17 12:37:15 PM PDT 24
Finished Mar 17 12:38:03 PM PDT 24
Peak memory 200008 kb
Host smart-179ea44c-5606-4fcd-9d33-56f7e6d66d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234172556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2234172556
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4293975125
Short name T826
Test name
Test status
Simulation time 3520691617 ps
CPU time 6.27 seconds
Started Mar 17 12:37:19 PM PDT 24
Finished Mar 17 12:37:26 PM PDT 24
Peak memory 196084 kb
Host smart-a631163c-2015-4816-bf5d-fd8dfb7e74dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293975125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4293975125
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.715976560
Short name T840
Test name
Test status
Simulation time 5295780151 ps
CPU time 15.64 seconds
Started Mar 17 12:37:12 PM PDT 24
Finished Mar 17 12:37:29 PM PDT 24
Peak memory 199716 kb
Host smart-e43d6f8a-fb95-4de0-808c-d3eb41a2ea53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715976560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.715976560
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3322602636
Short name T1035
Test name
Test status
Simulation time 5709819174 ps
CPU time 1.74 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:37:17 PM PDT 24
Peak memory 199228 kb
Host smart-0b9719ad-b463-4673-93f8-02ecc0b959ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322602636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3322602636
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3629027307
Short name T279
Test name
Test status
Simulation time 45939522976 ps
CPU time 23.21 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:37:38 PM PDT 24
Peak memory 200020 kb
Host smart-9bb03a2a-17f2-4a49-80a7-2ce8030cf966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629027307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3629027307
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.674200705
Short name T975
Test name
Test status
Simulation time 129395063 ps
CPU time 0.55 seconds
Started Mar 17 12:37:16 PM PDT 24
Finished Mar 17 12:37:16 PM PDT 24
Peak memory 195444 kb
Host smart-b29a8673-0d5e-42d0-b37a-6c9dbcfc6c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674200705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.674200705
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.915978608
Short name T834
Test name
Test status
Simulation time 435793309113 ps
CPU time 100.85 seconds
Started Mar 17 12:37:11 PM PDT 24
Finished Mar 17 12:38:52 PM PDT 24
Peak memory 199916 kb
Host smart-99959eb7-525d-4eea-b21e-4c64928f26e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915978608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.915978608
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2373822788
Short name T402
Test name
Test status
Simulation time 133528430964 ps
CPU time 40.83 seconds
Started Mar 17 12:37:13 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 199804 kb
Host smart-957f6ab3-41f8-49d6-a9a1-c712ecf6d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373822788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2373822788
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.3646990132
Short name T629
Test name
Test status
Simulation time 251733810211 ps
CPU time 196.59 seconds
Started Mar 17 12:37:16 PM PDT 24
Finished Mar 17 12:40:32 PM PDT 24
Peak memory 199064 kb
Host smart-b03de5c1-f861-48b5-a404-dd581a14f7a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646990132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3646990132
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3871350392
Short name T917
Test name
Test status
Simulation time 220703481267 ps
CPU time 281.11 seconds
Started Mar 17 12:37:13 PM PDT 24
Finished Mar 17 12:41:54 PM PDT 24
Peak memory 199996 kb
Host smart-4659a27f-4cf7-43f3-ac2b-5a12ad32430f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871350392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3871350392
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2105259947
Short name T539
Test name
Test status
Simulation time 1370256605 ps
CPU time 3.09 seconds
Started Mar 17 12:37:17 PM PDT 24
Finished Mar 17 12:37:21 PM PDT 24
Peak memory 196112 kb
Host smart-4fb79011-d600-407b-9c4e-86509f00a1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105259947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2105259947
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2385886081
Short name T979
Test name
Test status
Simulation time 110322191303 ps
CPU time 78.11 seconds
Started Mar 17 12:37:12 PM PDT 24
Finished Mar 17 12:38:31 PM PDT 24
Peak memory 200072 kb
Host smart-6f154116-d0ab-40fb-a4d8-812b630f40a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385886081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2385886081
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.4176758713
Short name T623
Test name
Test status
Simulation time 13018704952 ps
CPU time 636.9 seconds
Started Mar 17 12:37:17 PM PDT 24
Finished Mar 17 12:47:55 PM PDT 24
Peak memory 199948 kb
Host smart-74f25adc-b3e2-4485-b665-baadcc194342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176758713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.4176758713
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.4018681052
Short name T929
Test name
Test status
Simulation time 1912224500 ps
CPU time 3.44 seconds
Started Mar 17 12:37:18 PM PDT 24
Finished Mar 17 12:37:22 PM PDT 24
Peak memory 197904 kb
Host smart-bc64e736-d378-4bcb-a815-4a73d9783d7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4018681052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4018681052
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.4244267029
Short name T259
Test name
Test status
Simulation time 22279602810 ps
CPU time 80.14 seconds
Started Mar 17 12:37:15 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 199984 kb
Host smart-a6eea8f8-259c-4f28-8345-e9c2565f0ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244267029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4244267029
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.278003349
Short name T1032
Test name
Test status
Simulation time 64497014877 ps
CPU time 22.41 seconds
Started Mar 17 12:37:19 PM PDT 24
Finished Mar 17 12:37:42 PM PDT 24
Peak memory 196088 kb
Host smart-d3ee97e9-8e62-4bef-b045-fe941c3b63f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278003349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.278003349
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3783471388
Short name T1016
Test name
Test status
Simulation time 113089623 ps
CPU time 0.84 seconds
Started Mar 17 12:37:13 PM PDT 24
Finished Mar 17 12:37:14 PM PDT 24
Peak memory 198256 kb
Host smart-5afc7a66-48e2-45d3-a96f-5c102ee4d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783471388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3783471388
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3059831227
Short name T614
Test name
Test status
Simulation time 2221145550 ps
CPU time 2.35 seconds
Started Mar 17 12:37:14 PM PDT 24
Finished Mar 17 12:37:17 PM PDT 24
Peak memory 198596 kb
Host smart-916618a0-8713-4c19-a315-b0e0a806566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059831227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3059831227
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3025034684
Short name T524
Test name
Test status
Simulation time 24791260395 ps
CPU time 38.45 seconds
Started Mar 17 12:37:16 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 200012 kb
Host smart-f2a61920-cfd9-4219-8434-3baab50a29e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025034684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3025034684
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3772668128
Short name T1033
Test name
Test status
Simulation time 23020965 ps
CPU time 0.56 seconds
Started Mar 17 12:37:19 PM PDT 24
Finished Mar 17 12:37:20 PM PDT 24
Peak memory 195404 kb
Host smart-1e6422f4-b6bf-4f09-ab66-33c81f8796a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772668128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3772668128
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.894495089
Short name T407
Test name
Test status
Simulation time 175039981547 ps
CPU time 620.83 seconds
Started Mar 17 12:37:11 PM PDT 24
Finished Mar 17 12:47:34 PM PDT 24
Peak memory 199988 kb
Host smart-954c2c53-d81d-493b-8ae8-8f11eeefdab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894495089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.894495089
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.188487061
Short name T639
Test name
Test status
Simulation time 84675275064 ps
CPU time 44.39 seconds
Started Mar 17 12:37:18 PM PDT 24
Finished Mar 17 12:38:03 PM PDT 24
Peak memory 199960 kb
Host smart-5307e694-967a-4202-aba6-7026f55a6e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188487061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.188487061
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3108387797
Short name T470
Test name
Test status
Simulation time 9916969462 ps
CPU time 14.99 seconds
Started Mar 17 12:37:21 PM PDT 24
Finished Mar 17 12:37:37 PM PDT 24
Peak memory 200024 kb
Host smart-0b65c9fa-b68c-455f-aacd-686ec8d567ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108387797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3108387797
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3871517434
Short name T1109
Test name
Test status
Simulation time 54612744538 ps
CPU time 98.42 seconds
Started Mar 17 12:37:20 PM PDT 24
Finished Mar 17 12:38:58 PM PDT 24
Peak memory 200120 kb
Host smart-153fcfd7-3ea1-42b4-ab63-b5950532119d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871517434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3871517434
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1247481671
Short name T969
Test name
Test status
Simulation time 63391823597 ps
CPU time 58.71 seconds
Started Mar 17 12:37:22 PM PDT 24
Finished Mar 17 12:38:21 PM PDT 24
Peak memory 199980 kb
Host smart-8846de19-deba-4d28-9a28-8d2e2ed63970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247481671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1247481671
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1767480821
Short name T1097
Test name
Test status
Simulation time 7472727426 ps
CPU time 3.29 seconds
Started Mar 17 12:37:21 PM PDT 24
Finished Mar 17 12:37:25 PM PDT 24
Peak memory 198472 kb
Host smart-1b4085ef-abc9-4453-8480-91aa35e3ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767480821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1767480821
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2456577703
Short name T654
Test name
Test status
Simulation time 55002284296 ps
CPU time 48.61 seconds
Started Mar 17 12:37:22 PM PDT 24
Finished Mar 17 12:38:12 PM PDT 24
Peak memory 208260 kb
Host smart-aa4dcac7-b6e0-499a-b015-dbfc4374eee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456577703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2456577703
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.982838314
Short name T787
Test name
Test status
Simulation time 8194517321 ps
CPU time 115.41 seconds
Started Mar 17 12:37:20 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 199936 kb
Host smart-b2d6a597-af6a-47de-a7ac-73eff160b85b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982838314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.982838314
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.4111514283
Short name T576
Test name
Test status
Simulation time 5131453370 ps
CPU time 11.2 seconds
Started Mar 17 12:37:23 PM PDT 24
Finished Mar 17 12:37:35 PM PDT 24
Peak memory 199088 kb
Host smart-e5914ec4-5d27-4078-861c-20f80a14ad7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111514283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4111514283
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2188072628
Short name T593
Test name
Test status
Simulation time 9026876295 ps
CPU time 15.31 seconds
Started Mar 17 12:37:19 PM PDT 24
Finished Mar 17 12:37:35 PM PDT 24
Peak memory 200004 kb
Host smart-c3a640e9-ba1c-4604-ab35-456ff1ce2d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188072628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2188072628
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3931051117
Short name T688
Test name
Test status
Simulation time 3111195644 ps
CPU time 1.42 seconds
Started Mar 17 12:37:20 PM PDT 24
Finished Mar 17 12:37:21 PM PDT 24
Peak memory 196040 kb
Host smart-9b724acc-2baa-4253-8e45-2e24ed674fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931051117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3931051117
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1773417658
Short name T448
Test name
Test status
Simulation time 5566629193 ps
CPU time 21.81 seconds
Started Mar 17 12:37:13 PM PDT 24
Finished Mar 17 12:37:35 PM PDT 24
Peak memory 199856 kb
Host smart-85213353-e7a4-4093-afb7-f5ac70c65fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773417658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1773417658
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2288469545
Short name T24
Test name
Test status
Simulation time 306058217704 ps
CPU time 148.91 seconds
Started Mar 17 12:37:20 PM PDT 24
Finished Mar 17 12:39:49 PM PDT 24
Peak memory 208488 kb
Host smart-dd104f6e-92fb-41f0-9aa3-428f08d5a8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288469545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2288469545
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3208050564
Short name T536
Test name
Test status
Simulation time 7189278365 ps
CPU time 14.94 seconds
Started Mar 17 12:37:20 PM PDT 24
Finished Mar 17 12:37:35 PM PDT 24
Peak memory 199292 kb
Host smart-371f96fa-4350-4294-a15c-f6fc5bd47f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208050564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3208050564
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2648786838
Short name T288
Test name
Test status
Simulation time 61479943359 ps
CPU time 23.28 seconds
Started Mar 17 12:37:17 PM PDT 24
Finished Mar 17 12:37:40 PM PDT 24
Peak memory 200228 kb
Host smart-fd66a590-7692-4a00-a4c3-6805d03b5242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648786838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2648786838
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4286540353
Short name T974
Test name
Test status
Simulation time 22212830 ps
CPU time 0.51 seconds
Started Mar 17 12:37:28 PM PDT 24
Finished Mar 17 12:37:29 PM PDT 24
Peak memory 194456 kb
Host smart-9df51e54-c2eb-47a2-b4ce-8230d84df2d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286540353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4286540353
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.740487159
Short name T746
Test name
Test status
Simulation time 134412619898 ps
CPU time 58.9 seconds
Started Mar 17 12:37:22 PM PDT 24
Finished Mar 17 12:38:21 PM PDT 24
Peak memory 200012 kb
Host smart-32c632b6-33e4-46b7-90e4-c65df0fd2a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740487159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.740487159
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.886221748
Short name T477
Test name
Test status
Simulation time 16690022864 ps
CPU time 30.81 seconds
Started Mar 17 12:37:20 PM PDT 24
Finished Mar 17 12:37:51 PM PDT 24
Peak memory 200036 kb
Host smart-014be294-36ac-494e-b3eb-81e613881d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886221748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.886221748
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.1072454704
Short name T1041
Test name
Test status
Simulation time 5871951173 ps
CPU time 4.49 seconds
Started Mar 17 12:37:22 PM PDT 24
Finished Mar 17 12:37:28 PM PDT 24
Peak memory 199992 kb
Host smart-3b41fac2-6871-443c-a43d-57a73d7b0063
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072454704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1072454704
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.282013701
Short name T20
Test name
Test status
Simulation time 44532006026 ps
CPU time 164.38 seconds
Started Mar 17 12:37:19 PM PDT 24
Finished Mar 17 12:40:04 PM PDT 24
Peak memory 200012 kb
Host smart-d5992675-8bf0-471b-af35-0b3deb0fcccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282013701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.282013701
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2991731341
Short name T784
Test name
Test status
Simulation time 8036449121 ps
CPU time 9.39 seconds
Started Mar 17 12:37:23 PM PDT 24
Finished Mar 17 12:37:33 PM PDT 24
Peak memory 199632 kb
Host smart-653aa8fc-7c4f-4518-abce-8b0c344c77aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991731341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2991731341
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3821797754
Short name T263
Test name
Test status
Simulation time 132213838835 ps
CPU time 57.24 seconds
Started Mar 17 12:37:23 PM PDT 24
Finished Mar 17 12:38:21 PM PDT 24
Peak memory 200260 kb
Host smart-92ec8683-4a39-4df0-bef0-44ac42b92a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821797754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3821797754
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.568956331
Short name T816
Test name
Test status
Simulation time 3218352879 ps
CPU time 45.45 seconds
Started Mar 17 12:37:18 PM PDT 24
Finished Mar 17 12:38:04 PM PDT 24
Peak memory 200064 kb
Host smart-ccdeea7c-b03e-48e7-b50f-f720e0a31e9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568956331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.568956331
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2872609050
Short name T395
Test name
Test status
Simulation time 4576835416 ps
CPU time 14.71 seconds
Started Mar 17 12:37:21 PM PDT 24
Finished Mar 17 12:37:36 PM PDT 24
Peak memory 199472 kb
Host smart-b0c51b5c-2ab4-4f2d-8e73-8be7e62d54fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872609050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2872609050
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2822116314
Short name T1058
Test name
Test status
Simulation time 113283474276 ps
CPU time 18.61 seconds
Started Mar 17 12:37:21 PM PDT 24
Finished Mar 17 12:37:40 PM PDT 24
Peak memory 199868 kb
Host smart-61f2d666-d93c-467f-86aa-576e5753dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822116314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2822116314
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3254331779
Short name T459
Test name
Test status
Simulation time 4355226515 ps
CPU time 8.08 seconds
Started Mar 17 12:37:21 PM PDT 24
Finished Mar 17 12:37:29 PM PDT 24
Peak memory 196084 kb
Host smart-ee0c34e7-065c-4762-b6a8-b61cf1a54b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254331779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3254331779
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1692540408
Short name T672
Test name
Test status
Simulation time 494898114 ps
CPU time 2.08 seconds
Started Mar 17 12:37:23 PM PDT 24
Finished Mar 17 12:37:26 PM PDT 24
Peak memory 198348 kb
Host smart-4a11c303-2290-4221-a494-e296d7a5c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692540408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1692540408
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.994641361
Short name T322
Test name
Test status
Simulation time 336825734774 ps
CPU time 598.83 seconds
Started Mar 17 12:37:27 PM PDT 24
Finished Mar 17 12:47:26 PM PDT 24
Peak memory 200416 kb
Host smart-9c9360d0-bb5e-4829-bbe9-38be2e3e574b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994641361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.994641361
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.878295356
Short name T786
Test name
Test status
Simulation time 1172428212 ps
CPU time 3.7 seconds
Started Mar 17 12:37:22 PM PDT 24
Finished Mar 17 12:37:27 PM PDT 24
Peak memory 199204 kb
Host smart-d5039426-5849-484c-99ee-3f5175fc0b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878295356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.878295356
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1174420986
Short name T721
Test name
Test status
Simulation time 96770556605 ps
CPU time 113.88 seconds
Started Mar 17 12:37:20 PM PDT 24
Finished Mar 17 12:39:14 PM PDT 24
Peak memory 199884 kb
Host smart-6acf7ca1-0052-4e95-9993-6c4e7e0da92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174420986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1174420986
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.565896432
Short name T405
Test name
Test status
Simulation time 28295257 ps
CPU time 0.56 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:37:32 PM PDT 24
Peak memory 194376 kb
Host smart-4753f24d-a1d6-4365-9602-61d59743f386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565896432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.565896432
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2844256352
Short name T670
Test name
Test status
Simulation time 50464022098 ps
CPU time 75.57 seconds
Started Mar 17 12:37:27 PM PDT 24
Finished Mar 17 12:38:43 PM PDT 24
Peak memory 200356 kb
Host smart-a2183156-1034-4de6-aee8-5f779baa2b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844256352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2844256352
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2168651
Short name T307
Test name
Test status
Simulation time 56097397655 ps
CPU time 61.07 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:38:34 PM PDT 24
Peak memory 199880 kb
Host smart-65c6f76b-b056-4ee1-9229-5ac662c2b897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2168651
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2921611262
Short name T616
Test name
Test status
Simulation time 323244443210 ps
CPU time 75.34 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:38:47 PM PDT 24
Peak memory 199956 kb
Host smart-162d970a-3ff6-4de7-b9bf-c542d8f1ca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921611262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2921611262
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.431164744
Short name T857
Test name
Test status
Simulation time 55870457962 ps
CPU time 27.5 seconds
Started Mar 17 12:37:28 PM PDT 24
Finished Mar 17 12:37:57 PM PDT 24
Peak memory 199972 kb
Host smart-8bfcf6fc-6dbe-41f1-8eae-71c77b1fd72a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431164744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.431164744
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.714038953
Short name T1013
Test name
Test status
Simulation time 211599886079 ps
CPU time 183.69 seconds
Started Mar 17 12:37:30 PM PDT 24
Finished Mar 17 12:40:34 PM PDT 24
Peak memory 199936 kb
Host smart-4e0ddf27-cc09-4af1-a020-0de41dbc14d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=714038953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.714038953
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3646949204
Short name T473
Test name
Test status
Simulation time 1549973767 ps
CPU time 1.37 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:37:34 PM PDT 24
Peak memory 197340 kb
Host smart-0e90581c-3982-4fd9-b396-688f25c0404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646949204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3646949204
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.502488936
Short name T796
Test name
Test status
Simulation time 48984089646 ps
CPU time 86.51 seconds
Started Mar 17 12:37:25 PM PDT 24
Finished Mar 17 12:38:52 PM PDT 24
Peak memory 199936 kb
Host smart-12d05222-bb38-4851-bc34-447c8113dc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502488936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.502488936
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3271616797
Short name T491
Test name
Test status
Simulation time 5615321489 ps
CPU time 130.21 seconds
Started Mar 17 12:37:26 PM PDT 24
Finished Mar 17 12:39:37 PM PDT 24
Peak memory 200012 kb
Host smart-5bc3439b-f970-4ee9-9cf8-821c563e8ccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271616797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3271616797
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.918007874
Short name T381
Test name
Test status
Simulation time 4702978623 ps
CPU time 20.31 seconds
Started Mar 17 12:37:29 PM PDT 24
Finished Mar 17 12:37:50 PM PDT 24
Peak memory 200064 kb
Host smart-bbe83750-08d0-40a9-bd34-dc4e91857a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918007874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.918007874
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.4230760659
Short name T856
Test name
Test status
Simulation time 122839881839 ps
CPU time 217.67 seconds
Started Mar 17 12:37:25 PM PDT 24
Finished Mar 17 12:41:03 PM PDT 24
Peak memory 200028 kb
Host smart-2357d8ae-3af9-46f7-8bd7-ebf190067b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230760659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4230760659
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1190922695
Short name T484
Test name
Test status
Simulation time 66675449596 ps
CPU time 27.91 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:38:00 PM PDT 24
Peak memory 196076 kb
Host smart-7d313145-2b4f-42d8-8e04-bedb1b4bd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190922695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1190922695
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3737121236
Short name T1005
Test name
Test status
Simulation time 297667425 ps
CPU time 1.14 seconds
Started Mar 17 12:37:30 PM PDT 24
Finished Mar 17 12:37:31 PM PDT 24
Peak memory 198604 kb
Host smart-79332949-b481-4275-a598-94e5a4a351fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737121236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3737121236
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.781489656
Short name T668
Test name
Test status
Simulation time 380607742479 ps
CPU time 2080.41 seconds
Started Mar 17 12:37:27 PM PDT 24
Finished Mar 17 01:12:08 PM PDT 24
Peak memory 199976 kb
Host smart-87fc80db-e865-4fc9-8334-8b3405ad43d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781489656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.781489656
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2635435748
Short name T40
Test name
Test status
Simulation time 33771745556 ps
CPU time 398.24 seconds
Started Mar 17 12:37:28 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 213764 kb
Host smart-d7d6bcd7-e548-42bf-8f48-3a8e36b38b64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635435748 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2635435748
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1329595664
Short name T869
Test name
Test status
Simulation time 6365195862 ps
CPU time 29.98 seconds
Started Mar 17 12:37:25 PM PDT 24
Finished Mar 17 12:37:56 PM PDT 24
Peak memory 199940 kb
Host smart-8c61d090-b140-4c93-b47c-58f832fbcf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329595664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1329595664
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2202078455
Short name T1023
Test name
Test status
Simulation time 28727669348 ps
CPU time 46.15 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:38:18 PM PDT 24
Peak memory 200008 kb
Host smart-0f1bbcb0-7325-40bf-8de5-4261b4f2b6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202078455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2202078455
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3707682250
Short name T842
Test name
Test status
Simulation time 12138854 ps
CPU time 0.56 seconds
Started Mar 17 12:37:34 PM PDT 24
Finished Mar 17 12:37:35 PM PDT 24
Peak memory 195452 kb
Host smart-8b4a59b7-dc61-40e0-ba79-cd6c3796d58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707682250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3707682250
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1373184605
Short name T848
Test name
Test status
Simulation time 14250146985 ps
CPU time 23.55 seconds
Started Mar 17 12:37:28 PM PDT 24
Finished Mar 17 12:37:52 PM PDT 24
Peak memory 199904 kb
Host smart-7d6e02b9-9a2b-464b-b29c-ee19fda23a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373184605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1373184605
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.4109489092
Short name T801
Test name
Test status
Simulation time 68193977315 ps
CPU time 30.17 seconds
Started Mar 17 12:37:26 PM PDT 24
Finished Mar 17 12:37:56 PM PDT 24
Peak memory 199688 kb
Host smart-c0073378-eb4f-4a56-b5a9-ab0025fc1d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109489092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.4109489092
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1591022507
Short name T261
Test name
Test status
Simulation time 23565159762 ps
CPU time 26.49 seconds
Started Mar 17 12:37:28 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 200016 kb
Host smart-9d6e9069-8ba7-4134-8a16-548091b320cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591022507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1591022507
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3579217460
Short name T887
Test name
Test status
Simulation time 546761954122 ps
CPU time 466.87 seconds
Started Mar 17 12:37:34 PM PDT 24
Finished Mar 17 12:45:22 PM PDT 24
Peak memory 200232 kb
Host smart-a39e9343-12d0-4819-86e4-cd166eab6802
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579217460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3579217460
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.762922504
Short name T767
Test name
Test status
Simulation time 169079797550 ps
CPU time 787.12 seconds
Started Mar 17 12:37:36 PM PDT 24
Finished Mar 17 12:50:44 PM PDT 24
Peak memory 199952 kb
Host smart-1e600719-ecb3-4726-9c07-00c5906a4454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762922504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.762922504
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2363648111
Short name T1031
Test name
Test status
Simulation time 6209452391 ps
CPU time 10.83 seconds
Started Mar 17 12:37:35 PM PDT 24
Finished Mar 17 12:37:47 PM PDT 24
Peak memory 199508 kb
Host smart-a8e0f203-dffa-4521-a25a-deeda76e9a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363648111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2363648111
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.254327930
Short name T535
Test name
Test status
Simulation time 96427201272 ps
CPU time 237.14 seconds
Started Mar 17 12:37:35 PM PDT 24
Finished Mar 17 12:41:34 PM PDT 24
Peak memory 200228 kb
Host smart-8e86d788-6285-4d77-affd-122f27d2f349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254327930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.254327930
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3970635902
Short name T970
Test name
Test status
Simulation time 5605091225 ps
CPU time 348.16 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:43:21 PM PDT 24
Peak memory 200100 kb
Host smart-cd8fd7a7-b3b0-46a9-a59a-fd3657de75a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3970635902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3970635902
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.824902225
Short name T904
Test name
Test status
Simulation time 2233436029 ps
CPU time 13.14 seconds
Started Mar 17 12:37:36 PM PDT 24
Finished Mar 17 12:37:50 PM PDT 24
Peak memory 198568 kb
Host smart-4033647d-9c0d-45d2-9b26-aad8d7c2adc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824902225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.824902225
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.609454444
Short name T957
Test name
Test status
Simulation time 71402477861 ps
CPU time 14.77 seconds
Started Mar 17 12:37:35 PM PDT 24
Finished Mar 17 12:37:51 PM PDT 24
Peak memory 199956 kb
Host smart-eb7d5dd2-7b8d-4d02-a763-e6f9eba9dd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609454444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.609454444
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1495142222
Short name T1092
Test name
Test status
Simulation time 41952669596 ps
CPU time 16.77 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:37:48 PM PDT 24
Peak memory 196088 kb
Host smart-079c237a-c9a9-4b93-8dc9-4cd6913c3727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495142222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1495142222
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3196363701
Short name T389
Test name
Test status
Simulation time 802695746 ps
CPU time 3.85 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:37:36 PM PDT 24
Peak memory 199872 kb
Host smart-fe2ae745-6cc3-49b3-8dba-c642d2516948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196363701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3196363701
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2624306420
Short name T114
Test name
Test status
Simulation time 188878477163 ps
CPU time 275.01 seconds
Started Mar 17 12:37:36 PM PDT 24
Finished Mar 17 12:42:12 PM PDT 24
Peak memory 199968 kb
Host smart-634327f5-32a8-469a-9bf4-80de5995a793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624306420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2624306420
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3350977133
Short name T366
Test name
Test status
Simulation time 599666964 ps
CPU time 1.87 seconds
Started Mar 17 12:37:33 PM PDT 24
Finished Mar 17 12:37:36 PM PDT 24
Peak memory 198304 kb
Host smart-6131c541-4d7f-40a0-a186-a9933dbe0fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350977133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3350977133
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3044132969
Short name T759
Test name
Test status
Simulation time 78768571436 ps
CPU time 161.27 seconds
Started Mar 17 12:37:32 PM PDT 24
Finished Mar 17 12:40:14 PM PDT 24
Peak memory 199944 kb
Host smart-ee3b0bbe-6450-4f40-b2ae-0d0e94e028ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044132969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3044132969
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2242843771
Short name T392
Test name
Test status
Simulation time 108113904 ps
CPU time 0.53 seconds
Started Mar 17 12:37:42 PM PDT 24
Finished Mar 17 12:37:43 PM PDT 24
Peak memory 194940 kb
Host smart-eabf0166-bafb-45ff-97a7-67885cda7059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242843771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2242843771
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1281932827
Short name T709
Test name
Test status
Simulation time 25167894909 ps
CPU time 46.91 seconds
Started Mar 17 12:37:39 PM PDT 24
Finished Mar 17 12:38:26 PM PDT 24
Peak memory 199996 kb
Host smart-730f61db-58d1-440d-8c34-53a2ac9f5b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281932827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1281932827
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2978381299
Short name T643
Test name
Test status
Simulation time 102963178157 ps
CPU time 29.28 seconds
Started Mar 17 12:37:33 PM PDT 24
Finished Mar 17 12:38:03 PM PDT 24
Peak memory 199996 kb
Host smart-9cd30c80-f1d6-4706-acc5-65184086a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978381299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2978381299
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3698003883
Short name T398
Test name
Test status
Simulation time 65084283766 ps
CPU time 93.32 seconds
Started Mar 17 12:37:33 PM PDT 24
Finished Mar 17 12:39:06 PM PDT 24
Peak memory 199784 kb
Host smart-dd28002c-1a0c-4be8-8338-18ac21e8f9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698003883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3698003883
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.818007368
Short name T359
Test name
Test status
Simulation time 42918889699 ps
CPU time 33.33 seconds
Started Mar 17 12:37:34 PM PDT 24
Finished Mar 17 12:38:08 PM PDT 24
Peak memory 200012 kb
Host smart-10b3639d-4228-47cf-8e4c-1a56d96f6270
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818007368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.818007368
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2139254332
Short name T603
Test name
Test status
Simulation time 61085745420 ps
CPU time 107.25 seconds
Started Mar 17 12:37:44 PM PDT 24
Finished Mar 17 12:39:34 PM PDT 24
Peak memory 199952 kb
Host smart-95a857d0-2829-4fcf-a476-69d90a750195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139254332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2139254332
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1678013651
Short name T780
Test name
Test status
Simulation time 1518276887 ps
CPU time 3.12 seconds
Started Mar 17 12:37:42 PM PDT 24
Finished Mar 17 12:37:46 PM PDT 24
Peak memory 199184 kb
Host smart-9dcec187-f5b2-47a7-ac5f-ac1e3d82c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678013651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1678013651
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3245313036
Short name T297
Test name
Test status
Simulation time 25579277730 ps
CPU time 66.95 seconds
Started Mar 17 12:37:34 PM PDT 24
Finished Mar 17 12:38:42 PM PDT 24
Peak memory 198892 kb
Host smart-cee4ca23-605b-408e-950d-1370b9e0ae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245313036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3245313036
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3253789242
Short name T382
Test name
Test status
Simulation time 11635629285 ps
CPU time 652.14 seconds
Started Mar 17 12:37:41 PM PDT 24
Finished Mar 17 12:48:33 PM PDT 24
Peak memory 199980 kb
Host smart-2197ff3a-ae25-45a1-b72f-d34aff22e989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253789242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3253789242
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1118814560
Short name T513
Test name
Test status
Simulation time 1169121792 ps
CPU time 2.68 seconds
Started Mar 17 12:37:33 PM PDT 24
Finished Mar 17 12:37:37 PM PDT 24
Peak memory 198012 kb
Host smart-9a7f213d-b01c-4e96-8c6a-b163af3958e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118814560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1118814560
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3817267887
Short name T751
Test name
Test status
Simulation time 109750985201 ps
CPU time 167.71 seconds
Started Mar 17 12:37:43 PM PDT 24
Finished Mar 17 12:40:31 PM PDT 24
Peak memory 200036 kb
Host smart-470ca623-e31e-47be-bfcb-016c76e6d57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817267887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3817267887
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3749059480
Short name T27
Test name
Test status
Simulation time 38462049259 ps
CPU time 17.21 seconds
Started Mar 17 12:37:33 PM PDT 24
Finished Mar 17 12:37:50 PM PDT 24
Peak memory 196104 kb
Host smart-6fe34194-1087-44eb-9a7a-47d7dc6be1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749059480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3749059480
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3370622322
Short name T621
Test name
Test status
Simulation time 1073467050 ps
CPU time 1.35 seconds
Started Mar 17 12:37:39 PM PDT 24
Finished Mar 17 12:37:40 PM PDT 24
Peak memory 199216 kb
Host smart-31872154-b1e1-4faa-9939-9f9394f6d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370622322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3370622322
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2346240924
Short name T977
Test name
Test status
Simulation time 132166926118 ps
CPU time 202.32 seconds
Started Mar 17 12:37:44 PM PDT 24
Finished Mar 17 12:41:10 PM PDT 24
Peak memory 199988 kb
Host smart-d9922661-ae36-4943-a66e-d4f32179150a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346240924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2346240924
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2056572182
Short name T333
Test name
Test status
Simulation time 17866890214 ps
CPU time 199.21 seconds
Started Mar 17 12:37:43 PM PDT 24
Finished Mar 17 12:41:03 PM PDT 24
Peak memory 216648 kb
Host smart-d57f302e-95e2-4700-b48b-57d077a5cead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056572182 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2056572182
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3480744829
Short name T740
Test name
Test status
Simulation time 1099746517 ps
CPU time 1.97 seconds
Started Mar 17 12:37:42 PM PDT 24
Finished Mar 17 12:37:44 PM PDT 24
Peak memory 198772 kb
Host smart-f7b19e2f-6f85-4ab0-bffa-d637ee25db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480744829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3480744829
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3353456067
Short name T1073
Test name
Test status
Simulation time 57306651271 ps
CPU time 28.68 seconds
Started Mar 17 12:37:33 PM PDT 24
Finished Mar 17 12:38:03 PM PDT 24
Peak memory 199920 kb
Host smart-1388ee39-a35b-4d36-baab-8b0e65c01aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353456067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3353456067
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2539545760
Short name T1034
Test name
Test status
Simulation time 16454587 ps
CPU time 0.52 seconds
Started Mar 17 12:34:13 PM PDT 24
Finished Mar 17 12:34:14 PM PDT 24
Peak memory 194832 kb
Host smart-a723e476-3279-4090-bdc6-74d8043882ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539545760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2539545760
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1223062559
Short name T963
Test name
Test status
Simulation time 63052172470 ps
CPU time 90.1 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:35:34 PM PDT 24
Peak memory 200036 kb
Host smart-17bf0d3a-d1e4-4af9-b02c-9958b3981eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223062559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1223062559
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2587008416
Short name T160
Test name
Test status
Simulation time 128595447821 ps
CPU time 33.15 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:39 PM PDT 24
Peak memory 200128 kb
Host smart-df498c02-20f1-4417-b69a-cc8124db234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587008416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2587008416
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2350960897
Short name T608
Test name
Test status
Simulation time 247931886591 ps
CPU time 52.8 seconds
Started Mar 17 12:34:03 PM PDT 24
Finished Mar 17 12:34:56 PM PDT 24
Peak memory 199992 kb
Host smart-6f36a5bf-f8e3-4fc4-8be0-efa3f4d1f097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350960897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2350960897
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3419536318
Short name T461
Test name
Test status
Simulation time 31498103798 ps
CPU time 13.08 seconds
Started Mar 17 12:34:08 PM PDT 24
Finished Mar 17 12:34:21 PM PDT 24
Peak memory 197188 kb
Host smart-5bc9758e-b23e-44db-a7e7-931fa59b4b02
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419536318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3419536318
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.302370156
Short name T466
Test name
Test status
Simulation time 74040806320 ps
CPU time 429.54 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:41:16 PM PDT 24
Peak memory 200024 kb
Host smart-a2b0d488-5c8f-4237-bec6-d532813a9884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302370156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.302370156
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1110229172
Short name T53
Test name
Test status
Simulation time 8363500061 ps
CPU time 15.46 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:34:21 PM PDT 24
Peak memory 199528 kb
Host smart-a0c7677f-2c99-47ec-9933-e1530117a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110229172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1110229172
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.230796142
Short name T85
Test name
Test status
Simulation time 104769923737 ps
CPU time 93.29 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:35:40 PM PDT 24
Peak memory 198796 kb
Host smart-991c906b-1cf1-412f-aad4-0cbfdf2f7063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230796142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.230796142
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1081239020
Short name T463
Test name
Test status
Simulation time 17828475150 ps
CPU time 227.49 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:37:54 PM PDT 24
Peak memory 199952 kb
Host smart-3da02ad5-105a-4b6c-9525-c69617fcd54f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081239020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1081239020
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2459162532
Short name T421
Test name
Test status
Simulation time 2945723739 ps
CPU time 6.56 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:13 PM PDT 24
Peak memory 198276 kb
Host smart-86398f34-7004-4856-b251-c595e55e8a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459162532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2459162532
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1772331642
Short name T628
Test name
Test status
Simulation time 114735101203 ps
CPU time 46.02 seconds
Started Mar 17 12:34:08 PM PDT 24
Finished Mar 17 12:34:54 PM PDT 24
Peak memory 199184 kb
Host smart-3de3941b-292b-46f8-889e-712cb3a40a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772331642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1772331642
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2500602694
Short name T301
Test name
Test status
Simulation time 4924744301 ps
CPU time 2.58 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:09 PM PDT 24
Peak memory 196284 kb
Host smart-ea3e2290-9208-451c-ab86-af745e052531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500602694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2500602694
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1405047588
Short name T441
Test name
Test status
Simulation time 123618353 ps
CPU time 0.87 seconds
Started Mar 17 12:34:04 PM PDT 24
Finished Mar 17 12:34:05 PM PDT 24
Peak memory 197196 kb
Host smart-035bfbdf-7a45-429d-8b73-62f940c65f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405047588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1405047588
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.929372616
Short name T62
Test name
Test status
Simulation time 215638383555 ps
CPU time 484.43 seconds
Started Mar 17 12:34:05 PM PDT 24
Finished Mar 17 12:42:10 PM PDT 24
Peak memory 224800 kb
Host smart-8b3ba16b-49cd-4457-9b55-01c80c2af4ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929372616 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.929372616
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1762051314
Short name T451
Test name
Test status
Simulation time 1956650781 ps
CPU time 3.15 seconds
Started Mar 17 12:34:08 PM PDT 24
Finished Mar 17 12:34:11 PM PDT 24
Peak memory 197776 kb
Host smart-ca0eda2c-fbcb-4bf5-baf9-d33ea31d1c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762051314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1762051314
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.819221505
Short name T271
Test name
Test status
Simulation time 80009181491 ps
CPU time 26.33 seconds
Started Mar 17 12:34:06 PM PDT 24
Finished Mar 17 12:34:33 PM PDT 24
Peak memory 200072 kb
Host smart-26b7497b-94b7-4669-ac4b-2e97a24c0d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819221505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.819221505
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.4286127828
Short name T922
Test name
Test status
Simulation time 62767772019 ps
CPU time 28.4 seconds
Started Mar 17 12:37:42 PM PDT 24
Finished Mar 17 12:38:11 PM PDT 24
Peak memory 199124 kb
Host smart-289ae54b-4810-491a-b0e4-ebcc3f72fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286127828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4286127828
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1399190249
Short name T226
Test name
Test status
Simulation time 24212468706 ps
CPU time 38.37 seconds
Started Mar 17 12:37:42 PM PDT 24
Finished Mar 17 12:38:20 PM PDT 24
Peak memory 200144 kb
Host smart-a5be02ec-0d06-4760-807a-c8eb9511e3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399190249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1399190249
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1607959219
Short name T717
Test name
Test status
Simulation time 158809698855 ps
CPU time 227.13 seconds
Started Mar 17 12:37:42 PM PDT 24
Finished Mar 17 12:41:29 PM PDT 24
Peak memory 200052 kb
Host smart-41b8f75e-eedf-45a7-b6a7-ec49284f66d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607959219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1607959219
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3776312772
Short name T56
Test name
Test status
Simulation time 13141681916 ps
CPU time 26.76 seconds
Started Mar 17 12:37:43 PM PDT 24
Finished Mar 17 12:38:10 PM PDT 24
Peak memory 199944 kb
Host smart-39ead314-b64c-4681-8b8e-85bc0fcc68be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776312772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3776312772
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.4214107311
Short name T203
Test name
Test status
Simulation time 41114013373 ps
CPU time 35.69 seconds
Started Mar 17 12:37:41 PM PDT 24
Finished Mar 17 12:38:17 PM PDT 24
Peak memory 200024 kb
Host smart-278b3086-e67e-4357-9d39-bf3ce4c1ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214107311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4214107311
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3371243506
Short name T865
Test name
Test status
Simulation time 94670531796 ps
CPU time 25.33 seconds
Started Mar 17 12:37:44 PM PDT 24
Finished Mar 17 12:38:12 PM PDT 24
Peak memory 199844 kb
Host smart-0dcea720-9b83-486f-a752-3e054545cbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371243506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3371243506
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3173981311
Short name T224
Test name
Test status
Simulation time 17095373743 ps
CPU time 30.56 seconds
Started Mar 17 12:37:41 PM PDT 24
Finished Mar 17 12:38:12 PM PDT 24
Peak memory 200048 kb
Host smart-2c0ee6c8-14d3-43ee-9763-1c2690322c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173981311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3173981311
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2123203648
Short name T1110
Test name
Test status
Simulation time 8474469802 ps
CPU time 13.72 seconds
Started Mar 17 12:37:37 PM PDT 24
Finished Mar 17 12:37:52 PM PDT 24
Peak memory 199824 kb
Host smart-36b6b187-25c2-4820-bc85-be2f0cc1cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123203648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2123203648
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.789065665
Short name T671
Test name
Test status
Simulation time 99944628820 ps
CPU time 51.9 seconds
Started Mar 17 12:37:42 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 200000 kb
Host smart-1acb287b-c4ba-483a-9db8-02d0484db107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789065665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.789065665
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1400691613
Short name T429
Test name
Test status
Simulation time 30544305413 ps
CPU time 14.36 seconds
Started Mar 17 12:37:44 PM PDT 24
Finished Mar 17 12:38:02 PM PDT 24
Peak memory 199632 kb
Host smart-1e64174c-c37f-4cc9-b721-981ef675e285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400691613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1400691613
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.4062485137
Short name T108
Test name
Test status
Simulation time 47661975532 ps
CPU time 247.58 seconds
Started Mar 17 12:37:51 PM PDT 24
Finished Mar 17 12:41:58 PM PDT 24
Peak memory 216500 kb
Host smart-094c31f0-dfc8-4f03-91c8-5265615b12bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062485137 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.4062485137
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1742137844
Short name T516
Test name
Test status
Simulation time 12877050 ps
CPU time 0.55 seconds
Started Mar 17 12:34:11 PM PDT 24
Finished Mar 17 12:34:12 PM PDT 24
Peak memory 195436 kb
Host smart-eb835093-ff7a-4e90-8d31-e03cc598d7b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742137844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1742137844
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.801882016
Short name T812
Test name
Test status
Simulation time 35239792928 ps
CPU time 24.91 seconds
Started Mar 17 12:34:13 PM PDT 24
Finished Mar 17 12:34:38 PM PDT 24
Peak memory 200020 kb
Host smart-24aa85cf-3cd5-4482-9f34-20740cbe1dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801882016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.801882016
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.849005055
Short name T1039
Test name
Test status
Simulation time 49082465659 ps
CPU time 56.28 seconds
Started Mar 17 12:34:10 PM PDT 24
Finished Mar 17 12:35:07 PM PDT 24
Peak memory 200104 kb
Host smart-cc00bceb-7804-4d2c-b79d-36571262037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849005055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.849005055
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4178329288
Short name T556
Test name
Test status
Simulation time 10459885408 ps
CPU time 16.52 seconds
Started Mar 17 12:34:11 PM PDT 24
Finished Mar 17 12:34:28 PM PDT 24
Peak memory 199900 kb
Host smart-6728f61c-d050-407f-902d-419f5df710d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178329288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4178329288
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.267398701
Short name T123
Test name
Test status
Simulation time 15275390644 ps
CPU time 15.25 seconds
Started Mar 17 12:34:12 PM PDT 24
Finished Mar 17 12:34:28 PM PDT 24
Peak memory 199224 kb
Host smart-7496dbaa-5a4f-45f8-b613-46535d3ee2e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267398701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.267398701
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2822673351
Short name T725
Test name
Test status
Simulation time 79027077440 ps
CPU time 281.83 seconds
Started Mar 17 12:34:11 PM PDT 24
Finished Mar 17 12:38:54 PM PDT 24
Peak memory 200056 kb
Host smart-59430873-0f87-4531-a4db-32b8a1463e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822673351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2822673351
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2244348679
Short name T676
Test name
Test status
Simulation time 1776989567 ps
CPU time 1.34 seconds
Started Mar 17 12:34:14 PM PDT 24
Finished Mar 17 12:34:16 PM PDT 24
Peak memory 195828 kb
Host smart-6c00468f-d27e-492c-9097-b18c0aeb0277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244348679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2244348679
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3264458766
Short name T266
Test name
Test status
Simulation time 20915405059 ps
CPU time 8.51 seconds
Started Mar 17 12:34:12 PM PDT 24
Finished Mar 17 12:34:21 PM PDT 24
Peak memory 197484 kb
Host smart-41247f6e-de96-4839-9dbf-2cbb647176e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264458766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3264458766
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.590518756
Short name T59
Test name
Test status
Simulation time 8150090740 ps
CPU time 369.28 seconds
Started Mar 17 12:34:14 PM PDT 24
Finished Mar 17 12:40:25 PM PDT 24
Peak memory 199980 kb
Host smart-5ef586cc-f5d7-42bb-adef-d9108ebd532f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590518756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.590518756
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1606195087
Short name T394
Test name
Test status
Simulation time 6774354031 ps
CPU time 62.24 seconds
Started Mar 17 12:34:13 PM PDT 24
Finished Mar 17 12:35:15 PM PDT 24
Peak memory 198232 kb
Host smart-7af77966-6739-4987-b65a-1f52bf29ca25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606195087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1606195087
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.944076213
Short name T137
Test name
Test status
Simulation time 50458474942 ps
CPU time 17.35 seconds
Started Mar 17 12:34:15 PM PDT 24
Finished Mar 17 12:34:34 PM PDT 24
Peak memory 197828 kb
Host smart-7929ee0f-8034-4f82-b163-d8c4d002e903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944076213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.944076213
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2032534486
Short name T378
Test name
Test status
Simulation time 4034263626 ps
CPU time 1.28 seconds
Started Mar 17 12:34:11 PM PDT 24
Finished Mar 17 12:34:13 PM PDT 24
Peak memory 196036 kb
Host smart-2a4f8be9-0b18-4daf-970a-378487477dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032534486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2032534486
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2498024432
Short name T497
Test name
Test status
Simulation time 11179791468 ps
CPU time 7.64 seconds
Started Mar 17 12:34:15 PM PDT 24
Finished Mar 17 12:34:24 PM PDT 24
Peak memory 199380 kb
Host smart-cb7386fa-745b-4812-95b7-4ec4acbb6b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498024432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2498024432
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.717395528
Short name T985
Test name
Test status
Simulation time 135595587540 ps
CPU time 226.45 seconds
Started Mar 17 12:34:11 PM PDT 24
Finished Mar 17 12:37:58 PM PDT 24
Peak memory 199972 kb
Host smart-f2e5dca5-5f7e-4c8b-ba30-61bed1b34f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717395528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.717395528
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.4167584889
Short name T377
Test name
Test status
Simulation time 1858792878 ps
CPU time 2.25 seconds
Started Mar 17 12:34:15 PM PDT 24
Finished Mar 17 12:34:18 PM PDT 24
Peak memory 199612 kb
Host smart-1e8712a6-58ab-4bc5-b184-04c98281ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167584889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.4167584889
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3705354192
Short name T98
Test name
Test status
Simulation time 62472142770 ps
CPU time 101.96 seconds
Started Mar 17 12:34:12 PM PDT 24
Finished Mar 17 12:35:54 PM PDT 24
Peak memory 199944 kb
Host smart-49dd07c2-9e55-4e54-a9ad-6da1638430d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705354192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3705354192
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4248822892
Short name T458
Test name
Test status
Simulation time 143542841968 ps
CPU time 33.37 seconds
Started Mar 17 12:37:49 PM PDT 24
Finished Mar 17 12:38:23 PM PDT 24
Peak memory 200000 kb
Host smart-097084ea-8267-432c-adc8-a08202f91b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248822892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4248822892
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.876029837
Short name T624
Test name
Test status
Simulation time 21635492571 ps
CPU time 36.07 seconds
Started Mar 17 12:37:52 PM PDT 24
Finished Mar 17 12:38:28 PM PDT 24
Peak memory 199900 kb
Host smart-10dff96c-9f78-4cfe-8a1f-9db35eaec55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876029837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.876029837
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3258326186
Short name T232
Test name
Test status
Simulation time 16487909789 ps
CPU time 24.5 seconds
Started Mar 17 12:37:50 PM PDT 24
Finished Mar 17 12:38:15 PM PDT 24
Peak memory 199980 kb
Host smart-5c8ee255-702d-4597-88f9-4b6da66da0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258326186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3258326186
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3090372938
Short name T577
Test name
Test status
Simulation time 162277396062 ps
CPU time 188.87 seconds
Started Mar 17 12:37:52 PM PDT 24
Finished Mar 17 12:41:01 PM PDT 24
Peak memory 199996 kb
Host smart-4deb83f1-b9ee-4dc5-b794-7f792770d7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090372938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3090372938
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1522796678
Short name T38
Test name
Test status
Simulation time 180630122244 ps
CPU time 317.6 seconds
Started Mar 17 12:37:50 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 210020 kb
Host smart-ead583ca-5a62-410f-9b67-ff77b4f8d9b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522796678 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1522796678
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2259098853
Short name T156
Test name
Test status
Simulation time 46447199558 ps
CPU time 39.92 seconds
Started Mar 17 12:37:51 PM PDT 24
Finished Mar 17 12:38:32 PM PDT 24
Peak memory 199892 kb
Host smart-131ee3ad-73e6-4515-8002-86e1db666c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259098853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2259098853
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.802489521
Short name T460
Test name
Test status
Simulation time 27328758598 ps
CPU time 44.96 seconds
Started Mar 17 12:37:51 PM PDT 24
Finished Mar 17 12:38:36 PM PDT 24
Peak memory 200028 kb
Host smart-2d128985-8ad5-4080-b7a1-d073f8b771fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802489521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.802489521
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.319046250
Short name T221
Test name
Test status
Simulation time 248536003700 ps
CPU time 18.89 seconds
Started Mar 17 12:37:52 PM PDT 24
Finished Mar 17 12:38:11 PM PDT 24
Peak memory 199492 kb
Host smart-de49a074-aede-4086-a94d-b2d08125f6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319046250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.319046250
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.915090437
Short name T330
Test name
Test status
Simulation time 40480837215 ps
CPU time 158.16 seconds
Started Mar 17 12:37:51 PM PDT 24
Finished Mar 17 12:40:30 PM PDT 24
Peak memory 216476 kb
Host smart-0552ba73-0b26-44b6-8597-d0fb8cd2c5c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915090437 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.915090437
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.631975993
Short name T680
Test name
Test status
Simulation time 36058663602 ps
CPU time 28.27 seconds
Started Mar 17 12:37:49 PM PDT 24
Finished Mar 17 12:38:18 PM PDT 24
Peak memory 199956 kb
Host smart-113be5bf-0c6d-438d-bfa7-493c076d806d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631975993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.631975993
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1489093159
Short name T981
Test name
Test status
Simulation time 15403071290 ps
CPU time 11.73 seconds
Started Mar 17 12:37:52 PM PDT 24
Finished Mar 17 12:38:04 PM PDT 24
Peak memory 199436 kb
Host smart-df46e89a-2697-48a9-8e29-a1eb41350936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489093159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1489093159
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1320613018
Short name T39
Test name
Test status
Simulation time 15886329455 ps
CPU time 180.96 seconds
Started Mar 17 12:37:53 PM PDT 24
Finished Mar 17 12:40:54 PM PDT 24
Peak memory 208232 kb
Host smart-663e49a2-010d-4614-aa06-c6f1466ad427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320613018 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1320613018
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1465105019
Short name T611
Test name
Test status
Simulation time 34244092361 ps
CPU time 85.21 seconds
Started Mar 17 12:37:52 PM PDT 24
Finished Mar 17 12:39:18 PM PDT 24
Peak memory 199892 kb
Host smart-9e040661-8928-49b3-b6a4-bcb17f92a38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465105019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1465105019
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2055536991
Short name T406
Test name
Test status
Simulation time 112581366 ps
CPU time 0.54 seconds
Started Mar 17 12:34:17 PM PDT 24
Finished Mar 17 12:34:18 PM PDT 24
Peak memory 195480 kb
Host smart-1d8881ea-2df1-41ae-a087-16545c178853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055536991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2055536991
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3705108420
Short name T431
Test name
Test status
Simulation time 27064441635 ps
CPU time 45.73 seconds
Started Mar 17 12:34:16 PM PDT 24
Finished Mar 17 12:35:02 PM PDT 24
Peak memory 199720 kb
Host smart-1d6e5f47-5a35-4c5c-9f65-d71203bf9f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705108420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3705108420
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2419306353
Short name T162
Test name
Test status
Simulation time 99042946526 ps
CPU time 41.06 seconds
Started Mar 17 12:34:16 PM PDT 24
Finished Mar 17 12:34:58 PM PDT 24
Peak memory 199932 kb
Host smart-79e69ca4-5976-43e6-af25-487e67b8bf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419306353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2419306353
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.310216751
Short name T528
Test name
Test status
Simulation time 157392294874 ps
CPU time 290.16 seconds
Started Mar 17 12:34:15 PM PDT 24
Finished Mar 17 12:39:06 PM PDT 24
Peak memory 200020 kb
Host smart-9d3c7db9-5487-40ca-9a1a-b29b8e60bed6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310216751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.310216751
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3712558821
Short name T702
Test name
Test status
Simulation time 76814469953 ps
CPU time 375.72 seconds
Started Mar 17 12:34:22 PM PDT 24
Finished Mar 17 12:40:38 PM PDT 24
Peak memory 199836 kb
Host smart-a44fc392-8e16-4c33-ab5d-f7d55012867a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712558821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3712558821
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.326273584
Short name T665
Test name
Test status
Simulation time 1812039959 ps
CPU time 3.71 seconds
Started Mar 17 12:34:16 PM PDT 24
Finished Mar 17 12:34:20 PM PDT 24
Peak memory 195936 kb
Host smart-4f1899bc-a4f2-409f-93e5-29f70c935ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326273584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.326273584
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1635245104
Short name T1045
Test name
Test status
Simulation time 46991678503 ps
CPU time 89.08 seconds
Started Mar 17 12:34:10 PM PDT 24
Finished Mar 17 12:35:40 PM PDT 24
Peak memory 199324 kb
Host smart-e437eaf3-0a2a-441e-a219-de1eda25bdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635245104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1635245104
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1401908707
Short name T482
Test name
Test status
Simulation time 10914388390 ps
CPU time 135.31 seconds
Started Mar 17 12:34:21 PM PDT 24
Finished Mar 17 12:36:37 PM PDT 24
Peak memory 200112 kb
Host smart-a3fc1d6f-459b-420e-8615-e4b152e10a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401908707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1401908707
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1792433703
Short name T498
Test name
Test status
Simulation time 4883090965 ps
CPU time 15.47 seconds
Started Mar 17 12:34:15 PM PDT 24
Finished Mar 17 12:34:31 PM PDT 24
Peak memory 199068 kb
Host smart-90976295-d5a6-4a07-8372-dedc074cfc3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792433703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1792433703
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.526854941
Short name T1008
Test name
Test status
Simulation time 66234139992 ps
CPU time 59.26 seconds
Started Mar 17 12:34:12 PM PDT 24
Finished Mar 17 12:35:12 PM PDT 24
Peak memory 199880 kb
Host smart-a3d899d3-a037-4648-a119-c5e6bc617432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526854941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.526854941
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3251045096
Short name T619
Test name
Test status
Simulation time 5943847074 ps
CPU time 9.99 seconds
Started Mar 17 12:34:16 PM PDT 24
Finished Mar 17 12:34:27 PM PDT 24
Peak memory 195892 kb
Host smart-cf1abdc5-5bc0-47ad-9be5-d6c5bc4ab0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251045096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3251045096
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2611755449
Short name T677
Test name
Test status
Simulation time 653397844 ps
CPU time 1.59 seconds
Started Mar 17 12:34:14 PM PDT 24
Finished Mar 17 12:34:16 PM PDT 24
Peak memory 199560 kb
Host smart-f7d850f1-aac4-4725-a1de-89bdd651938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611755449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2611755449
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1382483276
Short name T532
Test name
Test status
Simulation time 289436563338 ps
CPU time 1715.49 seconds
Started Mar 17 12:34:18 PM PDT 24
Finished Mar 17 01:02:54 PM PDT 24
Peak memory 200036 kb
Host smart-c2669713-dd45-434a-8d99-28e8a8d1cfed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382483276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1382483276
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.218850069
Short name T793
Test name
Test status
Simulation time 1684359181 ps
CPU time 1.72 seconds
Started Mar 17 12:34:10 PM PDT 24
Finished Mar 17 12:34:11 PM PDT 24
Peak memory 199492 kb
Host smart-b18e092f-7dd1-4ca5-9cf2-79b04fa5db21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218850069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.218850069
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3307254176
Short name T568
Test name
Test status
Simulation time 18090639385 ps
CPU time 7.62 seconds
Started Mar 17 12:34:15 PM PDT 24
Finished Mar 17 12:34:24 PM PDT 24
Peak memory 199604 kb
Host smart-585475f4-6f25-4327-83a1-dbd84448f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307254176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3307254176
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2840494504
Short name T630
Test name
Test status
Simulation time 303290224453 ps
CPU time 157.83 seconds
Started Mar 17 12:37:49 PM PDT 24
Finished Mar 17 12:40:27 PM PDT 24
Peak memory 200012 kb
Host smart-f84f6d7f-0d0c-4e48-baac-3ab399908d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840494504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2840494504
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2399972475
Short name T103
Test name
Test status
Simulation time 51854507965 ps
CPU time 249.25 seconds
Started Mar 17 12:37:49 PM PDT 24
Finished Mar 17 12:41:59 PM PDT 24
Peak memory 215544 kb
Host smart-f9236fe4-736c-4c4f-8b6b-9cd3d7d2ddc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399972475 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2399972475
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.578171436
Short name T195
Test name
Test status
Simulation time 4758289850 ps
CPU time 3.16 seconds
Started Mar 17 12:37:48 PM PDT 24
Finished Mar 17 12:37:52 PM PDT 24
Peak memory 200128 kb
Host smart-1556107d-e369-40de-8888-e71e7801c3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578171436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.578171436
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.727401662
Short name T329
Test name
Test status
Simulation time 29957760943 ps
CPU time 429.31 seconds
Started Mar 17 12:37:52 PM PDT 24
Finished Mar 17 12:45:02 PM PDT 24
Peak memory 216792 kb
Host smart-5d4f7c51-b20c-45f3-8e51-c2f83db365e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727401662 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.727401662
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2268407608
Short name T710
Test name
Test status
Simulation time 16081352251 ps
CPU time 28.6 seconds
Started Mar 17 12:37:50 PM PDT 24
Finished Mar 17 12:38:19 PM PDT 24
Peak memory 199924 kb
Host smart-90484aaf-8607-46cd-bd7f-db31d2bc8fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268407608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2268407608
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.593970747
Short name T107
Test name
Test status
Simulation time 116875899880 ps
CPU time 301.06 seconds
Started Mar 17 12:37:49 PM PDT 24
Finished Mar 17 12:42:50 PM PDT 24
Peak memory 216528 kb
Host smart-75e43d83-42e7-443c-942b-c8eb51627093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593970747 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.593970747
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1454721270
Short name T731
Test name
Test status
Simulation time 77727266397 ps
CPU time 72.77 seconds
Started Mar 17 12:37:59 PM PDT 24
Finished Mar 17 12:39:12 PM PDT 24
Peak memory 199928 kb
Host smart-9dd58728-be37-4a55-a0b4-4ebfb41db368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454721270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1454721270
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3919200622
Short name T236
Test name
Test status
Simulation time 133442383769 ps
CPU time 15.01 seconds
Started Mar 17 12:38:01 PM PDT 24
Finished Mar 17 12:38:16 PM PDT 24
Peak memory 199944 kb
Host smart-ea72be0e-0095-4d70-b40c-5c43e021da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919200622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3919200622
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3867896131
Short name T163
Test name
Test status
Simulation time 158969675268 ps
CPU time 266.52 seconds
Started Mar 17 12:37:59 PM PDT 24
Finished Mar 17 12:42:26 PM PDT 24
Peak memory 200136 kb
Host smart-8fc161a0-e1f9-4e4b-943a-ba79080be34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867896131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3867896131
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1067097282
Short name T344
Test name
Test status
Simulation time 48995562491 ps
CPU time 9.47 seconds
Started Mar 17 12:37:59 PM PDT 24
Finished Mar 17 12:38:08 PM PDT 24
Peak memory 199924 kb
Host smart-b3e3907c-cc6f-4bbf-b81e-43c223509060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067097282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1067097282
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3982513159
Short name T768
Test name
Test status
Simulation time 224348933108 ps
CPU time 118.88 seconds
Started Mar 17 12:37:59 PM PDT 24
Finished Mar 17 12:39:58 PM PDT 24
Peak memory 200144 kb
Host smart-5476e71b-87fd-467b-be1b-f110d1df016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982513159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3982513159
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1500977413
Short name T34
Test name
Test status
Simulation time 44300012919 ps
CPU time 509.88 seconds
Started Mar 17 12:37:59 PM PDT 24
Finished Mar 17 12:46:29 PM PDT 24
Peak memory 216660 kb
Host smart-ca273e09-399a-4480-b490-111dd2c639fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500977413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1500977413
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1185656252
Short name T795
Test name
Test status
Simulation time 49145905526 ps
CPU time 32.71 seconds
Started Mar 17 12:37:58 PM PDT 24
Finished Mar 17 12:38:31 PM PDT 24
Peak memory 200072 kb
Host smart-5caea172-6d0e-468c-b0cb-3df1d9499fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185656252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1185656252
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2540143184
Short name T687
Test name
Test status
Simulation time 14884742 ps
CPU time 0.55 seconds
Started Mar 17 12:34:22 PM PDT 24
Finished Mar 17 12:34:23 PM PDT 24
Peak memory 195328 kb
Host smart-89c638cf-feb5-45a0-b896-539715a9cc57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540143184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2540143184
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.4258445156
Short name T121
Test name
Test status
Simulation time 153272129217 ps
CPU time 48.55 seconds
Started Mar 17 12:34:19 PM PDT 24
Finished Mar 17 12:35:09 PM PDT 24
Peak memory 199948 kb
Host smart-57bf1640-9f25-4605-9b11-b41b513f5f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258445156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.4258445156
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1752972199
Short name T890
Test name
Test status
Simulation time 33927916907 ps
CPU time 28.22 seconds
Started Mar 17 12:34:23 PM PDT 24
Finished Mar 17 12:34:51 PM PDT 24
Peak memory 199936 kb
Host smart-31e0b724-879d-4302-901b-1c68e89b3b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752972199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1752972199
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2934972013
Short name T141
Test name
Test status
Simulation time 45769249609 ps
CPU time 19.37 seconds
Started Mar 17 12:34:22 PM PDT 24
Finished Mar 17 12:34:42 PM PDT 24
Peak memory 200000 kb
Host smart-07983029-22ce-4e71-a816-30b47653dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934972013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2934972013
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1154218684
Short name T711
Test name
Test status
Simulation time 19379585579 ps
CPU time 21.2 seconds
Started Mar 17 12:34:21 PM PDT 24
Finished Mar 17 12:34:42 PM PDT 24
Peak memory 199940 kb
Host smart-7e41dd01-0175-498e-a6cb-b3235e483de7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154218684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1154218684
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.842850421
Short name T273
Test name
Test status
Simulation time 134903498905 ps
CPU time 498.45 seconds
Started Mar 17 12:34:20 PM PDT 24
Finished Mar 17 12:42:39 PM PDT 24
Peak memory 200044 kb
Host smart-d5189755-71b3-4506-8d74-5ee9f9427acd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842850421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.842850421
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1443573170
Short name T435
Test name
Test status
Simulation time 11428071158 ps
CPU time 8.64 seconds
Started Mar 17 12:34:18 PM PDT 24
Finished Mar 17 12:34:27 PM PDT 24
Peak memory 199340 kb
Host smart-e92545fd-3077-4393-8b24-9f50beca630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443573170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1443573170
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1988956994
Short name T1
Test name
Test status
Simulation time 17806624742 ps
CPU time 11.61 seconds
Started Mar 17 12:34:18 PM PDT 24
Finished Mar 17 12:34:30 PM PDT 24
Peak memory 195580 kb
Host smart-56b02c61-3ce4-47c2-bc8e-da101108f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988956994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1988956994
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2847441928
Short name T43
Test name
Test status
Simulation time 13159804385 ps
CPU time 633.62 seconds
Started Mar 17 12:34:21 PM PDT 24
Finished Mar 17 12:44:55 PM PDT 24
Peak memory 199984 kb
Host smart-1359930d-d24c-4a1f-9f6f-90279ba509e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2847441928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2847441928
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2851429343
Short name T1044
Test name
Test status
Simulation time 4496019774 ps
CPU time 36.02 seconds
Started Mar 17 12:34:28 PM PDT 24
Finished Mar 17 12:35:04 PM PDT 24
Peak memory 199996 kb
Host smart-85e6fa9b-374d-47a8-862c-845e89d69ffe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851429343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2851429343
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.274701088
Short name T26
Test name
Test status
Simulation time 158718788544 ps
CPU time 206.99 seconds
Started Mar 17 12:34:19 PM PDT 24
Finished Mar 17 12:37:47 PM PDT 24
Peak memory 200232 kb
Host smart-0fe39687-d7e7-40d1-b13f-3f23e822f5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274701088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.274701088
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.824378592
Short name T293
Test name
Test status
Simulation time 3037820395 ps
CPU time 2.88 seconds
Started Mar 17 12:34:20 PM PDT 24
Finished Mar 17 12:34:23 PM PDT 24
Peak memory 195880 kb
Host smart-4c61e898-e41e-45c8-9b87-7e3a5d334624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824378592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.824378592
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.512092976
Short name T723
Test name
Test status
Simulation time 535396613 ps
CPU time 2.44 seconds
Started Mar 17 12:34:28 PM PDT 24
Finished Mar 17 12:34:30 PM PDT 24
Peak memory 198792 kb
Host smart-7ba1d7f4-177a-4a7e-8e7b-629230ff65b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512092976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.512092976
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2611144412
Short name T338
Test name
Test status
Simulation time 9615186480 ps
CPU time 10.52 seconds
Started Mar 17 12:34:19 PM PDT 24
Finished Mar 17 12:34:30 PM PDT 24
Peak memory 200032 kb
Host smart-d0930e68-62c1-40ab-8a47-f666ec8724e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611144412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2611144412
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2209569345
Short name T371
Test name
Test status
Simulation time 6314677051 ps
CPU time 23.37 seconds
Started Mar 17 12:34:21 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 199932 kb
Host smart-a95bec4d-e62f-4b1c-997e-fb6fa5f529d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209569345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2209569345
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2870208950
Short name T525
Test name
Test status
Simulation time 49239639603 ps
CPU time 90.1 seconds
Started Mar 17 12:34:20 PM PDT 24
Finished Mar 17 12:35:50 PM PDT 24
Peak memory 200036 kb
Host smart-e69fb1d8-4571-4e45-825d-b56ae0f13110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870208950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2870208950
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2595756954
Short name T144
Test name
Test status
Simulation time 30283931542 ps
CPU time 21.29 seconds
Started Mar 17 12:38:01 PM PDT 24
Finished Mar 17 12:38:22 PM PDT 24
Peak memory 200088 kb
Host smart-9164acb1-5de6-43ae-95c3-cf4989ee65e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595756954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2595756954
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.25200937
Short name T335
Test name
Test status
Simulation time 292029437131 ps
CPU time 1542.6 seconds
Started Mar 17 12:38:00 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 216724 kb
Host smart-0a8363e7-e3f1-47a6-ab0c-7ec0214bab94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200937 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.25200937
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2044739298
Short name T813
Test name
Test status
Simulation time 169954076555 ps
CPU time 135.43 seconds
Started Mar 17 12:38:01 PM PDT 24
Finished Mar 17 12:40:16 PM PDT 24
Peak memory 199992 kb
Host smart-77522364-ddaa-4dcc-b980-970a418f823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044739298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2044739298
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3253709176
Short name T340
Test name
Test status
Simulation time 14090314195 ps
CPU time 24.37 seconds
Started Mar 17 12:37:59 PM PDT 24
Finished Mar 17 12:38:23 PM PDT 24
Peak memory 198768 kb
Host smart-aea9c31a-9e0b-4fb2-a809-40faa5a20430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253709176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3253709176
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3218043772
Short name T158
Test name
Test status
Simulation time 31635023617 ps
CPU time 56.94 seconds
Started Mar 17 12:38:00 PM PDT 24
Finished Mar 17 12:38:57 PM PDT 24
Peak memory 199932 kb
Host smart-a0d74a56-6526-4f28-86d3-88f438e8122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218043772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3218043772
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2316829118
Short name T211
Test name
Test status
Simulation time 15953510825 ps
CPU time 22.84 seconds
Started Mar 17 12:38:00 PM PDT 24
Finished Mar 17 12:38:23 PM PDT 24
Peak memory 199756 kb
Host smart-9ad0c3c6-a4fc-4023-9870-806e09c0eb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316829118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2316829118
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.4191573707
Short name T140
Test name
Test status
Simulation time 52836757965 ps
CPU time 23.96 seconds
Started Mar 17 12:38:02 PM PDT 24
Finished Mar 17 12:38:26 PM PDT 24
Peak memory 199956 kb
Host smart-bebad3db-04af-4a39-a420-4079d7beadd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191573707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.4191573707
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.89604969
Short name T341
Test name
Test status
Simulation time 48527198131 ps
CPU time 198.31 seconds
Started Mar 17 12:38:00 PM PDT 24
Finished Mar 17 12:41:18 PM PDT 24
Peak memory 199980 kb
Host smart-1de4556f-349a-4b1f-aef0-e5254547ef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89604969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.89604969
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1305807402
Short name T164
Test name
Test status
Simulation time 144562349603 ps
CPU time 59.19 seconds
Started Mar 17 12:37:58 PM PDT 24
Finished Mar 17 12:38:57 PM PDT 24
Peak memory 199716 kb
Host smart-e7104043-80dd-4540-a7f6-f924e2183788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305807402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1305807402
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.951664819
Short name T105
Test name
Test status
Simulation time 1113152976408 ps
CPU time 873.89 seconds
Started Mar 17 12:37:58 PM PDT 24
Finished Mar 17 12:52:32 PM PDT 24
Peak memory 225832 kb
Host smart-e7a90230-d046-4208-b883-c9d3be10b530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951664819 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.951664819
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1706822423
Short name T100
Test name
Test status
Simulation time 19484734935 ps
CPU time 21.39 seconds
Started Mar 17 12:37:58 PM PDT 24
Finished Mar 17 12:38:20 PM PDT 24
Peak memory 199900 kb
Host smart-5c901c3d-a49a-4ca3-bedc-30f51e255b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706822423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1706822423
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.283448250
Short name T109
Test name
Test status
Simulation time 88571166144 ps
CPU time 756.51 seconds
Started Mar 17 12:37:59 PM PDT 24
Finished Mar 17 12:50:36 PM PDT 24
Peak memory 224760 kb
Host smart-adc5bf94-6aab-4c57-a5eb-ad0e65803a24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283448250 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.283448250
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4174619353
Short name T1038
Test name
Test status
Simulation time 48811127 ps
CPU time 0.58 seconds
Started Mar 17 12:34:25 PM PDT 24
Finished Mar 17 12:34:26 PM PDT 24
Peak memory 194824 kb
Host smart-2d9fe54f-fd4e-4828-8b95-78fd9ef065d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174619353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4174619353
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.4187553367
Short name T311
Test name
Test status
Simulation time 89514327655 ps
CPU time 82.11 seconds
Started Mar 17 12:34:27 PM PDT 24
Finished Mar 17 12:35:50 PM PDT 24
Peak memory 199976 kb
Host smart-00357424-f592-4182-9af4-d13eff08d4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187553367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.4187553367
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2890413727
Short name T128
Test name
Test status
Simulation time 10765006759 ps
CPU time 17.98 seconds
Started Mar 17 12:34:21 PM PDT 24
Finished Mar 17 12:34:40 PM PDT 24
Peak memory 199904 kb
Host smart-1451c32d-711a-46a1-b575-7272cafbe869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890413727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2890413727
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1600386667
Short name T225
Test name
Test status
Simulation time 178950975922 ps
CPU time 28.2 seconds
Started Mar 17 12:34:22 PM PDT 24
Finished Mar 17 12:34:51 PM PDT 24
Peak memory 200040 kb
Host smart-4e87476f-cc27-438c-b81c-24abda8cb7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600386667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1600386667
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1172932262
Short name T946
Test name
Test status
Simulation time 79665074588 ps
CPU time 139.86 seconds
Started Mar 17 12:34:20 PM PDT 24
Finished Mar 17 12:36:40 PM PDT 24
Peak memory 199596 kb
Host smart-67cf6952-947b-4b2c-ac23-3c5a0caf98c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172932262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1172932262
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2995504031
Short name T627
Test name
Test status
Simulation time 79406064493 ps
CPU time 402.31 seconds
Started Mar 17 12:34:26 PM PDT 24
Finished Mar 17 12:41:08 PM PDT 24
Peak memory 200004 kb
Host smart-d8b2e86c-e1c0-4c83-8504-f022cc126592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995504031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2995504031
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2432803541
Short name T1051
Test name
Test status
Simulation time 4442914629 ps
CPU time 8.82 seconds
Started Mar 17 12:34:26 PM PDT 24
Finished Mar 17 12:34:35 PM PDT 24
Peak memory 199328 kb
Host smart-a25d0923-a1e8-474a-a329-cb5ee84f5b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432803541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2432803541
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3711579556
Short name T270
Test name
Test status
Simulation time 121489142400 ps
CPU time 184.89 seconds
Started Mar 17 12:34:19 PM PDT 24
Finished Mar 17 12:37:24 PM PDT 24
Peak memory 208080 kb
Host smart-429b4ddc-1d0a-4686-a740-cc4d348f7997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711579556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3711579556
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.326011754
Short name T669
Test name
Test status
Simulation time 10169873607 ps
CPU time 129.28 seconds
Started Mar 17 12:34:28 PM PDT 24
Finished Mar 17 12:36:38 PM PDT 24
Peak memory 200040 kb
Host smart-1503a0b7-821c-456a-986b-f9eef6efc073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326011754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.326011754
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.196729133
Short name T444
Test name
Test status
Simulation time 2734130441 ps
CPU time 7.98 seconds
Started Mar 17 12:34:27 PM PDT 24
Finished Mar 17 12:34:36 PM PDT 24
Peak memory 198952 kb
Host smart-ae729681-a284-4d53-9a51-4c9facdb2293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196729133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.196729133
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3305454863
Short name T881
Test name
Test status
Simulation time 166038651819 ps
CPU time 200.75 seconds
Started Mar 17 12:34:27 PM PDT 24
Finished Mar 17 12:37:47 PM PDT 24
Peak memory 199964 kb
Host smart-96d572f3-abf4-49f1-843b-33ce8a2565d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305454863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3305454863
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3220554884
Short name T1037
Test name
Test status
Simulation time 2945652245 ps
CPU time 4.03 seconds
Started Mar 17 12:34:27 PM PDT 24
Finished Mar 17 12:34:32 PM PDT 24
Peak memory 195896 kb
Host smart-52f4ec25-6169-46ea-bfd1-aca9e725fb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220554884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3220554884
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3140368625
Short name T479
Test name
Test status
Simulation time 5629996470 ps
CPU time 12.98 seconds
Started Mar 17 12:34:19 PM PDT 24
Finished Mar 17 12:34:33 PM PDT 24
Peak memory 200024 kb
Host smart-951d4338-f289-45e2-aef2-6c0041a68336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140368625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3140368625
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3508354727
Short name T675
Test name
Test status
Simulation time 207176358333 ps
CPU time 510.65 seconds
Started Mar 17 12:34:26 PM PDT 24
Finished Mar 17 12:42:57 PM PDT 24
Peak memory 199952 kb
Host smart-7d36c435-ace9-4cf4-9e1d-cc0f7351cc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508354727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3508354727
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.706955339
Short name T527
Test name
Test status
Simulation time 7110939392 ps
CPU time 9.18 seconds
Started Mar 17 12:34:29 PM PDT 24
Finished Mar 17 12:34:39 PM PDT 24
Peak memory 199384 kb
Host smart-4c9cea25-105e-4149-a478-f2d5b80020e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706955339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.706955339
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1235666441
Short name T939
Test name
Test status
Simulation time 12773262597 ps
CPU time 8.98 seconds
Started Mar 17 12:34:21 PM PDT 24
Finished Mar 17 12:34:30 PM PDT 24
Peak memory 199984 kb
Host smart-1644b6dd-35ba-47c3-8e10-80356520a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235666441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1235666441
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3080955875
Short name T19
Test name
Test status
Simulation time 24736504005 ps
CPU time 39.39 seconds
Started Mar 17 12:37:58 PM PDT 24
Finished Mar 17 12:38:37 PM PDT 24
Peak memory 199956 kb
Host smart-aef78388-a773-4a3a-ad02-31e6c4a46b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080955875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3080955875
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1377484105
Short name T334
Test name
Test status
Simulation time 117314139160 ps
CPU time 596.94 seconds
Started Mar 17 12:37:58 PM PDT 24
Finished Mar 17 12:47:55 PM PDT 24
Peak memory 216476 kb
Host smart-0b72738f-86cb-4216-a114-48537ba5ef16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377484105 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1377484105
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.29121796
Short name T190
Test name
Test status
Simulation time 103777824785 ps
CPU time 15.01 seconds
Started Mar 17 12:38:08 PM PDT 24
Finished Mar 17 12:38:23 PM PDT 24
Peak memory 200008 kb
Host smart-87406e59-f3ce-402d-ade2-b8505566281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29121796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.29121796
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4207957641
Short name T237
Test name
Test status
Simulation time 28363091353 ps
CPU time 15.32 seconds
Started Mar 17 12:38:09 PM PDT 24
Finished Mar 17 12:38:25 PM PDT 24
Peak memory 199964 kb
Host smart-3ec492c7-a7b6-4815-b726-32bfc96d90cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207957641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4207957641
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2291184950
Short name T588
Test name
Test status
Simulation time 21913567898 ps
CPU time 13.81 seconds
Started Mar 17 12:38:08 PM PDT 24
Finished Mar 17 12:38:22 PM PDT 24
Peak memory 199928 kb
Host smart-3ee6b5c1-b3bb-491a-bf12-407dc01c7342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291184950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2291184950
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1537655517
Short name T210
Test name
Test status
Simulation time 175184846210 ps
CPU time 70.27 seconds
Started Mar 17 12:38:11 PM PDT 24
Finished Mar 17 12:39:21 PM PDT 24
Peak memory 200024 kb
Host smart-f7ae00e2-d90b-4411-bd39-36bb33da862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537655517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1537655517
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1889478398
Short name T636
Test name
Test status
Simulation time 168122050705 ps
CPU time 73.57 seconds
Started Mar 17 12:38:11 PM PDT 24
Finished Mar 17 12:39:25 PM PDT 24
Peak memory 200000 kb
Host smart-fa8c4a6a-60f5-40ae-adc9-ddbabe491137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889478398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1889478398
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4155622427
Short name T982
Test name
Test status
Simulation time 22258552769 ps
CPU time 53.09 seconds
Started Mar 17 12:38:08 PM PDT 24
Finished Mar 17 12:39:01 PM PDT 24
Peak memory 200072 kb
Host smart-97ae5dec-b66d-41e2-913a-3e4f6ffda951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155622427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4155622427
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2301221953
Short name T229
Test name
Test status
Simulation time 35129075879 ps
CPU time 8.34 seconds
Started Mar 17 12:38:09 PM PDT 24
Finished Mar 17 12:38:18 PM PDT 24
Peak memory 199948 kb
Host smart-eecbaea0-ec95-4359-8355-084258dec2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301221953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2301221953
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3445694801
Short name T328
Test name
Test status
Simulation time 28942606790 ps
CPU time 170.6 seconds
Started Mar 17 12:38:10 PM PDT 24
Finished Mar 17 12:41:00 PM PDT 24
Peak memory 216204 kb
Host smart-dc86055c-5e31-4c2e-a8fd-7f0bc0cfd361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445694801 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3445694801
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1713563805
Short name T876
Test name
Test status
Simulation time 27732555058 ps
CPU time 44.74 seconds
Started Mar 17 12:38:11 PM PDT 24
Finished Mar 17 12:38:57 PM PDT 24
Peak memory 199960 kb
Host smart-e112e7ba-a807-4fcd-a2a7-dc0ab5085b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713563805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1713563805
Directory /workspace/99.uart_fifo_reset/latest
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