Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83531	1			T1	440		T2	3		T3	6
all_values[1]	83531	1			T1	440		T2	3		T3	6
all_values[2]	83531	1			T1	440		T2	3		T3	6
all_values[3]	83531	1			T1	440		T2	3		T3	6
all_values[4]	83531	1			T1	440		T2	3		T3	6
all_values[5]	83531	1			T1	440		T2	3		T3	6
all_values[6]	83531	1			T1	440		T2	3		T3	6
all_values[7]	83531	1			T1	440		T2	3		T3	6

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345493

1

T1

1489

T2

12

T3

22

auto[1]

322755

1

T1

2031

T2

12

T3

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

625780

1

T1

3366

T2

19

T3

43

auto[1]

42468

1

T1

154

T2

5

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	26074	1			T1	251		T6	10		T7	15
all_values[0]	auto[0]	auto[1]	16165	1			T1	64		T2	3		T4	2
all_values[0]	auto[1]	auto[0]	24097	1			T1	38		T3	4		T6	5
all_values[0]	auto[1]	auto[1]	17195	1			T1	87		T3	2		T6	2
all_values[1]	auto[0]	auto[0]	39954	1			T1	43		T3	2		T4	2
all_values[1]	auto[0]	auto[1]	1319	1			T11	3		T47	16		T116	19
all_values[1]	auto[1]	auto[0]	40836	1			T1	397		T2	3		T3	2
all_values[1]	auto[1]	auto[1]	1422	1			T3	2		T20	17		T16	3
all_values[2]	auto[0]	auto[0]	41734	1			T1	60		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	2329	1			T1	1		T4	1		T5	1
all_values[2]	auto[1]	auto[0]	37395	1			T1	377		T2	1		T3	5
all_values[2]	auto[1]	auto[1]	2073	1			T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[0]	41250	1			T1	168		T2	3		T3	4
all_values[3]	auto[0]	auto[1]	246	1			T13	1		T15	2		T142	1
all_values[3]	auto[1]	auto[0]	41821	1			T1	272		T3	2		T7	27
all_values[3]	auto[1]	auto[1]	214	1			T11	1		T12	1		T13	2
all_values[4]	auto[0]	auto[0]	44039	1			T1	110		T2	3		T3	6
all_values[4]	auto[0]	auto[1]	245	1			T13	11		T21	6		T180	1
all_values[4]	auto[1]	auto[0]	38919	1			T1	330		T6	29		T7	6
all_values[4]	auto[1]	auto[1]	328	1			T11	1		T21	4		T252	1
all_values[5]	auto[0]	auto[0]	45218	1			T1	168		T2	3		T3	4
all_values[5]	auto[0]	auto[1]	109	1			T11	1		T35	1		T38	2
all_values[5]	auto[1]	auto[0]	38066	1			T1	272		T3	2		T6	11
all_values[5]	auto[1]	auto[1]	138	1			T11	2		T15	2		T25	1
all_values[6]	auto[0]	auto[0]	45391	1			T1	320		T3	2		T4	2
all_values[6]	auto[0]	auto[1]	111	1			T11	2		T25	3		T35	1
all_values[6]	auto[1]	auto[0]	37901	1			T1	120		T2	3		T3	4
all_values[6]	auto[1]	auto[1]	128	1			T15	1		T25	5		T35	1
all_values[7]	auto[0]	auto[0]	41093	1			T1	304		T3	4		T4	2
all_values[7]	auto[0]	auto[1]	216	1			T252	1		T22	2		T25	4
all_values[7]	auto[1]	auto[0]	41992	1			T1	136		T2	3		T3	2
all_values[7]	auto[1]	auto[1]	230	1			T11	1		T24	1		T13	2