Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	1	21	95.45

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	1	21	95.45	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

1972

1

T1

2

T2

1

T3

1

auto[UartRx]

1972

1

T1

2

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3815	1			T1	4		T2	2		T3	2
values[1]	21	1			T25	1		T38	1		T98	3
values[2]	6	1			T11	2		T125	1		T52	2
values[3]	12	1			T35	1		T40	2		T125	1
values[4]	10	1			T11	1		T25	1		T98	2
values[5]	11	1			T25	2		T38	1		T247	1
values[6]	14	1			T37	1		T39	1		T247	1
values[7]	12	1			T25	1		T26	1		T36	1
values[8]	12	1			T26	1		T38	1		T39	1
values[9]	8	1			T26	1		T37	1		T38	2
values[10]	12	1			T11	1		T34	1		T36	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	1	21	95.45	1

Automatically Generated Cross Bins for uart_reset_cg_cc

Uncovered bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	NUMBER	STATUS
[auto[UartTx]]	[values[4]]	0	1	1

Covered bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	1941	1			T1	2		T2	1		T3	1
auto[UartTx]	values[1]	10	1			T25	1		T98	1		T248	1
auto[UartTx]	values[2]	2	1			T11	1		T52	1		-	-
auto[UartTx]	values[3]	2	1			T100	1		T249	1		-	-
auto[UartTx]	values[5]	4	1			T25	1		T38	1		T248	1
auto[UartTx]	values[6]	3	1			T98	1		T250	1		T100	1
auto[UartTx]	values[7]	4	1			T36	1		T39	2		T249	1
auto[UartTx]	values[8]	2	1			T99	1		T251	1		-	-
auto[UartTx]	values[9]	1	1			T38	1		-	-		-	-
auto[UartTx]	values[10]	2	1			T250	1		T228	1		-	-
auto[UartRx]	values[0]	1874	1			T1	2		T2	1		T3	1
auto[UartRx]	values[1]	11	1			T38	1		T98	2		T250	1
auto[UartRx]	values[2]	4	1			T11	1		T125	1		T52	1
auto[UartRx]	values[3]	10	1			T35	1		T40	2		T125	1
auto[UartRx]	values[4]	10	1			T11	1		T25	1		T98	2
auto[UartRx]	values[5]	7	1			T25	1		T247	1		T99	1
auto[UartRx]	values[6]	11	1			T37	1		T39	1		T247	1
auto[UartRx]	values[7]	8	1			T25	1		T26	1		T39	1
auto[UartRx]	values[8]	10	1			T26	1		T38	1		T39	1
auto[UartRx]	values[9]	7	1			T26	1		T37	1		T38	1
auto[UartRx]	values[10]	10	1			T11	1		T34	1		T36	2