Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1878	1			T1	7		T3	1		T6	3
auto[BaudRate115200]	1623	1			T6	4		T7	1		T8	1
auto[BaudRate230400]	1604	1			T1	7		T2	1		T3	2
auto[BaudRate128Kbps]	1565	1			T1	7		T3	3		T6	2
auto[BaudRate256Kbps]	1796	1			T1	2		T2	3		T3	1
auto[BaudRate1Mbps]	1401	1			T1	5		T2	2		T5	1
auto[BaudRate1p5Mbps]	990	1			T1	3		T5	1		T20	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1015	1			T19	2		T181	10		T117	9
freqs[25]	734	1			T16	9		T42	2		T140	10
freqs[48]	386	1			T142	8		T103	5		T152	19
freqs[50]	659	1			T43	9		T13	3		T180	37
freqs[100]	1010	1			T1	31		T46	9		T127	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	203	1			T181	2		T117	3		T271	2
auto[BaudRate9600]	freqs[25]	116	1			T16	2		T42	1		T140	2
auto[BaudRate9600]	freqs[48]	52	1			T142	1		T103	1		T322	2
auto[BaudRate9600]	freqs[50]	106	1			T180	4		T132	1		T112	12
auto[BaudRate9600]	freqs[100]	203	1			T1	7		T25	12		T111	3
auto[BaudRate115200]	freqs[24]	153	1			T19	1		T181	3		T117	2
auto[BaudRate115200]	freqs[25]	114	1			T16	1		T140	2		T264	1
auto[BaudRate115200]	freqs[48]	57	1			T142	2		T103	1		T152	2
auto[BaudRate115200]	freqs[50]	77	1			T43	3		T180	6		T112	5
auto[BaudRate115200]	freqs[100]	109	1			T46	3		T127	2		T25	3
auto[BaudRate230400]	freqs[24]	154	1			T181	1		T117	1		T260	1
auto[BaudRate230400]	freqs[25]	92	1			T16	1		T140	3		T129	1
auto[BaudRate230400]	freqs[48]	57	1			T103	1		T152	2		T322	1
auto[BaudRate230400]	freqs[50]	88	1			T43	2		T180	7		T135	2
auto[BaudRate230400]	freqs[100]	131	1			T1	7		T46	2		T127	2
auto[BaudRate128Kbps]	freqs[24]	140	1			T19	1		T181	2		T271	1
auto[BaudRate128Kbps]	freqs[25]	119	1			T16	2		T42	1		T140	1
auto[BaudRate128Kbps]	freqs[48]	53	1			T152	2		T322	4		T246	2
auto[BaudRate128Kbps]	freqs[50]	101	1			T43	1		T13	3		T180	6
auto[BaudRate128Kbps]	freqs[100]	136	1			T1	7		T256	1		T128	3
auto[BaudRate256Kbps]	freqs[24]	151	1			T117	2		T323	3		T260	1
auto[BaudRate256Kbps]	freqs[25]	115	1			T16	1		T140	1		T264	2
auto[BaudRate256Kbps]	freqs[48]	57	1			T142	3		T103	1		T152	6
auto[BaudRate256Kbps]	freqs[50]	110	1			T43	2		T180	5		T135	2
auto[BaudRate256Kbps]	freqs[100]	153	1			T1	2		T46	1		T127	3
auto[BaudRate1Mbps]	freqs[24]	149	1			T181	1		T260	2		T26	4
auto[BaudRate1Mbps]	freqs[25]	120	1			T16	1		T140	1		T264	2
auto[BaudRate1Mbps]	freqs[48]	64	1			T142	2		T103	1		T152	5
auto[BaudRate1Mbps]	freqs[50]	84	1			T180	3		T132	1		T258	3
auto[BaudRate1Mbps]	freqs[100]	141	1			T1	5		T46	2		T127	1
auto[BaudRate1p5Mbps]	freqs[25]	58	1			T16	1		T129	1		T283	1
auto[BaudRate1p5Mbps]	freqs[48]	46	1			T152	2		T322	4		T246	2
auto[BaudRate1p5Mbps]	freqs[50]	93	1			T43	1		T180	6		T132	1
auto[BaudRate1p5Mbps]	freqs[100]	137	1			T1	3		T46	1		T127	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded