Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83531	1			T1	440		T2	3		T3	6
all_pins[1]	83531	1			T1	440		T2	3		T3	6
all_pins[2]	83531	1			T1	440		T2	3		T3	6
all_pins[3]	83531	1			T1	440		T2	3		T3	6
all_pins[4]	83531	1			T1	440		T2	3		T3	6
all_pins[5]	83531	1			T1	440		T2	3		T3	6
all_pins[6]	83531	1			T1	440		T2	3		T3	6
all_pins[7]	83531	1			T1	440		T2	3		T3	6

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	645790	1			T1	3431		T2	22		T3	43
values[0x1]	22458	1			T1	89		T2	2		T3	5
transitions[0x0=>0x1]	21531	1			T1	89		T2	2		T3	5
transitions[0x1=>0x0]	21101	1			T1	89		T2	2		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	66290	1			T1	353		T2	3		T3	4
all_pins[0]	values[0x1]	17241	1			T1	87		T3	2		T6	2
all_pins[0]	transitions[0x0=>0x1]	16740	1			T1	87		T3	2		T6	2
all_pins[0]	transitions[0x1=>0x0]	919	1			T3	2		T11	1		T48	1
all_pins[1]	values[0x0]	82111	1			T1	440		T2	3		T3	4
all_pins[1]	values[0x1]	1420	1			T3	2		T20	17		T16	3
all_pins[1]	transitions[0x0=>0x1]	1324	1			T3	2		T20	16		T16	3
all_pins[1]	transitions[0x1=>0x0]	2034	1			T1	2		T2	2		T3	1
all_pins[2]	values[0x0]	81401	1			T1	438		T2	1		T3	5
all_pins[2]	values[0x1]	2130	1			T1	2		T2	2		T3	1
all_pins[2]	transitions[0x0=>0x1]	2079	1			T1	2		T2	2		T3	1
all_pins[2]	transitions[0x1=>0x0]	163	1			T11	1		T12	1		T13	2
all_pins[3]	values[0x0]	83317	1			T1	440		T2	3		T3	6
all_pins[3]	values[0x1]	214	1			T11	1		T12	1		T13	2
all_pins[3]	transitions[0x0=>0x1]	178	1			T11	1		T12	1		T13	2
all_pins[3]	transitions[0x1=>0x0]	292	1			T11	1		T21	4		T252	1
all_pins[4]	values[0x0]	83203	1			T1	440		T2	3		T3	6
all_pins[4]	values[0x1]	328	1			T11	1		T21	4		T252	1
all_pins[4]	transitions[0x0=>0x1]	280	1			T11	1		T21	3		T252	1
all_pins[4]	transitions[0x1=>0x0]	119	1			T11	2		T13	2		T15	2
all_pins[5]	values[0x0]	83364	1			T1	440		T2	3		T3	6
all_pins[5]	values[0x1]	167	1			T11	2		T13	2		T15	2
all_pins[5]	transitions[0x0=>0x1]	128	1			T11	2		T13	2		T15	1
all_pins[5]	transitions[0x1=>0x0]	689	1			T16	2		T46	1		T48	2
all_pins[6]	values[0x0]	82803	1			T1	440		T2	3		T3	6
all_pins[6]	values[0x1]	728	1			T16	2		T46	1		T48	2
all_pins[6]	transitions[0x0=>0x1]	687	1			T16	2		T46	1		T48	2
all_pins[6]	transitions[0x1=>0x0]	189	1			T11	1		T24	1		T13	2
all_pins[7]	values[0x0]	83301	1			T1	440		T2	3		T3	6
all_pins[7]	values[0x1]	230	1			T11	1		T24	1		T13	2
all_pins[7]	transitions[0x0=>0x1]	115	1			T24	1		T13	2		T15	2
all_pins[7]	transitions[0x1=>0x0]	16696	1			T1	87		T3	1		T6	1