Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5703794	1			T1	8999		T2	5		T6	7
all_levels[1]	849740	1			T1	595		T3	12		T6	1
all_levels[2]	248639	1			T1	597		T6	2		T10	24
all_levels[3]	165763	1			T1	581		T10	31		T20	15
all_levels[4]	200025	1			T1	586		T6	2		T10	28
all_levels[5]	190311	1			T1	601		T6	2		T10	29
all_levels[6]	165058	1			T1	600		T6	1		T10	34
all_levels[7]	169795	1			T1	590		T6	6		T10	25
all_levels[8]	220196	1			T1	589		T6	1		T8	1
all_levels[9]	519024	1			T1	589		T6	1		T10	31
all_levels[10]	200553	1			T1	579		T3	4		T10	28
all_levels[11]	242835	1			T1	602		T6	1		T10	31
all_levels[12]	194166	1			T1	586		T8	2		T10	28
all_levels[13]	388030	1			T1	590		T8	7		T10	26
all_levels[14]	162862	1			T1	13486		T7	2		T10	27
all_levels[15]	151770	1			T1	301		T7	4		T10	28
all_levels[16]	228664	1			T1	301		T2	4		T7	1
all_levels[17]	395223	1			T1	299		T3	1		T7	2
all_levels[18]	498815	1			T1	304		T10	30		T20	5
all_levels[19]	231911	1			T1	301		T10	18		T20	10
all_levels[20]	142696	1			T1	283		T10	26		T20	12
all_levels[21]	439230	1			T1	291		T10	25		T20	6
all_levels[22]	196538	1			T1	302		T10	29		T20	11
all_levels[23]	184881	1			T1	287		T10	23		T20	11
all_levels[24]	147240	1			T1	301		T10	30		T20	5
all_levels[25]	408803	1			T1	294		T10	24		T20	3
all_levels[26]	246757	1			T1	303		T6	7		T10	27
all_levels[27]	127627	1			T1	299		T10	27		T20	13
all_levels[28]	132061	1			T1	293		T6	2		T10	27
all_levels[29]	146125	1			T1	298		T10	31		T20	4
all_levels[30]	162207	1			T1	308		T10	29		T20	3
all_levels[31]	421425	1			T1	297		T10	1150		T20	4
all_levels[32]	10546807	1			T1	2383		T2	6		T7	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24425760

1

T1

37614

T2

8

T3

12

auto[1]

3811

1

T1

1

T2

7

T3

5

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5701783	1			T1	8999		T2	3		T6	5
all_levels[0]	auto[1]	2011	1			T2	2		T6	2		T7	6
all_levels[1]	auto[0]	849448	1			T1	595		T3	9		T6	1
all_levels[1]	auto[1]	292	1			T3	3		T20	1		T42	1
all_levels[2]	auto[0]	248607	1			T1	597		T6	2		T10	24
all_levels[2]	auto[1]	32	1			T27	1		T142	2		T147	1
all_levels[3]	auto[0]	165632	1			T1	581		T10	31		T20	15
all_levels[3]	auto[1]	131	1			T21	5		T180	1		T260	1
all_levels[4]	auto[0]	199994	1			T1	586		T6	2		T10	28
all_levels[4]	auto[1]	31	1			T181	1		T146	1		T219	1
all_levels[5]	auto[0]	190290	1			T1	601		T6	2		T10	29
all_levels[5]	auto[1]	21	1			T20	2		T116	1		T254	1
all_levels[6]	auto[0]	165039	1			T1	600		T6	1		T10	34
all_levels[6]	auto[1]	19	1			T186	1		T325	1		T209	1
all_levels[7]	auto[0]	169610	1			T1	590		T6	6		T10	25
all_levels[7]	auto[1]	185	1			T265	3		T96	1		T38	4
all_levels[8]	auto[0]	220173	1			T1	589		T6	1		T8	1
all_levels[8]	auto[1]	23	1			T50	1		T166	1		T297	1
all_levels[9]	auto[0]	518995	1			T1	589		T6	1		T10	31
all_levels[9]	auto[1]	29	1			T46	1		T137	1		T284	1
all_levels[10]	auto[0]	200534	1			T1	579		T3	2		T10	28
all_levels[10]	auto[1]	19	1			T3	2		T140	3		T142	2
all_levels[11]	auto[0]	242806	1			T1	602		T6	1		T10	31
all_levels[11]	auto[1]	29	1			T122	1		T178	1		T120	1
all_levels[12]	auto[0]	194143	1			T1	586		T8	2		T10	28
all_levels[12]	auto[1]	23	1			T181	2		T95	1		T321	2
all_levels[13]	auto[0]	388006	1			T1	590		T8	7		T10	26
all_levels[13]	auto[1]	24	1			T146	1		T302	3		T93	1
all_levels[14]	auto[0]	162843	1			T1	13486		T7	2		T10	27
all_levels[14]	auto[1]	19	1			T131	2		T180	1		T325	1
all_levels[15]	auto[0]	151706	1			T1	301		T7	4		T10	28
all_levels[15]	auto[1]	64	1			T259	13		T27	2		T278	4
all_levels[16]	auto[0]	228642	1			T1	301		T2	2		T7	1
all_levels[16]	auto[1]	22	1			T2	2		T326	3		T327	1
all_levels[17]	auto[0]	395197	1			T1	299		T3	1		T7	2
all_levels[17]	auto[1]	26	1			T20	1		T181	2		T277	1
all_levels[18]	auto[0]	498792	1			T1	304		T10	30		T20	5
all_levels[18]	auto[1]	23	1			T140	1		T146	2		T137	1
all_levels[19]	auto[0]	231896	1			T1	301		T10	18		T20	10
all_levels[19]	auto[1]	15	1			T146	1		T328	1		T151	1
all_levels[20]	auto[0]	142677	1			T1	283		T10	26		T20	12
all_levels[20]	auto[1]	19	1			T129	1		T122	1		T329	1
all_levels[21]	auto[0]	439212	1			T1	291		T10	25		T20	6
all_levels[21]	auto[1]	18	1			T147	3		T322	1		T279	4
all_levels[22]	auto[0]	196517	1			T1	302		T10	29		T20	11
all_levels[22]	auto[1]	21	1			T146	1		T186	2		T193	1
all_levels[23]	auto[0]	184865	1			T1	287		T10	23		T20	11
all_levels[23]	auto[1]	16	1			T193	2		T194	1		T327	2
all_levels[24]	auto[0]	147221	1			T1	301		T10	30		T20	5
all_levels[24]	auto[1]	19	1			T49	1		T132	1		T302	2
all_levels[25]	auto[0]	408779	1			T1	294		T10	24		T20	3
all_levels[25]	auto[1]	24	1			T286	1		T189	1		T156	1
all_levels[26]	auto[0]	246737	1			T1	303		T6	3		T10	27
all_levels[26]	auto[1]	20	1			T6	4		T183	1		T220	1
all_levels[27]	auto[0]	127608	1			T1	299		T10	27		T20	13
all_levels[27]	auto[1]	19	1			T181	1		T112	3		T266	1
all_levels[28]	auto[0]	132047	1			T1	293		T6	2		T10	27
all_levels[28]	auto[1]	14	1			T103	1		T178	1		T194	1
all_levels[29]	auto[0]	146103	1			T1	298		T10	31		T20	4
all_levels[29]	auto[1]	22	1			T190	1		T330	3		T331	1
all_levels[30]	auto[0]	162174	1			T1	308		T10	29		T20	3
all_levels[30]	auto[1]	33	1			T271	1		T231	1		T120	1
all_levels[31]	auto[0]	421416	1			T1	297		T10	1150		T20	4
all_levels[31]	auto[1]	9	1			T332	1		T333	1		T236	1
all_levels[32]	auto[0]	10546268	1			T1	2382		T2	3		T7	2
all_levels[32]	auto[1]	539	1			T1	1		T2	3		T8	1