Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
508 |
1 |
|
|
T11 |
7 |
|
T15 |
4 |
|
T25 |
15 |
all_values[1] |
508 |
1 |
|
|
T11 |
7 |
|
T15 |
4 |
|
T25 |
15 |
all_values[2] |
508 |
1 |
|
|
T11 |
7 |
|
T15 |
4 |
|
T25 |
15 |
all_values[3] |
508 |
1 |
|
|
T11 |
7 |
|
T15 |
4 |
|
T25 |
15 |
all_values[4] |
508 |
1 |
|
|
T11 |
7 |
|
T15 |
4 |
|
T25 |
15 |
all_values[5] |
508 |
1 |
|
|
T11 |
7 |
|
T15 |
4 |
|
T25 |
15 |
all_values[6] |
508 |
1 |
|
|
T11 |
7 |
|
T15 |
4 |
|
T25 |
15 |
all_values[7] |
508 |
1 |
|
|
T11 |
7 |
|
T15 |
4 |
|
T25 |
15 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2094 |
1 |
|
|
T11 |
33 |
|
T15 |
20 |
|
T25 |
60 |
auto[1] |
1970 |
1 |
|
|
T11 |
23 |
|
T15 |
12 |
|
T25 |
60 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1490 |
1 |
|
|
T11 |
23 |
|
T15 |
13 |
|
T25 |
40 |
auto[1] |
2574 |
1 |
|
|
T11 |
33 |
|
T15 |
19 |
|
T25 |
80 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2386 |
1 |
|
|
T11 |
31 |
|
T15 |
19 |
|
T25 |
71 |
auto[1] |
1678 |
1 |
|
|
T11 |
25 |
|
T15 |
13 |
|
T25 |
49 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
48 |
4 |
44 |
91.67 |
4 |
Automatically Generated Cross Bins |
48 |
4 |
44 |
91.67 |
4 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Element holes
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER | STATUS |
[all_values[0]] |
[auto[0]] |
* |
[auto[0]] |
-- |
-- |
2 |
|
[all_values[1]] |
[auto[0]] |
* |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
156 |
1 |
|
|
T11 |
3 |
|
T15 |
3 |
|
T25 |
7 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
153 |
1 |
|
|
T11 |
1 |
|
T25 |
4 |
|
T36 |
3 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
102 |
1 |
|
|
T11 |
1 |
|
T15 |
1 |
|
T25 |
2 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
97 |
1 |
|
|
T11 |
2 |
|
T25 |
2 |
|
T35 |
2 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
145 |
1 |
|
|
T11 |
2 |
|
T15 |
1 |
|
T25 |
2 |
all_values[1] |
auto[0] |
auto[1] |
auto[0] |
145 |
1 |
|
|
T11 |
3 |
|
T15 |
1 |
|
T25 |
7 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
116 |
1 |
|
|
T11 |
1 |
|
T15 |
1 |
|
T25 |
4 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
102 |
1 |
|
|
T11 |
1 |
|
T15 |
1 |
|
T25 |
2 |
all_values[2] |
auto[0] |
auto[0] |
auto[0] |
111 |
1 |
|
|
T25 |
1 |
|
T35 |
4 |
|
T36 |
3 |
all_values[2] |
auto[0] |
auto[0] |
auto[1] |
41 |
1 |
|
|
T25 |
1 |
|
T38 |
3 |
|
T112 |
1 |
all_values[2] |
auto[0] |
auto[1] |
auto[0] |
89 |
1 |
|
|
T11 |
3 |
|
T15 |
1 |
|
T25 |
2 |
all_values[2] |
auto[0] |
auto[1] |
auto[1] |
55 |
1 |
|
|
T15 |
1 |
|
T25 |
3 |
|
T36 |
3 |
all_values[2] |
auto[1] |
auto[0] |
auto[1] |
119 |
1 |
|
|
T11 |
3 |
|
T15 |
1 |
|
T25 |
2 |
all_values[2] |
auto[1] |
auto[1] |
auto[1] |
93 |
1 |
|
|
T11 |
1 |
|
T15 |
1 |
|
T25 |
6 |
all_values[3] |
auto[0] |
auto[0] |
auto[0] |
104 |
1 |
|
|
T11 |
4 |
|
T15 |
2 |
|
T36 |
2 |
all_values[3] |
auto[0] |
auto[0] |
auto[1] |
57 |
1 |
|
|
T15 |
1 |
|
T25 |
4 |
|
T35 |
1 |
all_values[3] |
auto[0] |
auto[1] |
auto[0] |
97 |
1 |
|
|
T25 |
4 |
|
T35 |
2 |
|
T38 |
4 |
all_values[3] |
auto[0] |
auto[1] |
auto[1] |
40 |
1 |
|
|
T36 |
3 |
|
T38 |
1 |
|
T112 |
1 |
all_values[3] |
auto[1] |
auto[0] |
auto[1] |
122 |
1 |
|
|
T11 |
3 |
|
T15 |
1 |
|
T25 |
6 |
all_values[3] |
auto[1] |
auto[1] |
auto[1] |
88 |
1 |
|
|
T25 |
1 |
|
T35 |
2 |
|
T36 |
3 |
all_values[4] |
auto[0] |
auto[0] |
auto[0] |
102 |
1 |
|
|
T11 |
3 |
|
T15 |
2 |
|
T25 |
3 |
all_values[4] |
auto[0] |
auto[0] |
auto[1] |
43 |
1 |
|
|
T25 |
3 |
|
T35 |
3 |
|
T38 |
3 |
all_values[4] |
auto[0] |
auto[1] |
auto[0] |
89 |
1 |
|
|
T11 |
1 |
|
T25 |
1 |
|
T35 |
2 |
all_values[4] |
auto[0] |
auto[1] |
auto[1] |
65 |
1 |
|
|
T25 |
2 |
|
T38 |
3 |
|
T112 |
3 |
all_values[4] |
auto[1] |
auto[0] |
auto[1] |
102 |
1 |
|
|
T11 |
2 |
|
T15 |
2 |
|
T25 |
3 |
all_values[4] |
auto[1] |
auto[1] |
auto[1] |
107 |
1 |
|
|
T11 |
1 |
|
T25 |
3 |
|
T36 |
5 |
all_values[5] |
auto[0] |
auto[0] |
auto[0] |
93 |
1 |
|
|
T11 |
2 |
|
T25 |
4 |
|
T35 |
2 |
all_values[5] |
auto[0] |
auto[0] |
auto[1] |
51 |
1 |
|
|
T39 |
1 |
|
T40 |
2 |
|
T125 |
1 |
all_values[5] |
auto[0] |
auto[1] |
auto[0] |
87 |
1 |
|
|
T11 |
1 |
|
T15 |
1 |
|
T25 |
6 |
all_values[5] |
auto[0] |
auto[1] |
auto[1] |
60 |
1 |
|
|
T11 |
1 |
|
T15 |
1 |
|
T25 |
1 |
all_values[5] |
auto[1] |
auto[0] |
auto[1] |
104 |
1 |
|
|
T15 |
1 |
|
T25 |
2 |
|
T35 |
2 |
all_values[5] |
auto[1] |
auto[1] |
auto[1] |
113 |
1 |
|
|
T11 |
3 |
|
T15 |
1 |
|
T25 |
2 |
all_values[6] |
auto[0] |
auto[0] |
auto[0] |
105 |
1 |
|
|
T15 |
2 |
|
T25 |
3 |
|
T35 |
3 |
all_values[6] |
auto[0] |
auto[0] |
auto[1] |
42 |
1 |
|
|
T11 |
2 |
|
T25 |
1 |
|
T113 |
1 |
all_values[6] |
auto[0] |
auto[1] |
auto[0] |
98 |
1 |
|
|
T11 |
2 |
|
T15 |
1 |
|
T25 |
1 |
all_values[6] |
auto[0] |
auto[1] |
auto[1] |
49 |
1 |
|
|
T25 |
2 |
|
T35 |
1 |
|
T112 |
1 |
all_values[6] |
auto[1] |
auto[0] |
auto[1] |
102 |
1 |
|
|
T11 |
3 |
|
T15 |
1 |
|
T25 |
1 |
all_values[6] |
auto[1] |
auto[1] |
auto[1] |
112 |
1 |
|
|
T25 |
7 |
|
T36 |
3 |
|
T38 |
5 |
all_values[7] |
auto[0] |
auto[0] |
auto[0] |
127 |
1 |
|
|
T11 |
2 |
|
T15 |
1 |
|
T25 |
4 |
all_values[7] |
auto[0] |
auto[0] |
auto[1] |
41 |
1 |
|
|
T25 |
2 |
|
T35 |
2 |
|
T36 |
1 |
all_values[7] |
auto[0] |
auto[1] |
auto[0] |
98 |
1 |
|
|
T15 |
1 |
|
T25 |
2 |
|
T36 |
4 |
all_values[7] |
auto[0] |
auto[1] |
auto[1] |
43 |
1 |
|
|
T11 |
1 |
|
T25 |
1 |
|
T35 |
1 |
all_values[7] |
auto[1] |
auto[0] |
auto[1] |
109 |
1 |
|
|
T11 |
2 |
|
T25 |
5 |
|
T35 |
1 |
all_values[7] |
auto[1] |
auto[1] |
auto[1] |
90 |
1 |
|
|
T11 |
2 |
|
T15 |
2 |
|
T25 |
1 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |