Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.27 97.90 100.00 98.80 100.00 99.55


Total test records in report: 1248
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T1034 /workspace/coverage/default/5.uart_tx_rx.3406741349 Mar 19 03:09:47 PM PDT 24 Mar 19 03:11:03 PM PDT 24 379029576266 ps
T1035 /workspace/coverage/default/17.uart_alert_test.1838571842 Mar 19 03:10:05 PM PDT 24 Mar 19 03:10:07 PM PDT 24 15946059 ps
T1036 /workspace/coverage/default/30.uart_fifo_reset.1228965957 Mar 19 03:10:47 PM PDT 24 Mar 19 03:12:27 PM PDT 24 113457350753 ps
T1037 /workspace/coverage/default/26.uart_fifo_full.3167810406 Mar 19 03:10:26 PM PDT 24 Mar 19 03:12:44 PM PDT 24 92436840163 ps
T1038 /workspace/coverage/default/24.uart_fifo_reset.2473063907 Mar 19 03:10:23 PM PDT 24 Mar 19 03:10:38 PM PDT 24 17612030915 ps
T1039 /workspace/coverage/default/19.uart_stress_all.4086941246 Mar 19 03:10:14 PM PDT 24 Mar 19 03:36:06 PM PDT 24 399087742777 ps
T1040 /workspace/coverage/default/48.uart_rx_oversample.423137837 Mar 19 03:12:06 PM PDT 24 Mar 19 03:12:21 PM PDT 24 6725052633 ps
T1041 /workspace/coverage/default/24.uart_noise_filter.386842738 Mar 19 03:10:25 PM PDT 24 Mar 19 03:12:10 PM PDT 24 192309945971 ps
T1042 /workspace/coverage/default/30.uart_noise_filter.847360092 Mar 19 03:10:44 PM PDT 24 Mar 19 03:10:55 PM PDT 24 12786880528 ps
T1043 /workspace/coverage/default/13.uart_fifo_overflow.1241143898 Mar 19 03:09:55 PM PDT 24 Mar 19 03:11:07 PM PDT 24 174009648502 ps
T1044 /workspace/coverage/default/23.uart_smoke.955994395 Mar 19 03:10:12 PM PDT 24 Mar 19 03:10:13 PM PDT 24 558011863 ps
T1045 /workspace/coverage/default/27.uart_alert_test.2510552365 Mar 19 03:10:34 PM PDT 24 Mar 19 03:10:35 PM PDT 24 13113591 ps
T1046 /workspace/coverage/default/39.uart_fifo_reset.2273908097 Mar 19 03:11:29 PM PDT 24 Mar 19 03:12:47 PM PDT 24 136399388061 ps
T1047 /workspace/coverage/default/234.uart_fifo_reset.4095750390 Mar 19 03:13:07 PM PDT 24 Mar 19 03:15:21 PM PDT 24 102560356523 ps
T1048 /workspace/coverage/default/46.uart_fifo_full.3663334356 Mar 19 03:11:54 PM PDT 24 Mar 19 03:12:10 PM PDT 24 17000397542 ps
T1049 /workspace/coverage/default/23.uart_rx_start_bit_filter.2226425535 Mar 19 03:10:23 PM PDT 24 Mar 19 03:10:26 PM PDT 24 3806425626 ps
T1050 /workspace/coverage/default/23.uart_fifo_overflow.3218848491 Mar 19 03:10:12 PM PDT 24 Mar 19 03:10:49 PM PDT 24 16823608915 ps
T1051 /workspace/coverage/default/24.uart_perf.4137183165 Mar 19 03:10:24 PM PDT 24 Mar 19 03:32:14 PM PDT 24 25043380145 ps
T1052 /workspace/coverage/default/42.uart_tx_rx.3369290600 Mar 19 03:11:43 PM PDT 24 Mar 19 03:12:06 PM PDT 24 34746186994 ps
T1053 /workspace/coverage/default/32.uart_noise_filter.1851092285 Mar 19 03:10:57 PM PDT 24 Mar 19 03:12:42 PM PDT 24 178256783869 ps
T1054 /workspace/coverage/default/39.uart_loopback.2753301074 Mar 19 03:11:30 PM PDT 24 Mar 19 03:11:34 PM PDT 24 736123090 ps
T1055 /workspace/coverage/default/130.uart_fifo_reset.940054020 Mar 19 03:12:43 PM PDT 24 Mar 19 03:16:26 PM PDT 24 161633467746 ps
T1056 /workspace/coverage/default/82.uart_fifo_reset.915561378 Mar 19 03:12:26 PM PDT 24 Mar 19 03:12:42 PM PDT 24 112308453949 ps
T1057 /workspace/coverage/default/24.uart_tx_ovrd.3346491330 Mar 19 03:10:23 PM PDT 24 Mar 19 03:10:27 PM PDT 24 1203246505 ps
T1058 /workspace/coverage/default/3.uart_rx_start_bit_filter.2388746932 Mar 19 03:09:29 PM PDT 24 Mar 19 03:09:33 PM PDT 24 1925308731 ps
T1059 /workspace/coverage/default/35.uart_perf.578360080 Mar 19 03:11:16 PM PDT 24 Mar 19 03:13:44 PM PDT 24 14129950668 ps
T1060 /workspace/coverage/default/16.uart_tx_rx.2080426426 Mar 19 03:10:08 PM PDT 24 Mar 19 03:12:00 PM PDT 24 157886700046 ps
T239 /workspace/coverage/default/68.uart_fifo_reset.2890357896 Mar 19 03:12:15 PM PDT 24 Mar 19 03:16:29 PM PDT 24 139390001348 ps
T1061 /workspace/coverage/default/23.uart_loopback.420647754 Mar 19 03:10:29 PM PDT 24 Mar 19 03:10:41 PM PDT 24 6938722276 ps
T1062 /workspace/coverage/default/260.uart_fifo_reset.2026516509 Mar 19 03:13:33 PM PDT 24 Mar 19 03:13:58 PM PDT 24 10948528148 ps
T1063 /workspace/coverage/default/46.uart_long_xfer_wo_dly.1520449125 Mar 19 03:11:51 PM PDT 24 Mar 19 03:19:25 PM PDT 24 81785399965 ps
T1064 /workspace/coverage/default/46.uart_rx_oversample.2493110396 Mar 19 03:11:56 PM PDT 24 Mar 19 03:12:46 PM PDT 24 6086565661 ps
T1065 /workspace/coverage/default/47.uart_noise_filter.441277294 Mar 19 03:11:50 PM PDT 24 Mar 19 03:12:53 PM PDT 24 33150000639 ps
T1066 /workspace/coverage/default/10.uart_rx_oversample.738753022 Mar 19 03:09:51 PM PDT 24 Mar 19 03:09:56 PM PDT 24 6539287368 ps
T1067 /workspace/coverage/default/44.uart_loopback.734684489 Mar 19 03:11:40 PM PDT 24 Mar 19 03:11:50 PM PDT 24 7911095236 ps
T1068 /workspace/coverage/default/15.uart_long_xfer_wo_dly.2757050472 Mar 19 03:10:02 PM PDT 24 Mar 19 03:25:19 PM PDT 24 95019214791 ps
T1069 /workspace/coverage/default/19.uart_fifo_reset.382043953 Mar 19 03:10:03 PM PDT 24 Mar 19 03:10:23 PM PDT 24 178890525554 ps
T1070 /workspace/coverage/default/20.uart_fifo_overflow.154440404 Mar 19 03:10:21 PM PDT 24 Mar 19 03:14:49 PM PDT 24 168754851431 ps
T1071 /workspace/coverage/default/24.uart_long_xfer_wo_dly.641374391 Mar 19 03:10:22 PM PDT 24 Mar 19 03:22:58 PM PDT 24 123000773525 ps
T1072 /workspace/coverage/default/3.uart_long_xfer_wo_dly.792063245 Mar 19 03:09:28 PM PDT 24 Mar 19 03:15:02 PM PDT 24 232653065433 ps
T1073 /workspace/coverage/default/5.uart_rx_oversample.369619804 Mar 19 03:09:25 PM PDT 24 Mar 19 03:09:31 PM PDT 24 1682788788 ps
T1074 /workspace/coverage/default/83.uart_fifo_reset.4054098976 Mar 19 03:12:27 PM PDT 24 Mar 19 03:13:13 PM PDT 24 185337988007 ps
T1075 /workspace/coverage/default/23.uart_fifo_reset.4242744844 Mar 19 03:10:16 PM PDT 24 Mar 19 03:10:57 PM PDT 24 437105861701 ps
T1076 /workspace/coverage/default/153.uart_fifo_reset.2424849851 Mar 19 03:12:48 PM PDT 24 Mar 19 03:13:42 PM PDT 24 73133051216 ps
T1077 /workspace/coverage/default/6.uart_noise_filter.1156304893 Mar 19 03:09:29 PM PDT 24 Mar 19 03:10:08 PM PDT 24 24575865850 ps
T1078 /workspace/coverage/default/49.uart_stress_all.582940326 Mar 19 03:12:07 PM PDT 24 Mar 19 03:14:57 PM PDT 24 311206310642 ps
T214 /workspace/coverage/default/74.uart_fifo_reset.2856474068 Mar 19 03:12:15 PM PDT 24 Mar 19 03:12:33 PM PDT 24 24653324765 ps
T1079 /workspace/coverage/default/47.uart_fifo_overflow.177636778 Mar 19 03:11:54 PM PDT 24 Mar 19 03:14:27 PM PDT 24 228478145546 ps
T1080 /workspace/coverage/default/3.uart_stress_all.1527775752 Mar 19 03:09:25 PM PDT 24 Mar 19 03:12:58 PM PDT 24 76828766701 ps
T1081 /workspace/coverage/default/28.uart_long_xfer_wo_dly.3949111095 Mar 19 03:10:46 PM PDT 24 Mar 19 03:16:21 PM PDT 24 69728936272 ps
T1082 /workspace/coverage/default/1.uart_long_xfer_wo_dly.904458485 Mar 19 03:09:20 PM PDT 24 Mar 19 03:22:50 PM PDT 24 116023575995 ps
T1083 /workspace/coverage/default/21.uart_intr.1900921564 Mar 19 03:10:17 PM PDT 24 Mar 19 03:10:41 PM PDT 24 42249431437 ps
T1084 /workspace/coverage/default/28.uart_tx_ovrd.4249144761 Mar 19 03:10:45 PM PDT 24 Mar 19 03:10:48 PM PDT 24 1253340070 ps
T1085 /workspace/coverage/default/36.uart_tx_rx.762485770 Mar 19 03:11:16 PM PDT 24 Mar 19 03:11:45 PM PDT 24 26854771541 ps
T1086 /workspace/coverage/default/46.uart_loopback.422186218 Mar 19 03:11:53 PM PDT 24 Mar 19 03:11:59 PM PDT 24 5050143236 ps
T1087 /workspace/coverage/default/35.uart_smoke.3499350571 Mar 19 03:10:57 PM PDT 24 Mar 19 03:11:16 PM PDT 24 5887110786 ps
T1088 /workspace/coverage/default/5.uart_rx_parity_err.3561112838 Mar 19 03:09:27 PM PDT 24 Mar 19 03:10:41 PM PDT 24 52695741521 ps
T240 /workspace/coverage/default/251.uart_fifo_reset.1310702202 Mar 19 03:13:20 PM PDT 24 Mar 19 03:13:44 PM PDT 24 12549071812 ps
T1089 /workspace/coverage/default/26.uart_rx_parity_err.1998601510 Mar 19 03:10:34 PM PDT 24 Mar 19 03:11:13 PM PDT 24 43864566812 ps
T1090 /workspace/coverage/default/40.uart_stress_all.63164183 Mar 19 03:11:34 PM PDT 24 Mar 19 03:12:05 PM PDT 24 145121893420 ps
T1091 /workspace/coverage/default/39.uart_perf.773725616 Mar 19 03:11:29 PM PDT 24 Mar 19 03:18:47 PM PDT 24 8856912986 ps
T1092 /workspace/coverage/default/49.uart_rx_oversample.2821808319 Mar 19 03:12:08 PM PDT 24 Mar 19 03:12:11 PM PDT 24 1589686570 ps
T1093 /workspace/coverage/default/31.uart_tx_rx.3601119079 Mar 19 03:10:46 PM PDT 24 Mar 19 03:11:22 PM PDT 24 29319866069 ps
T1094 /workspace/coverage/default/4.uart_long_xfer_wo_dly.242997027 Mar 19 03:09:35 PM PDT 24 Mar 19 03:18:18 PM PDT 24 62796346117 ps
T1095 /workspace/coverage/default/27.uart_loopback.3080783802 Mar 19 03:10:35 PM PDT 24 Mar 19 03:10:54 PM PDT 24 10563774229 ps
T1096 /workspace/coverage/default/26.uart_rx_start_bit_filter.962010217 Mar 19 03:10:34 PM PDT 24 Mar 19 03:10:36 PM PDT 24 5224861322 ps
T1097 /workspace/coverage/default/27.uart_smoke.871701821 Mar 19 03:10:36 PM PDT 24 Mar 19 03:10:39 PM PDT 24 722195808 ps
T1098 /workspace/coverage/default/0.uart_long_xfer_wo_dly.656087890 Mar 19 03:09:18 PM PDT 24 Mar 19 03:12:01 PM PDT 24 40853132144 ps
T1099 /workspace/coverage/default/0.uart_fifo_reset.3855247071 Mar 19 03:09:11 PM PDT 24 Mar 19 03:09:19 PM PDT 24 52433163242 ps
T1100 /workspace/coverage/default/57.uart_fifo_reset.2676433151 Mar 19 03:12:10 PM PDT 24 Mar 19 03:12:58 PM PDT 24 57531874320 ps
T1101 /workspace/coverage/default/9.uart_tx_ovrd.2975102266 Mar 19 03:09:51 PM PDT 24 Mar 19 03:10:09 PM PDT 24 6535368920 ps
T1102 /workspace/coverage/default/13.uart_rx_parity_err.3050833145 Mar 19 03:09:48 PM PDT 24 Mar 19 03:10:06 PM PDT 24 29124622398 ps
T1103 /workspace/coverage/default/3.uart_fifo_overflow.1194679329 Mar 19 03:09:29 PM PDT 24 Mar 19 03:09:51 PM PDT 24 47506027782 ps
T1104 /workspace/coverage/default/36.uart_rx_oversample.1439661272 Mar 19 03:11:15 PM PDT 24 Mar 19 03:11:18 PM PDT 24 1271803949 ps
T1105 /workspace/coverage/default/44.uart_alert_test.216120789 Mar 19 03:11:42 PM PDT 24 Mar 19 03:11:43 PM PDT 24 11568622 ps
T1106 /workspace/coverage/default/35.uart_tx_ovrd.1657907356 Mar 19 03:11:15 PM PDT 24 Mar 19 03:11:19 PM PDT 24 857379378 ps
T1107 /workspace/coverage/default/16.uart_smoke.520770890 Mar 19 03:10:08 PM PDT 24 Mar 19 03:10:09 PM PDT 24 250331660 ps
T1108 /workspace/coverage/default/15.uart_tx_rx.3067584101 Mar 19 03:09:51 PM PDT 24 Mar 19 03:11:40 PM PDT 24 113088537987 ps
T1109 /workspace/coverage/default/17.uart_rx_start_bit_filter.2643533709 Mar 19 03:10:04 PM PDT 24 Mar 19 03:10:06 PM PDT 24 3481200740 ps
T1110 /workspace/coverage/default/42.uart_stress_all_with_rand_reset.847181763 Mar 19 03:11:41 PM PDT 24 Mar 19 03:17:55 PM PDT 24 365052013356 ps
T1111 /workspace/coverage/default/199.uart_fifo_reset.2529460246 Mar 19 03:12:58 PM PDT 24 Mar 19 03:13:59 PM PDT 24 229240867712 ps
T1112 /workspace/coverage/default/26.uart_fifo_overflow.3416365387 Mar 19 03:10:22 PM PDT 24 Mar 19 03:10:26 PM PDT 24 8049236500 ps
T1113 /workspace/coverage/default/37.uart_tx_ovrd.1836353916 Mar 19 03:11:31 PM PDT 24 Mar 19 03:11:50 PM PDT 24 7158768931 ps
T1114 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1389435580 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:45 PM PDT 24 234537737 ps
T1115 /workspace/coverage/cover_reg_top/39.uart_intr_test.3467741508 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:59 PM PDT 24 25164947 ps
T115 /workspace/coverage/cover_reg_top/43.uart_intr_test.2457600959 Mar 19 02:47:01 PM PDT 24 Mar 19 02:47:02 PM PDT 24 15951453 ps
T79 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4064346640 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 166242334 ps
T70 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2764713882 Mar 19 02:46:48 PM PDT 24 Mar 19 02:46:49 PM PDT 24 15010946 ps
T1116 /workspace/coverage/cover_reg_top/14.uart_intr_test.396934505 Mar 19 02:46:49 PM PDT 24 Mar 19 02:46:49 PM PDT 24 23308796 ps
T62 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2654889322 Mar 19 02:46:35 PM PDT 24 Mar 19 02:46:37 PM PDT 24 14622328 ps
T71 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2870199270 Mar 19 02:46:59 PM PDT 24 Mar 19 02:47:00 PM PDT 24 34592831 ps
T72 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3970663898 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:43 PM PDT 24 36328955 ps
T101 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3517112006 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:45 PM PDT 24 138572192 ps
T68 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.818351780 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:46 PM PDT 24 335686079 ps
T1117 /workspace/coverage/cover_reg_top/27.uart_intr_test.3463824791 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:00 PM PDT 24 131826598 ps
T73 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2288463028 Mar 19 02:46:38 PM PDT 24 Mar 19 02:46:41 PM PDT 24 12698186 ps
T74 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3536127509 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 163979180 ps
T63 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3463427772 Mar 19 02:46:56 PM PDT 24 Mar 19 02:46:56 PM PDT 24 78263348 ps
T1118 /workspace/coverage/cover_reg_top/9.uart_intr_test.1276884131 Mar 19 02:46:47 PM PDT 24 Mar 19 02:46:48 PM PDT 24 31572516 ps
T1119 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1627832305 Mar 19 02:46:48 PM PDT 24 Mar 19 02:46:51 PM PDT 24 103617099 ps
T80 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1560001574 Mar 19 02:46:47 PM PDT 24 Mar 19 02:46:48 PM PDT 24 49552795 ps
T1120 /workspace/coverage/cover_reg_top/10.uart_intr_test.2400421311 Mar 19 02:46:46 PM PDT 24 Mar 19 02:46:48 PM PDT 24 14938630 ps
T1121 /workspace/coverage/cover_reg_top/0.uart_intr_test.1200748970 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:43 PM PDT 24 149100727 ps
T1122 /workspace/coverage/cover_reg_top/35.uart_intr_test.4196672156 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:58 PM PDT 24 15748134 ps
T1123 /workspace/coverage/cover_reg_top/4.uart_intr_test.54391635 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:43 PM PDT 24 13017188 ps
T1124 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4115818556 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:59 PM PDT 24 76774059 ps
T1125 /workspace/coverage/cover_reg_top/2.uart_intr_test.2469666630 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:43 PM PDT 24 14320083 ps
T1126 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1242032543 Mar 19 02:46:36 PM PDT 24 Mar 19 02:46:40 PM PDT 24 334701729 ps
T1127 /workspace/coverage/cover_reg_top/17.uart_intr_test.2295593634 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:58 PM PDT 24 16663076 ps
T75 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.801909222 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:57 PM PDT 24 58112529 ps
T1128 /workspace/coverage/cover_reg_top/19.uart_tl_errors.179813116 Mar 19 02:47:02 PM PDT 24 Mar 19 02:47:04 PM PDT 24 235071909 ps
T1129 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.261246826 Mar 19 02:46:38 PM PDT 24 Mar 19 02:46:41 PM PDT 24 101030199 ps
T1130 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3478540308 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:45 PM PDT 24 31408410 ps
T1131 /workspace/coverage/cover_reg_top/28.uart_intr_test.2024016416 Mar 19 02:46:55 PM PDT 24 Mar 19 02:46:56 PM PDT 24 146423331 ps
T1132 /workspace/coverage/cover_reg_top/7.uart_intr_test.1886184406 Mar 19 02:46:46 PM PDT 24 Mar 19 02:46:48 PM PDT 24 12251101 ps
T1133 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1882505220 Mar 19 02:46:38 PM PDT 24 Mar 19 02:46:42 PM PDT 24 13380922 ps
T1134 /workspace/coverage/cover_reg_top/37.uart_intr_test.2171175157 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 215660175 ps
T1135 /workspace/coverage/cover_reg_top/22.uart_intr_test.2187892666 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:58 PM PDT 24 28027546 ps
T1136 /workspace/coverage/cover_reg_top/31.uart_intr_test.3581075574 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:00 PM PDT 24 69341218 ps
T81 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.62319357 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 92770307 ps
T1137 /workspace/coverage/cover_reg_top/11.uart_intr_test.2650379911 Mar 19 02:46:49 PM PDT 24 Mar 19 02:46:50 PM PDT 24 44996427 ps
T1138 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1442756703 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:57 PM PDT 24 20921642 ps
T1139 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3160059157 Mar 19 02:46:55 PM PDT 24 Mar 19 02:46:56 PM PDT 24 150663758 ps
T102 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1849764417 Mar 19 02:46:38 PM PDT 24 Mar 19 02:46:43 PM PDT 24 222167049 ps
T76 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3907622340 Mar 19 02:46:49 PM PDT 24 Mar 19 02:46:50 PM PDT 24 22450485 ps
T123 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1529586462 Mar 19 02:46:38 PM PDT 24 Mar 19 02:46:41 PM PDT 24 57569363 ps
T1140 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2648652206 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 142168497 ps
T1141 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3697705713 Mar 19 02:46:46 PM PDT 24 Mar 19 02:46:48 PM PDT 24 14271170 ps
T1142 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1536975920 Mar 19 02:46:49 PM PDT 24 Mar 19 02:46:52 PM PDT 24 104509655 ps
T1143 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4026823233 Mar 19 02:46:58 PM PDT 24 Mar 19 02:47:00 PM PDT 24 23274012 ps
T77 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3460846405 Mar 19 02:46:49 PM PDT 24 Mar 19 02:46:50 PM PDT 24 62850156 ps
T84 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4185008169 Mar 19 02:46:59 PM PDT 24 Mar 19 02:47:00 PM PDT 24 74056190 ps
T1144 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.803150893 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 50112447 ps
T78 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3284246210 Mar 19 02:46:55 PM PDT 24 Mar 19 02:46:56 PM PDT 24 12545774 ps
T1145 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.566968966 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:43 PM PDT 24 41442212 ps
T82 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1809471785 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:59 PM PDT 24 72556039 ps
T64 /workspace/coverage/cover_reg_top/4.uart_csr_rw.656152513 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:43 PM PDT 24 35523964 ps
T1146 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1347244819 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 108907885 ps
T1147 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2359699267 Mar 19 02:46:55 PM PDT 24 Mar 19 02:46:56 PM PDT 24 52696125 ps
T1148 /workspace/coverage/cover_reg_top/24.uart_intr_test.4169119594 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:58 PM PDT 24 22839333 ps
T1149 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1183723802 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:02 PM PDT 24 30291276 ps
T1150 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3098013740 Mar 19 02:46:47 PM PDT 24 Mar 19 02:46:48 PM PDT 24 54230385 ps
T1151 /workspace/coverage/cover_reg_top/23.uart_intr_test.2543207147 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:59 PM PDT 24 15051743 ps
T1152 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2922394352 Mar 19 02:47:02 PM PDT 24 Mar 19 02:47:04 PM PDT 24 248476888 ps
T1153 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.848835489 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:44 PM PDT 24 323939573 ps
T1154 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2999902794 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 64482573 ps
T1155 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.38155256 Mar 19 02:46:46 PM PDT 24 Mar 19 02:46:48 PM PDT 24 274062948 ps
T1156 /workspace/coverage/cover_reg_top/46.uart_intr_test.1232790296 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 11805040 ps
T1157 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2074769445 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:45 PM PDT 24 25583291 ps
T1158 /workspace/coverage/cover_reg_top/48.uart_intr_test.3878507466 Mar 19 02:47:01 PM PDT 24 Mar 19 02:47:01 PM PDT 24 14092322 ps
T1159 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1987851655 Mar 19 02:46:50 PM PDT 24 Mar 19 02:46:50 PM PDT 24 22817201 ps
T1160 /workspace/coverage/cover_reg_top/20.uart_intr_test.3003034446 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:58 PM PDT 24 20433528 ps
T1161 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3614113484 Mar 19 02:46:59 PM PDT 24 Mar 19 02:47:01 PM PDT 24 359298712 ps
T1162 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1502508984 Mar 19 02:46:48 PM PDT 24 Mar 19 02:46:49 PM PDT 24 123489393 ps
T1163 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4190541833 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 106026215 ps
T1164 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2055707208 Mar 19 02:46:59 PM PDT 24 Mar 19 02:47:00 PM PDT 24 28076239 ps
T1165 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3293968300 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 49560029 ps
T1166 /workspace/coverage/cover_reg_top/45.uart_intr_test.1918366793 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 83889214 ps
T1167 /workspace/coverage/cover_reg_top/15.uart_intr_test.2636642452 Mar 19 02:47:02 PM PDT 24 Mar 19 02:47:03 PM PDT 24 32548613 ps
T1168 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2167293050 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 19838278 ps
T1169 /workspace/coverage/cover_reg_top/0.uart_csr_rw.869838707 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 133001202 ps
T1170 /workspace/coverage/cover_reg_top/14.uart_csr_rw.481449971 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:58 PM PDT 24 19538491 ps
T1171 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1172346852 Mar 19 02:46:59 PM PDT 24 Mar 19 02:46:59 PM PDT 24 27186752 ps
T1172 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1544127017 Mar 19 02:46:48 PM PDT 24 Mar 19 02:46:49 PM PDT 24 46647654 ps
T1173 /workspace/coverage/cover_reg_top/18.uart_csr_rw.97459702 Mar 19 02:46:56 PM PDT 24 Mar 19 02:46:57 PM PDT 24 114453349 ps
T1174 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4215078115 Mar 19 02:46:38 PM PDT 24 Mar 19 02:46:41 PM PDT 24 87143748 ps
T1175 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3179726530 Mar 19 02:47:03 PM PDT 24 Mar 19 02:47:05 PM PDT 24 317184802 ps
T1176 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4040288963 Mar 19 02:46:45 PM PDT 24 Mar 19 02:46:47 PM PDT 24 38194704 ps
T1177 /workspace/coverage/cover_reg_top/36.uart_intr_test.855752477 Mar 19 02:47:02 PM PDT 24 Mar 19 02:47:03 PM PDT 24 12346982 ps
T83 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2282589806 Mar 19 02:46:47 PM PDT 24 Mar 19 02:46:48 PM PDT 24 91273810 ps
T124 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2209893694 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 277321921 ps
T1178 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.189557942 Mar 19 02:46:47 PM PDT 24 Mar 19 02:46:48 PM PDT 24 130280469 ps
T1179 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2915659313 Mar 19 02:46:46 PM PDT 24 Mar 19 02:46:48 PM PDT 24 32320353 ps
T1180 /workspace/coverage/cover_reg_top/16.uart_intr_test.195533312 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:59 PM PDT 24 22670734 ps
T1181 /workspace/coverage/cover_reg_top/3.uart_intr_test.1352477877 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 65361967 ps
T1182 /workspace/coverage/cover_reg_top/49.uart_intr_test.3080830815 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 39811345 ps
T1183 /workspace/coverage/cover_reg_top/38.uart_intr_test.1380533314 Mar 19 02:47:02 PM PDT 24 Mar 19 02:47:03 PM PDT 24 33287101 ps
T1184 /workspace/coverage/cover_reg_top/8.uart_intr_test.3587069921 Mar 19 02:46:48 PM PDT 24 Mar 19 02:46:49 PM PDT 24 20856431 ps
T1185 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2386255037 Mar 19 02:46:47 PM PDT 24 Mar 19 02:46:50 PM PDT 24 580708321 ps
T1186 /workspace/coverage/cover_reg_top/12.uart_intr_test.4164061573 Mar 19 02:46:48 PM PDT 24 Mar 19 02:46:49 PM PDT 24 14216272 ps
T1187 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3406940072 Mar 19 02:46:45 PM PDT 24 Mar 19 02:46:48 PM PDT 24 43848104 ps
T1188 /workspace/coverage/cover_reg_top/5.uart_intr_test.2673419635 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 15973424 ps
T1189 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3538162692 Mar 19 02:46:38 PM PDT 24 Mar 19 02:46:41 PM PDT 24 17434764 ps
T1190 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3206788430 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 25123274 ps
T1191 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2818347065 Mar 19 02:46:50 PM PDT 24 Mar 19 02:46:50 PM PDT 24 14532073 ps
T1192 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1611928071 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:58 PM PDT 24 25338478 ps
T1193 /workspace/coverage/cover_reg_top/30.uart_intr_test.3401123940 Mar 19 02:47:01 PM PDT 24 Mar 19 02:47:01 PM PDT 24 42714400 ps
T1194 /workspace/coverage/cover_reg_top/44.uart_intr_test.2094874161 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 35345797 ps
T85 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3895319047 Mar 19 02:46:48 PM PDT 24 Mar 19 02:46:49 PM PDT 24 113581765 ps
T1195 /workspace/coverage/cover_reg_top/42.uart_intr_test.1711839133 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 50152271 ps
T1196 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3823821317 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:43 PM PDT 24 12868325 ps
T1197 /workspace/coverage/cover_reg_top/25.uart_intr_test.591183205 Mar 19 02:46:59 PM PDT 24 Mar 19 02:46:59 PM PDT 24 35648292 ps
T86 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3814675103 Mar 19 02:46:56 PM PDT 24 Mar 19 02:46:57 PM PDT 24 693445777 ps
T65 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3629326411 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 36023413 ps
T1198 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2970738604 Mar 19 02:46:38 PM PDT 24 Mar 19 02:46:41 PM PDT 24 39290931 ps
T1199 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2926992050 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 345218588 ps
T1200 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.86670899 Mar 19 02:47:02 PM PDT 24 Mar 19 02:47:03 PM PDT 24 127717966 ps
T66 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.596217969 Mar 19 02:46:42 PM PDT 24 Mar 19 02:46:44 PM PDT 24 111710223 ps
T1201 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4276190568 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 257022309 ps
T1202 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1470602024 Mar 19 02:46:55 PM PDT 24 Mar 19 02:46:55 PM PDT 24 64178448 ps
T1203 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1605198003 Mar 19 02:46:50 PM PDT 24 Mar 19 02:46:51 PM PDT 24 14334050 ps
T1204 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2359806644 Mar 19 02:46:49 PM PDT 24 Mar 19 02:46:50 PM PDT 24 130023075 ps
T1205 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1487426819 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:43 PM PDT 24 248874513 ps
T1206 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2076151184 Mar 19 02:46:47 PM PDT 24 Mar 19 02:46:48 PM PDT 24 54642042 ps
T1207 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2920275737 Mar 19 02:46:50 PM PDT 24 Mar 19 02:46:50 PM PDT 24 87546231 ps
T1208 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3573086559 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:43 PM PDT 24 18488379 ps
T1209 /workspace/coverage/cover_reg_top/41.uart_intr_test.1085726234 Mar 19 02:47:01 PM PDT 24 Mar 19 02:47:01 PM PDT 24 30675842 ps
T1210 /workspace/coverage/cover_reg_top/34.uart_intr_test.723783814 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:59 PM PDT 24 11456659 ps
T1211 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.4135201270 Mar 19 02:46:56 PM PDT 24 Mar 19 02:46:56 PM PDT 24 28734594 ps
T1212 /workspace/coverage/cover_reg_top/32.uart_intr_test.52748171 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:58 PM PDT 24 142472697 ps
T1213 /workspace/coverage/cover_reg_top/13.uart_intr_test.948007111 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 40074337 ps
T1214 /workspace/coverage/cover_reg_top/29.uart_intr_test.3290187060 Mar 19 02:46:56 PM PDT 24 Mar 19 02:46:57 PM PDT 24 42957024 ps
T1215 /workspace/coverage/cover_reg_top/19.uart_intr_test.4077104044 Mar 19 02:46:59 PM PDT 24 Mar 19 02:46:59 PM PDT 24 43596479 ps
T1216 /workspace/coverage/cover_reg_top/26.uart_intr_test.1757336464 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:59 PM PDT 24 14652584 ps
T1217 /workspace/coverage/cover_reg_top/40.uart_intr_test.3674682537 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 14921002 ps
T1218 /workspace/coverage/cover_reg_top/15.uart_csr_rw.4175055909 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:00 PM PDT 24 17242949 ps
T1219 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2581510854 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 87963954 ps
T1220 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2469283003 Mar 19 02:46:48 PM PDT 24 Mar 19 02:46:49 PM PDT 24 16385930 ps
T1221 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3167207814 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:44 PM PDT 24 19457251 ps
T1222 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1733620244 Mar 19 02:46:55 PM PDT 24 Mar 19 02:46:56 PM PDT 24 47138372 ps
T1223 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1416043142 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 43950959 ps
T1224 /workspace/coverage/cover_reg_top/0.uart_tl_errors.552670490 Mar 19 02:46:42 PM PDT 24 Mar 19 02:46:46 PM PDT 24 111898840 ps
T1225 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4154711568 Mar 19 02:46:50 PM PDT 24 Mar 19 02:46:51 PM PDT 24 32314381 ps
T1226 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4039665547 Mar 19 02:47:01 PM PDT 24 Mar 19 02:47:02 PM PDT 24 86730574 ps
T1227 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1753006377 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:58 PM PDT 24 18405611 ps
T1228 /workspace/coverage/cover_reg_top/6.uart_intr_test.3504378738 Mar 19 02:46:39 PM PDT 24 Mar 19 02:46:42 PM PDT 24 17624674 ps
T1229 /workspace/coverage/cover_reg_top/47.uart_intr_test.3382166600 Mar 19 02:46:56 PM PDT 24 Mar 19 02:46:56 PM PDT 24 73125507 ps
T1230 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1628955458 Mar 19 02:46:59 PM PDT 24 Mar 19 02:47:00 PM PDT 24 17953699 ps
T1231 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1355891897 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 84137737 ps
T1232 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2232003057 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 69091652 ps
T1233 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1213327079 Mar 19 02:47:03 PM PDT 24 Mar 19 02:47:03 PM PDT 24 23081615 ps
T1234 /workspace/coverage/cover_reg_top/1.uart_intr_test.941187681 Mar 19 02:46:42 PM PDT 24 Mar 19 02:46:44 PM PDT 24 31215466 ps
T67 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1256954429 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:59 PM PDT 24 13671148 ps
T1235 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1725099327 Mar 19 02:46:59 PM PDT 24 Mar 19 02:47:00 PM PDT 24 80120342 ps
T1236 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1413101862 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:45 PM PDT 24 144552599 ps
T1237 /workspace/coverage/cover_reg_top/12.uart_tl_errors.306571887 Mar 19 02:46:56 PM PDT 24 Mar 19 02:46:57 PM PDT 24 237694960 ps
T69 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3950368548 Mar 19 02:58:13 PM PDT 24 Mar 19 02:58:16 PM PDT 24 318154266 ps
T1238 /workspace/coverage/cover_reg_top/33.uart_intr_test.788418046 Mar 19 02:46:58 PM PDT 24 Mar 19 02:46:58 PM PDT 24 14668009 ps
T1239 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1650371714 Mar 19 02:47:03 PM PDT 24 Mar 19 02:47:04 PM PDT 24 293768760 ps
T1240 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3668680355 Mar 19 02:46:42 PM PDT 24 Mar 19 02:46:45 PM PDT 24 93161253 ps
T1241 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.614751384 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:44 PM PDT 24 41330208 ps
T1242 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2446786643 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 180565051 ps
T1243 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2460818317 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 108783253 ps
T1244 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1854521508 Mar 19 02:46:41 PM PDT 24 Mar 19 02:46:45 PM PDT 24 36866522 ps
T1245 /workspace/coverage/cover_reg_top/2.uart_csr_rw.91718096 Mar 19 02:46:40 PM PDT 24 Mar 19 02:46:44 PM PDT 24 196757894 ps
T1246 /workspace/coverage/cover_reg_top/18.uart_intr_test.2403719102 Mar 19 02:46:56 PM PDT 24 Mar 19 02:46:56 PM PDT 24 33276306 ps
T1247 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3455984047 Mar 19 02:46:57 PM PDT 24 Mar 19 02:46:58 PM PDT 24 110248627 ps
T1248 /workspace/coverage/cover_reg_top/21.uart_intr_test.2397169726 Mar 19 02:47:03 PM PDT 24 Mar 19 02:47:04 PM PDT 24 41766896 ps

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.117000650
Short name T10
Test name
Test status
Simulation time 362156109099 ps
CPU time 273.45 seconds
Started Mar 19 03:10:02 PM PDT 24
Finished Mar 19 03:14:36 PM PDT 24
Peak memory 199968 kb
Host smart-a13c9aeb-6006-42bb-9e6f-e094896c47e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117000650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.117000650
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.4225633296
Short name T11
Test name
Test status
Simulation time 389921558712 ps
CPU time 1748.82 seconds
Started Mar 19 03:12:28 PM PDT 24
Finished Mar 19 03:41:37 PM PDT 24
Peak memory 229024 kb
Host smart-65ed1508-3e70-42f8-b1a1-0a1f0ce70824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225633296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.4225633296
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.539717224
Short name T122
Test name
Test status
Simulation time 463973250450 ps
CPU time 522.85 seconds
Started Mar 19 03:09:36 PM PDT 24
Finished Mar 19 03:18:19 PM PDT 24
Peak memory 215820 kb
Host smart-4210353f-2851-4a22-836e-944d934fceaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539717224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.539717224
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all.606132861
Short name T180
Test name
Test status
Simulation time 242021811127 ps
CPU time 183.98 seconds
Started Mar 19 03:11:51 PM PDT 24
Finished Mar 19 03:14:55 PM PDT 24
Peak memory 200156 kb
Host smart-6081641d-e313-4921-9606-4da695110389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606132861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.606132861
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all.3376411495
Short name T96
Test name
Test status
Simulation time 185246466948 ps
CPU time 126.4 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:12:21 PM PDT 24
Peak memory 200104 kb
Host smart-1aaf2b8a-970f-404c-99f7-6a897d79617b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376411495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3376411495
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3225570787
Short name T25
Test name
Test status
Simulation time 84414538311 ps
CPU time 1153.59 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:29:06 PM PDT 24
Peak memory 216712 kb
Host smart-f4a254a6-4511-49b6-b55c-8dd9d3a3d164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225570787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3225570787
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.2419562819
Short name T152
Test name
Test status
Simulation time 136457240816 ps
CPU time 424.49 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:18:36 PM PDT 24
Peak memory 200200 kb
Host smart-17b034df-29f2-4079-b633-7a9d2f02bb78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419562819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2419562819
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_sec_cm.793879815
Short name T31
Test name
Test status
Simulation time 218169673 ps
CPU time 0.89 seconds
Started Mar 19 03:09:28 PM PDT 24
Finished Mar 19 03:09:30 PM PDT 24
Peak memory 218572 kb
Host smart-c4664293-cf68-497f-bedf-340a7d23ec71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793879815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.793879815
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/21.uart_perf.765311247
Short name T43
Test name
Test status
Simulation time 20273514852 ps
CPU time 612.68 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:20:26 PM PDT 24
Peak memory 200260 kb
Host smart-51c825f5-efeb-450e-87a0-27db839a001c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765311247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.765311247
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2483207571
Short name T16
Test name
Test status
Simulation time 130064377445 ps
CPU time 65.58 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:12:03 PM PDT 24
Peak memory 200232 kb
Host smart-0d552925-8381-4c53-a411-4d72a19aefff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483207571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2483207571
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1445838319
Short name T116
Test name
Test status
Simulation time 196167565189 ps
CPU time 122.84 seconds
Started Mar 19 03:12:49 PM PDT 24
Finished Mar 19 03:14:52 PM PDT 24
Peak memory 200192 kb
Host smart-e1481128-a7e9-4992-a939-03b5d3239567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445838319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1445838319
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.1386318249
Short name T297
Test name
Test status
Simulation time 375823475390 ps
CPU time 422.63 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:18:17 PM PDT 24
Peak memory 200148 kb
Host smart-091522be-0e9c-469d-844d-376a89aecddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386318249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1386318249
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.800171909
Short name T260
Test name
Test status
Simulation time 196013599659 ps
CPU time 78.4 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 200180 kb
Host smart-9735a472-6b87-4d49-a2ca-217e15720051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800171909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.800171909
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.2099612929
Short name T27
Test name
Test status
Simulation time 125494041504 ps
CPU time 159.33 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:12:31 PM PDT 24
Peak memory 216704 kb
Host smart-46d19082-bd82-495b-a5e2-aa7ace115648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099612929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2099612929
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2654889322
Short name T62
Test name
Test status
Simulation time 14622328 ps
CPU time 0.58 seconds
Started Mar 19 02:46:35 PM PDT 24
Finished Mar 19 02:46:37 PM PDT 24
Peak memory 195812 kb
Host smart-c92dd5ff-33c3-427f-ad0c-c0f041b5fa68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654889322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2654889322
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2740984034
Short name T12
Test name
Test status
Simulation time 52643060982 ps
CPU time 14.82 seconds
Started Mar 19 03:13:46 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 200116 kb
Host smart-7e5bd882-57f2-41bb-867a-dc92fdd15419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740984034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2740984034
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1809471785
Short name T82
Test name
Test status
Simulation time 72556039 ps
CPU time 1.32 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 199744 kb
Host smart-53abad28-61f2-48d5-b279-4060ddab9ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809471785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1809471785
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1583900966
Short name T20
Test name
Test status
Simulation time 184605825990 ps
CPU time 362.15 seconds
Started Mar 19 03:11:56 PM PDT 24
Finished Mar 19 03:17:58 PM PDT 24
Peak memory 200140 kb
Host smart-f1d8f1b8-715f-4dcf-82cb-1bb27cd29da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583900966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1583900966
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.756503817
Short name T15
Test name
Test status
Simulation time 489403247673 ps
CPU time 95.24 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:11:27 PM PDT 24
Peak memory 200100 kb
Host smart-72566e26-e902-46c0-840d-ef3550d4292f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756503817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.756503817
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3107842516
Short name T178
Test name
Test status
Simulation time 228001915897 ps
CPU time 44.98 seconds
Started Mar 19 03:12:54 PM PDT 24
Finished Mar 19 03:13:39 PM PDT 24
Peak memory 200172 kb
Host smart-5fbc91d8-6069-4a31-9395-27a6cd82c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107842516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3107842516
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2740972915
Short name T28
Test name
Test status
Simulation time 41782063 ps
CPU time 0.57 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:09:53 PM PDT 24
Peak memory 195680 kb
Host smart-d2593438-9d95-44bb-86f0-4d80f10dac01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740972915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2740972915
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1505825370
Short name T38
Test name
Test status
Simulation time 80336301878 ps
CPU time 443.84 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:19:39 PM PDT 24
Peak memory 216660 kb
Host smart-ce8bccd1-0fcd-46d7-9f5f-31b3224791c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505825370 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1505825370
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1501477562
Short name T138
Test name
Test status
Simulation time 204109769710 ps
CPU time 56.46 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:13:44 PM PDT 24
Peak memory 200208 kb
Host smart-03a7251b-049f-4ff9-9f23-377eb8b31e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501477562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1501477562
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.2901491491
Short name T155
Test name
Test status
Simulation time 197954236448 ps
CPU time 686.45 seconds
Started Mar 19 03:10:20 PM PDT 24
Finished Mar 19 03:21:47 PM PDT 24
Peak memory 208528 kb
Host smart-0f33739f-d029-4069-9f48-ca6b77fdf6a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901491491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2901491491
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_fifo_full.691880768
Short name T132
Test name
Test status
Simulation time 35757414181 ps
CPU time 53.61 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:10:21 PM PDT 24
Peak memory 200120 kb
Host smart-3fde80a2-6963-4531-9f5d-63cf189027be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691880768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.691880768
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1304258869
Short name T6
Test name
Test status
Simulation time 390413487019 ps
CPU time 172.57 seconds
Started Mar 19 03:13:08 PM PDT 24
Finished Mar 19 03:16:01 PM PDT 24
Peak memory 200164 kb
Host smart-d5d189eb-411e-4e9c-9199-d5a4b9918105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304258869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1304258869
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2288463028
Short name T73
Test name
Test status
Simulation time 12698186 ps
CPU time 0.62 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:41 PM PDT 24
Peak memory 196004 kb
Host smart-9d21f1df-7900-4940-8ca0-87c2c0a5c482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288463028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2288463028
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.818351780
Short name T68
Test name
Test status
Simulation time 335686079 ps
CPU time 2.63 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:46 PM PDT 24
Peak memory 197564 kb
Host smart-622522a9-efcd-4d4a-be66-3fef242d3b0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818351780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.818351780
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/default/25.uart_stress_all.2315284493
Short name T477
Test name
Test status
Simulation time 671635241701 ps
CPU time 240.82 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:14:26 PM PDT 24
Peak memory 200212 kb
Host smart-5e928f23-1907-44b3-a2e9-cfa55dae50c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315284493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2315284493
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3115134126
Short name T220
Test name
Test status
Simulation time 180659881148 ps
CPU time 75.66 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:13:59 PM PDT 24
Peak memory 200240 kb
Host smart-01536e54-2c43-43ce-ac61-dd182e9329a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115134126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3115134126
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1550097240
Short name T145
Test name
Test status
Simulation time 126903094513 ps
CPU time 47.78 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:10:40 PM PDT 24
Peak memory 200124 kb
Host smart-cdd1766f-3d2d-4298-a09c-95b4d7a1f35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550097240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1550097240
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3292263860
Short name T125
Test name
Test status
Simulation time 266471334375 ps
CPU time 1067.93 seconds
Started Mar 19 03:12:18 PM PDT 24
Finished Mar 19 03:30:07 PM PDT 24
Peak memory 224916 kb
Host smart-c2a6b402-72c1-457c-aff3-3f3a8991ccdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292263860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3292263860
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3848278623
Short name T457
Test name
Test status
Simulation time 15637386783 ps
CPU time 25.33 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:30 PM PDT 24
Peak memory 199808 kb
Host smart-195542f4-c11f-4335-ab9a-6111f71f22f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848278623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3848278623
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.4101177664
Short name T140
Test name
Test status
Simulation time 166720914952 ps
CPU time 76.12 seconds
Started Mar 19 03:13:10 PM PDT 24
Finished Mar 19 03:14:27 PM PDT 24
Peak memory 200172 kb
Host smart-b876788a-6508-44e4-bf03-d893549e7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101177664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4101177664
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.395511027
Short name T169
Test name
Test status
Simulation time 146360103132 ps
CPU time 51.24 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:13:33 PM PDT 24
Peak memory 200116 kb
Host smart-d10da406-e541-4fd2-ad37-e7d64a4456cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395511027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.395511027
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.520612181
Short name T189
Test name
Test status
Simulation time 80189684358 ps
CPU time 203.34 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:15:39 PM PDT 24
Peak memory 200176 kb
Host smart-155ad2d5-dda6-46a6-8af1-c3fc45816248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520612181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.520612181
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.62319357
Short name T81
Test name
Test status
Simulation time 92770307 ps
CPU time 1.45 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 199696 kb
Host smart-29082896-5dbd-4ace-98d1-193070ed84d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62319357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.62319357
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3236622168
Short name T428
Test name
Test status
Simulation time 69047253499 ps
CPU time 137.9 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:11:27 PM PDT 24
Peak memory 200192 kb
Host smart-1340734a-fb01-474a-9410-b95d6011e594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236622168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3236622168
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1446419540
Short name T279
Test name
Test status
Simulation time 201543411001 ps
CPU time 197.13 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:16:05 PM PDT 24
Peak memory 200204 kb
Host smart-908f380f-cefb-44d5-9d12-77c0685f911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446419540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1446419540
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_perf.2515829652
Short name T106
Test name
Test status
Simulation time 23404066562 ps
CPU time 622.39 seconds
Started Mar 19 03:10:37 PM PDT 24
Finished Mar 19 03:20:59 PM PDT 24
Peak memory 200072 kb
Host smart-ed9be961-c691-4168-b937-8b3afead83c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515829652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2515829652
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2899241789
Short name T229
Test name
Test status
Simulation time 130464982626 ps
CPU time 113.35 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:14:35 PM PDT 24
Peak memory 200128 kb
Host smart-c7b68aa8-641e-4453-a334-dcd15ec67749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899241789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2899241789
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3232259177
Short name T120
Test name
Test status
Simulation time 30857291745 ps
CPU time 66.69 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:13:50 PM PDT 24
Peak memory 200228 kb
Host smart-cb246811-7ed1-4144-a617-15a7e5c2926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232259177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3232259177
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1384216053
Short name T49
Test name
Test status
Simulation time 81011987168 ps
CPU time 86.78 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:10:40 PM PDT 24
Peak memory 199660 kb
Host smart-6ee86ba9-c5ca-4b4a-b3b6-1b58bce33060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384216053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1384216053
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_tx_rx.583657083
Short name T296
Test name
Test status
Simulation time 95802052580 ps
CPU time 159.08 seconds
Started Mar 19 03:09:46 PM PDT 24
Finished Mar 19 03:12:25 PM PDT 24
Peak memory 200180 kb
Host smart-eaaee108-1983-4cf5-aab4-7778c5d63822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583657083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.583657083
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2097069356
Short name T194
Test name
Test status
Simulation time 25469989697 ps
CPU time 47.61 seconds
Started Mar 19 03:12:39 PM PDT 24
Finished Mar 19 03:13:27 PM PDT 24
Peak memory 200224 kb
Host smart-9469703e-67b6-4784-b1d0-c3498a6627ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097069356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2097069356
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1062433250
Short name T201
Test name
Test status
Simulation time 55339708090 ps
CPU time 92.6 seconds
Started Mar 19 03:12:58 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 200124 kb
Host smart-c253c5ad-81ad-4f8d-a8c3-69a2fdbfd633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062433250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1062433250
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2273599905
Short name T216
Test name
Test status
Simulation time 228673019141 ps
CPU time 40.69 seconds
Started Mar 19 03:13:34 PM PDT 24
Finished Mar 19 03:14:15 PM PDT 24
Peak memory 200152 kb
Host smart-51514a9a-9383-4f58-b5ea-dacc777fec6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273599905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2273599905
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1586165972
Short name T211
Test name
Test status
Simulation time 101636845829 ps
CPU time 171.19 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:14:05 PM PDT 24
Peak memory 200200 kb
Host smart-d69f0cc1-5067-44e7-9443-e1bf767a2117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586165972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1586165972
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.2043746795
Short name T175
Test name
Test status
Simulation time 139483849377 ps
CPU time 263.46 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:13:54 PM PDT 24
Peak memory 200180 kb
Host smart-f3c22117-4774-4716-b873-a7241c23ba62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043746795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2043746795
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1424046443
Short name T95
Test name
Test status
Simulation time 91681020160 ps
CPU time 106.86 seconds
Started Mar 19 03:12:52 PM PDT 24
Finished Mar 19 03:14:39 PM PDT 24
Peak memory 200144 kb
Host smart-be2852f6-2a20-4d28-ac11-b9ce127dc1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424046443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1424046443
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2630180244
Short name T203
Test name
Test status
Simulation time 41175879260 ps
CPU time 208.46 seconds
Started Mar 19 03:12:52 PM PDT 24
Finished Mar 19 03:16:21 PM PDT 24
Peak memory 200236 kb
Host smart-2e2ff1a5-ab4f-4a3b-b94c-7dae6668ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630180244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2630180244
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1172906452
Short name T190
Test name
Test status
Simulation time 24043624036 ps
CPU time 18.38 seconds
Started Mar 19 03:12:52 PM PDT 24
Finished Mar 19 03:13:11 PM PDT 24
Peak memory 199992 kb
Host smart-845adae7-20d6-4622-b576-6655b0fd6b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172906452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1172906452
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3335716475
Short name T228
Test name
Test status
Simulation time 721001788869 ps
CPU time 1752.01 seconds
Started Mar 19 03:09:31 PM PDT 24
Finished Mar 19 03:38:43 PM PDT 24
Peak memory 226016 kb
Host smart-4bb92153-6d96-4217-87e5-c016459ddd0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335716475 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3335716475
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.671421885
Short name T142
Test name
Test status
Simulation time 91350526453 ps
CPU time 77.54 seconds
Started Mar 19 03:13:08 PM PDT 24
Finished Mar 19 03:14:26 PM PDT 24
Peak memory 200072 kb
Host smart-f3efc126-5b00-4755-b0bf-a7ec9a2f61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671421885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.671421885
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1659433521
Short name T47
Test name
Test status
Simulation time 55276626856 ps
CPU time 82.61 seconds
Started Mar 19 03:13:33 PM PDT 24
Finished Mar 19 03:14:56 PM PDT 24
Peak memory 200216 kb
Host smart-56e39f77-91ba-4429-9e95-b56f091591ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659433521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1659433521
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2418809862
Short name T437
Test name
Test status
Simulation time 9869348423 ps
CPU time 16.29 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:14:02 PM PDT 24
Peak memory 199772 kb
Host smart-57c29fe2-ef46-4ed1-b334-eb5a062365bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418809862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2418809862
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all.3239512793
Short name T232
Test name
Test status
Simulation time 75288163602 ps
CPU time 39.58 seconds
Started Mar 19 03:12:04 PM PDT 24
Finished Mar 19 03:12:44 PM PDT 24
Peak memory 200220 kb
Host smart-ad68a40d-b00e-4e1d-b29b-0dc0013e8d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239512793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3239512793
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.905016913
Short name T249
Test name
Test status
Simulation time 27744223685 ps
CPU time 307.6 seconds
Started Mar 19 03:12:16 PM PDT 24
Finished Mar 19 03:17:24 PM PDT 24
Peak memory 214360 kb
Host smart-51889122-bfdd-4540-a627-8153a8db85c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905016913 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.905016913
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1873965550
Short name T224
Test name
Test status
Simulation time 112287925869 ps
CPU time 190.91 seconds
Started Mar 19 03:12:25 PM PDT 24
Finished Mar 19 03:15:37 PM PDT 24
Peak memory 200116 kb
Host smart-00a9a153-797e-43c6-9316-8fd341abcbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873965550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1873965550
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.788451333
Short name T213
Test name
Test status
Simulation time 45156362701 ps
CPU time 18.96 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:13:02 PM PDT 24
Peak memory 200188 kb
Host smart-1f9f3140-be95-4fdd-9eb2-0fc618955afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788451333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.788451333
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.132263243
Short name T512
Test name
Test status
Simulation time 16301501180 ps
CPU time 36.06 seconds
Started Mar 19 03:09:52 PM PDT 24
Finished Mar 19 03:10:29 PM PDT 24
Peak memory 200168 kb
Host smart-4a5f47b5-7c52-48ef-afb9-91eb927ff233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132263243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.132263243
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.237390572
Short name T251
Test name
Test status
Simulation time 9530306124 ps
CPU time 58.53 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:11:05 PM PDT 24
Peak memory 208424 kb
Host smart-2c5cacc6-81d6-419a-b9a7-6ceae2611ff9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237390572 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.237390572
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.404237813
Short name T326
Test name
Test status
Simulation time 204054803070 ps
CPU time 82.71 seconds
Started Mar 19 03:12:48 PM PDT 24
Finished Mar 19 03:14:11 PM PDT 24
Peak memory 200204 kb
Host smart-3b6f9649-82b6-43c7-a045-72778a6fecc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404237813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.404237813
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.906233891
Short name T188
Test name
Test status
Simulation time 15567053525 ps
CPU time 23.32 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:13:11 PM PDT 24
Peak memory 200180 kb
Host smart-0444d017-8465-49f5-9881-090db4eb3117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906233891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.906233891
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1463619668
Short name T173
Test name
Test status
Simulation time 108518125840 ps
CPU time 57.71 seconds
Started Mar 19 03:12:49 PM PDT 24
Finished Mar 19 03:13:47 PM PDT 24
Peak memory 200076 kb
Host smart-5a82fa65-82f4-4a68-bee1-7bf8bce6a7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463619668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1463619668
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2901534750
Short name T205
Test name
Test status
Simulation time 115276225132 ps
CPU time 24.48 seconds
Started Mar 19 03:13:00 PM PDT 24
Finished Mar 19 03:13:25 PM PDT 24
Peak memory 200224 kb
Host smart-beff2111-e1b8-4d68-b98f-c50bf8185638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901534750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2901534750
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.737029745
Short name T144
Test name
Test status
Simulation time 72607157834 ps
CPU time 91.63 seconds
Started Mar 19 03:13:03 PM PDT 24
Finished Mar 19 03:14:35 PM PDT 24
Peak memory 200216 kb
Host smart-bf08d16e-93ee-41fd-bc31-c07894f30c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737029745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.737029745
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2418654702
Short name T241
Test name
Test status
Simulation time 96050390039 ps
CPU time 134 seconds
Started Mar 19 03:13:00 PM PDT 24
Finished Mar 19 03:15:14 PM PDT 24
Peak memory 200100 kb
Host smart-219442ce-4d55-4ce8-95fe-b7f491ea81b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418654702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2418654702
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3402239658
Short name T179
Test name
Test status
Simulation time 65823576842 ps
CPU time 98.68 seconds
Started Mar 19 03:13:03 PM PDT 24
Finished Mar 19 03:14:42 PM PDT 24
Peak memory 199944 kb
Host smart-0903a77c-2f8e-4368-9ea7-17ae5d1106e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402239658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3402239658
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1310702202
Short name T240
Test name
Test status
Simulation time 12549071812 ps
CPU time 23.63 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:13:44 PM PDT 24
Peak memory 200160 kb
Host smart-b51321fc-92df-4e03-930c-3cf336c4cdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310702202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1310702202
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1906613689
Short name T221
Test name
Test status
Simulation time 31983670931 ps
CPU time 28.82 seconds
Started Mar 19 03:13:47 PM PDT 24
Finished Mar 19 03:14:16 PM PDT 24
Peak memory 200160 kb
Host smart-152b5e91-c426-46cd-aa86-9a9b855f67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906613689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1906613689
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3676269874
Short name T243
Test name
Test status
Simulation time 43911901591 ps
CPU time 52.6 seconds
Started Mar 19 03:09:32 PM PDT 24
Finished Mar 19 03:10:25 PM PDT 24
Peak memory 200212 kb
Host smart-a2c554e1-9c9f-4627-8049-5edf76e32475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676269874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3676269874
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2890357896
Short name T239
Test name
Test status
Simulation time 139390001348 ps
CPU time 253.75 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:16:29 PM PDT 24
Peak memory 200188 kb
Host smart-36801b6a-a8ab-45c2-a84d-70d18db36d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890357896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2890357896
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3530303079
Short name T250
Test name
Test status
Simulation time 156354561732 ps
CPU time 174.28 seconds
Started Mar 19 03:12:26 PM PDT 24
Finished Mar 19 03:15:21 PM PDT 24
Peak memory 216672 kb
Host smart-a7ebbe9b-3ed5-461b-9f82-5020fd9cd2b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530303079 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3530303079
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1208065744
Short name T242
Test name
Test status
Simulation time 50325474133 ps
CPU time 22.09 seconds
Started Mar 19 03:12:26 PM PDT 24
Finished Mar 19 03:12:48 PM PDT 24
Peak memory 200192 kb
Host smart-a99a8c90-f782-4b8a-9c81-4e6c63e7ede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208065744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1208065744
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.261246826
Short name T1129
Test name
Test status
Simulation time 101030199 ps
CPU time 0.68 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:41 PM PDT 24
Peak memory 195244 kb
Host smart-3be00422-113b-4d83-aa5b-8f42639fece3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261246826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.261246826
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1854521508
Short name T1244
Test name
Test status
Simulation time 36866522 ps
CPU time 1.49 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 198544 kb
Host smart-95c10be3-0b9d-4c89-87c2-391ac6c038d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854521508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1854521508
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.803150893
Short name T1144
Test name
Test status
Simulation time 50112447 ps
CPU time 0.59 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 195796 kb
Host smart-c5abef05-6fa6-49c9-bae3-669fe0d4d7e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803150893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.803150893
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4215078115
Short name T1174
Test name
Test status
Simulation time 87143748 ps
CPU time 0.82 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:41 PM PDT 24
Peak memory 200244 kb
Host smart-86e2a743-4319-443c-be1a-338d4498807f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215078115 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.4215078115
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.869838707
Short name T1169
Test name
Test status
Simulation time 133001202 ps
CPU time 0.66 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 195852 kb
Host smart-5d8136dd-bf0b-4169-ad3c-289a904abc29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869838707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.869838707
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1200748970
Short name T1121
Test name
Test status
Simulation time 149100727 ps
CPU time 0.57 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 194796 kb
Host smart-61cab161-07dd-443f-b420-1199b17ef8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200748970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1200748970
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1355891897
Short name T1231
Test name
Test status
Simulation time 84137737 ps
CPU time 0.65 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 196140 kb
Host smart-f18934af-8f04-4a3e-911a-3fc4d9de6e73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355891897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1355891897
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.552670490
Short name T1224
Test name
Test status
Simulation time 111898840 ps
CPU time 2.1 seconds
Started Mar 19 02:46:42 PM PDT 24
Finished Mar 19 02:46:46 PM PDT 24
Peak memory 200524 kb
Host smart-f8fc0f0b-2184-4b22-83f1-0d4d4e830432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552670490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.552670490
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.848835489
Short name T1153
Test name
Test status
Simulation time 323939573 ps
CPU time 0.94 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 199204 kb
Host smart-6f1efaab-e466-4686-93e7-1eabcfa08f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848835489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.848835489
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2970738604
Short name T1198
Test name
Test status
Simulation time 39290931 ps
CPU time 0.7 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:41 PM PDT 24
Peak memory 195840 kb
Host smart-9e240957-90c3-48b6-9b4d-2c85bb40f62f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970738604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2970738604
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3517112006
Short name T101
Test name
Test status
Simulation time 138572192 ps
CPU time 1.71 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 198136 kb
Host smart-2b411a35-d764-40e7-9c2d-61d979c578de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517112006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3517112006
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3573086559
Short name T1208
Test name
Test status
Simulation time 18488379 ps
CPU time 0.64 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 195824 kb
Host smart-a7e6e6fb-7403-496a-be09-e41df8d33693
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573086559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3573086559
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1347244819
Short name T1146
Test name
Test status
Simulation time 108907885 ps
CPU time 0.88 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200108 kb
Host smart-1f9c677f-e3d4-4737-869c-54fada31ac79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347244819 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1347244819
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.941187681
Short name T1234
Test name
Test status
Simulation time 31215466 ps
CPU time 0.59 seconds
Started Mar 19 02:46:42 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 194816 kb
Host smart-6182c334-4a25-4929-b32a-d259f7724ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941187681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.941187681
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3536127509
Short name T74
Test name
Test status
Simulation time 163979180 ps
CPU time 0.73 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 197376 kb
Host smart-0ffd60e2-e52f-4783-a37a-774559f1326e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536127509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3536127509
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3478540308
Short name T1130
Test name
Test status
Simulation time 31408410 ps
CPU time 1.71 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 200500 kb
Host smart-65376d4b-2797-43fe-941b-bf2910de08d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478540308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3478540308
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1416043142
Short name T1223
Test name
Test status
Simulation time 43950959 ps
CPU time 0.97 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 199344 kb
Host smart-62af15c6-6457-45ef-8aae-19af9668ccd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416043142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1416043142
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2446786643
Short name T1242
Test name
Test status
Simulation time 180565051 ps
CPU time 1.33 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 200332 kb
Host smart-443fc9a6-2f58-40de-b189-cb5005b21136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446786643 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2446786643
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2764713882
Short name T70
Test name
Test status
Simulation time 15010946 ps
CPU time 0.57 seconds
Started Mar 19 02:46:48 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 195720 kb
Host smart-2e1c14b4-336f-4353-a5b4-7e66dbdc4cef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764713882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2764713882
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2400421311
Short name T1120
Test name
Test status
Simulation time 14938630 ps
CPU time 0.57 seconds
Started Mar 19 02:46:46 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 194792 kb
Host smart-b88609ba-c925-47d2-a673-1d1c838e6cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400421311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2400421311
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3460846405
Short name T77
Test name
Test status
Simulation time 62850156 ps
CPU time 0.66 seconds
Started Mar 19 02:46:49 PM PDT 24
Finished Mar 19 02:46:50 PM PDT 24
Peak memory 196976 kb
Host smart-90d41bd4-6d01-4a19-98bf-f45c009f83c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460846405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3460846405
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1627832305
Short name T1119
Test name
Test status
Simulation time 103617099 ps
CPU time 2.32 seconds
Started Mar 19 02:46:48 PM PDT 24
Finished Mar 19 02:46:51 PM PDT 24
Peak memory 200504 kb
Host smart-a23c8b52-76c3-40d2-ba64-a06ba030a55b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627832305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1627832305
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3614113484
Short name T1161
Test name
Test status
Simulation time 359298712 ps
CPU time 1.35 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 199796 kb
Host smart-de432140-e679-43ed-961b-4aa5760ed520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614113484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3614113484
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.38155256
Short name T1155
Test name
Test status
Simulation time 274062948 ps
CPU time 0.77 seconds
Started Mar 19 02:46:46 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 200260 kb
Host smart-25a7f0b3-cb4e-45c0-a970-bd41bc59ed11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38155256 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.38155256
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3160059157
Short name T1139
Test name
Test status
Simulation time 150663758 ps
CPU time 0.57 seconds
Started Mar 19 02:46:55 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 195812 kb
Host smart-e2433c49-166a-4430-bd5b-56a92f5424c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160059157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3160059157
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2650379911
Short name T1137
Test name
Test status
Simulation time 44996427 ps
CPU time 0.62 seconds
Started Mar 19 02:46:49 PM PDT 24
Finished Mar 19 02:46:50 PM PDT 24
Peak memory 194820 kb
Host smart-ce74b33a-b6ef-40eb-9942-6dd4892ec12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650379911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2650379911
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4154711568
Short name T1225
Test name
Test status
Simulation time 32314381 ps
CPU time 0.76 seconds
Started Mar 19 02:46:50 PM PDT 24
Finished Mar 19 02:46:51 PM PDT 24
Peak memory 197632 kb
Host smart-d80f425a-840e-436d-a677-a1679cce97d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154711568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.4154711568
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3406940072
Short name T1187
Test name
Test status
Simulation time 43848104 ps
CPU time 2.36 seconds
Started Mar 19 02:46:45 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 200516 kb
Host smart-fc3b35f3-42b0-4279-bd32-065c037ddde2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406940072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3406940072
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1733620244
Short name T1222
Test name
Test status
Simulation time 47138372 ps
CPU time 1.17 seconds
Started Mar 19 02:46:55 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 200528 kb
Host smart-85355613-19cc-447d-93cf-a2490eaabe73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733620244 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1733620244
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3907622340
Short name T76
Test name
Test status
Simulation time 22450485 ps
CPU time 0.6 seconds
Started Mar 19 02:46:49 PM PDT 24
Finished Mar 19 02:46:50 PM PDT 24
Peak memory 195812 kb
Host smart-3f4ad080-7599-4149-bf9d-efc58197a376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907622340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3907622340
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.4164061573
Short name T1186
Test name
Test status
Simulation time 14216272 ps
CPU time 0.56 seconds
Started Mar 19 02:46:48 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 194648 kb
Host smart-35a58336-20fa-45b8-b419-e2cf4236579c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164061573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4164061573
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1213327079
Short name T1233
Test name
Test status
Simulation time 23081615 ps
CPU time 0.69 seconds
Started Mar 19 02:47:03 PM PDT 24
Finished Mar 19 02:47:03 PM PDT 24
Peak memory 195432 kb
Host smart-ed9d8955-fee7-4439-a5a9-3e043ce8cd42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213327079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1213327079
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.306571887
Short name T1237
Test name
Test status
Simulation time 237694960 ps
CPU time 1.03 seconds
Started Mar 19 02:46:56 PM PDT 24
Finished Mar 19 02:46:57 PM PDT 24
Peak memory 200284 kb
Host smart-2196f49e-1467-41c9-b35d-a9f45f1ba25f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306571887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.306571887
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2282589806
Short name T83
Test name
Test status
Simulation time 91273810 ps
CPU time 1.34 seconds
Started Mar 19 02:46:47 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 199720 kb
Host smart-1babf0cd-9322-4cdd-9d2c-fffb2d4a47ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282589806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2282589806
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2055707208
Short name T1164
Test name
Test status
Simulation time 28076239 ps
CPU time 0.85 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 200080 kb
Host smart-12628aef-9abf-441d-8253-bb3d7f3a8f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055707208 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2055707208
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1470602024
Short name T1202
Test name
Test status
Simulation time 64178448 ps
CPU time 0.57 seconds
Started Mar 19 02:46:55 PM PDT 24
Finished Mar 19 02:46:55 PM PDT 24
Peak memory 195812 kb
Host smart-2891cc0a-ce71-4064-999a-04bf60f89966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470602024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1470602024
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.948007111
Short name T1213
Test name
Test status
Simulation time 40074337 ps
CPU time 0.58 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 194704 kb
Host smart-4dce8e39-9193-4758-8270-bbc6c01c3e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948007111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.948007111
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1987851655
Short name T1159
Test name
Test status
Simulation time 22817201 ps
CPU time 0.68 seconds
Started Mar 19 02:46:50 PM PDT 24
Finished Mar 19 02:46:50 PM PDT 24
Peak memory 195312 kb
Host smart-8beda320-afe3-47ab-a81e-aaeae9d963e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987851655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1987851655
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3179726530
Short name T1175
Test name
Test status
Simulation time 317184802 ps
CPU time 1.87 seconds
Started Mar 19 02:47:03 PM PDT 24
Finished Mar 19 02:47:05 PM PDT 24
Peak memory 200544 kb
Host smart-d5bd73c0-5c52-4715-bd56-cb49850c4286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179726530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3179726530
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1502508984
Short name T1162
Test name
Test status
Simulation time 123489393 ps
CPU time 0.95 seconds
Started Mar 19 02:46:48 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 199296 kb
Host smart-6caef895-cac4-4d0f-86ab-8a0c25fa44a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502508984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1502508984
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4026823233
Short name T1143
Test name
Test status
Simulation time 23274012 ps
CPU time 1.02 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 200292 kb
Host smart-a649080e-3282-46fa-964d-c7c511333c14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026823233 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4026823233
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.481449971
Short name T1170
Test name
Test status
Simulation time 19538491 ps
CPU time 0.6 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 195848 kb
Host smart-20f65b6d-bdf1-4cf5-a8e6-2c999572bde3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481449971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.481449971
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.396934505
Short name T1116
Test name
Test status
Simulation time 23308796 ps
CPU time 0.58 seconds
Started Mar 19 02:46:49 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 194784 kb
Host smart-ea99793e-df69-4af6-9004-5aa87fb796d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396934505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.396934505
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3455984047
Short name T1247
Test name
Test status
Simulation time 110248627 ps
CPU time 0.81 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 197168 kb
Host smart-b550af8a-f0b8-4218-82d7-951862570819
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455984047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3455984047
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1183723802
Short name T1149
Test name
Test status
Simulation time 30291276 ps
CPU time 1.53 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:02 PM PDT 24
Peak memory 200324 kb
Host smart-e8d72a2f-c4e1-4aac-8e6e-2307fbe25753
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183723802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1183723802
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3895319047
Short name T85
Test name
Test status
Simulation time 113581765 ps
CPU time 1.32 seconds
Started Mar 19 02:46:48 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 199764 kb
Host smart-64ba3ab4-a272-47f0-ab27-262bedc61f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895319047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3895319047
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4115818556
Short name T1124
Test name
Test status
Simulation time 76774059 ps
CPU time 1.16 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 200520 kb
Host smart-017658ca-eb43-4661-aadb-5cba3fe5cd65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115818556 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4115818556
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.4175055909
Short name T1218
Test name
Test status
Simulation time 17242949 ps
CPU time 0.67 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 195944 kb
Host smart-4df74312-7ae3-4ca7-bdde-6b1e81ac4a47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175055909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4175055909
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2636642452
Short name T1167
Test name
Test status
Simulation time 32548613 ps
CPU time 0.57 seconds
Started Mar 19 02:47:02 PM PDT 24
Finished Mar 19 02:47:03 PM PDT 24
Peak memory 194812 kb
Host smart-43a80c54-9f45-4575-84fc-fc0a4363c177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636642452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2636642452
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2359699267
Short name T1147
Test name
Test status
Simulation time 52696125 ps
CPU time 0.69 seconds
Started Mar 19 02:46:55 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 196800 kb
Host smart-1d1994d4-2983-4bab-a4de-34a937e47646
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359699267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2359699267
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2922394352
Short name T1152
Test name
Test status
Simulation time 248476888 ps
CPU time 2.41 seconds
Started Mar 19 02:47:02 PM PDT 24
Finished Mar 19 02:47:04 PM PDT 24
Peak memory 200504 kb
Host smart-a96b44f1-b436-4196-abfa-db6b92ce77f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922394352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2922394352
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4039665547
Short name T1226
Test name
Test status
Simulation time 86730574 ps
CPU time 0.97 seconds
Started Mar 19 02:47:01 PM PDT 24
Finished Mar 19 02:47:02 PM PDT 24
Peak memory 199380 kb
Host smart-30fc6499-d0b2-443a-b7f5-5505c56c2b40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039665547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.4039665547
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1753006377
Short name T1227
Test name
Test status
Simulation time 18405611 ps
CPU time 0.87 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 200312 kb
Host smart-73e47306-6458-4b9f-8816-3c255ce78dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753006377 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1753006377
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1256954429
Short name T67
Test name
Test status
Simulation time 13671148 ps
CPU time 0.63 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 195900 kb
Host smart-55070843-8006-41f3-afc2-608b1d5d0f0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256954429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1256954429
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.195533312
Short name T1180
Test name
Test status
Simulation time 22670734 ps
CPU time 0.57 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 194752 kb
Host smart-ac7d9766-9481-43ad-9782-7457dff1fc1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195533312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.195533312
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.4135201270
Short name T1211
Test name
Test status
Simulation time 28734594 ps
CPU time 0.76 seconds
Started Mar 19 02:46:56 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 197512 kb
Host smart-ad213f1d-1b3b-4c1d-9a15-3e06fe3a1c35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135201270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.4135201270
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1725099327
Short name T1235
Test name
Test status
Simulation time 80120342 ps
CPU time 1.34 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 200528 kb
Host smart-c0077408-ef48-487f-92a5-f1bdce965478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725099327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1725099327
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1650371714
Short name T1239
Test name
Test status
Simulation time 293768760 ps
CPU time 1.33 seconds
Started Mar 19 02:47:03 PM PDT 24
Finished Mar 19 02:47:04 PM PDT 24
Peak memory 199856 kb
Host smart-b381c2f8-59e9-479c-96d5-3ed887e48640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650371714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1650371714
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1611928071
Short name T1192
Test name
Test status
Simulation time 25338478 ps
CPU time 1.15 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 200556 kb
Host smart-a5793df6-9520-4908-a36b-679d68566f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611928071 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1611928071
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1628955458
Short name T1230
Test name
Test status
Simulation time 17953699 ps
CPU time 0.6 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 196152 kb
Host smart-ccb78fc3-a38b-43d5-be1a-49968b883670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628955458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1628955458
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2295593634
Short name T1127
Test name
Test status
Simulation time 16663076 ps
CPU time 0.59 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 194828 kb
Host smart-83ca9dbf-3bf5-4764-8a6c-c853d5457967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295593634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2295593634
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.86670899
Short name T1200
Test name
Test status
Simulation time 127717966 ps
CPU time 0.72 seconds
Started Mar 19 02:47:02 PM PDT 24
Finished Mar 19 02:47:03 PM PDT 24
Peak memory 196112 kb
Host smart-af3f8ab7-e4ae-458b-97b5-d1517cdbab44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86670899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_
outstanding.86670899
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2460818317
Short name T1243
Test name
Test status
Simulation time 108783253 ps
CPU time 1.38 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 200508 kb
Host smart-b4610194-ec91-49e8-b3c0-bf9d6078f51e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460818317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2460818317
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3814675103
Short name T86
Test name
Test status
Simulation time 693445777 ps
CPU time 1.28 seconds
Started Mar 19 02:46:56 PM PDT 24
Finished Mar 19 02:46:57 PM PDT 24
Peak memory 199696 kb
Host smart-91289ea6-28bc-4563-9eaf-b10fb7951114
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814675103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3814675103
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1442756703
Short name T1138
Test name
Test status
Simulation time 20921642 ps
CPU time 0.71 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:57 PM PDT 24
Peak memory 198784 kb
Host smart-5515f6a4-1db3-467d-8cd4-e98324df3cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442756703 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1442756703
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.97459702
Short name T1173
Test name
Test status
Simulation time 114453349 ps
CPU time 0.6 seconds
Started Mar 19 02:46:56 PM PDT 24
Finished Mar 19 02:46:57 PM PDT 24
Peak memory 195808 kb
Host smart-93ef3ca1-1b3c-4ac2-9a7a-16a0da2314ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97459702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.97459702
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2403719102
Short name T1246
Test name
Test status
Simulation time 33276306 ps
CPU time 0.58 seconds
Started Mar 19 02:46:56 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 194860 kb
Host smart-d0bface6-54b4-4bfe-8b0a-31813ee1b5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403719102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2403719102
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.801909222
Short name T75
Test name
Test status
Simulation time 58112529 ps
CPU time 0.74 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:57 PM PDT 24
Peak memory 197532 kb
Host smart-a8cb2585-e36a-46d7-ae8e-b42bd25f2e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801909222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.801909222
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2167293050
Short name T1168
Test name
Test status
Simulation time 19838278 ps
CPU time 1.01 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 199744 kb
Host smart-f5ea9fc2-e8ba-49f8-a4de-eb718a927365
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167293050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2167293050
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1172346852
Short name T1171
Test name
Test status
Simulation time 27186752 ps
CPU time 0.65 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 197556 kb
Host smart-96167513-84a1-49b0-97dd-94eb9c14e539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172346852 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1172346852
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3463427772
Short name T63
Test name
Test status
Simulation time 78263348 ps
CPU time 0.58 seconds
Started Mar 19 02:46:56 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 195768 kb
Host smart-ae4b4d80-2d30-4e4e-8b44-2c49612aca78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463427772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3463427772
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.4077104044
Short name T1215
Test name
Test status
Simulation time 43596479 ps
CPU time 0.57 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 194864 kb
Host smart-333ac33b-f848-45f6-bda0-547dcd1bbcbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077104044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4077104044
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2870199270
Short name T71
Test name
Test status
Simulation time 34592831 ps
CPU time 0.64 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 196092 kb
Host smart-e27dcaa1-6a5a-439b-9778-cfc7dbe8be9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870199270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2870199270
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.179813116
Short name T1128
Test name
Test status
Simulation time 235071909 ps
CPU time 2.18 seconds
Started Mar 19 02:47:02 PM PDT 24
Finished Mar 19 02:47:04 PM PDT 24
Peak memory 200524 kb
Host smart-6b9787d7-99d6-43ab-baa7-b158de76702d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179813116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.179813116
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4185008169
Short name T84
Test name
Test status
Simulation time 74056190 ps
CPU time 1.28 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 200068 kb
Host smart-5a9872e4-82b6-49a5-854f-6e9e4ab46448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185008169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4185008169
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2232003057
Short name T1232
Test name
Test status
Simulation time 69091652 ps
CPU time 0.7 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 195168 kb
Host smart-89c56f1f-8678-48ab-91d9-4e7916a4ddf5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232003057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2232003057
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1242032543
Short name T1126
Test name
Test status
Simulation time 334701729 ps
CPU time 2.46 seconds
Started Mar 19 02:46:36 PM PDT 24
Finished Mar 19 02:46:40 PM PDT 24
Peak memory 198132 kb
Host smart-eb3264bd-7f1b-4713-b31a-0d6ca2e72a39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242032543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1242032543
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3293968300
Short name T1165
Test name
Test status
Simulation time 49560029 ps
CPU time 0.88 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200308 kb
Host smart-b319670d-e35d-459e-8c89-6ca3afed672d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293968300 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3293968300
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.91718096
Short name T1245
Test name
Test status
Simulation time 196757894 ps
CPU time 0.6 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 195816 kb
Host smart-14c504ae-c071-40c2-a331-0a649a10edb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91718096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.91718096
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2469666630
Short name T1125
Test name
Test status
Simulation time 14320083 ps
CPU time 0.6 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 194784 kb
Host smart-d879400a-d7c5-4db6-8946-3e45f2cc29fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469666630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2469666630
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3823821317
Short name T1196
Test name
Test status
Simulation time 12868325 ps
CPU time 0.66 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 196020 kb
Host smart-a0cabaf1-79e7-4487-a131-c928f9312ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823821317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3823821317
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3206788430
Short name T1190
Test name
Test status
Simulation time 25123274 ps
CPU time 1.31 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200484 kb
Host smart-3664e6ce-4817-426b-ad63-e47b6d9e1780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206788430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3206788430
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2926992050
Short name T1199
Test name
Test status
Simulation time 345218588 ps
CPU time 1.34 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 199944 kb
Host smart-27081c54-aa7f-461d-8c79-ecf2b4d3ba48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926992050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2926992050
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3003034446
Short name T1160
Test name
Test status
Simulation time 20433528 ps
CPU time 0.56 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 194812 kb
Host smart-8b23fb9c-6052-4da3-b909-e6a7831f429e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003034446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3003034446
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2397169726
Short name T1248
Test name
Test status
Simulation time 41766896 ps
CPU time 0.56 seconds
Started Mar 19 02:47:03 PM PDT 24
Finished Mar 19 02:47:04 PM PDT 24
Peak memory 194792 kb
Host smart-9d5bf1ec-e50f-4184-a97b-b8f145f07b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397169726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2397169726
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2187892666
Short name T1135
Test name
Test status
Simulation time 28027546 ps
CPU time 0.56 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 194768 kb
Host smart-ed952a2b-101b-48e3-9a97-39f24c518c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187892666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2187892666
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2543207147
Short name T1151
Test name
Test status
Simulation time 15051743 ps
CPU time 0.61 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 194896 kb
Host smart-c62538ef-d78b-4048-b62e-9dc9acfd7962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543207147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2543207147
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4169119594
Short name T1148
Test name
Test status
Simulation time 22839333 ps
CPU time 0.57 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 194828 kb
Host smart-4d6aa4ac-9fcc-43f1-ab3c-481c03c18a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169119594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4169119594
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.591183205
Short name T1197
Test name
Test status
Simulation time 35648292 ps
CPU time 0.6 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 194856 kb
Host smart-70398189-e76f-4c38-bfda-d55b9df0d12b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591183205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.591183205
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1757336464
Short name T1216
Test name
Test status
Simulation time 14652584 ps
CPU time 0.56 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 194800 kb
Host smart-6957fbc0-4320-4fb0-bd04-a1863079aacf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757336464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1757336464
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3463824791
Short name T1117
Test name
Test status
Simulation time 131826598 ps
CPU time 0.56 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 194652 kb
Host smart-e53f7b1e-6d94-46bc-8924-b1563e003fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463824791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3463824791
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2024016416
Short name T1131
Test name
Test status
Simulation time 146423331 ps
CPU time 0.61 seconds
Started Mar 19 02:46:55 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 194768 kb
Host smart-4ca88777-9d3c-4a3b-80dc-77d1a0d60fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024016416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2024016416
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3290187060
Short name T1214
Test name
Test status
Simulation time 42957024 ps
CPU time 0.59 seconds
Started Mar 19 02:46:56 PM PDT 24
Finished Mar 19 02:46:57 PM PDT 24
Peak memory 194776 kb
Host smart-5bc7cfc5-c6ff-48e1-b911-bc750bb69f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290187060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3290187060
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.596217969
Short name T66
Test name
Test status
Simulation time 111710223 ps
CPU time 0.79 seconds
Started Mar 19 02:46:42 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 196772 kb
Host smart-f7ef5965-e207-4216-843d-3e348d5807eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596217969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.596217969
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1882505220
Short name T1133
Test name
Test status
Simulation time 13380922 ps
CPU time 0.6 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:42 PM PDT 24
Peak memory 195832 kb
Host smart-460e8b1e-47c9-456b-b97c-52f9431f12ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882505220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1882505220
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3167207814
Short name T1221
Test name
Test status
Simulation time 19457251 ps
CPU time 0.86 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200268 kb
Host smart-50f2fb8d-2e0f-403f-8cf1-def31b7eb39f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167207814 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3167207814
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3970663898
Short name T72
Test name
Test status
Simulation time 36328955 ps
CPU time 0.64 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 196056 kb
Host smart-81a77e78-213e-47f0-a4ad-08f3c2fc445a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970663898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3970663898
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1352477877
Short name T1181
Test name
Test status
Simulation time 65361967 ps
CPU time 0.58 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 194748 kb
Host smart-600dbef1-0c79-41d6-9036-54eed9b5b9a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352477877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1352477877
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2074769445
Short name T1157
Test name
Test status
Simulation time 25583291 ps
CPU time 0.83 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 197592 kb
Host smart-cead1a50-9a1e-4e87-95c2-442c0aed08b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074769445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2074769445
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1849764417
Short name T102
Test name
Test status
Simulation time 222167049 ps
CPU time 2.31 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 200548 kb
Host smart-f488af82-0e60-42cc-84a3-6675c0f4c3c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849764417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1849764417
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3668680355
Short name T1240
Test name
Test status
Simulation time 93161253 ps
CPU time 1.4 seconds
Started Mar 19 02:46:42 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 199948 kb
Host smart-7e650d9d-cc59-4a2e-badc-a584d6112ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668680355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3668680355
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3401123940
Short name T1193
Test name
Test status
Simulation time 42714400 ps
CPU time 0.6 seconds
Started Mar 19 02:47:01 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 194808 kb
Host smart-35c76d61-2104-45c0-b2d8-cf424fdb278f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401123940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3401123940
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3581075574
Short name T1136
Test name
Test status
Simulation time 69341218 ps
CPU time 0.57 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 194716 kb
Host smart-bc18bd74-f41a-41ee-b6c6-8cc698c22d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581075574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3581075574
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.52748171
Short name T1212
Test name
Test status
Simulation time 142472697 ps
CPU time 0.58 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 194836 kb
Host smart-8be1f764-4a8a-4e9f-b867-adaefb5bb12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52748171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.52748171
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.788418046
Short name T1238
Test name
Test status
Simulation time 14668009 ps
CPU time 0.55 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 194836 kb
Host smart-40c9d7c0-3a47-4f23-8169-bd593ef0a1c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788418046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.788418046
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.723783814
Short name T1210
Test name
Test status
Simulation time 11456659 ps
CPU time 0.57 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 194844 kb
Host smart-05fb65ca-effc-4739-b6ca-f43a60e67179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723783814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.723783814
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4196672156
Short name T1122
Test name
Test status
Simulation time 15748134 ps
CPU time 0.59 seconds
Started Mar 19 02:46:57 PM PDT 24
Finished Mar 19 02:46:58 PM PDT 24
Peak memory 194852 kb
Host smart-1735ca7f-dc3d-49ad-898a-2eaee8bad431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196672156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4196672156
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.855752477
Short name T1177
Test name
Test status
Simulation time 12346982 ps
CPU time 0.64 seconds
Started Mar 19 02:47:02 PM PDT 24
Finished Mar 19 02:47:03 PM PDT 24
Peak memory 194748 kb
Host smart-7292e233-a84a-4107-a4e8-425d6c3531f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855752477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.855752477
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2171175157
Short name T1134
Test name
Test status
Simulation time 215660175 ps
CPU time 0.6 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 194732 kb
Host smart-0182715c-89ed-4564-8cf6-6a14519241da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171175157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2171175157
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1380533314
Short name T1183
Test name
Test status
Simulation time 33287101 ps
CPU time 0.65 seconds
Started Mar 19 02:47:02 PM PDT 24
Finished Mar 19 02:47:03 PM PDT 24
Peak memory 194760 kb
Host smart-07ea011a-d4fb-4c30-9489-bd5d2a6bad05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380533314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1380533314
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3467741508
Short name T1115
Test name
Test status
Simulation time 25164947 ps
CPU time 0.57 seconds
Started Mar 19 02:46:58 PM PDT 24
Finished Mar 19 02:46:59 PM PDT 24
Peak memory 194744 kb
Host smart-b11e3a4a-a308-480b-b520-e0114ff7355b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467741508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3467741508
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3629326411
Short name T65
Test name
Test status
Simulation time 36023413 ps
CPU time 0.82 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 196708 kb
Host smart-cdd0c744-e526-413b-9aef-b16ff3108e01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629326411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3629326411
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3950368548
Short name T69
Test name
Test status
Simulation time 318154266 ps
CPU time 2.31 seconds
Started Mar 19 02:58:13 PM PDT 24
Finished Mar 19 02:58:16 PM PDT 24
Peak memory 198520 kb
Host smart-72b579e1-0cac-4eff-8f4c-ec0250ac1595
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950368548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3950368548
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.566968966
Short name T1145
Test name
Test status
Simulation time 41442212 ps
CPU time 0.6 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 195772 kb
Host smart-776eae30-8dc8-43bc-a043-6318115ad62b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566968966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.566968966
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4190541833
Short name T1163
Test name
Test status
Simulation time 106026215 ps
CPU time 0.83 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200276 kb
Host smart-8d930c81-c046-4252-999a-76ab1d813722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190541833 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4190541833
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.656152513
Short name T64
Test name
Test status
Simulation time 35523964 ps
CPU time 0.57 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 195824 kb
Host smart-06421468-bd33-4cab-bb19-b300e54a01b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656152513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.656152513
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.54391635
Short name T1123
Test name
Test status
Simulation time 13017188 ps
CPU time 0.6 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 194768 kb
Host smart-e6c932af-8f00-4d1b-8b64-58284c1700af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54391635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.54391635
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4276190568
Short name T1201
Test name
Test status
Simulation time 257022309 ps
CPU time 0.76 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 197424 kb
Host smart-597682fb-b608-4415-9642-12fc3ea576ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276190568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4276190568
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1389435580
Short name T1114
Test name
Test status
Simulation time 234537737 ps
CPU time 2.01 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 200468 kb
Host smart-264c80ed-3c30-4dc9-b6a4-58803c177621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389435580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1389435580
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1529586462
Short name T123
Test name
Test status
Simulation time 57569363 ps
CPU time 1.01 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:41 PM PDT 24
Peak memory 199744 kb
Host smart-08c67eaa-81f4-4231-beaa-b6eb8dac9cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529586462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1529586462
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3674682537
Short name T1217
Test name
Test status
Simulation time 14921002 ps
CPU time 0.6 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 194860 kb
Host smart-fb378751-8529-4c03-9f7d-917638089b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674682537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3674682537
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1085726234
Short name T1209
Test name
Test status
Simulation time 30675842 ps
CPU time 0.6 seconds
Started Mar 19 02:47:01 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 194844 kb
Host smart-88de3623-3157-4628-bb82-7728e10a2a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085726234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1085726234
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1711839133
Short name T1195
Test name
Test status
Simulation time 50152271 ps
CPU time 0.58 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 194732 kb
Host smart-84437d24-6c69-4343-84af-0b3605438389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711839133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1711839133
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2457600959
Short name T115
Test name
Test status
Simulation time 15951453 ps
CPU time 0.64 seconds
Started Mar 19 02:47:01 PM PDT 24
Finished Mar 19 02:47:02 PM PDT 24
Peak memory 194844 kb
Host smart-56da24a0-354d-46ad-b089-54fc65777dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457600959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2457600959
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2094874161
Short name T1194
Test name
Test status
Simulation time 35345797 ps
CPU time 0.6 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 194780 kb
Host smart-b165af34-9b0b-4a81-819c-ad985cef2751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094874161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2094874161
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1918366793
Short name T1166
Test name
Test status
Simulation time 83889214 ps
CPU time 0.61 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 194792 kb
Host smart-bdd7cab1-d30f-4dd8-9ede-d3ed31496c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918366793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1918366793
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1232790296
Short name T1156
Test name
Test status
Simulation time 11805040 ps
CPU time 0.58 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 194764 kb
Host smart-5b24818a-78e5-486d-9074-c4f3f529ccaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232790296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1232790296
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3382166600
Short name T1229
Test name
Test status
Simulation time 73125507 ps
CPU time 0.57 seconds
Started Mar 19 02:46:56 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 194812 kb
Host smart-a9063c9a-2b34-41d8-88e5-0244e076c854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382166600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3382166600
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3878507466
Short name T1158
Test name
Test status
Simulation time 14092322 ps
CPU time 0.62 seconds
Started Mar 19 02:47:01 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 194776 kb
Host smart-0ce45b53-9c84-4629-a770-ecad0b7973e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878507466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3878507466
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3080830815
Short name T1182
Test name
Test status
Simulation time 39811345 ps
CPU time 0.59 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 194796 kb
Host smart-0851b050-e185-4077-a7a0-e6c7dfa4bfd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080830815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3080830815
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2999902794
Short name T1154
Test name
Test status
Simulation time 64482573 ps
CPU time 0.74 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 198440 kb
Host smart-572be9f5-0878-48c1-9dfe-440015790bf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999902794 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2999902794
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3538162692
Short name T1189
Test name
Test status
Simulation time 17434764 ps
CPU time 0.6 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:41 PM PDT 24
Peak memory 195824 kb
Host smart-c7741f67-48d9-4f3c-a850-28b163afecdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538162692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3538162692
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2673419635
Short name T1188
Test name
Test status
Simulation time 15973424 ps
CPU time 0.59 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 193672 kb
Host smart-c19c1b3f-29c2-4b70-81e8-e4bfb79e58c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673419635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2673419635
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.614751384
Short name T1241
Test name
Test status
Simulation time 41330208 ps
CPU time 0.64 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 196288 kb
Host smart-af966bbb-7286-435d-abed-6ab3d54465cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614751384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.614751384
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1413101862
Short name T1236
Test name
Test status
Simulation time 144552599 ps
CPU time 2.06 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 200516 kb
Host smart-21a7b12e-21a9-436a-9ae7-66999cd8a4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413101862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1413101862
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2581510854
Short name T1219
Test name
Test status
Simulation time 87963954 ps
CPU time 0.96 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 199392 kb
Host smart-993bbe9f-85b0-44eb-8ef3-6aad2d363844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581510854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2581510854
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2076151184
Short name T1206
Test name
Test status
Simulation time 54642042 ps
CPU time 0.93 seconds
Started Mar 19 02:46:47 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 200304 kb
Host smart-c2b0b932-2169-4af1-a634-a25e3acae629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076151184 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2076151184
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2915659313
Short name T1179
Test name
Test status
Simulation time 32320353 ps
CPU time 0.62 seconds
Started Mar 19 02:46:46 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 196156 kb
Host smart-30157d7d-4a0a-4f9c-b255-4becc5904699
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915659313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2915659313
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3504378738
Short name T1228
Test name
Test status
Simulation time 17624674 ps
CPU time 0.58 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:42 PM PDT 24
Peak memory 194784 kb
Host smart-43fe2c7f-0490-44a5-b890-e6068d8df9b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504378738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3504378738
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.189557942
Short name T1178
Test name
Test status
Simulation time 130280469 ps
CPU time 0.75 seconds
Started Mar 19 02:46:47 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 196512 kb
Host smart-3894620b-3379-48a3-bb37-f926ba99c797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189557942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.189557942
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1487426819
Short name T1205
Test name
Test status
Simulation time 248874513 ps
CPU time 2.36 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 200560 kb
Host smart-c14e2014-d223-4f54-b0e5-933b213ab0be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487426819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1487426819
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2209893694
Short name T124
Test name
Test status
Simulation time 277321921 ps
CPU time 1.26 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 199712 kb
Host smart-c8b21817-c0dc-4457-a170-b5d6ba5782b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209893694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2209893694
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2469283003
Short name T1220
Test name
Test status
Simulation time 16385930 ps
CPU time 1.03 seconds
Started Mar 19 02:46:48 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 200228 kb
Host smart-03ee0726-fee2-4b8e-b4cd-0e8c3ff2506d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469283003 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2469283003
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2818347065
Short name T1191
Test name
Test status
Simulation time 14532073 ps
CPU time 0.65 seconds
Started Mar 19 02:46:50 PM PDT 24
Finished Mar 19 02:46:50 PM PDT 24
Peak memory 195956 kb
Host smart-729ef42c-83a0-477e-a0da-f9cd734036fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818347065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2818347065
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1886184406
Short name T1132
Test name
Test status
Simulation time 12251101 ps
CPU time 0.57 seconds
Started Mar 19 02:46:46 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 194776 kb
Host smart-bf99b568-3485-49d3-b7f8-38f1d9df5c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886184406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1886184406
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2920275737
Short name T1207
Test name
Test status
Simulation time 87546231 ps
CPU time 0.74 seconds
Started Mar 19 02:46:50 PM PDT 24
Finished Mar 19 02:46:50 PM PDT 24
Peak memory 197420 kb
Host smart-1932167d-77a2-4dab-91f2-cce9f890abff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920275737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2920275737
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2648652206
Short name T1140
Test name
Test status
Simulation time 142168497 ps
CPU time 1.5 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 200332 kb
Host smart-3836c85f-592a-4bca-b756-845b5e199223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648652206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2648652206
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2359806644
Short name T1204
Test name
Test status
Simulation time 130023075 ps
CPU time 0.91 seconds
Started Mar 19 02:46:49 PM PDT 24
Finished Mar 19 02:46:50 PM PDT 24
Peak memory 199080 kb
Host smart-56fb121c-e37f-466e-8f7f-56c1ea028548
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359806644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2359806644
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1544127017
Short name T1172
Test name
Test status
Simulation time 46647654 ps
CPU time 0.8 seconds
Started Mar 19 02:46:48 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 200284 kb
Host smart-67a2200a-cbde-461d-8e7f-7484c3479ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544127017 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1544127017
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3284246210
Short name T78
Test name
Test status
Simulation time 12545774 ps
CPU time 0.59 seconds
Started Mar 19 02:46:55 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 195816 kb
Host smart-586ca051-b2f7-4a72-b99e-d939da178bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284246210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3284246210
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3587069921
Short name T1184
Test name
Test status
Simulation time 20856431 ps
CPU time 0.58 seconds
Started Mar 19 02:46:48 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 194880 kb
Host smart-6ea73bd0-4c7b-479a-89b4-edb2bde1084b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587069921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3587069921
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4040288963
Short name T1176
Test name
Test status
Simulation time 38194704 ps
CPU time 0.63 seconds
Started Mar 19 02:46:45 PM PDT 24
Finished Mar 19 02:46:47 PM PDT 24
Peak memory 195964 kb
Host smart-e436f167-e04d-4bf1-ba00-82f6837bbc13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040288963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4040288963
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1536975920
Short name T1142
Test name
Test status
Simulation time 104509655 ps
CPU time 2.02 seconds
Started Mar 19 02:46:49 PM PDT 24
Finished Mar 19 02:46:52 PM PDT 24
Peak memory 200544 kb
Host smart-237bac38-aff1-4405-bbc2-8aebdcd2b8bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536975920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1536975920
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4064346640
Short name T79
Test name
Test status
Simulation time 166242334 ps
CPU time 0.97 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 199272 kb
Host smart-ad6473ed-18aa-4f20-b508-8637814a258b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064346640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4064346640
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3098013740
Short name T1150
Test name
Test status
Simulation time 54230385 ps
CPU time 0.77 seconds
Started Mar 19 02:46:47 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 199188 kb
Host smart-77220d30-684c-4a03-be75-314af4721d31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098013740 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3098013740
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3697705713
Short name T1141
Test name
Test status
Simulation time 14271170 ps
CPU time 0.58 seconds
Started Mar 19 02:46:46 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 195820 kb
Host smart-f80356e0-8b9d-4a4b-9f39-708bd7635735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697705713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3697705713
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1276884131
Short name T1118
Test name
Test status
Simulation time 31572516 ps
CPU time 0.55 seconds
Started Mar 19 02:46:47 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 194812 kb
Host smart-825acb95-604d-4b5a-822f-59fca1adb87c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276884131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1276884131
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1605198003
Short name T1203
Test name
Test status
Simulation time 14334050 ps
CPU time 0.67 seconds
Started Mar 19 02:46:50 PM PDT 24
Finished Mar 19 02:46:51 PM PDT 24
Peak memory 196288 kb
Host smart-755ac3e3-2a1f-4fb7-ab19-25012199cb1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605198003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1605198003
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2386255037
Short name T1185
Test name
Test status
Simulation time 580708321 ps
CPU time 2.51 seconds
Started Mar 19 02:46:47 PM PDT 24
Finished Mar 19 02:46:50 PM PDT 24
Peak memory 200524 kb
Host smart-dea48554-81df-4794-aabf-5cb7388013c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386255037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2386255037
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1560001574
Short name T80
Test name
Test status
Simulation time 49552795 ps
CPU time 0.95 seconds
Started Mar 19 02:46:47 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 199500 kb
Host smart-39b0e1ad-43d4-4077-becd-75b3f2babbcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560001574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1560001574
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3439245488
Short name T371
Test name
Test status
Simulation time 86159945 ps
CPU time 0.56 seconds
Started Mar 19 03:09:26 PM PDT 24
Finished Mar 19 03:09:27 PM PDT 24
Peak memory 195664 kb
Host smart-4dd85203-fc02-4236-8b35-a184569be1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439245488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3439245488
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3089940510
Short name T836
Test name
Test status
Simulation time 89234283604 ps
CPU time 152.89 seconds
Started Mar 19 03:09:25 PM PDT 24
Finished Mar 19 03:11:58 PM PDT 24
Peak memory 200232 kb
Host smart-f54c2a81-ade8-4d62-bb94-be49f41fc093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089940510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3089940510
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1250510009
Short name T502
Test name
Test status
Simulation time 27157957206 ps
CPU time 48.24 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:10:12 PM PDT 24
Peak memory 200108 kb
Host smart-1e9af8df-bfd0-4cc2-badc-2759d7d9f8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250510009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1250510009
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3855247071
Short name T1099
Test name
Test status
Simulation time 52433163242 ps
CPU time 6.94 seconds
Started Mar 19 03:09:11 PM PDT 24
Finished Mar 19 03:09:19 PM PDT 24
Peak memory 200152 kb
Host smart-05d4dc90-0268-4ce4-b9ff-4ecc9aae7d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855247071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3855247071
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2710958709
Short name T310
Test name
Test status
Simulation time 74468941362 ps
CPU time 125.39 seconds
Started Mar 19 03:09:16 PM PDT 24
Finished Mar 19 03:11:21 PM PDT 24
Peak memory 200188 kb
Host smart-a7d11ba8-891b-49b6-a782-6dd370d7de8b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710958709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2710958709
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.656087890
Short name T1098
Test name
Test status
Simulation time 40853132144 ps
CPU time 161.75 seconds
Started Mar 19 03:09:18 PM PDT 24
Finished Mar 19 03:12:01 PM PDT 24
Peak memory 200220 kb
Host smart-7aa0f3ba-7de5-4345-bb34-bcbd9f8c1512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=656087890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.656087890
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2023253088
Short name T487
Test name
Test status
Simulation time 12151262721 ps
CPU time 6.87 seconds
Started Mar 19 03:09:19 PM PDT 24
Finished Mar 19 03:09:27 PM PDT 24
Peak memory 198848 kb
Host smart-e2f86150-b2a6-4a46-b1b9-fd85b3720873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023253088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2023253088
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.1418457601
Short name T901
Test name
Test status
Simulation time 13583032529 ps
CPU time 647.79 seconds
Started Mar 19 03:09:15 PM PDT 24
Finished Mar 19 03:20:03 PM PDT 24
Peak memory 200140 kb
Host smart-17f3f73e-7bbf-41f7-959c-cbea1af109b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418457601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1418457601
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2970516831
Short name T548
Test name
Test status
Simulation time 5069283124 ps
CPU time 43.7 seconds
Started Mar 19 03:09:18 PM PDT 24
Finished Mar 19 03:10:02 PM PDT 24
Peak memory 198292 kb
Host smart-e70ff19e-efbd-4bc8-ab96-9d02299fd945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970516831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2970516831
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3215209626
Short name T821
Test name
Test status
Simulation time 30984376715 ps
CPU time 45.25 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:09:59 PM PDT 24
Peak memory 199940 kb
Host smart-b3bc9c78-04e7-476e-8613-a6d83853739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215209626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3215209626
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1758832774
Short name T619
Test name
Test status
Simulation time 3481865014 ps
CPU time 1.85 seconds
Started Mar 19 03:09:18 PM PDT 24
Finished Mar 19 03:09:20 PM PDT 24
Peak memory 196244 kb
Host smart-66e0bace-f8ef-4038-ade8-9036f35aeec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758832774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1758832774
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2351082366
Short name T88
Test name
Test status
Simulation time 65089797 ps
CPU time 0.89 seconds
Started Mar 19 03:09:14 PM PDT 24
Finished Mar 19 03:09:15 PM PDT 24
Peak memory 218504 kb
Host smart-c8cbf4e6-e9c9-4e46-90b9-cbb1eabdc864
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351082366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2351082366
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1251157933
Short name T673
Test name
Test status
Simulation time 6158818810 ps
CPU time 17.8 seconds
Started Mar 19 03:09:18 PM PDT 24
Finished Mar 19 03:09:36 PM PDT 24
Peak memory 199964 kb
Host smart-f41da3e2-3e65-4054-89b0-66d9ba9e245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251157933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1251157933
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2092510363
Short name T446
Test name
Test status
Simulation time 411715630390 ps
CPU time 1180.02 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:29:04 PM PDT 24
Peak memory 200200 kb
Host smart-724671c8-c9ee-48f4-b6e4-2cbc158a39e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092510363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2092510363
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2852978041
Short name T480
Test name
Test status
Simulation time 6709904347 ps
CPU time 15.62 seconds
Started Mar 19 03:09:12 PM PDT 24
Finished Mar 19 03:09:28 PM PDT 24
Peak memory 200180 kb
Host smart-37099b35-7c27-49a3-83bf-5a746900ff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852978041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2852978041
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_alert_test.627423525
Short name T948
Test name
Test status
Simulation time 35189222 ps
CPU time 0.63 seconds
Started Mar 19 03:09:19 PM PDT 24
Finished Mar 19 03:09:20 PM PDT 24
Peak memory 195648 kb
Host smart-11b23ced-c29c-4cef-801c-e03a4af64ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627423525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.627423525
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3210301761
Short name T934
Test name
Test status
Simulation time 76479799348 ps
CPU time 69.16 seconds
Started Mar 19 03:09:23 PM PDT 24
Finished Mar 19 03:10:33 PM PDT 24
Peak memory 200108 kb
Host smart-187b5aaf-f4e1-4a55-8f80-94206e2b34ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210301761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3210301761
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4293446150
Short name T1017
Test name
Test status
Simulation time 85137240243 ps
CPU time 70.62 seconds
Started Mar 19 03:09:18 PM PDT 24
Finished Mar 19 03:10:29 PM PDT 24
Peak memory 200208 kb
Host smart-e192998d-ec47-4ade-a961-b0f63409e3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293446150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4293446150
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.24504298
Short name T409
Test name
Test status
Simulation time 105494778085 ps
CPU time 40.41 seconds
Started Mar 19 03:09:21 PM PDT 24
Finished Mar 19 03:10:02 PM PDT 24
Peak memory 200128 kb
Host smart-b6730452-9692-48ba-a8f2-37e48f489b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24504298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.24504298
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.996074499
Short name T613
Test name
Test status
Simulation time 49832047380 ps
CPU time 18.71 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:09:43 PM PDT 24
Peak memory 199976 kb
Host smart-c5cd75ae-31f2-4826-bd63-86ecb88fd05c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996074499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.996074499
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.904458485
Short name T1082
Test name
Test status
Simulation time 116023575995 ps
CPU time 809.29 seconds
Started Mar 19 03:09:20 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 200192 kb
Host smart-4f64d9c6-e00d-4754-a372-f3f3e148e775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=904458485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.904458485
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1307215610
Short name T964
Test name
Test status
Simulation time 574235541 ps
CPU time 0.71 seconds
Started Mar 19 03:09:21 PM PDT 24
Finished Mar 19 03:09:22 PM PDT 24
Peak memory 196316 kb
Host smart-164f16bd-f305-49ca-a5f0-23794dae3c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307215610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1307215610
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.4221133791
Short name T1012
Test name
Test status
Simulation time 17605266310 ps
CPU time 13.49 seconds
Started Mar 19 03:09:16 PM PDT 24
Finished Mar 19 03:09:30 PM PDT 24
Peak memory 194856 kb
Host smart-d62b4d4a-ea2d-4ef8-88a9-26fbf2a87133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221133791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4221133791
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2208445234
Short name T254
Test name
Test status
Simulation time 28345355883 ps
CPU time 334.95 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:14:49 PM PDT 24
Peak memory 200132 kb
Host smart-83be8207-c4db-4f0f-beef-4908daac903f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208445234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2208445234
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.44422306
Short name T334
Test name
Test status
Simulation time 1193000086 ps
CPU time 1.06 seconds
Started Mar 19 03:09:25 PM PDT 24
Finished Mar 19 03:09:26 PM PDT 24
Peak memory 195664 kb
Host smart-fdfb931f-3cb2-4acd-9643-3655e940d32a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44422306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.44422306
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1810751368
Short name T517
Test name
Test status
Simulation time 216578538546 ps
CPU time 122.41 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:11:16 PM PDT 24
Peak memory 200196 kb
Host smart-2ddf8dd9-c99a-46a2-8fc4-340d3a9084fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810751368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1810751368
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1974175273
Short name T880
Test name
Test status
Simulation time 2206942552 ps
CPU time 1.11 seconds
Started Mar 19 03:09:19 PM PDT 24
Finished Mar 19 03:09:20 PM PDT 24
Peak memory 195668 kb
Host smart-20bcd1d5-045e-4858-935d-ffc44fd3a2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974175273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1974175273
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.438774923
Short name T32
Test name
Test status
Simulation time 36673919 ps
CPU time 0.78 seconds
Started Mar 19 03:09:20 PM PDT 24
Finished Mar 19 03:09:21 PM PDT 24
Peak memory 218488 kb
Host smart-001819c2-1bf4-4839-8615-37a1e5a7eeb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438774923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.438774923
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1263073162
Short name T460
Test name
Test status
Simulation time 492010193 ps
CPU time 1.57 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:09:11 PM PDT 24
Peak memory 198904 kb
Host smart-46976ec7-395a-43c9-9da1-92634e4221cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263073162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1263073162
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2939568457
Short name T504
Test name
Test status
Simulation time 345448231753 ps
CPU time 297.33 seconds
Started Mar 19 03:09:18 PM PDT 24
Finished Mar 19 03:14:16 PM PDT 24
Peak memory 208576 kb
Host smart-5c09fa35-9745-4fcc-94a3-aab4e3975a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939568457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2939568457
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.472527058
Short name T886
Test name
Test status
Simulation time 7918465893 ps
CPU time 14.29 seconds
Started Mar 19 03:09:16 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 200124 kb
Host smart-640d3ddf-4b96-4311-8af8-741f92b7c5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472527058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.472527058
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.840992771
Short name T635
Test name
Test status
Simulation time 40115652034 ps
CPU time 17.38 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:09:41 PM PDT 24
Peak memory 200028 kb
Host smart-59799f0e-89d5-4da6-82cf-4597afdd1f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840992771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.840992771
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2644524506
Short name T1002
Test name
Test status
Simulation time 12477126 ps
CPU time 0.56 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:09:52 PM PDT 24
Peak memory 195660 kb
Host smart-31f30b3c-5984-4244-b0b4-a99c3613af89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644524506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2644524506
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3521831320
Short name T442
Test name
Test status
Simulation time 65647110868 ps
CPU time 44.36 seconds
Started Mar 19 03:09:44 PM PDT 24
Finished Mar 19 03:10:29 PM PDT 24
Peak memory 200212 kb
Host smart-f69e80d5-8c98-4b6f-a08f-89dddb2e6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521831320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3521831320
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1013675437
Short name T1015
Test name
Test status
Simulation time 41466429688 ps
CPU time 31.18 seconds
Started Mar 19 03:09:46 PM PDT 24
Finished Mar 19 03:10:18 PM PDT 24
Peak memory 199936 kb
Host smart-1a069d0c-e6dd-4e21-864a-627dfeb2dea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013675437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1013675437
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1993688332
Short name T693
Test name
Test status
Simulation time 44991392047 ps
CPU time 73.06 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:11:05 PM PDT 24
Peak memory 200216 kb
Host smart-77668b4b-e931-4e6a-b2a1-ab24e1c9b01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993688332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1993688332
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2004022153
Short name T119
Test name
Test status
Simulation time 26817058029 ps
CPU time 6.98 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:09:55 PM PDT 24
Peak memory 199760 kb
Host smart-5799d948-2e23-4246-9505-896f366f4ad5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004022153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2004022153
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2507005256
Short name T557
Test name
Test status
Simulation time 108680377229 ps
CPU time 283.93 seconds
Started Mar 19 03:09:44 PM PDT 24
Finished Mar 19 03:14:28 PM PDT 24
Peak memory 200176 kb
Host smart-090d0e56-6e75-4844-863a-38d6436fca83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507005256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2507005256
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2955938659
Short name T323
Test name
Test status
Simulation time 71632342 ps
CPU time 0.6 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:09:49 PM PDT 24
Peak memory 196068 kb
Host smart-212d94db-cb2f-4ee5-8236-046daa89e159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955938659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2955938659
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.302411566
Short name T643
Test name
Test status
Simulation time 11274554835 ps
CPU time 18.68 seconds
Started Mar 19 03:09:43 PM PDT 24
Finished Mar 19 03:10:02 PM PDT 24
Peak memory 198132 kb
Host smart-1f2606bf-4440-4aa3-9b06-b061fe12dfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302411566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.302411566
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3925875365
Short name T990
Test name
Test status
Simulation time 1940267195 ps
CPU time 31.39 seconds
Started Mar 19 03:09:43 PM PDT 24
Finished Mar 19 03:10:14 PM PDT 24
Peak memory 200184 kb
Host smart-c896b4b0-a039-48ae-a038-6233039dae20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925875365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3925875365
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.738753022
Short name T1066
Test name
Test status
Simulation time 6539287368 ps
CPU time 3.85 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 199360 kb
Host smart-a0027cd1-742a-4c19-8712-7b794b318fd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738753022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.738753022
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1039991789
Short name T559
Test name
Test status
Simulation time 19264708814 ps
CPU time 37.48 seconds
Started Mar 19 03:09:45 PM PDT 24
Finished Mar 19 03:10:23 PM PDT 24
Peak memory 200216 kb
Host smart-59229b30-893f-40ff-bc41-c2243cc32caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039991789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1039991789
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2482429028
Short name T816
Test name
Test status
Simulation time 2792981779 ps
CPU time 1.64 seconds
Started Mar 19 03:09:41 PM PDT 24
Finished Mar 19 03:09:42 PM PDT 24
Peak memory 195976 kb
Host smart-228730fc-4ada-49ba-a7af-6b9d8e1ab402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482429028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2482429028
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4202403825
Short name T292
Test name
Test status
Simulation time 540588069 ps
CPU time 1.08 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:09:52 PM PDT 24
Peak memory 198548 kb
Host smart-11b5fb97-5b6d-4a93-916b-a661417ff49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202403825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4202403825
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.192865547
Short name T938
Test name
Test status
Simulation time 131387271434 ps
CPU time 398.11 seconds
Started Mar 19 03:09:46 PM PDT 24
Finished Mar 19 03:16:24 PM PDT 24
Peak memory 200160 kb
Host smart-5dcf528a-3a2e-44ef-b3c0-7ad085b7b8f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192865547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.192865547
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.690299509
Short name T488
Test name
Test status
Simulation time 1772360409 ps
CPU time 1.51 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:09:51 PM PDT 24
Peak memory 198360 kb
Host smart-b1d5795e-9ffa-4d17-8166-be47e850d09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690299509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.690299509
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3059672754
Short name T496
Test name
Test status
Simulation time 52302538201 ps
CPU time 65.75 seconds
Started Mar 19 03:09:49 PM PDT 24
Finished Mar 19 03:10:56 PM PDT 24
Peak memory 200132 kb
Host smart-1094fba4-ec57-4bd1-9c9c-b25fb0b0221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059672754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3059672754
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3726752715
Short name T877
Test name
Test status
Simulation time 90592626786 ps
CPU time 90.56 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:14:14 PM PDT 24
Peak memory 199952 kb
Host smart-a7b0d3dd-4827-4627-8706-5db4c6142e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726752715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3726752715
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1695478560
Short name T285
Test name
Test status
Simulation time 157686039575 ps
CPU time 59.39 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:13:41 PM PDT 24
Peak memory 200192 kb
Host smart-0429667d-689a-46ef-9a31-f9349ebaff02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695478560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1695478560
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2787343320
Short name T529
Test name
Test status
Simulation time 112173654690 ps
CPU time 73.73 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:13:56 PM PDT 24
Peak memory 200168 kb
Host smart-e8d8d02e-733b-43cb-a8e9-77d9989abdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787343320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2787343320
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1897107971
Short name T204
Test name
Test status
Simulation time 126066623990 ps
CPU time 203.85 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 200204 kb
Host smart-66598d7a-1f84-4223-a843-bb3a1632d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897107971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1897107971
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3741978880
Short name T996
Test name
Test status
Simulation time 124214335844 ps
CPU time 57.88 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:13:39 PM PDT 24
Peak memory 200176 kb
Host smart-40b2c76f-e26c-45ab-9a86-ede58058fc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741978880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3741978880
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2956197532
Short name T905
Test name
Test status
Simulation time 17559069554 ps
CPU time 26.72 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:07 PM PDT 24
Peak memory 199808 kb
Host smart-a33e0c3f-ab02-4790-b578-315ad42bc466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956197532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2956197532
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1592558230
Short name T148
Test name
Test status
Simulation time 24654241145 ps
CPU time 46.14 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:27 PM PDT 24
Peak memory 200132 kb
Host smart-51a666f6-0ecc-42c9-a12b-2f73c8fe56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592558230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1592558230
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.672699037
Short name T392
Test name
Test status
Simulation time 34366236 ps
CPU time 0.61 seconds
Started Mar 19 03:09:46 PM PDT 24
Finished Mar 19 03:09:47 PM PDT 24
Peak memory 195680 kb
Host smart-25ff331f-3ad9-4dde-b5d5-ce7123033f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672699037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.672699037
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2588719622
Short name T149
Test name
Test status
Simulation time 106666044580 ps
CPU time 23.25 seconds
Started Mar 19 03:09:44 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 200152 kb
Host smart-e0548bd6-f71e-4d45-8698-0c49c37cb253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588719622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2588719622
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1494124424
Short name T570
Test name
Test status
Simulation time 20709222450 ps
CPU time 38.25 seconds
Started Mar 19 03:09:49 PM PDT 24
Finished Mar 19 03:10:30 PM PDT 24
Peak memory 200096 kb
Host smart-b4af911f-7490-4910-84c3-39f389d23afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494124424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1494124424
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.698825104
Short name T857
Test name
Test status
Simulation time 7737853770 ps
CPU time 11.88 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 196784 kb
Host smart-f8e72694-784f-4b24-8a16-cfd59bb4c797
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698825104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.698825104
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4108550938
Short name T951
Test name
Test status
Simulation time 162336927075 ps
CPU time 1208.89 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:30:01 PM PDT 24
Peak memory 200108 kb
Host smart-b7175800-4352-4343-b9b3-298414463a14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108550938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4108550938
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1326217257
Short name T1007
Test name
Test status
Simulation time 5928266010 ps
CPU time 11.33 seconds
Started Mar 19 03:09:49 PM PDT 24
Finished Mar 19 03:10:02 PM PDT 24
Peak memory 198048 kb
Host smart-b203fb56-3469-490e-99ab-0920b9eb036e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326217257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1326217257
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.851969003
Short name T126
Test name
Test status
Simulation time 16408551753 ps
CPU time 33.32 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:10:26 PM PDT 24
Peak memory 198896 kb
Host smart-e85cbab7-38ed-4cfb-9f76-be38ff7ca7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851969003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.851969003
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.584313841
Short name T628
Test name
Test status
Simulation time 7981358466 ps
CPU time 99.23 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:11:28 PM PDT 24
Peak memory 200168 kb
Host smart-03a15a94-5931-4402-95be-756765dd166c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584313841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.584313841
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1536128393
Short name T866
Test name
Test status
Simulation time 1683636814 ps
CPU time 9.42 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:09:59 PM PDT 24
Peak memory 198032 kb
Host smart-ac1b3500-3ec4-46db-96cc-c7536bd4aafb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536128393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1536128393
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2743805456
Short name T128
Test name
Test status
Simulation time 17232839726 ps
CPU time 31.63 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:10:21 PM PDT 24
Peak memory 200168 kb
Host smart-2aa7c053-fe8a-45f9-83a5-43f6df683a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743805456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2743805456
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.251939433
Short name T483
Test name
Test status
Simulation time 3536373087 ps
CPU time 6.39 seconds
Started Mar 19 03:09:49 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 196212 kb
Host smart-85f6f434-6958-4f1c-8853-b33c43d83964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251939433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.251939433
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.338446708
Short name T361
Test name
Test status
Simulation time 537604119 ps
CPU time 1.15 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:09:54 PM PDT 24
Peak memory 199620 kb
Host smart-84f50683-7409-4654-a93c-b74ed1de8a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338446708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.338446708
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2638569679
Short name T888
Test name
Test status
Simulation time 120431360419 ps
CPU time 143.42 seconds
Started Mar 19 03:09:44 PM PDT 24
Finished Mar 19 03:12:08 PM PDT 24
Peak memory 215676 kb
Host smart-c08140d5-6577-486e-a7c0-25ed431e1079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638569679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2638569679
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2561841318
Short name T314
Test name
Test status
Simulation time 7440180926 ps
CPU time 16.11 seconds
Started Mar 19 03:09:47 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 200076 kb
Host smart-67f70f2d-ace2-4f32-b90f-6bfb92d03bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561841318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2561841318
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.9809628
Short name T782
Test name
Test status
Simulation time 71645601551 ps
CPU time 61.42 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:42 PM PDT 24
Peak memory 199784 kb
Host smart-579618a8-ae5f-4dc6-824d-12b2165b68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9809628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.9809628
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1585465455
Short name T776
Test name
Test status
Simulation time 65464239277 ps
CPU time 98.01 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:14:19 PM PDT 24
Peak memory 200196 kb
Host smart-4eb9addd-5e61-4fb1-815b-130aaf331bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585465455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1585465455
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1992607065
Short name T171
Test name
Test status
Simulation time 125786144771 ps
CPU time 60.62 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:40 PM PDT 24
Peak memory 200240 kb
Host smart-19225f78-1c42-44c2-8612-89ae5bba82e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992607065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1992607065
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.458884477
Short name T900
Test name
Test status
Simulation time 44057771209 ps
CPU time 17.26 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:13:01 PM PDT 24
Peak memory 200140 kb
Host smart-c8b1c263-9753-4426-9680-284128704c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458884477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.458884477
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1068184601
Short name T894
Test name
Test status
Simulation time 2685536189 ps
CPU time 6.2 seconds
Started Mar 19 03:12:38 PM PDT 24
Finished Mar 19 03:12:44 PM PDT 24
Peak memory 200148 kb
Host smart-e0dc8602-57f8-4538-b13e-87ea15faaace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068184601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1068184601
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.730548503
Short name T472
Test name
Test status
Simulation time 138258405828 ps
CPU time 35.56 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:13:19 PM PDT 24
Peak memory 200224 kb
Host smart-b739bc8a-706d-4226-aa8c-7246a642998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730548503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.730548503
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4076210767
Short name T325
Test name
Test status
Simulation time 104954164649 ps
CPU time 165.47 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:15:28 PM PDT 24
Peak memory 200140 kb
Host smart-fd4a98ef-5fe3-4103-a352-68ef8ac06155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076210767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4076210767
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3079104565
Short name T522
Test name
Test status
Simulation time 51624453323 ps
CPU time 24.15 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:13:05 PM PDT 24
Peak memory 200212 kb
Host smart-0c57d61a-e365-4ccd-b5ea-a516d0482a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079104565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3079104565
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3585563907
Short name T913
Test name
Test status
Simulation time 131959805107 ps
CPU time 336.03 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:18:17 PM PDT 24
Peak memory 200232 kb
Host smart-96846f8c-b07d-47be-a044-053998b7b78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585563907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3585563907
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3971068280
Short name T156
Test name
Test status
Simulation time 83741816657 ps
CPU time 67.85 seconds
Started Mar 19 03:09:44 PM PDT 24
Finished Mar 19 03:10:52 PM PDT 24
Peak memory 200192 kb
Host smart-c39b2b97-c980-4d42-97d8-35e2e34a0950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971068280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3971068280
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.4142252029
Short name T837
Test name
Test status
Simulation time 50712192439 ps
CPU time 19.88 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:10:12 PM PDT 24
Peak memory 199860 kb
Host smart-d7b233be-8937-44ec-b26f-99c8cd93cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142252029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4142252029
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2114716225
Short name T564
Test name
Test status
Simulation time 19872696065 ps
CPU time 24.72 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:10:14 PM PDT 24
Peak memory 200188 kb
Host smart-fa08f3f7-7d67-433c-b4d7-fca2617797fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114716225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2114716225
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2719352976
Short name T618
Test name
Test status
Simulation time 48722616349 ps
CPU time 5.81 seconds
Started Mar 19 03:09:47 PM PDT 24
Finished Mar 19 03:09:53 PM PDT 24
Peak memory 198212 kb
Host smart-be827817-768b-4d63-9ffe-2d9da1562215
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719352976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2719352976
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3454511610
Short name T728
Test name
Test status
Simulation time 69693926293 ps
CPU time 577.33 seconds
Started Mar 19 03:09:53 PM PDT 24
Finished Mar 19 03:19:31 PM PDT 24
Peak memory 200196 kb
Host smart-5bfbbd8b-fc7f-446a-8766-e0d82151fcce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454511610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3454511610
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1905711587
Short name T478
Test name
Test status
Simulation time 4755426847 ps
CPU time 13.95 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:18 PM PDT 24
Peak memory 200048 kb
Host smart-327f6967-18c5-48d3-bb75-d2b8fe0f359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905711587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1905711587
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2437618536
Short name T908
Test name
Test status
Simulation time 226763025937 ps
CPU time 187.11 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:12:56 PM PDT 24
Peak memory 208216 kb
Host smart-a20c969b-20b9-4f8e-932d-41703cedf6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437618536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2437618536
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1597398560
Short name T969
Test name
Test status
Simulation time 10255114284 ps
CPU time 195.66 seconds
Started Mar 19 03:10:03 PM PDT 24
Finished Mar 19 03:13:20 PM PDT 24
Peak memory 200204 kb
Host smart-ac6323d4-ed96-46bc-9c9b-293c63a85216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597398560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1597398560
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3799014725
Short name T692
Test name
Test status
Simulation time 3530154830 ps
CPU time 15.61 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:10:05 PM PDT 24
Peak memory 198268 kb
Host smart-6f9ed0ac-88e7-4e4b-bdf1-85b5afad9675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3799014725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3799014725
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4150502338
Short name T348
Test name
Test status
Simulation time 21193520339 ps
CPU time 41.59 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:10:31 PM PDT 24
Peak memory 200180 kb
Host smart-7a0ed806-a018-4c8b-9bce-d90adc84741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150502338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4150502338
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1362642516
Short name T467
Test name
Test status
Simulation time 6686752782 ps
CPU time 10.96 seconds
Started Mar 19 03:09:43 PM PDT 24
Finished Mar 19 03:09:54 PM PDT 24
Peak memory 196296 kb
Host smart-7e549168-96c1-4b67-b417-bcd3b483a609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362642516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1362642516
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3928905539
Short name T19
Test name
Test status
Simulation time 874857534 ps
CPU time 2.42 seconds
Started Mar 19 03:09:43 PM PDT 24
Finished Mar 19 03:09:46 PM PDT 24
Peak memory 199044 kb
Host smart-80483a42-5122-42cc-94e7-7b00aa358a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928905539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3928905539
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3217570135
Short name T274
Test name
Test status
Simulation time 1183071928723 ps
CPU time 175.99 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:12:48 PM PDT 24
Peak memory 208488 kb
Host smart-eb640613-b2a9-465d-bae3-b7b2e049dc77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217570135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3217570135
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.558776227
Short name T497
Test name
Test status
Simulation time 6228492879 ps
CPU time 18.19 seconds
Started Mar 19 03:09:55 PM PDT 24
Finished Mar 19 03:10:14 PM PDT 24
Peak memory 200100 kb
Host smart-8e13c780-cace-4549-b3e1-8bba87ef12cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558776227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.558776227
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2567749759
Short name T769
Test name
Test status
Simulation time 115364166752 ps
CPU time 66.66 seconds
Started Mar 19 03:09:49 PM PDT 24
Finished Mar 19 03:10:57 PM PDT 24
Peak memory 200156 kb
Host smart-7c48182d-4a5b-42a0-baf5-b9a7897915fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567749759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2567749759
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.396702128
Short name T699
Test name
Test status
Simulation time 178374427159 ps
CPU time 62.15 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:42 PM PDT 24
Peak memory 200116 kb
Host smart-1c593656-e61e-4466-bb08-927c4cb1624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396702128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.396702128
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.322576100
Short name T185
Test name
Test status
Simulation time 175289539771 ps
CPU time 72.96 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:13:56 PM PDT 24
Peak memory 200192 kb
Host smart-615162da-2c99-4394-83b6-36b8e04df3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322576100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.322576100
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3321609314
Short name T591
Test name
Test status
Simulation time 30030640859 ps
CPU time 13.61 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:12:55 PM PDT 24
Peak memory 199412 kb
Host smart-06910b4c-50c5-4d52-a7b3-bde326ab816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321609314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3321609314
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2041161497
Short name T450
Test name
Test status
Simulation time 54516425610 ps
CPU time 24.09 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:13:07 PM PDT 24
Peak memory 197924 kb
Host smart-ad90c6db-ead0-48ca-a120-eadcc55a9673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041161497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2041161497
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1873501598
Short name T756
Test name
Test status
Simulation time 114744721351 ps
CPU time 59.26 seconds
Started Mar 19 03:12:39 PM PDT 24
Finished Mar 19 03:13:39 PM PDT 24
Peak memory 200224 kb
Host smart-becc5cb8-50c5-4ccd-b147-a6b6f93eeec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873501598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1873501598
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3828659933
Short name T761
Test name
Test status
Simulation time 17469298847 ps
CPU time 26.47 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:07 PM PDT 24
Peak memory 200100 kb
Host smart-b0576043-1bf6-496e-811f-d77a504857a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828659933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3828659933
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1367940051
Short name T475
Test name
Test status
Simulation time 192298776481 ps
CPU time 30.47 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:13:13 PM PDT 24
Peak memory 199824 kb
Host smart-538332b9-26b7-4355-8ae4-5719ff4a887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367940051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1367940051
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.507008008
Short name T118
Test name
Test status
Simulation time 94490126087 ps
CPU time 71.38 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:13:55 PM PDT 24
Peak memory 200164 kb
Host smart-3b8de9ce-2290-4f14-9f90-7676c7dc1173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507008008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.507008008
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3546800653
Short name T883
Test name
Test status
Simulation time 15043134037 ps
CPU time 28.6 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:13:10 PM PDT 24
Peak memory 200108 kb
Host smart-08ca8f5f-8cac-4782-b39a-5504ed3cd659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546800653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3546800653
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.826635041
Short name T612
Test name
Test status
Simulation time 20830906 ps
CPU time 0.55 seconds
Started Mar 19 03:09:49 PM PDT 24
Finished Mar 19 03:09:52 PM PDT 24
Peak memory 195660 kb
Host smart-70b929fc-fc16-41ed-a726-1046365aa42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826635041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.826635041
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1193800610
Short name T280
Test name
Test status
Simulation time 250470093955 ps
CPU time 91.57 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:11:23 PM PDT 24
Peak memory 200208 kb
Host smart-f848726a-78b8-4688-b765-93e6a983b21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193800610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1193800610
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1241143898
Short name T1043
Test name
Test status
Simulation time 174009648502 ps
CPU time 71.42 seconds
Started Mar 19 03:09:55 PM PDT 24
Finished Mar 19 03:11:07 PM PDT 24
Peak memory 200116 kb
Host smart-a22825be-2256-4e37-9bb0-6d798de2eb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241143898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1241143898
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3987466417
Short name T385
Test name
Test status
Simulation time 127113398309 ps
CPU time 55.02 seconds
Started Mar 19 03:09:52 PM PDT 24
Finished Mar 19 03:10:49 PM PDT 24
Peak memory 200136 kb
Host smart-e0968a3b-e0c9-4618-9cf5-15ae67e61dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987466417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3987466417
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2648152863
Short name T21
Test name
Test status
Simulation time 15921331469 ps
CPU time 17.31 seconds
Started Mar 19 03:09:53 PM PDT 24
Finished Mar 19 03:10:11 PM PDT 24
Peak memory 200064 kb
Host smart-72c8a64e-6084-47d5-ab46-55530bbc5548
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648152863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2648152863
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4251760786
Short name T439
Test name
Test status
Simulation time 103021130618 ps
CPU time 171.09 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:12:43 PM PDT 24
Peak memory 200128 kb
Host smart-e0ab5b38-6ca5-49ec-a889-b34929c436bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251760786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4251760786
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1091538039
Short name T336
Test name
Test status
Simulation time 122905491 ps
CPU time 0.79 seconds
Started Mar 19 03:09:54 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 197316 kb
Host smart-891dac8a-d2ba-4306-9054-3b894cd487b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091538039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1091538039
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1774656126
Short name T443
Test name
Test status
Simulation time 50991572402 ps
CPU time 56.64 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:10:50 PM PDT 24
Peak memory 200240 kb
Host smart-2373277e-8379-467f-8f38-6166762e9b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774656126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1774656126
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2171181053
Short name T424
Test name
Test status
Simulation time 13839917255 ps
CPU time 344.64 seconds
Started Mar 19 03:09:54 PM PDT 24
Finished Mar 19 03:15:39 PM PDT 24
Peak memory 200148 kb
Host smart-c94e78a2-2bb8-44cd-850f-27fa392bc7da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171181053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2171181053
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4106043825
Short name T373
Test name
Test status
Simulation time 3009068819 ps
CPU time 20.02 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:10:13 PM PDT 24
Peak memory 198356 kb
Host smart-986fec4a-9f98-41c7-97c3-7a2dc221f266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106043825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4106043825
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3050833145
Short name T1102
Test name
Test status
Simulation time 29124622398 ps
CPU time 16.68 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:10:06 PM PDT 24
Peak memory 200168 kb
Host smart-29625e04-5e1f-4b8c-a2b8-a0dc118e9c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050833145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3050833145
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.815573285
Short name T295
Test name
Test status
Simulation time 2825664754 ps
CPU time 5.08 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:09:57 PM PDT 24
Peak memory 195968 kb
Host smart-f2440397-7c46-4d68-9697-fef85df4464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815573285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.815573285
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2334937434
Short name T389
Test name
Test status
Simulation time 6323597797 ps
CPU time 15.09 seconds
Started Mar 19 03:09:49 PM PDT 24
Finished Mar 19 03:10:05 PM PDT 24
Peak memory 199876 kb
Host smart-1b82d135-4aac-40bd-a5b6-ab607d0a7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334937434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2334937434
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2314306668
Short name T338
Test name
Test status
Simulation time 1141053355 ps
CPU time 2.17 seconds
Started Mar 19 03:10:00 PM PDT 24
Finished Mar 19 03:10:02 PM PDT 24
Peak memory 198820 kb
Host smart-6ea3e8c0-2a34-463d-9b9a-ab0b7ffc3e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314306668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2314306668
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.653351585
Short name T269
Test name
Test status
Simulation time 101264914801 ps
CPU time 45.33 seconds
Started Mar 19 03:10:03 PM PDT 24
Finished Mar 19 03:10:50 PM PDT 24
Peak memory 200068 kb
Host smart-07050995-fa8b-45d3-a549-bdceaa1b058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653351585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.653351585
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.940054020
Short name T1055
Test name
Test status
Simulation time 161633467746 ps
CPU time 222.89 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 200228 kb
Host smart-ceb6eefa-5af3-4271-81ce-c64b04d92e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940054020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.940054020
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1876682459
Short name T909
Test name
Test status
Simulation time 61043885003 ps
CPU time 97.94 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:14:22 PM PDT 24
Peak memory 200132 kb
Host smart-7ef115ab-a237-4403-bf34-10cce6350c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876682459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1876682459
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2474720207
Short name T644
Test name
Test status
Simulation time 155480415808 ps
CPU time 30.95 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:11 PM PDT 24
Peak memory 200148 kb
Host smart-1118688d-2c9f-436b-b448-1a25f15f8866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474720207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2474720207
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2610067345
Short name T210
Test name
Test status
Simulation time 45802167847 ps
CPU time 27.88 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:08 PM PDT 24
Peak memory 200124 kb
Host smart-e67c21fa-861d-48ac-9195-0879a350c13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610067345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2610067345
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1968691543
Short name T801
Test name
Test status
Simulation time 192759220957 ps
CPU time 89.57 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:14:10 PM PDT 24
Peak memory 200208 kb
Host smart-a390c23a-0b9d-42d4-91b2-8d86edf15338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968691543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1968691543
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4196463144
Short name T198
Test name
Test status
Simulation time 83293723153 ps
CPU time 112.25 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:14:33 PM PDT 24
Peak memory 200132 kb
Host smart-452e8098-6902-413b-83cf-2f938d6800ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196463144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4196463144
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2852954564
Short name T994
Test name
Test status
Simulation time 142532508941 ps
CPU time 122.79 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:14:45 PM PDT 24
Peak memory 200180 kb
Host smart-94de49b9-7879-41bc-bcea-faf1d2084ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852954564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2852954564
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3374155888
Short name T610
Test name
Test status
Simulation time 142312338066 ps
CPU time 60.94 seconds
Started Mar 19 03:12:40 PM PDT 24
Finished Mar 19 03:13:41 PM PDT 24
Peak memory 200164 kb
Host smart-2b20098b-2f3d-4349-abd6-ff01c0ce5a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374155888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3374155888
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.615940663
Short name T30
Test name
Test status
Simulation time 30971464 ps
CPU time 0.52 seconds
Started Mar 19 03:09:52 PM PDT 24
Finished Mar 19 03:09:54 PM PDT 24
Peak memory 195012 kb
Host smart-a796607c-4513-4427-8e70-89627980c881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615940663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.615940663
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1957621669
Short name T403
Test name
Test status
Simulation time 52933003677 ps
CPU time 99.59 seconds
Started Mar 19 03:09:58 PM PDT 24
Finished Mar 19 03:11:38 PM PDT 24
Peak memory 199984 kb
Host smart-c01dc9f7-05d3-4398-9ec9-8d517b836aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957621669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1957621669
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3078942857
Short name T481
Test name
Test status
Simulation time 66671068309 ps
CPU time 52.46 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:10:46 PM PDT 24
Peak memory 200136 kb
Host smart-7c10246f-7902-4f31-b875-7662404c1d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078942857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3078942857
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.3643778864
Short name T560
Test name
Test status
Simulation time 33345219754 ps
CPU time 60.62 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:10:54 PM PDT 24
Peak memory 199872 kb
Host smart-1bd81ec3-b6e2-46dc-8e3f-b7619d325281
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643778864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3643778864
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_loopback.1760211831
Short name T366
Test name
Test status
Simulation time 6172512318 ps
CPU time 17.01 seconds
Started Mar 19 03:10:00 PM PDT 24
Finished Mar 19 03:10:17 PM PDT 24
Peak memory 199964 kb
Host smart-50dcaaaa-5524-4f8f-ac1a-d2b328501119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760211831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1760211831
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1313226021
Short name T422
Test name
Test status
Simulation time 21355929176 ps
CPU time 15.03 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 200184 kb
Host smart-ea399cf2-76dd-4c8b-9162-edc96d31c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313226021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1313226021
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.45090607
Short name T850
Test name
Test status
Simulation time 13103993856 ps
CPU time 412.81 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:16:45 PM PDT 24
Peak memory 200148 kb
Host smart-33786c15-3920-496e-98ae-a3da7a1a3685
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45090607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.45090607
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1147821207
Short name T596
Test name
Test status
Simulation time 7458270061 ps
CPU time 36.42 seconds
Started Mar 19 03:09:53 PM PDT 24
Finished Mar 19 03:10:30 PM PDT 24
Peak memory 198416 kb
Host smart-5d8b7ac9-0f24-4f2f-8e32-65c612413772
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147821207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1147821207
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2711001666
Short name T930
Test name
Test status
Simulation time 33331922837 ps
CPU time 15.8 seconds
Started Mar 19 03:09:59 PM PDT 24
Finished Mar 19 03:10:15 PM PDT 24
Peak memory 199488 kb
Host smart-7d54bb56-fcbc-494d-aa28-fe63f9a39b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711001666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2711001666
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2145263858
Short name T307
Test name
Test status
Simulation time 44475997417 ps
CPU time 35.99 seconds
Started Mar 19 03:09:53 PM PDT 24
Finished Mar 19 03:10:30 PM PDT 24
Peak memory 196004 kb
Host smart-fe808bf7-17be-47a4-b94c-c0b1c54499ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145263858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2145263858
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4034893826
Short name T961
Test name
Test status
Simulation time 310281975 ps
CPU time 1.68 seconds
Started Mar 19 03:09:54 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 198372 kb
Host smart-49b63b93-f04c-4751-97dd-766b43937c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034893826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4034893826
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2096284444
Short name T657
Test name
Test status
Simulation time 149567486739 ps
CPU time 856.5 seconds
Started Mar 19 03:09:58 PM PDT 24
Finished Mar 19 03:24:14 PM PDT 24
Peak memory 200212 kb
Host smart-30991021-ccce-4e18-961f-b504a69910ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096284444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2096284444
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2048121129
Short name T827
Test name
Test status
Simulation time 539678842 ps
CPU time 2.35 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:09:55 PM PDT 24
Peak memory 199860 kb
Host smart-948867fa-e9ee-4c8c-aaf6-3ec19c68089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048121129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2048121129
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2986322473
Short name T420
Test name
Test status
Simulation time 64015202530 ps
CPU time 143.08 seconds
Started Mar 19 03:09:53 PM PDT 24
Finished Mar 19 03:12:17 PM PDT 24
Peak memory 200136 kb
Host smart-f515f683-5c07-46a8-baa3-08038b5a57e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986322473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2986322473
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.234824998
Short name T181
Test name
Test status
Simulation time 47998757160 ps
CPU time 34.63 seconds
Started Mar 19 03:12:48 PM PDT 24
Finished Mar 19 03:13:23 PM PDT 24
Peak memory 200188 kb
Host smart-bd4ba214-2d1f-423e-a5d9-97dcb8eed9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234824998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.234824998
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.238063840
Short name T1031
Test name
Test status
Simulation time 48372443077 ps
CPU time 87.55 seconds
Started Mar 19 03:12:48 PM PDT 24
Finished Mar 19 03:14:16 PM PDT 24
Peak memory 200208 kb
Host smart-74a03cd6-ca69-44af-b9f0-a4e6791c4c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238063840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.238063840
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3527638595
Short name T236
Test name
Test status
Simulation time 254746086283 ps
CPU time 97.45 seconds
Started Mar 19 03:12:53 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 200220 kb
Host smart-a355949b-1610-4c21-b584-84d129abeae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527638595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3527638595
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1439548601
Short name T912
Test name
Test status
Simulation time 147988824383 ps
CPU time 577.08 seconds
Started Mar 19 03:12:49 PM PDT 24
Finished Mar 19 03:22:26 PM PDT 24
Peak memory 200220 kb
Host smart-6ef1bb66-5b33-4760-b96b-0c121059de08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439548601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1439548601
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.18841428
Short name T1011
Test name
Test status
Simulation time 24030190865 ps
CPU time 41.21 seconds
Started Mar 19 03:12:55 PM PDT 24
Finished Mar 19 03:13:36 PM PDT 24
Peak memory 200252 kb
Host smart-dbad32eb-ab43-4a72-9de7-726c26a4e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18841428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.18841428
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4198614743
Short name T303
Test name
Test status
Simulation time 24779522866 ps
CPU time 12.25 seconds
Started Mar 19 03:12:48 PM PDT 24
Finished Mar 19 03:13:01 PM PDT 24
Peak memory 200224 kb
Host smart-8c1d8ba5-8eec-4ff4-a071-bbff2c09a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198614743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4198614743
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.400622948
Short name T882
Test name
Test status
Simulation time 109624766472 ps
CPU time 31.94 seconds
Started Mar 19 03:12:48 PM PDT 24
Finished Mar 19 03:13:21 PM PDT 24
Peak memory 200188 kb
Host smart-2f0dbebf-c5ee-4d2a-905b-d380ce53d929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400622948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.400622948
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1322329347
Short name T534
Test name
Test status
Simulation time 22952580 ps
CPU time 0.57 seconds
Started Mar 19 03:10:08 PM PDT 24
Finished Mar 19 03:10:09 PM PDT 24
Peak memory 195692 kb
Host smart-69b13f91-138d-428e-81e7-db084bc3e7f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322329347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1322329347
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1805107934
Short name T923
Test name
Test status
Simulation time 43513746067 ps
CPU time 40.49 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:46 PM PDT 24
Peak memory 200220 kb
Host smart-237e255a-fda5-4aa2-8496-1c2a04a4faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805107934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1805107934
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1355573264
Short name T696
Test name
Test status
Simulation time 77796818100 ps
CPU time 41.04 seconds
Started Mar 19 03:09:50 PM PDT 24
Finished Mar 19 03:10:33 PM PDT 24
Peak memory 200140 kb
Host smart-3d5579e5-f318-4eef-a7a9-f5b747bff036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355573264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1355573264
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.4026803015
Short name T590
Test name
Test status
Simulation time 37811920389 ps
CPU time 57.44 seconds
Started Mar 19 03:09:54 PM PDT 24
Finished Mar 19 03:10:52 PM PDT 24
Peak memory 200128 kb
Host smart-0c35047c-ec01-4f65-9228-d5a3290bd71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026803015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4026803015
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2946966427
Short name T638
Test name
Test status
Simulation time 22200731732 ps
CPU time 40.06 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:45 PM PDT 24
Peak memory 199940 kb
Host smart-10535e89-fb1f-4f1d-98b9-c4dd943daa41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946966427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2946966427
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2757050472
Short name T1068
Test name
Test status
Simulation time 95019214791 ps
CPU time 915.95 seconds
Started Mar 19 03:10:02 PM PDT 24
Finished Mar 19 03:25:19 PM PDT 24
Peak memory 200212 kb
Host smart-5ffe0f6f-0138-4e88-bd06-ab1a72ec0f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757050472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2757050472
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3332594790
Short name T715
Test name
Test status
Simulation time 57832069 ps
CPU time 0.69 seconds
Started Mar 19 03:10:07 PM PDT 24
Finished Mar 19 03:10:08 PM PDT 24
Peak memory 196272 kb
Host smart-bd08b1c0-7326-4b22-bc76-80168d85e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332594790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3332594790
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2944795801
Short name T651
Test name
Test status
Simulation time 18711284076 ps
CPU time 31.08 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:36 PM PDT 24
Peak memory 198124 kb
Host smart-3cb1b071-871c-4ca4-b72d-1f204d19b07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944795801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2944795801
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3035890340
Short name T537
Test name
Test status
Simulation time 10755056044 ps
CPU time 474.36 seconds
Started Mar 19 03:10:08 PM PDT 24
Finished Mar 19 03:18:03 PM PDT 24
Peak memory 200192 kb
Host smart-3e1b97a8-e98a-4831-b8ce-6eae16f9579f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035890340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3035890340
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2818591094
Short name T698
Test name
Test status
Simulation time 5625697961 ps
CPU time 3.24 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 198264 kb
Host smart-a9c35705-d27d-4f04-bbac-9dd886c15dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818591094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2818591094
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.4157224970
Short name T168
Test name
Test status
Simulation time 167011457618 ps
CPU time 30.04 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:35 PM PDT 24
Peak memory 200184 kb
Host smart-4d227c3b-ef91-426e-8bb8-e647a5019ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157224970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4157224970
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3979139197
Short name T593
Test name
Test status
Simulation time 4402517827 ps
CPU time 1 seconds
Started Mar 19 03:10:09 PM PDT 24
Finished Mar 19 03:10:10 PM PDT 24
Peak memory 196552 kb
Host smart-df499f9d-e0ff-4e56-be2a-467be0619479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979139197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3979139197
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2104045215
Short name T746
Test name
Test status
Simulation time 473707674 ps
CPU time 2.85 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 198340 kb
Host smart-14c9097a-9140-44bc-a1ce-fe365d4d602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104045215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2104045215
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3044825413
Short name T114
Test name
Test status
Simulation time 238599924276 ps
CPU time 111.54 seconds
Started Mar 19 03:10:07 PM PDT 24
Finished Mar 19 03:11:59 PM PDT 24
Peak memory 200160 kb
Host smart-49717161-e900-4240-82e7-b16c61ca1342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044825413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3044825413
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2671923409
Short name T399
Test name
Test status
Simulation time 1003167986 ps
CPU time 3.6 seconds
Started Mar 19 03:10:02 PM PDT 24
Finished Mar 19 03:10:06 PM PDT 24
Peak memory 199416 kb
Host smart-dcee5480-f095-4dd5-a5e9-0f363224e63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671923409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2671923409
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3067584101
Short name T1108
Test name
Test status
Simulation time 113088537987 ps
CPU time 108.25 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:11:40 PM PDT 24
Peak memory 200180 kb
Host smart-fe7d91a9-a213-4b0c-95a9-04f17cbba72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067584101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3067584101
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2424849851
Short name T1076
Test name
Test status
Simulation time 73133051216 ps
CPU time 54.4 seconds
Started Mar 19 03:12:48 PM PDT 24
Finished Mar 19 03:13:42 PM PDT 24
Peak memory 200172 kb
Host smart-a18fe5d5-f80f-4e79-b2ae-42d34cfa90c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424849851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2424849851
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1508352630
Short name T974
Test name
Test status
Simulation time 103375900606 ps
CPU time 71 seconds
Started Mar 19 03:12:50 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 200120 kb
Host smart-7a295d47-4c28-44fe-a179-cd32a4b52bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508352630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1508352630
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3951061343
Short name T753
Test name
Test status
Simulation time 156252936497 ps
CPU time 25.82 seconds
Started Mar 19 03:12:49 PM PDT 24
Finished Mar 19 03:13:15 PM PDT 24
Peak memory 200172 kb
Host smart-f33ed156-ffb5-44cf-b261-091f5ec7a14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951061343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3951061343
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.533382108
Short name T783
Test name
Test status
Simulation time 24452246561 ps
CPU time 38.25 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:13:26 PM PDT 24
Peak memory 199816 kb
Host smart-467cbdcf-a806-4d62-8225-720b9d71cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533382108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.533382108
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1490115326
Short name T449
Test name
Test status
Simulation time 36331362691 ps
CPU time 70.26 seconds
Started Mar 19 03:12:53 PM PDT 24
Finished Mar 19 03:14:04 PM PDT 24
Peak memory 200236 kb
Host smart-fae8f89f-115b-46ba-b493-4c323d63dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490115326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1490115326
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.182397610
Short name T607
Test name
Test status
Simulation time 116470965494 ps
CPU time 27.35 seconds
Started Mar 19 03:12:55 PM PDT 24
Finished Mar 19 03:13:22 PM PDT 24
Peak memory 200216 kb
Host smart-36ee97d7-50a5-4a7a-906b-538bbcbc3b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182397610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.182397610
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2593397029
Short name T408
Test name
Test status
Simulation time 57949706670 ps
CPU time 91.51 seconds
Started Mar 19 03:12:53 PM PDT 24
Finished Mar 19 03:14:25 PM PDT 24
Peak memory 200152 kb
Host smart-ac06b625-bb77-40ee-b406-a07aacd87731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593397029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2593397029
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.763683336
Short name T921
Test name
Test status
Simulation time 44280889 ps
CPU time 0.58 seconds
Started Mar 19 03:10:07 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 195664 kb
Host smart-79e7caae-4eb7-437a-b1f0-1f7981586bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763683336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.763683336
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3752527846
Short name T94
Test name
Test status
Simulation time 36586804712 ps
CPU time 45.88 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:51 PM PDT 24
Peak memory 200216 kb
Host smart-5d0fe8fa-99fd-44e9-b413-fc8095e18ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752527846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3752527846
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1589163309
Short name T308
Test name
Test status
Simulation time 109003702690 ps
CPU time 94.26 seconds
Started Mar 19 03:10:07 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 200156 kb
Host smart-db7d3664-e632-4772-bd42-f93c7975d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589163309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1589163309
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.4285645092
Short name T331
Test name
Test status
Simulation time 193876986539 ps
CPU time 235.52 seconds
Started Mar 19 03:10:01 PM PDT 24
Finished Mar 19 03:13:57 PM PDT 24
Peak memory 200084 kb
Host smart-8aa4a748-7f07-4047-a8e0-3f93d167faff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285645092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.4285645092
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2468731852
Short name T121
Test name
Test status
Simulation time 70473519579 ps
CPU time 117.8 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:12:03 PM PDT 24
Peak memory 200220 kb
Host smart-c49d819c-7333-4a62-b5c0-8e977e528daf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468731852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2468731852
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.57247623
Short name T501
Test name
Test status
Simulation time 75823457086 ps
CPU time 707.99 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:21:54 PM PDT 24
Peak memory 200172 kb
Host smart-b6f1e2e3-5cc2-42aa-9f9b-c75e2739bff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57247623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.57247623
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1287481868
Short name T770
Test name
Test status
Simulation time 5924803057 ps
CPU time 3.94 seconds
Started Mar 19 03:09:59 PM PDT 24
Finished Mar 19 03:10:03 PM PDT 24
Peak memory 200188 kb
Host smart-0e1e108e-3b08-4df5-955c-ec1b1f9a33b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287481868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1287481868
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1927253033
Short name T476
Test name
Test status
Simulation time 143771771702 ps
CPU time 110.61 seconds
Started Mar 19 03:10:00 PM PDT 24
Finished Mar 19 03:11:50 PM PDT 24
Peak memory 200292 kb
Host smart-6857418d-dcc0-43c1-84cd-df92fb220260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927253033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1927253033
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2771635101
Short name T51
Test name
Test status
Simulation time 6754139032 ps
CPU time 295.24 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:15:00 PM PDT 24
Peak memory 200184 kb
Host smart-7c24a95b-e853-4359-b9d1-b09a80a6db7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771635101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2771635101
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3151313869
Short name T983
Test name
Test status
Simulation time 1716566236 ps
CPU time 2.14 seconds
Started Mar 19 03:10:01 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 198752 kb
Host smart-13daa229-2ece-4ba2-aa22-9ec9863b00d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151313869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3151313869
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2890563555
Short name T936
Test name
Test status
Simulation time 189959918863 ps
CPU time 26.72 seconds
Started Mar 19 03:10:03 PM PDT 24
Finished Mar 19 03:10:30 PM PDT 24
Peak memory 199352 kb
Host smart-e7502114-527d-42ee-9fd9-efcc5e1f9880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890563555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2890563555
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.896061812
Short name T263
Test name
Test status
Simulation time 2470665700 ps
CPU time 1.64 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 196012 kb
Host smart-2403cbe9-380b-454e-844a-5d1740760951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896061812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.896061812
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.520770890
Short name T1107
Test name
Test status
Simulation time 250331660 ps
CPU time 1.31 seconds
Started Mar 19 03:10:08 PM PDT 24
Finished Mar 19 03:10:09 PM PDT 24
Peak memory 198384 kb
Host smart-af40aaca-6915-42cc-867c-716524018206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520770890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.520770890
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1115052197
Short name T665
Test name
Test status
Simulation time 123029518998 ps
CPU time 220.88 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:13:45 PM PDT 24
Peak memory 216356 kb
Host smart-baf4754a-c71f-4eed-8662-09281c0445dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115052197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1115052197
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.449915689
Short name T520
Test name
Test status
Simulation time 676846370 ps
CPU time 2.44 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:08 PM PDT 24
Peak memory 200000 kb
Host smart-c7ce27d1-1533-4818-9c6f-969eb2110b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449915689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.449915689
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2080426426
Short name T1060
Test name
Test status
Simulation time 157886700046 ps
CPU time 110.39 seconds
Started Mar 19 03:10:08 PM PDT 24
Finished Mar 19 03:12:00 PM PDT 24
Peak memory 200080 kb
Host smart-369f7ae3-fd9e-4559-8a07-9fe89a5fc056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080426426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2080426426
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3064000209
Short name T578
Test name
Test status
Simulation time 55512556978 ps
CPU time 101.49 seconds
Started Mar 19 03:12:49 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 200168 kb
Host smart-461fb382-9a3d-4b9e-a5bf-5f4fcb84c927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064000209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3064000209
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.4202427198
Short name T942
Test name
Test status
Simulation time 16994259875 ps
CPU time 52.47 seconds
Started Mar 19 03:12:49 PM PDT 24
Finished Mar 19 03:13:41 PM PDT 24
Peak memory 200192 kb
Host smart-33b878af-6ecc-4c9b-a5a4-e3849149aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202427198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.4202427198
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3908591520
Short name T785
Test name
Test status
Simulation time 35338231654 ps
CPU time 15.86 seconds
Started Mar 19 03:12:53 PM PDT 24
Finished Mar 19 03:13:09 PM PDT 24
Peak memory 200216 kb
Host smart-0f66fb28-74e5-467d-9c56-5ffeb2afc163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908591520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3908591520
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3525459380
Short name T627
Test name
Test status
Simulation time 72906639665 ps
CPU time 25.16 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:13:13 PM PDT 24
Peak memory 200172 kb
Host smart-9a306bbe-71fc-4ed4-bc62-687bf59d54c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525459380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3525459380
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3852774410
Short name T176
Test name
Test status
Simulation time 44455248434 ps
CPU time 52.06 seconds
Started Mar 19 03:12:55 PM PDT 24
Finished Mar 19 03:13:48 PM PDT 24
Peak memory 200176 kb
Host smart-895cfbb2-8449-45eb-aaff-fe0f862c4075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852774410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3852774410
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3897239968
Short name T1030
Test name
Test status
Simulation time 92029392521 ps
CPU time 152.83 seconds
Started Mar 19 03:12:51 PM PDT 24
Finished Mar 19 03:15:24 PM PDT 24
Peak memory 199796 kb
Host smart-eece50d2-0ffd-4735-85e3-0e7ebeb85752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897239968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3897239968
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2835604997
Short name T954
Test name
Test status
Simulation time 66134600875 ps
CPU time 110.89 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:14:38 PM PDT 24
Peak memory 200176 kb
Host smart-d628cf1e-72cd-45e6-a833-daeaa4524065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835604997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2835604997
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1838571842
Short name T1035
Test name
Test status
Simulation time 15946059 ps
CPU time 0.54 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 195612 kb
Host smart-7a5c2f23-ac1d-4ff0-be7b-5c10ed517adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838571842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1838571842
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2176555324
Short name T127
Test name
Test status
Simulation time 45549781794 ps
CPU time 76.74 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:11:22 PM PDT 24
Peak memory 200196 kb
Host smart-ec171f28-0333-44c6-bda1-5f9a6c6685e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176555324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2176555324
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2836002497
Short name T588
Test name
Test status
Simulation time 83474644610 ps
CPU time 21.83 seconds
Started Mar 19 03:10:03 PM PDT 24
Finished Mar 19 03:10:26 PM PDT 24
Peak memory 200176 kb
Host smart-549e907c-9b31-4c17-90a0-4d19fc962ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836002497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2836002497
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2065063342
Short name T941
Test name
Test status
Simulation time 37226165101 ps
CPU time 103.8 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:11:49 PM PDT 24
Peak memory 200220 kb
Host smart-f9048b2b-4b92-4f08-8db0-b43754bb1002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065063342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2065063342
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1525109007
Short name T713
Test name
Test status
Simulation time 66089589840 ps
CPU time 50.63 seconds
Started Mar 19 03:10:07 PM PDT 24
Finished Mar 19 03:10:58 PM PDT 24
Peak memory 200088 kb
Host smart-7044d0a1-b042-480b-bb2f-3fc8d5d7b1d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525109007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1525109007
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2487170049
Short name T730
Test name
Test status
Simulation time 120856763074 ps
CPU time 474.46 seconds
Started Mar 19 03:10:01 PM PDT 24
Finished Mar 19 03:17:56 PM PDT 24
Peak memory 200124 kb
Host smart-f23788ac-a221-45a7-9459-416218b950fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487170049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2487170049
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.78143697
Short name T337
Test name
Test status
Simulation time 9151650562 ps
CPU time 15.03 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:19 PM PDT 24
Peak memory 198788 kb
Host smart-a293f76f-9838-47ba-acc5-1da38c88484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78143697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.78143697
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1272335372
Short name T579
Test name
Test status
Simulation time 86504713247 ps
CPU time 163.85 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:12:49 PM PDT 24
Peak memory 200080 kb
Host smart-92bd7762-6e23-467f-8461-57a0d6eca29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272335372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1272335372
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3597111216
Short name T851
Test name
Test status
Simulation time 6740189326 ps
CPU time 94.15 seconds
Started Mar 19 03:09:59 PM PDT 24
Finished Mar 19 03:11:33 PM PDT 24
Peak memory 200204 kb
Host smart-0904b97e-57ef-4392-bafc-1e92b304f243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597111216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3597111216
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3151764624
Short name T438
Test name
Test status
Simulation time 2636275709 ps
CPU time 19.47 seconds
Started Mar 19 03:10:01 PM PDT 24
Finished Mar 19 03:10:21 PM PDT 24
Peak memory 198488 kb
Host smart-6fb34e0d-6229-44b2-a098-12fa992b9f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151764624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3151764624
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2643533709
Short name T1109
Test name
Test status
Simulation time 3481200740 ps
CPU time 1.32 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:06 PM PDT 24
Peak memory 196540 kb
Host smart-714bcbac-f6f2-4de5-9bf5-f11267468c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643533709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2643533709
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1829004901
Short name T506
Test name
Test status
Simulation time 5987984603 ps
CPU time 18.49 seconds
Started Mar 19 03:10:08 PM PDT 24
Finished Mar 19 03:10:28 PM PDT 24
Peak memory 200048 kb
Host smart-cdb8ce8b-7d04-4bc2-b4fb-d5a858359eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829004901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1829004901
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.936795160
Short name T1
Test name
Test status
Simulation time 18159018940 ps
CPU time 113.99 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:12:00 PM PDT 24
Peak memory 200196 kb
Host smart-3dd363cf-65bb-44be-897c-823b2d412d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936795160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.936795160
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.4198810442
Short name T875
Test name
Test status
Simulation time 1275132616 ps
CPU time 2.56 seconds
Started Mar 19 03:10:07 PM PDT 24
Finished Mar 19 03:10:10 PM PDT 24
Peak memory 198556 kb
Host smart-a33d776f-9ad0-413f-8101-f2a96a0126ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198810442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.4198810442
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2904311314
Short name T1009
Test name
Test status
Simulation time 18364169294 ps
CPU time 27.37 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:33 PM PDT 24
Peak memory 200164 kb
Host smart-f68b79e0-b73f-4ba3-80cb-0ebc2e92334c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904311314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2904311314
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.4127360931
Short name T137
Test name
Test status
Simulation time 147560221506 ps
CPU time 34.53 seconds
Started Mar 19 03:12:55 PM PDT 24
Finished Mar 19 03:13:30 PM PDT 24
Peak memory 200176 kb
Host smart-e5b9a0b1-3483-4cd0-ad10-ff6ed77e2abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127360931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4127360931
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.741820044
Short name T752
Test name
Test status
Simulation time 349111187744 ps
CPU time 37.81 seconds
Started Mar 19 03:12:55 PM PDT 24
Finished Mar 19 03:13:33 PM PDT 24
Peak memory 200240 kb
Host smart-0350a75c-91c6-42ff-990e-c4636c2486c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741820044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.741820044
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2941528912
Short name T993
Test name
Test status
Simulation time 110982036607 ps
CPU time 53.43 seconds
Started Mar 19 03:12:49 PM PDT 24
Finished Mar 19 03:13:43 PM PDT 24
Peak memory 200192 kb
Host smart-ef1ae720-bed4-4585-8d74-2513f749dddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941528912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2941528912
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2102455209
Short name T18
Test name
Test status
Simulation time 74764299812 ps
CPU time 13.92 seconds
Started Mar 19 03:12:51 PM PDT 24
Finished Mar 19 03:13:05 PM PDT 24
Peak memory 200148 kb
Host smart-432f4b39-2ea2-4ce4-9590-5208718881d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102455209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2102455209
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1498434545
Short name T182
Test name
Test status
Simulation time 96466756560 ps
CPU time 148.96 seconds
Started Mar 19 03:12:50 PM PDT 24
Finished Mar 19 03:15:20 PM PDT 24
Peak memory 200204 kb
Host smart-696ed3ab-f16c-4909-856d-f1404ee661dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498434545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1498434545
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2348009364
Short name T451
Test name
Test status
Simulation time 241309236774 ps
CPU time 42.78 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:13:30 PM PDT 24
Peak memory 200132 kb
Host smart-3b8b6a45-5e9a-42e6-a7ed-800add68600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348009364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2348009364
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1791880361
Short name T129
Test name
Test status
Simulation time 34677790117 ps
CPU time 17.87 seconds
Started Mar 19 03:12:49 PM PDT 24
Finished Mar 19 03:13:07 PM PDT 24
Peak memory 200184 kb
Host smart-ee0e1ee6-5d0c-4981-913c-32fdecf947f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791880361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1791880361
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2603828965
Short name T286
Test name
Test status
Simulation time 178342502421 ps
CPU time 27.96 seconds
Started Mar 19 03:12:53 PM PDT 24
Finished Mar 19 03:13:22 PM PDT 24
Peak memory 200128 kb
Host smart-c8b1218b-2574-4d07-8c19-640ab78b5c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603828965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2603828965
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1813050144
Short name T755
Test name
Test status
Simulation time 125092191787 ps
CPU time 294.07 seconds
Started Mar 19 03:12:51 PM PDT 24
Finished Mar 19 03:17:45 PM PDT 24
Peak memory 199932 kb
Host smart-baed53c0-4e89-4091-bef2-77164ec94cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813050144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1813050144
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1049957738
Short name T904
Test name
Test status
Simulation time 55661755 ps
CPU time 0.54 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:06 PM PDT 24
Peak memory 195664 kb
Host smart-63ca35ce-5143-46d8-a3e7-21bc3e9bb459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049957738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1049957738
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.411661859
Short name T412
Test name
Test status
Simulation time 53027844232 ps
CPU time 55.95 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:11:00 PM PDT 24
Peak memory 200212 kb
Host smart-f5ae196a-963d-473f-82eb-d2ccbdad2695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411661859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.411661859
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1532043491
Short name T945
Test name
Test status
Simulation time 18356684772 ps
CPU time 32.8 seconds
Started Mar 19 03:10:08 PM PDT 24
Finished Mar 19 03:10:41 PM PDT 24
Peak memory 200216 kb
Host smart-7c477482-3e5d-4b19-965a-e9cdc035e653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532043491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1532043491
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.578842073
Short name T705
Test name
Test status
Simulation time 82939382072 ps
CPU time 178.43 seconds
Started Mar 19 03:10:03 PM PDT 24
Finished Mar 19 03:13:01 PM PDT 24
Peak memory 200168 kb
Host smart-73764863-b4f3-4558-a096-f4676e3828a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578842073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.578842073
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2064128238
Short name T892
Test name
Test status
Simulation time 54578297199 ps
CPU time 22.6 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:27 PM PDT 24
Peak memory 200108 kb
Host smart-418b2f69-989d-4e03-a78a-1c61a50aed1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064128238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2064128238
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2992577719
Short name T538
Test name
Test status
Simulation time 86275863958 ps
CPU time 879.31 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:24:44 PM PDT 24
Peak memory 200156 kb
Host smart-bd791531-8feb-479e-ad31-6688c6691f77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992577719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2992577719
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1666541903
Short name T791
Test name
Test status
Simulation time 3081439010 ps
CPU time 5.24 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:10 PM PDT 24
Peak memory 196280 kb
Host smart-63dc9a88-860b-4ebe-aff9-efcc750b563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666541903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1666541903
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.320610700
Short name T845
Test name
Test status
Simulation time 43122260795 ps
CPU time 81.04 seconds
Started Mar 19 03:10:07 PM PDT 24
Finished Mar 19 03:11:28 PM PDT 24
Peak memory 199720 kb
Host smart-4b9d0f97-5a0f-4648-8279-28d5f717f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320610700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.320610700
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3312222298
Short name T479
Test name
Test status
Simulation time 22750294437 ps
CPU time 180.99 seconds
Started Mar 19 03:10:02 PM PDT 24
Finished Mar 19 03:13:03 PM PDT 24
Peak memory 200128 kb
Host smart-ca8e8f73-be2d-47a2-bcd9-d5ba455d4818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312222298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3312222298
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.943070539
Short name T417
Test name
Test status
Simulation time 1583962464 ps
CPU time 4.66 seconds
Started Mar 19 03:10:02 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 198280 kb
Host smart-c0e124b1-ec1b-4875-a6df-5a25d634ca9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943070539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.943070539
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1172259967
Short name T970
Test name
Test status
Simulation time 45679010316 ps
CPU time 14.09 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:19 PM PDT 24
Peak memory 200200 kb
Host smart-f9fc1297-af3b-4bc1-a042-4b306f045849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172259967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1172259967
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1702959879
Short name T515
Test name
Test status
Simulation time 5729853188 ps
CPU time 2.26 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 196536 kb
Host smart-27382b28-6fef-43f3-93fa-ee793d272598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702959879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1702959879
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1547994327
Short name T380
Test name
Test status
Simulation time 495816165 ps
CPU time 1.91 seconds
Started Mar 19 03:10:03 PM PDT 24
Finished Mar 19 03:10:05 PM PDT 24
Peak memory 198904 kb
Host smart-c865d6f9-964c-4968-8a49-bb721592db83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547994327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1547994327
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3715503034
Short name T634
Test name
Test status
Simulation time 191682801491 ps
CPU time 655.68 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:21:00 PM PDT 24
Peak memory 200208 kb
Host smart-399d7266-39c3-4d83-8684-49caccd6944a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715503034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3715503034
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2237318532
Short name T262
Test name
Test status
Simulation time 461204637 ps
CPU time 1.57 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 197404 kb
Host smart-b4209142-9c13-462f-b984-0884c37d1f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237318532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2237318532
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2408541196
Short name T739
Test name
Test status
Simulation time 97118942954 ps
CPU time 83.98 seconds
Started Mar 19 03:10:06 PM PDT 24
Finished Mar 19 03:11:30 PM PDT 24
Peak memory 200148 kb
Host smart-9687b6fd-f62b-4606-a9d0-8a03e1544e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408541196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2408541196
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2419768532
Short name T859
Test name
Test status
Simulation time 34662094562 ps
CPU time 32.54 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:13:20 PM PDT 24
Peak memory 200148 kb
Host smart-46dcab39-5680-487a-983e-de5785ca6fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419768532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2419768532
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3608563474
Short name T484
Test name
Test status
Simulation time 97175339691 ps
CPU time 82.92 seconds
Started Mar 19 03:12:47 PM PDT 24
Finished Mar 19 03:14:10 PM PDT 24
Peak memory 200112 kb
Host smart-b3241412-9db3-4202-8504-b9242283335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608563474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3608563474
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2875634091
Short name T273
Test name
Test status
Simulation time 38366069556 ps
CPU time 68.33 seconds
Started Mar 19 03:12:53 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 200072 kb
Host smart-48fb9429-72de-4b87-82ec-51b9472dbfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875634091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2875634091
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2779247759
Short name T870
Test name
Test status
Simulation time 41930540275 ps
CPU time 30.01 seconds
Started Mar 19 03:13:00 PM PDT 24
Finished Mar 19 03:13:30 PM PDT 24
Peak memory 200004 kb
Host smart-1a6ed735-8625-4587-ab99-f5ea72e826ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779247759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2779247759
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1017141447
Short name T958
Test name
Test status
Simulation time 23964381786 ps
CPU time 49.07 seconds
Started Mar 19 03:12:59 PM PDT 24
Finished Mar 19 03:13:48 PM PDT 24
Peak memory 200200 kb
Host smart-038c5f78-d6c9-4ba6-95f7-c599bcbb546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017141447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1017141447
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2949191317
Short name T962
Test name
Test status
Simulation time 63318815206 ps
CPU time 56.13 seconds
Started Mar 19 03:12:59 PM PDT 24
Finished Mar 19 03:13:55 PM PDT 24
Peak memory 200184 kb
Host smart-56834eb2-76fd-44e2-b771-29cb2d11058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949191317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2949191317
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3289650788
Short name T649
Test name
Test status
Simulation time 12218407358 ps
CPU time 22.39 seconds
Started Mar 19 03:13:03 PM PDT 24
Finished Mar 19 03:13:25 PM PDT 24
Peak memory 200208 kb
Host smart-136677f7-95f5-47c1-b343-24bd2885d5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289650788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3289650788
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1450674373
Short name T233
Test name
Test status
Simulation time 124839794165 ps
CPU time 48.09 seconds
Started Mar 19 03:12:58 PM PDT 24
Finished Mar 19 03:13:46 PM PDT 24
Peak memory 200212 kb
Host smart-7e3b383a-b522-4a10-ade6-9fc4e203f2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450674373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1450674373
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2168309312
Short name T663
Test name
Test status
Simulation time 20449542026 ps
CPU time 32.88 seconds
Started Mar 19 03:13:03 PM PDT 24
Finished Mar 19 03:13:36 PM PDT 24
Peak memory 198844 kb
Host smart-9e39c5d7-fb54-4083-bf2f-70aa9f16ad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168309312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2168309312
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2153947477
Short name T781
Test name
Test status
Simulation time 40653844 ps
CPU time 0.55 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:10:16 PM PDT 24
Peak memory 195660 kb
Host smart-45017001-e121-490b-be54-757e09fb8387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153947477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2153947477
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2632414865
Short name T700
Test name
Test status
Simulation time 100397289249 ps
CPU time 106.91 seconds
Started Mar 19 03:10:00 PM PDT 24
Finished Mar 19 03:11:47 PM PDT 24
Peak memory 200052 kb
Host smart-d4fa1834-91d0-476a-a81f-ab8636961b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632414865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2632414865
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2099331748
Short name T601
Test name
Test status
Simulation time 22280994926 ps
CPU time 32.91 seconds
Started Mar 19 03:10:05 PM PDT 24
Finished Mar 19 03:10:39 PM PDT 24
Peak memory 200160 kb
Host smart-f9b088fe-4ac7-489d-aea1-2a88980f8581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099331748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2099331748
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.382043953
Short name T1069
Test name
Test status
Simulation time 178890525554 ps
CPU time 18.96 seconds
Started Mar 19 03:10:03 PM PDT 24
Finished Mar 19 03:10:23 PM PDT 24
Peak memory 200148 kb
Host smart-3c2fd70a-dfc7-4fa7-97ce-7f0044bc43f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382043953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.382043953
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.723918072
Short name T822
Test name
Test status
Simulation time 31609375772 ps
CPU time 32.97 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:10:48 PM PDT 24
Peak memory 200184 kb
Host smart-8ba736a6-c779-4992-bf8f-19669dd9dda4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723918072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.723918072
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1124638767
Short name T44
Test name
Test status
Simulation time 56585797713 ps
CPU time 254.07 seconds
Started Mar 19 03:10:12 PM PDT 24
Finished Mar 19 03:14:26 PM PDT 24
Peak memory 200212 kb
Host smart-183dca70-db4c-4459-b41f-5866b4804031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1124638767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1124638767
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.327998403
Short name T811
Test name
Test status
Simulation time 1506521179 ps
CPU time 1.97 seconds
Started Mar 19 03:10:11 PM PDT 24
Finished Mar 19 03:10:13 PM PDT 24
Peak memory 196368 kb
Host smart-873b61d2-daf5-4519-8277-d15ce72539b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327998403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.327998403
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2142294942
Short name T328
Test name
Test status
Simulation time 281070093509 ps
CPU time 51.56 seconds
Started Mar 19 03:10:11 PM PDT 24
Finished Mar 19 03:11:03 PM PDT 24
Peak memory 200456 kb
Host smart-d29d3227-4ba7-4c84-b0f4-e9c73f2fe4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142294942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2142294942
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3204510274
Short name T876
Test name
Test status
Simulation time 8290328342 ps
CPU time 228.06 seconds
Started Mar 19 03:10:16 PM PDT 24
Finished Mar 19 03:14:04 PM PDT 24
Peak memory 200184 kb
Host smart-3c2c9f52-631d-4272-a671-d2e5e3efcfd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204510274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3204510274
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2177952663
Short name T396
Test name
Test status
Simulation time 5610566625 ps
CPU time 4.2 seconds
Started Mar 19 03:10:03 PM PDT 24
Finished Mar 19 03:10:08 PM PDT 24
Peak memory 199300 kb
Host smart-68c8d50b-7d0d-460b-9d28-53fc0eb85c1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177952663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2177952663
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.642494426
Short name T775
Test name
Test status
Simulation time 111733334601 ps
CPU time 40.32 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:10:55 PM PDT 24
Peak memory 200076 kb
Host smart-9406e54e-8ba5-440a-b9e2-3eef6ebb283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642494426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.642494426
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.366471091
Short name T810
Test name
Test status
Simulation time 41603864372 ps
CPU time 30.62 seconds
Started Mar 19 03:10:11 PM PDT 24
Finished Mar 19 03:10:42 PM PDT 24
Peak memory 196272 kb
Host smart-685ce971-921b-4a00-a57a-fedf58f79e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366471091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.366471091
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2641021398
Short name T381
Test name
Test status
Simulation time 106460756 ps
CPU time 0.96 seconds
Started Mar 19 03:10:06 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 198148 kb
Host smart-926d48fe-280a-4b41-ac06-a80c6ca6ceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641021398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2641021398
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.4086941246
Short name T1039
Test name
Test status
Simulation time 399087742777 ps
CPU time 1551.78 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:36:06 PM PDT 24
Peak memory 200212 kb
Host smart-bdc56093-c659-4047-b23b-8402d9dc40f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086941246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4086941246
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2415271071
Short name T37
Test name
Test status
Simulation time 22233778502 ps
CPU time 260.39 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:14:34 PM PDT 24
Peak memory 216768 kb
Host smart-0e7f6c47-1f04-44e5-8bb8-de7bb457987d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415271071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2415271071
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2487507339
Short name T370
Test name
Test status
Simulation time 2031438553 ps
CPU time 2.11 seconds
Started Mar 19 03:10:16 PM PDT 24
Finished Mar 19 03:10:18 PM PDT 24
Peak memory 199884 kb
Host smart-e16378d0-0b5a-4bcb-b4a7-9d53984e8cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487507339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2487507339
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4187877195
Short name T267
Test name
Test status
Simulation time 73509469634 ps
CPU time 7.92 seconds
Started Mar 19 03:10:04 PM PDT 24
Finished Mar 19 03:10:12 PM PDT 24
Peak memory 197164 kb
Host smart-aa45e884-2b25-4a23-bbde-c5a75fe7f830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187877195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4187877195
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1673297268
Short name T490
Test name
Test status
Simulation time 11425727062 ps
CPU time 14.67 seconds
Started Mar 19 03:12:59 PM PDT 24
Finished Mar 19 03:13:14 PM PDT 24
Peak memory 199872 kb
Host smart-7d95ed62-f7af-4ad6-b673-bcdac955ea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673297268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1673297268
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.879620742
Short name T225
Test name
Test status
Simulation time 29058466047 ps
CPU time 28.2 seconds
Started Mar 19 03:13:01 PM PDT 24
Finished Mar 19 03:13:29 PM PDT 24
Peak memory 200168 kb
Host smart-9c8ee2f9-b51e-4912-83b2-a76549f9771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879620742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.879620742
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1678492572
Short name T440
Test name
Test status
Simulation time 26559825381 ps
CPU time 22.47 seconds
Started Mar 19 03:13:05 PM PDT 24
Finished Mar 19 03:13:27 PM PDT 24
Peak memory 200248 kb
Host smart-9e3497c8-4807-4b7f-b2ac-0152cabe6dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678492572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1678492572
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.92709597
Short name T237
Test name
Test status
Simulation time 71249759706 ps
CPU time 165.54 seconds
Started Mar 19 03:12:58 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 200212 kb
Host smart-63a71568-cb6c-41c4-bc12-3c98dd172d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92709597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.92709597
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4226794160
Short name T671
Test name
Test status
Simulation time 155095826266 ps
CPU time 78.56 seconds
Started Mar 19 03:12:58 PM PDT 24
Finished Mar 19 03:14:17 PM PDT 24
Peak memory 200144 kb
Host smart-e9d0b18d-7f6c-4d1c-b07a-62b854304639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226794160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4226794160
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2157397800
Short name T184
Test name
Test status
Simulation time 266441327400 ps
CPU time 141.94 seconds
Started Mar 19 03:12:59 PM PDT 24
Finished Mar 19 03:15:21 PM PDT 24
Peak memory 200244 kb
Host smart-d154059b-5984-49d8-b460-00b0afbda4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157397800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2157397800
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1583123941
Short name T1028
Test name
Test status
Simulation time 42067057566 ps
CPU time 48.72 seconds
Started Mar 19 03:12:59 PM PDT 24
Finished Mar 19 03:13:48 PM PDT 24
Peak memory 200148 kb
Host smart-982aa76e-a978-4547-8e0d-ef04107be910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583123941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1583123941
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2529460246
Short name T1111
Test name
Test status
Simulation time 229240867712 ps
CPU time 60.24 seconds
Started Mar 19 03:12:58 PM PDT 24
Finished Mar 19 03:13:59 PM PDT 24
Peak memory 200172 kb
Host smart-9dc3ac02-bc61-4188-b0fb-bda13f471542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529460246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2529460246
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1839914811
Short name T721
Test name
Test status
Simulation time 40206112 ps
CPU time 0.59 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:09:25 PM PDT 24
Peak memory 195660 kb
Host smart-d6ed3734-d4f2-4b25-9172-dabae7c2a77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839914811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1839914811
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2328267134
Short name T727
Test name
Test status
Simulation time 102595838275 ps
CPU time 41.47 seconds
Started Mar 19 03:09:14 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 200204 kb
Host smart-7615e1f2-f917-4e65-ba81-3c709ca82de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328267134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2328267134
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2581903278
Short name T652
Test name
Test status
Simulation time 26325528304 ps
CPU time 46.22 seconds
Started Mar 19 03:09:15 PM PDT 24
Finished Mar 19 03:10:01 PM PDT 24
Peak memory 199648 kb
Host smart-ec7f0d36-6f6e-4bf0-b6a8-d410b4cceade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581903278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2581903278
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3987189451
Short name T687
Test name
Test status
Simulation time 94387923628 ps
CPU time 72.88 seconds
Started Mar 19 03:09:18 PM PDT 24
Finished Mar 19 03:10:32 PM PDT 24
Peak memory 200176 kb
Host smart-b054a243-36f1-419b-b519-c4fbf66c706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987189451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3987189451
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.812115455
Short name T341
Test name
Test status
Simulation time 11242852073 ps
CPU time 6.77 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 199516 kb
Host smart-bafa5233-1559-4e4a-a58b-d04590ce1876
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812115455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.812115455
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3413149133
Short name T914
Test name
Test status
Simulation time 86671773441 ps
CPU time 306.54 seconds
Started Mar 19 03:09:26 PM PDT 24
Finished Mar 19 03:14:32 PM PDT 24
Peak memory 200148 kb
Host smart-59ae325c-f915-4728-9533-1b3726dff803
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413149133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3413149133
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.452015358
Short name T339
Test name
Test status
Simulation time 6381119921 ps
CPU time 5.87 seconds
Started Mar 19 03:09:25 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 199700 kb
Host smart-d97ab8f4-c060-42b2-8cef-5e536be3e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452015358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.452015358
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3483252335
Short name T363
Test name
Test status
Simulation time 6292104689 ps
CPU time 11.46 seconds
Started Mar 19 03:09:23 PM PDT 24
Finished Mar 19 03:09:34 PM PDT 24
Peak memory 196420 kb
Host smart-9f2d2f37-178e-4108-aad4-e3fab93d3b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483252335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3483252335
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.680361277
Short name T978
Test name
Test status
Simulation time 10326092402 ps
CPU time 599.75 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:19:30 PM PDT 24
Peak memory 200120 kb
Host smart-d1bdfd56-181e-4728-bb95-9fc87219e4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=680361277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.680361277
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.661212709
Short name T933
Test name
Test status
Simulation time 2566621307 ps
CPU time 4.99 seconds
Started Mar 19 03:09:21 PM PDT 24
Finished Mar 19 03:09:26 PM PDT 24
Peak memory 199092 kb
Host smart-b7d23873-1728-43e0-ab4e-7de902dc4f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661212709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.661212709
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3203526474
Short name T499
Test name
Test status
Simulation time 24556899991 ps
CPU time 48.49 seconds
Started Mar 19 03:09:19 PM PDT 24
Finished Mar 19 03:10:08 PM PDT 24
Peak memory 200220 kb
Host smart-7882528f-c435-4b9d-a538-69698c2f39aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203526474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3203526474
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2985293447
Short name T824
Test name
Test status
Simulation time 38162760432 ps
CPU time 52.13 seconds
Started Mar 19 03:09:11 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 196000 kb
Host smart-2c30b38c-c6d8-4b18-bfbd-556a6df34c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985293447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2985293447
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.2432470990
Short name T678
Test name
Test status
Simulation time 860780266 ps
CPU time 2.1 seconds
Started Mar 19 03:09:21 PM PDT 24
Finished Mar 19 03:09:24 PM PDT 24
Peak memory 198864 kb
Host smart-63771b74-7458-40b5-a1c9-08b65917139d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432470990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2432470990
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3473699821
Short name T863
Test name
Test status
Simulation time 709806218 ps
CPU time 1.98 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:09:26 PM PDT 24
Peak memory 198892 kb
Host smart-18408a28-8bc9-4bc1-9cb3-531d05cc84c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473699821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3473699821
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3715272683
Short name T561
Test name
Test status
Simulation time 56732267416 ps
CPU time 27.51 seconds
Started Mar 19 03:09:20 PM PDT 24
Finished Mar 19 03:09:48 PM PDT 24
Peak memory 200108 kb
Host smart-2a5ca180-aaba-45d4-9220-7e7b46bf7b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715272683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3715272683
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1890868136
Short name T583
Test name
Test status
Simulation time 22331674 ps
CPU time 0.56 seconds
Started Mar 19 03:10:20 PM PDT 24
Finished Mar 19 03:10:21 PM PDT 24
Peak memory 195632 kb
Host smart-0ecbf076-46ee-448d-a12d-ad1aeba3ce51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890868136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1890868136
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1519179362
Short name T977
Test name
Test status
Simulation time 127485239601 ps
CPU time 67.68 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:11:23 PM PDT 24
Peak memory 200184 kb
Host smart-be186e92-beb1-4bc4-bb7e-ac89cd249e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519179362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1519179362
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.154440404
Short name T1070
Test name
Test status
Simulation time 168754851431 ps
CPU time 267.65 seconds
Started Mar 19 03:10:21 PM PDT 24
Finished Mar 19 03:14:49 PM PDT 24
Peak memory 200172 kb
Host smart-149d00f0-e03e-43b0-8773-63404f769a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154440404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.154440404
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3898061922
Short name T172
Test name
Test status
Simulation time 85687054788 ps
CPU time 37.61 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:10:51 PM PDT 24
Peak memory 200184 kb
Host smart-285bb9d5-0ade-4ab3-9b96-d39d7b9f1d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898061922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3898061922
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3936230647
Short name T762
Test name
Test status
Simulation time 16342862407 ps
CPU time 26 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:10:40 PM PDT 24
Peak memory 196892 kb
Host smart-841afeeb-2bb3-4ac9-8a44-096d3da748f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936230647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3936230647
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2230923026
Short name T664
Test name
Test status
Simulation time 83699751246 ps
CPU time 626.25 seconds
Started Mar 19 03:10:12 PM PDT 24
Finished Mar 19 03:20:39 PM PDT 24
Peak memory 200124 kb
Host smart-a528b73d-7f03-4edc-892e-6d85265e87dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230923026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2230923026
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2394559245
Short name T485
Test name
Test status
Simulation time 8587706688 ps
CPU time 5.6 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:10:21 PM PDT 24
Peak memory 198720 kb
Host smart-9903e2d4-87f7-43fd-b885-16caa44bf446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394559245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2394559245
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3485492390
Short name T518
Test name
Test status
Simulation time 81300043919 ps
CPU time 144.67 seconds
Started Mar 19 03:10:16 PM PDT 24
Finished Mar 19 03:12:41 PM PDT 24
Peak memory 200312 kb
Host smart-4eebb045-85fe-4ac2-b804-94adc81ae7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485492390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3485492390
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3595320024
Short name T710
Test name
Test status
Simulation time 19593919274 ps
CPU time 237.62 seconds
Started Mar 19 03:10:16 PM PDT 24
Finished Mar 19 03:14:13 PM PDT 24
Peak memory 200188 kb
Host smart-251f538a-d0a2-4de4-9569-8bab2ea93f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595320024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3595320024
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2434588861
Short name T528
Test name
Test status
Simulation time 5924794307 ps
CPU time 54.6 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:11:10 PM PDT 24
Peak memory 198836 kb
Host smart-580ad55f-19cf-4388-99b8-0f23ecfe241f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434588861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2434588861
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1242413356
Short name T153
Test name
Test status
Simulation time 36064870529 ps
CPU time 15.67 seconds
Started Mar 19 03:10:22 PM PDT 24
Finished Mar 19 03:10:38 PM PDT 24
Peak memory 200144 kb
Host smart-920638d0-ae31-41f5-9309-12c7e2488861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242413356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1242413356
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3550720546
Short name T1024
Test name
Test status
Simulation time 36319097333 ps
CPU time 3.93 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:10:17 PM PDT 24
Peak memory 196288 kb
Host smart-b5566ce0-d298-4266-972e-edcb8ef17f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550720546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3550720546
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2720549017
Short name T299
Test name
Test status
Simulation time 257329186 ps
CPU time 1.25 seconds
Started Mar 19 03:10:17 PM PDT 24
Finished Mar 19 03:10:18 PM PDT 24
Peak memory 198896 kb
Host smart-4e2053ef-fcd8-4a56-843f-2cf0d82ee72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720549017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2720549017
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1999797262
Short name T731
Test name
Test status
Simulation time 2003813036 ps
CPU time 2.92 seconds
Started Mar 19 03:10:10 PM PDT 24
Finished Mar 19 03:10:13 PM PDT 24
Peak memory 198776 kb
Host smart-7d851f50-271d-4365-ae15-fb0250a523c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999797262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1999797262
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3222463371
Short name T823
Test name
Test status
Simulation time 37065550323 ps
CPU time 58.67 seconds
Started Mar 19 03:10:12 PM PDT 24
Finished Mar 19 03:11:10 PM PDT 24
Peak memory 200228 kb
Host smart-60bd35d0-62a1-4517-b9a7-778a2b825e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222463371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3222463371
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1518274383
Short name T166
Test name
Test status
Simulation time 40150589767 ps
CPU time 68.17 seconds
Started Mar 19 03:12:58 PM PDT 24
Finished Mar 19 03:14:06 PM PDT 24
Peak memory 200232 kb
Host smart-437274cf-3f97-4b14-8963-b342f8631f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518274383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1518274383
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1153709508
Short name T924
Test name
Test status
Simulation time 22664772534 ps
CPU time 49.58 seconds
Started Mar 19 03:13:01 PM PDT 24
Finished Mar 19 03:13:50 PM PDT 24
Peak memory 200184 kb
Host smart-8f88fd6a-19cb-4746-a7e9-368fc8be5549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153709508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1153709508
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1946792489
Short name T50
Test name
Test status
Simulation time 64672022943 ps
CPU time 138.84 seconds
Started Mar 19 03:12:58 PM PDT 24
Finished Mar 19 03:15:17 PM PDT 24
Peak memory 200208 kb
Host smart-eacc73bc-0693-455d-9ead-4db05fc592f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946792489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1946792489
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.511552880
Short name T549
Test name
Test status
Simulation time 39372336181 ps
CPU time 79.45 seconds
Started Mar 19 03:13:01 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 200148 kb
Host smart-26855007-1730-4015-94f3-03e5e8f795d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511552880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.511552880
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1993753968
Short name T161
Test name
Test status
Simulation time 28623401951 ps
CPU time 15.25 seconds
Started Mar 19 03:12:59 PM PDT 24
Finished Mar 19 03:13:15 PM PDT 24
Peak memory 200212 kb
Host smart-ea9d6a1c-e4ed-4012-90da-a8ad8e0046d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993753968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1993753968
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.156663400
Short name T935
Test name
Test status
Simulation time 123789433280 ps
CPU time 139.18 seconds
Started Mar 19 03:13:01 PM PDT 24
Finished Mar 19 03:15:21 PM PDT 24
Peak memory 200084 kb
Host smart-f40f6ee4-bde1-446b-baf2-ee405549ba76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156663400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.156663400
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1725528562
Short name T675
Test name
Test status
Simulation time 33628632596 ps
CPU time 28.09 seconds
Started Mar 19 03:12:59 PM PDT 24
Finished Mar 19 03:13:28 PM PDT 24
Peak memory 200184 kb
Host smart-a6820abc-e2eb-4f88-92dd-abf37e69532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725528562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1725528562
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2891873271
Short name T647
Test name
Test status
Simulation time 62835675740 ps
CPU time 23.57 seconds
Started Mar 19 03:13:00 PM PDT 24
Finished Mar 19 03:13:24 PM PDT 24
Peak memory 200060 kb
Host smart-f9593dfd-a485-4338-88e9-746c712227b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891873271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2891873271
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1060424814
Short name T784
Test name
Test status
Simulation time 16960397 ps
CPU time 0.56 seconds
Started Mar 19 03:10:17 PM PDT 24
Finished Mar 19 03:10:17 PM PDT 24
Peak memory 195608 kb
Host smart-636e2bec-e192-4fb2-800a-a8753855e435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060424814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1060424814
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3681644797
Short name T135
Test name
Test status
Simulation time 20534832786 ps
CPU time 16.9 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:10:30 PM PDT 24
Peak memory 199656 kb
Host smart-8bcbc279-a9e2-4bc3-9e08-06d74a94a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681644797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3681644797
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2355388060
Short name T980
Test name
Test status
Simulation time 28738210936 ps
CPU time 42.43 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:10:58 PM PDT 24
Peak memory 200212 kb
Host smart-6d0c2a51-fd87-4bd5-8ed5-02aee747a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355388060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2355388060
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1900921564
Short name T1083
Test name
Test status
Simulation time 42249431437 ps
CPU time 23.82 seconds
Started Mar 19 03:10:17 PM PDT 24
Finished Mar 19 03:10:41 PM PDT 24
Peak memory 200148 kb
Host smart-5f0e01ec-c75b-4a7a-a2fa-5c781a03f000
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900921564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1900921564
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.162553995
Short name T1018
Test name
Test status
Simulation time 118140565015 ps
CPU time 380.79 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:16:36 PM PDT 24
Peak memory 200168 kb
Host smart-e3f81693-cbc6-47bf-a7d8-ebe2e1541d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162553995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.162553995
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4183817074
Short name T572
Test name
Test status
Simulation time 9712490621 ps
CPU time 20.25 seconds
Started Mar 19 03:10:12 PM PDT 24
Finished Mar 19 03:10:32 PM PDT 24
Peak memory 200140 kb
Host smart-3a36e259-67be-4fb2-a325-7caed8b9cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183817074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4183817074
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1193924717
Short name T470
Test name
Test status
Simulation time 14570947340 ps
CPU time 5.27 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:10:19 PM PDT 24
Peak memory 194852 kb
Host smart-cc667c95-8011-46eb-b606-137b11a5d4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193924717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1193924717
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3498365101
Short name T441
Test name
Test status
Simulation time 3973198348 ps
CPU time 12.61 seconds
Started Mar 19 03:10:11 PM PDT 24
Finished Mar 19 03:10:24 PM PDT 24
Peak memory 199084 kb
Host smart-54e2e2cc-79cd-4835-8ad2-6485c313552e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498365101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3498365101
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.971125440
Short name T729
Test name
Test status
Simulation time 131934561553 ps
CPU time 42.39 seconds
Started Mar 19 03:10:16 PM PDT 24
Finished Mar 19 03:10:58 PM PDT 24
Peak memory 199216 kb
Host smart-d42bfec5-0223-447b-b356-4cb1585abfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971125440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.971125440
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3362557364
Short name T735
Test name
Test status
Simulation time 2687721382 ps
CPU time 1.5 seconds
Started Mar 19 03:10:16 PM PDT 24
Finished Mar 19 03:10:17 PM PDT 24
Peak memory 196008 kb
Host smart-64d91786-f50f-49cb-b0be-7de1127c6c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362557364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3362557364
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2978373516
Short name T289
Test name
Test status
Simulation time 904457312 ps
CPU time 2.32 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:10:16 PM PDT 24
Peak memory 200048 kb
Host smart-e2d62cdc-2fb8-4774-9725-116db6972eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978373516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2978373516
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.426373428
Short name T585
Test name
Test status
Simulation time 136307867094 ps
CPU time 238.41 seconds
Started Mar 19 03:10:11 PM PDT 24
Finished Mar 19 03:14:10 PM PDT 24
Peak memory 200200 kb
Host smart-2e33ebb3-e530-461a-94ee-66457ec8915c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426373428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.426373428
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3077668408
Short name T416
Test name
Test status
Simulation time 7539828228 ps
CPU time 7.57 seconds
Started Mar 19 03:10:12 PM PDT 24
Finished Mar 19 03:10:20 PM PDT 24
Peak memory 200136 kb
Host smart-71c57398-5287-45f8-a3fa-b30b57865895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077668408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3077668408
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1308058224
Short name T284
Test name
Test status
Simulation time 90153555340 ps
CPU time 35.94 seconds
Started Mar 19 03:10:11 PM PDT 24
Finished Mar 19 03:10:47 PM PDT 24
Peak memory 200232 kb
Host smart-864f0ec4-bee1-49e3-bdb8-7803ec65e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308058224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1308058224
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.595593297
Short name T982
Test name
Test status
Simulation time 101629798273 ps
CPU time 156.16 seconds
Started Mar 19 03:12:58 PM PDT 24
Finished Mar 19 03:15:35 PM PDT 24
Peak memory 200184 kb
Host smart-ca4d1efb-3bfe-4576-a191-ba6eac5e3c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595593297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.595593297
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2728533453
Short name T143
Test name
Test status
Simulation time 118549453527 ps
CPU time 194.46 seconds
Started Mar 19 03:13:00 PM PDT 24
Finished Mar 19 03:16:15 PM PDT 24
Peak memory 200132 kb
Host smart-98123ddf-4126-4bd7-b689-db7c5a327055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728533453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2728533453
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.364012252
Short name T626
Test name
Test status
Simulation time 45405125718 ps
CPU time 14 seconds
Started Mar 19 03:13:01 PM PDT 24
Finished Mar 19 03:13:15 PM PDT 24
Peak memory 200140 kb
Host smart-4afe40d1-1f80-4ff4-b48d-02f10966400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364012252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.364012252
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.883350203
Short name T646
Test name
Test status
Simulation time 192606012793 ps
CPU time 164.34 seconds
Started Mar 19 03:12:59 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 200204 kb
Host smart-93054be6-e99c-4f51-ae4a-ad5363c08831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883350203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.883350203
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4043187556
Short name T374
Test name
Test status
Simulation time 494537179612 ps
CPU time 78.93 seconds
Started Mar 19 03:13:00 PM PDT 24
Finished Mar 19 03:14:19 PM PDT 24
Peak memory 200180 kb
Host smart-be808baf-ea3f-4f22-a6fb-c34b9e138326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043187556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4043187556
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2225148877
Short name T642
Test name
Test status
Simulation time 49922954836 ps
CPU time 34.08 seconds
Started Mar 19 03:13:12 PM PDT 24
Finished Mar 19 03:13:47 PM PDT 24
Peak memory 200132 kb
Host smart-3f23af0b-6fa5-4c20-bcc2-c5e0f58a7251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225148877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2225148877
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.579859253
Short name T195
Test name
Test status
Simulation time 103886302581 ps
CPU time 163.07 seconds
Started Mar 19 03:13:13 PM PDT 24
Finished Mar 19 03:15:56 PM PDT 24
Peak memory 200132 kb
Host smart-00ed9b95-3cab-4482-b96c-c652b81f0e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579859253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.579859253
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4264046514
Short name T858
Test name
Test status
Simulation time 144193320951 ps
CPU time 45.79 seconds
Started Mar 19 03:13:10 PM PDT 24
Finished Mar 19 03:13:57 PM PDT 24
Peak memory 200172 kb
Host smart-c9166357-52e7-45ca-8922-73a63e401ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264046514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4264046514
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3605329633
Short name T907
Test name
Test status
Simulation time 100594200447 ps
CPU time 163.07 seconds
Started Mar 19 03:13:10 PM PDT 24
Finished Mar 19 03:15:54 PM PDT 24
Peak memory 200144 kb
Host smart-325bfec8-5171-4a28-bbbb-7741963c723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605329633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3605329633
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2369126118
Short name T532
Test name
Test status
Simulation time 50203646 ps
CPU time 0.56 seconds
Started Mar 19 03:10:19 PM PDT 24
Finished Mar 19 03:10:20 PM PDT 24
Peak memory 194560 kb
Host smart-3c5a1dab-8238-44d1-9c89-463c227abfdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369126118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2369126118
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3974600264
Short name T117
Test name
Test status
Simulation time 101240228734 ps
CPU time 41.95 seconds
Started Mar 19 03:10:16 PM PDT 24
Finished Mar 19 03:10:58 PM PDT 24
Peak memory 200192 kb
Host smart-34d23b20-d2c7-46d0-8a2c-f60abd59c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974600264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3974600264
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1818662045
Short name T482
Test name
Test status
Simulation time 97072713572 ps
CPU time 43.3 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:10:56 PM PDT 24
Peak memory 200104 kb
Host smart-be06dfe7-4761-41ff-b62a-1f674ad4ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818662045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1818662045
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2833575237
Short name T191
Test name
Test status
Simulation time 17353235780 ps
CPU time 40.23 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:10:53 PM PDT 24
Peak memory 200128 kb
Host smart-05c6fca4-b770-42c5-bca4-0346269c11d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833575237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2833575237
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1969434278
Short name T637
Test name
Test status
Simulation time 8960812367 ps
CPU time 16.37 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:10:31 PM PDT 24
Peak memory 199532 kb
Host smart-b932f08e-830f-43cd-9e3b-b25f1072a31c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969434278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1969434278
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4015905772
Short name T320
Test name
Test status
Simulation time 116245228561 ps
CPU time 239.58 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:14:14 PM PDT 24
Peak memory 200116 kb
Host smart-c34baed9-1081-4230-9b64-3bc5978e90e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015905772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4015905772
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2809133040
Short name T717
Test name
Test status
Simulation time 11675197671 ps
CPU time 9.85 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:10:24 PM PDT 24
Peak memory 198964 kb
Host smart-6a2528ac-202c-4059-bd8a-98db80260ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809133040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2809133040
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2924371800
Short name T834
Test name
Test status
Simulation time 188952279442 ps
CPU time 118.26 seconds
Started Mar 19 03:10:19 PM PDT 24
Finished Mar 19 03:12:18 PM PDT 24
Peak memory 208052 kb
Host smart-bd89184e-49bb-4257-8951-79bde5ad6c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924371800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2924371800
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1343273009
Short name T569
Test name
Test status
Simulation time 15214885618 ps
CPU time 716.95 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 200248 kb
Host smart-709308c6-353c-4f20-bc4c-ff8348f82379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343273009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1343273009
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1918552411
Short name T90
Test name
Test status
Simulation time 7249584918 ps
CPU time 32.91 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:10:48 PM PDT 24
Peak memory 198784 kb
Host smart-569374c1-eafe-4cd4-9eb3-d5b077a99b1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918552411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1918552411
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1143169764
Short name T636
Test name
Test status
Simulation time 31572555033 ps
CPU time 60.47 seconds
Started Mar 19 03:10:13 PM PDT 24
Finished Mar 19 03:11:13 PM PDT 24
Peak memory 200156 kb
Host smart-30bdc442-e006-4cde-89be-36775849bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143169764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1143169764
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1259492016
Short name T819
Test name
Test status
Simulation time 35357213457 ps
CPU time 30.94 seconds
Started Mar 19 03:10:19 PM PDT 24
Finished Mar 19 03:10:50 PM PDT 24
Peak memory 195964 kb
Host smart-0c33839d-382d-4448-b8c9-455f1d345133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259492016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1259492016
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2168803771
Short name T799
Test name
Test status
Simulation time 290277833 ps
CPU time 1.55 seconds
Started Mar 19 03:10:12 PM PDT 24
Finished Mar 19 03:10:13 PM PDT 24
Peak memory 199848 kb
Host smart-d1c7076f-f30b-4483-ba9b-9116570528d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168803771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2168803771
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2889394065
Short name T433
Test name
Test status
Simulation time 7495769087 ps
CPU time 10.72 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:10:25 PM PDT 24
Peak memory 200168 kb
Host smart-fc9e9e10-52a9-4752-8d1b-e4f8bf91b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889394065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2889394065
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.869290573
Short name T701
Test name
Test status
Simulation time 127530133029 ps
CPU time 117.99 seconds
Started Mar 19 03:10:15 PM PDT 24
Finished Mar 19 03:12:13 PM PDT 24
Peak memory 200212 kb
Host smart-1b05bddd-581a-4e85-8f29-8a892db6d24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869290573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.869290573
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.4114081883
Short name T514
Test name
Test status
Simulation time 19951685112 ps
CPU time 35.2 seconds
Started Mar 19 03:13:11 PM PDT 24
Finished Mar 19 03:13:47 PM PDT 24
Peak memory 200204 kb
Host smart-9f74cf75-cfd8-4a72-9a22-a24b4d462dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114081883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4114081883
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1850301446
Short name T193
Test name
Test status
Simulation time 61777733859 ps
CPU time 60.22 seconds
Started Mar 19 03:13:08 PM PDT 24
Finished Mar 19 03:14:08 PM PDT 24
Peak memory 200208 kb
Host smart-16b82460-a347-456a-b8cc-ca271466544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850301446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1850301446
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3197399684
Short name T629
Test name
Test status
Simulation time 64318268583 ps
CPU time 25.36 seconds
Started Mar 19 03:13:09 PM PDT 24
Finished Mar 19 03:13:35 PM PDT 24
Peak memory 200120 kb
Host smart-91e8f834-0de0-4ee7-b163-3cdb37e14d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197399684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3197399684
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3334197578
Short name T231
Test name
Test status
Simulation time 170831608099 ps
CPU time 61.59 seconds
Started Mar 19 03:13:10 PM PDT 24
Finished Mar 19 03:14:12 PM PDT 24
Peak memory 200240 kb
Host smart-ed9a4a9e-45c5-4974-a704-0ddf5ddad90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334197578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3334197578
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.642513305
Short name T986
Test name
Test status
Simulation time 37361661204 ps
CPU time 72.65 seconds
Started Mar 19 03:13:08 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 200184 kb
Host smart-058bcb66-5a6a-45a1-b046-83ce3132f6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642513305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.642513305
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3899191648
Short name T621
Test name
Test status
Simulation time 100064445605 ps
CPU time 173.05 seconds
Started Mar 19 03:13:08 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 200232 kb
Host smart-7d1ad016-0c48-49c0-a10a-60493fa0bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899191648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3899191648
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.375169855
Short name T1021
Test name
Test status
Simulation time 43709226149 ps
CPU time 19.56 seconds
Started Mar 19 03:13:08 PM PDT 24
Finished Mar 19 03:13:28 PM PDT 24
Peak memory 200136 kb
Host smart-2da048c9-b6dd-42ef-8a9b-7d927408d7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375169855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.375169855
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1881088729
Short name T712
Test name
Test status
Simulation time 173441394922 ps
CPU time 135.6 seconds
Started Mar 19 03:13:12 PM PDT 24
Finished Mar 19 03:15:28 PM PDT 24
Peak memory 200156 kb
Host smart-2013cf91-9c7f-45dc-8634-17f61a535e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881088729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1881088729
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3434415922
Short name T778
Test name
Test status
Simulation time 37395757627 ps
CPU time 73.74 seconds
Started Mar 19 03:13:10 PM PDT 24
Finished Mar 19 03:14:24 PM PDT 24
Peak memory 200208 kb
Host smart-4d4bac46-e507-4631-9ba4-2618546ccad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434415922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3434415922
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2624176156
Short name T356
Test name
Test status
Simulation time 54181498 ps
CPU time 0.56 seconds
Started Mar 19 03:10:22 PM PDT 24
Finished Mar 19 03:10:22 PM PDT 24
Peak memory 195664 kb
Host smart-69b394fe-c442-4652-8c1c-e5f3c1f0f1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624176156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2624176156
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1510474815
Short name T425
Test name
Test status
Simulation time 220294574669 ps
CPU time 29.58 seconds
Started Mar 19 03:10:19 PM PDT 24
Finished Mar 19 03:10:49 PM PDT 24
Peak memory 200128 kb
Host smart-9c45f60a-9bf7-494c-a920-915bf07ab154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510474815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1510474815
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3218848491
Short name T1050
Test name
Test status
Simulation time 16823608915 ps
CPU time 37.15 seconds
Started Mar 19 03:10:12 PM PDT 24
Finished Mar 19 03:10:49 PM PDT 24
Peak memory 200160 kb
Host smart-972980b0-ee55-4439-bfa1-3111ae958e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218848491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3218848491
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4242744844
Short name T1075
Test name
Test status
Simulation time 437105861701 ps
CPU time 40.9 seconds
Started Mar 19 03:10:16 PM PDT 24
Finished Mar 19 03:10:57 PM PDT 24
Peak memory 199476 kb
Host smart-77f5b0ec-2ee4-4f70-8e06-a28888e20f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242744844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4242744844
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3186508900
Short name T871
Test name
Test status
Simulation time 400421268034 ps
CPU time 606.53 seconds
Started Mar 19 03:10:20 PM PDT 24
Finished Mar 19 03:20:27 PM PDT 24
Peak memory 200184 kb
Host smart-1a40c29e-3534-49b4-850e-dd1f2c041cdb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186508900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3186508900
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2302526131
Short name T1025
Test name
Test status
Simulation time 158158000097 ps
CPU time 515.88 seconds
Started Mar 19 03:10:21 PM PDT 24
Finished Mar 19 03:18:57 PM PDT 24
Peak memory 200092 kb
Host smart-a66a8978-7e30-4a84-9939-eb4c48db2432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302526131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2302526131
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.420647754
Short name T1061
Test name
Test status
Simulation time 6938722276 ps
CPU time 12.51 seconds
Started Mar 19 03:10:29 PM PDT 24
Finished Mar 19 03:10:41 PM PDT 24
Peak memory 199224 kb
Host smart-e9d9fbee-32fc-44c0-8f13-ea4446c33f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420647754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.420647754
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2180817806
Short name T436
Test name
Test status
Simulation time 18273233926 ps
CPU time 15.17 seconds
Started Mar 19 03:10:28 PM PDT 24
Finished Mar 19 03:10:43 PM PDT 24
Peak memory 194772 kb
Host smart-0adbe1a6-cb8b-4cdf-b1b0-b697f2e8c6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180817806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2180817806
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1448418668
Short name T97
Test name
Test status
Simulation time 4813673790 ps
CPU time 282.36 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:15:07 PM PDT 24
Peak memory 200188 kb
Host smart-5983c4c7-5b70-4410-a7d4-305286a51e5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448418668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1448418668
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2473580851
Short name T968
Test name
Test status
Simulation time 6417358992 ps
CPU time 18.32 seconds
Started Mar 19 03:10:14 PM PDT 24
Finished Mar 19 03:10:33 PM PDT 24
Peak memory 198524 kb
Host smart-451ea46b-2e58-4af5-8d1f-625de0b27ef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473580851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2473580851
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2069318047
Short name T623
Test name
Test status
Simulation time 39196930545 ps
CPU time 73.74 seconds
Started Mar 19 03:10:23 PM PDT 24
Finished Mar 19 03:11:37 PM PDT 24
Peak memory 200148 kb
Host smart-8b162a61-b245-4f68-bae1-623071669ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069318047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2069318047
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2226425535
Short name T1049
Test name
Test status
Simulation time 3806425626 ps
CPU time 2.26 seconds
Started Mar 19 03:10:23 PM PDT 24
Finished Mar 19 03:10:26 PM PDT 24
Peak memory 196264 kb
Host smart-be9d6ab5-7b65-47b2-9708-ff68496d1db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226425535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2226425535
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.955994395
Short name T1044
Test name
Test status
Simulation time 558011863 ps
CPU time 1.15 seconds
Started Mar 19 03:10:12 PM PDT 24
Finished Mar 19 03:10:13 PM PDT 24
Peak memory 198400 kb
Host smart-1ac41444-a52b-41df-8f9f-803425446e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955994395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.955994395
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.639642889
Short name T112
Test name
Test status
Simulation time 310727580198 ps
CPU time 252.51 seconds
Started Mar 19 03:10:26 PM PDT 24
Finished Mar 19 03:14:39 PM PDT 24
Peak memory 200204 kb
Host smart-165b7161-2d36-4886-a988-d76a50831221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639642889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.639642889
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.420202921
Short name T788
Test name
Test status
Simulation time 6321958414 ps
CPU time 19.53 seconds
Started Mar 19 03:10:23 PM PDT 24
Finished Mar 19 03:10:42 PM PDT 24
Peak memory 199980 kb
Host smart-52af7289-68e7-41ff-8875-dee904f1769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420202921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.420202921
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1883862707
Short name T973
Test name
Test status
Simulation time 64666443388 ps
CPU time 114.07 seconds
Started Mar 19 03:10:20 PM PDT 24
Finished Mar 19 03:12:15 PM PDT 24
Peak memory 200120 kb
Host smart-1ec06e5f-183d-4d22-be22-717dc3864007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883862707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1883862707
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3079510266
Short name T777
Test name
Test status
Simulation time 15756659850 ps
CPU time 38.14 seconds
Started Mar 19 03:13:12 PM PDT 24
Finished Mar 19 03:13:50 PM PDT 24
Peak memory 200196 kb
Host smart-d0c3f7b7-c9ef-4ee6-87f1-2399aadcf975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079510266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3079510266
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2589517412
Short name T245
Test name
Test status
Simulation time 144772117466 ps
CPU time 190.54 seconds
Started Mar 19 03:13:09 PM PDT 24
Finished Mar 19 03:16:20 PM PDT 24
Peak memory 200212 kb
Host smart-ff9d613f-a36d-4da6-b544-b71cf70ac39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589517412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2589517412
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1861729439
Short name T937
Test name
Test status
Simulation time 30288207922 ps
CPU time 50.43 seconds
Started Mar 19 03:13:10 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 200132 kb
Host smart-c7b3d79e-5c0b-434d-8188-15e265fe2ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861729439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1861729439
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.4095750390
Short name T1047
Test name
Test status
Simulation time 102560356523 ps
CPU time 133.73 seconds
Started Mar 19 03:13:07 PM PDT 24
Finished Mar 19 03:15:21 PM PDT 24
Peak memory 200208 kb
Host smart-ad76323e-1cc0-4a47-b63e-8f6bfdb77c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095750390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.4095750390
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1800402088
Short name T469
Test name
Test status
Simulation time 16381909176 ps
CPU time 29.42 seconds
Started Mar 19 03:13:10 PM PDT 24
Finished Mar 19 03:13:40 PM PDT 24
Peak memory 200144 kb
Host smart-94f7f213-3782-46e9-97f1-5ff53ed707af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800402088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1800402088
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.180102246
Short name T895
Test name
Test status
Simulation time 95245966280 ps
CPU time 80.06 seconds
Started Mar 19 03:13:12 PM PDT 24
Finished Mar 19 03:14:33 PM PDT 24
Peak memory 200148 kb
Host smart-cb1bd533-df97-45fe-855f-a4ddeb91f4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180102246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.180102246
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3608694804
Short name T555
Test name
Test status
Simulation time 13730932652 ps
CPU time 22.59 seconds
Started Mar 19 03:13:12 PM PDT 24
Finished Mar 19 03:13:35 PM PDT 24
Peak memory 200208 kb
Host smart-7bc6c808-6361-49bb-8988-26a3fd1b883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608694804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3608694804
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3287508575
Short name T192
Test name
Test status
Simulation time 133508641657 ps
CPU time 233.33 seconds
Started Mar 19 03:13:10 PM PDT 24
Finished Mar 19 03:17:04 PM PDT 24
Peak memory 200208 kb
Host smart-4ac59488-bcc7-47de-84b7-af5283fdfb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287508575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3287508575
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2161779001
Short name T208
Test name
Test status
Simulation time 21556905406 ps
CPU time 40.14 seconds
Started Mar 19 03:13:12 PM PDT 24
Finished Mar 19 03:13:53 PM PDT 24
Peak memory 200224 kb
Host smart-0cfc0182-186a-4cfb-918a-e83e287a3ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161779001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2161779001
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3914430926
Short name T360
Test name
Test status
Simulation time 33692482 ps
CPU time 0.54 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:10:24 PM PDT 24
Peak memory 195140 kb
Host smart-3432b4ec-afbe-4be6-b088-11cf5c9eaa7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914430926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3914430926
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1778657425
Short name T943
Test name
Test status
Simulation time 48655357907 ps
CPU time 71.75 seconds
Started Mar 19 03:10:29 PM PDT 24
Finished Mar 19 03:11:41 PM PDT 24
Peak memory 200136 kb
Host smart-c1bf7b3e-fab4-4eed-8b22-80f06b6c6ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778657425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1778657425
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3520805278
Short name T163
Test name
Test status
Simulation time 71990910142 ps
CPU time 13.55 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:10:38 PM PDT 24
Peak memory 200192 kb
Host smart-26625eb9-4275-4506-b6f7-607d0fc0e759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520805278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3520805278
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2473063907
Short name T1038
Test name
Test status
Simulation time 17612030915 ps
CPU time 14.18 seconds
Started Mar 19 03:10:23 PM PDT 24
Finished Mar 19 03:10:38 PM PDT 24
Peak memory 200068 kb
Host smart-95e895e5-f3dd-4444-947b-eb8537a7e0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473063907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2473063907
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1289415111
Short name T351
Test name
Test status
Simulation time 33391310482 ps
CPU time 55.3 seconds
Started Mar 19 03:10:26 PM PDT 24
Finished Mar 19 03:11:21 PM PDT 24
Peak memory 199248 kb
Host smart-30c4704c-9200-4459-8827-1bbb32aafb5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289415111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1289415111
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.641374391
Short name T1071
Test name
Test status
Simulation time 123000773525 ps
CPU time 755.91 seconds
Started Mar 19 03:10:22 PM PDT 24
Finished Mar 19 03:22:58 PM PDT 24
Peak memory 200176 kb
Host smart-3b6b1ca9-48ca-492b-96fe-a501d2b15005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641374391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.641374391
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.341272236
Short name T1008
Test name
Test status
Simulation time 676933698 ps
CPU time 0.93 seconds
Started Mar 19 03:10:27 PM PDT 24
Finished Mar 19 03:10:28 PM PDT 24
Peak memory 196656 kb
Host smart-a0301ec2-332d-4519-81b2-ff42b7bb35f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341272236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.341272236
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.386842738
Short name T1041
Test name
Test status
Simulation time 192309945971 ps
CPU time 104.81 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:12:10 PM PDT 24
Peak memory 208256 kb
Host smart-142b819b-4b92-455f-b897-8cb5837a60ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386842738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.386842738
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.4137183165
Short name T1051
Test name
Test status
Simulation time 25043380145 ps
CPU time 1310.27 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:32:14 PM PDT 24
Peak memory 200124 kb
Host smart-a9987a95-230e-4905-9430-a503ff6982de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137183165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4137183165
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3238007982
Short name T352
Test name
Test status
Simulation time 6502323762 ps
CPU time 51.04 seconds
Started Mar 19 03:10:22 PM PDT 24
Finished Mar 19 03:11:13 PM PDT 24
Peak memory 199008 kb
Host smart-ebb6c10a-cf8b-47bf-a0c7-9f5823585bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238007982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3238007982
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2907717070
Short name T316
Test name
Test status
Simulation time 113104038970 ps
CPU time 196.58 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:13:40 PM PDT 24
Peak memory 200164 kb
Host smart-21cebaa9-7065-4cc9-962a-b9b567a4f465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907717070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2907717070
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1203248208
Short name T283
Test name
Test status
Simulation time 3296954985 ps
CPU time 2.06 seconds
Started Mar 19 03:10:26 PM PDT 24
Finished Mar 19 03:10:28 PM PDT 24
Peak memory 196256 kb
Host smart-aa243245-83ba-4227-897c-e08c4269778f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203248208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1203248208
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3268652950
Short name T922
Test name
Test status
Simulation time 6311332047 ps
CPU time 9.78 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:10:33 PM PDT 24
Peak memory 200008 kb
Host smart-0e02f2d5-6518-496b-849a-a7d682adb5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268652950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3268652950
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3264224534
Short name T545
Test name
Test status
Simulation time 219348749919 ps
CPU time 1341.25 seconds
Started Mar 19 03:10:22 PM PDT 24
Finished Mar 19 03:32:43 PM PDT 24
Peak memory 200192 kb
Host smart-76a748ae-79f4-4f52-8dd6-6c5cd53039f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264224534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3264224534
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3346491330
Short name T1057
Test name
Test status
Simulation time 1203246505 ps
CPU time 4.16 seconds
Started Mar 19 03:10:23 PM PDT 24
Finished Mar 19 03:10:27 PM PDT 24
Peak memory 199956 kb
Host smart-56c74e07-0150-4300-8fde-6cdc24a01fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346491330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3346491330
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.437391953
Short name T966
Test name
Test status
Simulation time 36821360631 ps
CPU time 60.35 seconds
Started Mar 19 03:10:28 PM PDT 24
Finished Mar 19 03:11:28 PM PDT 24
Peak memory 200160 kb
Host smart-2748bebb-7acf-4dc4-aa45-951700a22dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437391953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.437391953
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1951192365
Short name T543
Test name
Test status
Simulation time 45589245382 ps
CPU time 81.71 seconds
Started Mar 19 03:13:08 PM PDT 24
Finished Mar 19 03:14:31 PM PDT 24
Peak memory 200172 kb
Host smart-591ab3f2-e433-45f7-b52c-9c4e7955ec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951192365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1951192365
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1994071092
Short name T615
Test name
Test status
Simulation time 37213041740 ps
CPU time 18.65 seconds
Started Mar 19 03:13:13 PM PDT 24
Finished Mar 19 03:13:32 PM PDT 24
Peak memory 200144 kb
Host smart-3ec1b760-12d8-4d9a-8362-e84a45277590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994071092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1994071092
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.274184065
Short name T215
Test name
Test status
Simulation time 30406724270 ps
CPU time 47.34 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:14:08 PM PDT 24
Peak memory 200172 kb
Host smart-b8d10d6c-0603-4ecb-b5ca-68d7353036a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274184065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.274184065
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4026804545
Short name T856
Test name
Test status
Simulation time 7856629067 ps
CPU time 12.43 seconds
Started Mar 19 03:13:22 PM PDT 24
Finished Mar 19 03:13:35 PM PDT 24
Peak memory 199144 kb
Host smart-2b3e225b-e0b4-4932-8113-9c4b9c006056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026804545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4026804545
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1799922472
Short name T462
Test name
Test status
Simulation time 43500634469 ps
CPU time 35.88 seconds
Started Mar 19 03:13:25 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 200212 kb
Host smart-30c7cd10-ea93-4f3d-9314-393b2c84b6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799922472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1799922472
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2869543798
Short name T1016
Test name
Test status
Simulation time 299598104494 ps
CPU time 106.29 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:15:06 PM PDT 24
Peak memory 200124 kb
Host smart-96bc08b2-5025-490d-8712-1fd3bb402b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869543798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2869543798
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.965732469
Short name T401
Test name
Test status
Simulation time 131187604749 ps
CPU time 227.64 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:17:08 PM PDT 24
Peak memory 200132 kb
Host smart-ffa56da1-42b7-40ac-8643-4464145528f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965732469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.965732469
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2767513709
Short name T546
Test name
Test status
Simulation time 76659067771 ps
CPU time 8.4 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:13:28 PM PDT 24
Peak memory 200204 kb
Host smart-9016d732-06e9-4a3a-aeef-d9bfba3ccf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767513709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2767513709
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2638964120
Short name T766
Test name
Test status
Simulation time 200447626804 ps
CPU time 62.14 seconds
Started Mar 19 03:13:21 PM PDT 24
Finished Mar 19 03:14:23 PM PDT 24
Peak memory 200076 kb
Host smart-e7e86f87-d22a-4bee-9666-d094c9547074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638964120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2638964120
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2824048919
Short name T244
Test name
Test status
Simulation time 103321064417 ps
CPU time 46.01 seconds
Started Mar 19 03:13:21 PM PDT 24
Finished Mar 19 03:14:07 PM PDT 24
Peak memory 200216 kb
Host smart-bc8ef671-33e8-435d-8169-a1750ccdd629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824048919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2824048919
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2444204266
Short name T976
Test name
Test status
Simulation time 17605462 ps
CPU time 0.54 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:10:26 PM PDT 24
Peak memory 195668 kb
Host smart-85a3b672-ceaf-49bb-b7f1-be5159eeaca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444204266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2444204266
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1837164389
Short name T656
Test name
Test status
Simulation time 129448637517 ps
CPU time 38.04 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:11:03 PM PDT 24
Peak memory 200212 kb
Host smart-ed8b3267-0940-40df-ad6d-4434cfc3fa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837164389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1837164389
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2138430339
Short name T743
Test name
Test status
Simulation time 64778348845 ps
CPU time 30.47 seconds
Started Mar 19 03:10:26 PM PDT 24
Finished Mar 19 03:10:57 PM PDT 24
Peak memory 200068 kb
Host smart-4d6eccfe-af51-46bf-a572-aa7632ea7a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138430339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2138430339
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3491545773
Short name T645
Test name
Test status
Simulation time 103786133613 ps
CPU time 72.38 seconds
Started Mar 19 03:10:27 PM PDT 24
Finished Mar 19 03:11:39 PM PDT 24
Peak memory 200152 kb
Host smart-54f5645c-2835-4f96-9dba-606707de0951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491545773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3491545773
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.4104809800
Short name T690
Test name
Test status
Simulation time 63301437128 ps
CPU time 35.52 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:11:00 PM PDT 24
Peak memory 200224 kb
Host smart-287fe37d-1e82-49e3-86ee-656e082063e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104809800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4104809800
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.284597462
Short name T427
Test name
Test status
Simulation time 76090161699 ps
CPU time 484.31 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:18:29 PM PDT 24
Peak memory 200228 kb
Host smart-ad0d8b24-5cf9-44ea-a89f-5cacadef9561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284597462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.284597462
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2269817434
Short name T455
Test name
Test status
Simulation time 9205065202 ps
CPU time 8.27 seconds
Started Mar 19 03:10:23 PM PDT 24
Finished Mar 19 03:10:31 PM PDT 24
Peak memory 199472 kb
Host smart-423ee854-31ab-4a67-acb0-fbdc41ead095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269817434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2269817434
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.936500699
Short name T803
Test name
Test status
Simulation time 18884260018 ps
CPU time 30.78 seconds
Started Mar 19 03:10:22 PM PDT 24
Finished Mar 19 03:10:53 PM PDT 24
Peak memory 199064 kb
Host smart-4e4fc6a3-78dc-4ba5-8b6c-3a2798ec3168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936500699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.936500699
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3898589703
Short name T1029
Test name
Test status
Simulation time 21833753889 ps
CPU time 1365.02 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:33:11 PM PDT 24
Peak memory 200156 kb
Host smart-b674cb5e-b8a9-488b-81b6-aa448e580a88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898589703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3898589703
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1206680225
Short name T108
Test name
Test status
Simulation time 5536853358 ps
CPU time 12.72 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:10:37 PM PDT 24
Peak memory 198288 kb
Host smart-73e989bd-b92f-477b-a960-d18cca631f8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206680225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1206680225
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1191008748
Short name T841
Test name
Test status
Simulation time 67736621702 ps
CPU time 112.37 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:12:18 PM PDT 24
Peak memory 200224 kb
Host smart-9ee0d62b-88c1-4042-9dda-7ffea406fc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191008748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1191008748
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.205165237
Short name T551
Test name
Test status
Simulation time 3816192746 ps
CPU time 5.74 seconds
Started Mar 19 03:10:23 PM PDT 24
Finished Mar 19 03:10:29 PM PDT 24
Peak memory 196540 kb
Host smart-3a11d178-e1a9-47c8-97b0-a21494dbe2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205165237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.205165237
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1689111199
Short name T862
Test name
Test status
Simulation time 483847997 ps
CPU time 1.15 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:10:25 PM PDT 24
Peak memory 198656 kb
Host smart-740caa03-c097-40ad-8e63-ddf00914ba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689111199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1689111199
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2649214617
Short name T906
Test name
Test status
Simulation time 6676541895 ps
CPU time 13.19 seconds
Started Mar 19 03:10:26 PM PDT 24
Finished Mar 19 03:10:40 PM PDT 24
Peak memory 200084 kb
Host smart-46915b66-7a1c-4d5d-bab4-8785ce183970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649214617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2649214617
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.719667573
Short name T773
Test name
Test status
Simulation time 24930443512 ps
CPU time 53.07 seconds
Started Mar 19 03:10:23 PM PDT 24
Finished Mar 19 03:11:16 PM PDT 24
Peak memory 200124 kb
Host smart-18af198a-7ddd-40ec-98d2-60e269229eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719667573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.719667573
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.108928154
Short name T846
Test name
Test status
Simulation time 121397123791 ps
CPU time 19.4 seconds
Started Mar 19 03:13:22 PM PDT 24
Finished Mar 19 03:13:42 PM PDT 24
Peak memory 200224 kb
Host smart-266fada6-3951-414d-9abd-a2f37a5c084d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108928154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.108928154
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.143080482
Short name T230
Test name
Test status
Simulation time 120588444514 ps
CPU time 109.84 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:15:10 PM PDT 24
Peak memory 200172 kb
Host smart-c86f9b8a-5d82-466c-b342-21337f447737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143080482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.143080482
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1489260531
Short name T706
Test name
Test status
Simulation time 157111521063 ps
CPU time 202.22 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:16:42 PM PDT 24
Peak memory 200224 kb
Host smart-878192c3-7c65-4870-95d7-44292759429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489260531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1489260531
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2717846604
Short name T711
Test name
Test status
Simulation time 171731671137 ps
CPU time 31.22 seconds
Started Mar 19 03:13:22 PM PDT 24
Finished Mar 19 03:13:54 PM PDT 24
Peak memory 200172 kb
Host smart-fc07a657-088a-418a-9927-58a9b42c19bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717846604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2717846604
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1961937652
Short name T218
Test name
Test status
Simulation time 99888239778 ps
CPU time 36.51 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:13:56 PM PDT 24
Peak memory 200060 kb
Host smart-91be872f-7cb3-46fb-b8e0-cb5a16851458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961937652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1961937652
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2956008513
Short name T162
Test name
Test status
Simulation time 39012528092 ps
CPU time 32.45 seconds
Started Mar 19 03:13:22 PM PDT 24
Finished Mar 19 03:13:55 PM PDT 24
Peak memory 200168 kb
Host smart-e51774c9-24d0-4f7d-a707-50a6de89e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956008513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2956008513
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2014287937
Short name T7
Test name
Test status
Simulation time 209848582734 ps
CPU time 107.67 seconds
Started Mar 19 03:13:23 PM PDT 24
Finished Mar 19 03:15:11 PM PDT 24
Peak memory 200212 kb
Host smart-d905ed69-0033-4f1a-8899-5dd568156163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014287937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2014287937
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3040230638
Short name T103
Test name
Test status
Simulation time 85679187800 ps
CPU time 66.3 seconds
Started Mar 19 03:13:20 PM PDT 24
Finished Mar 19 03:14:27 PM PDT 24
Peak memory 200052 kb
Host smart-01c05b24-996b-43ac-951e-6bd7bdba17bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040230638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3040230638
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.360635449
Short name T177
Test name
Test status
Simulation time 70289823136 ps
CPU time 14.08 seconds
Started Mar 19 03:13:22 PM PDT 24
Finished Mar 19 03:13:36 PM PDT 24
Peak memory 200216 kb
Host smart-eae77366-1593-45b5-9cca-76dcb3405e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360635449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.360635449
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2589563898
Short name T843
Test name
Test status
Simulation time 13620584 ps
CPU time 0.55 seconds
Started Mar 19 03:10:40 PM PDT 24
Finished Mar 19 03:10:41 PM PDT 24
Peak memory 195628 kb
Host smart-fcda3612-5dd6-4569-b11a-88eca3638a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589563898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2589563898
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3167810406
Short name T1037
Test name
Test status
Simulation time 92436840163 ps
CPU time 137.91 seconds
Started Mar 19 03:10:26 PM PDT 24
Finished Mar 19 03:12:44 PM PDT 24
Peak memory 200408 kb
Host smart-c31a736a-2248-4188-a6d9-ceafffe46397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167810406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3167810406
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3416365387
Short name T1112
Test name
Test status
Simulation time 8049236500 ps
CPU time 4.74 seconds
Started Mar 19 03:10:22 PM PDT 24
Finished Mar 19 03:10:26 PM PDT 24
Peak memory 199496 kb
Host smart-c238d36b-29c6-41da-ab55-013243327d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416365387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3416365387
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.533921330
Short name T860
Test name
Test status
Simulation time 53191757128 ps
CPU time 77.07 seconds
Started Mar 19 03:10:25 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 200192 kb
Host smart-9953a00a-5897-412d-b088-7a0551dde8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533921330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.533921330
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1582747093
Short name T650
Test name
Test status
Simulation time 50105394942 ps
CPU time 23.37 seconds
Started Mar 19 03:10:33 PM PDT 24
Finished Mar 19 03:10:57 PM PDT 24
Peak memory 199280 kb
Host smart-ff890374-f16d-4969-8e11-b06dee554daf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582747093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1582747093
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1673968975
Short name T372
Test name
Test status
Simulation time 131554317364 ps
CPU time 518.26 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:19:14 PM PDT 24
Peak memory 200120 kb
Host smart-fa21d5fb-f118-4fe4-be8f-835625c6de6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673968975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1673968975
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1361898191
Short name T23
Test name
Test status
Simulation time 9616246589 ps
CPU time 14.72 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:10:49 PM PDT 24
Peak memory 200108 kb
Host smart-dd3f7c84-ef95-4053-91d4-3cfeb1b52e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361898191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1361898191
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.272470831
Short name T881
Test name
Test status
Simulation time 12240781898 ps
CPU time 27.94 seconds
Started Mar 19 03:10:38 PM PDT 24
Finished Mar 19 03:11:06 PM PDT 24
Peak memory 200276 kb
Host smart-7a3596ba-6b7b-44e1-b2e0-87c84fafc31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272470831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.272470831
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1359917441
Short name T737
Test name
Test status
Simulation time 31550359491 ps
CPU time 75.08 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:11:49 PM PDT 24
Peak memory 200188 kb
Host smart-9be53dec-67a0-42b0-aadf-7f54fbd6386b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359917441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1359917441
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4042821854
Short name T844
Test name
Test status
Simulation time 2726979300 ps
CPU time 9.2 seconds
Started Mar 19 03:10:27 PM PDT 24
Finished Mar 19 03:10:36 PM PDT 24
Peak memory 199256 kb
Host smart-45b7417f-bde6-49ec-817c-ca23bfd3a45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042821854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4042821854
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1998601510
Short name T1089
Test name
Test status
Simulation time 43864566812 ps
CPU time 39.17 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:11:13 PM PDT 24
Peak memory 200160 kb
Host smart-ae698d88-6270-4068-a5d6-10f875eea1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998601510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1998601510
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.962010217
Short name T1096
Test name
Test status
Simulation time 5224861322 ps
CPU time 2.76 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:10:36 PM PDT 24
Peak memory 196264 kb
Host smart-f74b7635-22bc-425c-b1b0-12103f0cb2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962010217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.962010217
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3249007212
Short name T910
Test name
Test status
Simulation time 6344432727 ps
CPU time 6.77 seconds
Started Mar 19 03:10:26 PM PDT 24
Finished Mar 19 03:10:33 PM PDT 24
Peak memory 200272 kb
Host smart-aceeff83-1c5c-4a3c-bfd7-e90b900a5d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249007212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3249007212
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3168676022
Short name T577
Test name
Test status
Simulation time 39027137584 ps
CPU time 1355.87 seconds
Started Mar 19 03:10:35 PM PDT 24
Finished Mar 19 03:33:11 PM PDT 24
Peak memory 200192 kb
Host smart-6742c863-8637-4de7-ad22-85164f62b7e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168676022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3168676022
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1117903630
Short name T680
Test name
Test status
Simulation time 449693446 ps
CPU time 1.85 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:10:38 PM PDT 24
Peak memory 198944 kb
Host smart-66c3a7e7-8d8b-45f2-840b-5b6238453ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117903630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1117903630
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1757625454
Short name T984
Test name
Test status
Simulation time 17954890454 ps
CPU time 9 seconds
Started Mar 19 03:10:24 PM PDT 24
Finished Mar 19 03:10:33 PM PDT 24
Peak memory 200052 kb
Host smart-a715c09a-68e3-423b-8ff4-d68f08870727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757625454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1757625454
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2026516509
Short name T1062
Test name
Test status
Simulation time 10948528148 ps
CPU time 24.46 seconds
Started Mar 19 03:13:33 PM PDT 24
Finished Mar 19 03:13:58 PM PDT 24
Peak memory 200128 kb
Host smart-98be8f3a-fb41-4fbd-801b-33e8e031c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026516509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2026516509
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1484110937
Short name T747
Test name
Test status
Simulation time 248966731416 ps
CPU time 102.75 seconds
Started Mar 19 03:13:36 PM PDT 24
Finished Mar 19 03:15:19 PM PDT 24
Peak memory 200220 kb
Host smart-2584c945-c28e-4ae0-b82c-8ed066b94e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484110937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1484110937
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1628330801
Short name T521
Test name
Test status
Simulation time 62026529675 ps
CPU time 19 seconds
Started Mar 19 03:13:33 PM PDT 24
Finished Mar 19 03:13:52 PM PDT 24
Peak memory 200100 kb
Host smart-f08fc83d-ce4d-49c2-a8e7-ba35a95eae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628330801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1628330801
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3928707005
Short name T147
Test name
Test status
Simulation time 17706661760 ps
CPU time 28.68 seconds
Started Mar 19 03:13:32 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 200204 kb
Host smart-26c0d2e1-59a9-48d2-b6df-6559e8cead63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928707005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3928707005
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3963602722
Short name T586
Test name
Test status
Simulation time 80347854658 ps
CPU time 142.68 seconds
Started Mar 19 03:13:35 PM PDT 24
Finished Mar 19 03:15:58 PM PDT 24
Peak memory 199984 kb
Host smart-acfcd517-a720-4ec6-97bf-a9c09b1394b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963602722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3963602722
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3725118124
Short name T186
Test name
Test status
Simulation time 41682395105 ps
CPU time 72.18 seconds
Started Mar 19 03:13:34 PM PDT 24
Finished Mar 19 03:14:47 PM PDT 24
Peak memory 200204 kb
Host smart-80085c5e-0a69-442e-81ce-a9ab46f989d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725118124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3725118124
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1738955545
Short name T159
Test name
Test status
Simulation time 107373369528 ps
CPU time 38.86 seconds
Started Mar 19 03:13:34 PM PDT 24
Finished Mar 19 03:14:12 PM PDT 24
Peak memory 200140 kb
Host smart-30846ff2-3455-4d22-ab9d-42df797d12c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738955545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1738955545
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2430807198
Short name T492
Test name
Test status
Simulation time 29201589417 ps
CPU time 23.83 seconds
Started Mar 19 03:13:35 PM PDT 24
Finished Mar 19 03:13:59 PM PDT 24
Peak memory 200188 kb
Host smart-0b5ae470-8303-43ac-bb92-3f633ff0083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430807198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2430807198
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3001937384
Short name T131
Test name
Test status
Simulation time 10526116003 ps
CPU time 23.16 seconds
Started Mar 19 03:13:33 PM PDT 24
Finished Mar 19 03:13:56 PM PDT 24
Peak memory 200276 kb
Host smart-b33518b3-7e1c-4f0d-bc71-fe47eed6b9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001937384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3001937384
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3938114989
Short name T391
Test name
Test status
Simulation time 81104394369 ps
CPU time 35.43 seconds
Started Mar 19 03:13:33 PM PDT 24
Finished Mar 19 03:14:09 PM PDT 24
Peak memory 200168 kb
Host smart-2f5dbf6b-2621-406e-9ce0-038409c8ab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938114989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3938114989
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2510552365
Short name T1045
Test name
Test status
Simulation time 13113591 ps
CPU time 0.58 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:10:35 PM PDT 24
Peak memory 195664 kb
Host smart-4bbe25fd-b9f1-46bb-adb5-ad8e2931fc25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510552365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2510552365
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.743399086
Short name T257
Test name
Test status
Simulation time 145928105048 ps
CPU time 83.27 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:11:59 PM PDT 24
Peak memory 200164 kb
Host smart-1fba2e50-0ae7-454d-9e4c-abbf4597d3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743399086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.743399086
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1156015162
Short name T8
Test name
Test status
Simulation time 66615211677 ps
CPU time 9.76 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:10:45 PM PDT 24
Peak memory 200084 kb
Host smart-ce3ddb10-6eed-42dc-bcee-dbccf162ec6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156015162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1156015162
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.845362237
Short name T568
Test name
Test status
Simulation time 157077038873 ps
CPU time 651.66 seconds
Started Mar 19 03:10:33 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 200044 kb
Host smart-6014110a-f240-47a6-bbd4-48c42f49f2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845362237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.845362237
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.4283380704
Short name T605
Test name
Test status
Simulation time 20001198142 ps
CPU time 10.4 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:10:46 PM PDT 24
Peak memory 199752 kb
Host smart-4bfbea4c-91ff-4a7e-8e80-bfa7ed798dd5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283380704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4283380704
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.964868777
Short name T631
Test name
Test status
Simulation time 144511810935 ps
CPU time 271.92 seconds
Started Mar 19 03:10:35 PM PDT 24
Finished Mar 19 03:15:07 PM PDT 24
Peak memory 200092 kb
Host smart-fb576de4-a328-48f6-943e-ee34c04df625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964868777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.964868777
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3080783802
Short name T1095
Test name
Test status
Simulation time 10563774229 ps
CPU time 19.44 seconds
Started Mar 19 03:10:35 PM PDT 24
Finished Mar 19 03:10:54 PM PDT 24
Peak memory 199308 kb
Host smart-d909dd60-1113-425d-a1ea-15d1d6a5ed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080783802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3080783802
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.4067306212
Short name T305
Test name
Test status
Simulation time 129699439704 ps
CPU time 48.27 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:11:23 PM PDT 24
Peak memory 199184 kb
Host smart-3e391626-610e-482d-b00e-e395ea5881c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067306212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.4067306212
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2565188059
Short name T353
Test name
Test status
Simulation time 5365143228 ps
CPU time 11.46 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:10:45 PM PDT 24
Peak memory 199368 kb
Host smart-0ddfed15-fec3-4613-9c34-efee9311260a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565188059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2565188059
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.927702274
Short name T527
Test name
Test status
Simulation time 160589296244 ps
CPU time 293.16 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:15:27 PM PDT 24
Peak memory 200208 kb
Host smart-75b4a9d4-b945-4862-8a5d-cd3a731db006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927702274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.927702274
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2003256067
Short name T498
Test name
Test status
Simulation time 4740518190 ps
CPU time 2.42 seconds
Started Mar 19 03:10:35 PM PDT 24
Finished Mar 19 03:10:37 PM PDT 24
Peak memory 196288 kb
Host smart-c1185e6c-efc0-4708-9218-d9ade0568772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003256067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2003256067
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.871701821
Short name T1097
Test name
Test status
Simulation time 722195808 ps
CPU time 2.84 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:10:39 PM PDT 24
Peak memory 200104 kb
Host smart-e8026a70-32b4-4d9c-99c1-f1f681f3c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871701821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.871701821
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3177200932
Short name T300
Test name
Test status
Simulation time 21096911169 ps
CPU time 64.82 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:11:41 PM PDT 24
Peak memory 200144 kb
Host smart-bb830afe-f572-45c2-8ba0-872c17d65763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177200932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3177200932
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.738835958
Short name T622
Test name
Test status
Simulation time 15755488940 ps
CPU time 5.74 seconds
Started Mar 19 03:10:33 PM PDT 24
Finished Mar 19 03:10:38 PM PDT 24
Peak memory 200180 kb
Host smart-e5720724-1b5f-49d8-93d0-6e49de9fa715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738835958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.738835958
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2187725676
Short name T867
Test name
Test status
Simulation time 52860227944 ps
CPU time 11.68 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:10:48 PM PDT 24
Peak memory 198984 kb
Host smart-c805b859-5bcc-4340-9ce4-c5ffdca4d6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187725676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2187725676
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3137204794
Short name T200
Test name
Test status
Simulation time 17554294169 ps
CPU time 39.16 seconds
Started Mar 19 03:13:35 PM PDT 24
Finished Mar 19 03:14:15 PM PDT 24
Peak memory 200224 kb
Host smart-9e830d57-224d-4995-a849-0b430c0fd1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137204794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3137204794
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1770175438
Short name T271
Test name
Test status
Simulation time 130870001720 ps
CPU time 59.58 seconds
Started Mar 19 03:13:35 PM PDT 24
Finished Mar 19 03:14:34 PM PDT 24
Peak memory 200180 kb
Host smart-c2061e7a-4f6c-4b16-b7a7-5192e40152f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770175438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1770175438
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3980168431
Short name T960
Test name
Test status
Simulation time 103572455631 ps
CPU time 163.94 seconds
Started Mar 19 03:13:32 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 200004 kb
Host smart-17d14442-8ab3-4165-a076-f01f7ef03b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980168431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3980168431
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1934297213
Short name T511
Test name
Test status
Simulation time 31212844950 ps
CPU time 48.34 seconds
Started Mar 19 03:13:33 PM PDT 24
Finished Mar 19 03:14:21 PM PDT 24
Peak memory 200192 kb
Host smart-ee2cff7a-6a86-4649-8bc7-067993920514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934297213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1934297213
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1564620227
Short name T604
Test name
Test status
Simulation time 110562360289 ps
CPU time 18.87 seconds
Started Mar 19 03:13:34 PM PDT 24
Finished Mar 19 03:13:53 PM PDT 24
Peak memory 200176 kb
Host smart-d44a65d2-3248-40f3-94eb-dc8cd6088b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564620227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1564620227
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2150087543
Short name T158
Test name
Test status
Simulation time 91724279204 ps
CPU time 41.84 seconds
Started Mar 19 03:13:33 PM PDT 24
Finished Mar 19 03:14:14 PM PDT 24
Peak memory 200208 kb
Host smart-0f38d96e-c4e4-40ba-b6bb-74058f3140ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150087543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2150087543
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2852048097
Short name T849
Test name
Test status
Simulation time 172904426851 ps
CPU time 143.84 seconds
Started Mar 19 03:13:35 PM PDT 24
Finished Mar 19 03:15:59 PM PDT 24
Peak memory 200196 kb
Host smart-1ba39cb0-9ab9-451a-909b-87b92755d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852048097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2852048097
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1013602061
Short name T763
Test name
Test status
Simulation time 77020767481 ps
CPU time 54.1 seconds
Started Mar 19 03:13:32 PM PDT 24
Finished Mar 19 03:14:26 PM PDT 24
Peak memory 200200 kb
Host smart-cb0c03a2-5eca-4d02-97dc-4a1336e804f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013602061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1013602061
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1412809486
Short name T533
Test name
Test status
Simulation time 12377258 ps
CPU time 0.55 seconds
Started Mar 19 03:10:45 PM PDT 24
Finished Mar 19 03:10:46 PM PDT 24
Peak memory 195016 kb
Host smart-8ec3f173-b1d0-48f5-b66b-dcb5e1ea41d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412809486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1412809486
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2574982212
Short name T167
Test name
Test status
Simulation time 173178070789 ps
CPU time 154.56 seconds
Started Mar 19 03:10:35 PM PDT 24
Finished Mar 19 03:13:09 PM PDT 24
Peak memory 200240 kb
Host smart-694abacd-7005-4b5a-b9c4-4152e05b8d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574982212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2574982212
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4035972955
Short name T759
Test name
Test status
Simulation time 70931548326 ps
CPU time 34.66 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:11:11 PM PDT 24
Peak memory 200204 kb
Host smart-f14139c3-ea90-4df3-9c9f-7ad47245c515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035972955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4035972955
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1518373930
Short name T234
Test name
Test status
Simulation time 37202339189 ps
CPU time 67.39 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:11:44 PM PDT 24
Peak memory 200136 kb
Host smart-0b4390c0-db3a-41ee-a9a7-b9b335162ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518373930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1518373930
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.68838139
Short name T571
Test name
Test status
Simulation time 12766397123 ps
CPU time 11.33 seconds
Started Mar 19 03:10:35 PM PDT 24
Finished Mar 19 03:10:47 PM PDT 24
Peak memory 199516 kb
Host smart-b402b6c7-a6a9-42a1-aa75-a3c0a4a48e94
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68838139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.68838139
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3949111095
Short name T1081
Test name
Test status
Simulation time 69728936272 ps
CPU time 335.31 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:16:21 PM PDT 24
Peak memory 200124 kb
Host smart-abbb5272-b714-4bba-a123-ed268d12bc38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949111095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3949111095
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3986561883
Short name T744
Test name
Test status
Simulation time 2402395472 ps
CPU time 2.25 seconds
Started Mar 19 03:10:48 PM PDT 24
Finished Mar 19 03:10:50 PM PDT 24
Peak memory 198856 kb
Host smart-5c6d2c88-db74-4acc-91e9-bf5eff5dbe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986561883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3986561883
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.634451614
Short name T358
Test name
Test status
Simulation time 36905068257 ps
CPU time 52.17 seconds
Started Mar 19 03:10:34 PM PDT 24
Finished Mar 19 03:11:26 PM PDT 24
Peak memory 200280 kb
Host smart-6c76e161-b341-40bd-a56c-11b9d1c40f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634451614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.634451614
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1903734795
Short name T306
Test name
Test status
Simulation time 12131289546 ps
CPU time 696.72 seconds
Started Mar 19 03:10:48 PM PDT 24
Finished Mar 19 03:22:25 PM PDT 24
Peak memory 200116 kb
Host smart-37238db0-ae44-4d76-8f04-6253a29d56e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903734795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1903734795
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1027511604
Short name T386
Test name
Test status
Simulation time 3592740633 ps
CPU time 7.15 seconds
Started Mar 19 03:10:33 PM PDT 24
Finished Mar 19 03:10:41 PM PDT 24
Peak memory 198492 kb
Host smart-7442f756-f7bb-4a54-8e1a-737ec3cc47d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027511604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1027511604
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2598154872
Short name T41
Test name
Test status
Simulation time 49506388421 ps
CPU time 88.38 seconds
Started Mar 19 03:10:48 PM PDT 24
Finished Mar 19 03:12:16 PM PDT 24
Peak memory 199968 kb
Host smart-dfe711c7-a0ae-49b0-9eda-5c8a7507e063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598154872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2598154872
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1586370624
Short name T317
Test name
Test status
Simulation time 6030753418 ps
CPU time 3.29 seconds
Started Mar 19 03:10:48 PM PDT 24
Finished Mar 19 03:10:51 PM PDT 24
Peak memory 196288 kb
Host smart-938f1f8d-7c0a-4028-9be1-79d5fec3a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586370624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1586370624
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2791627678
Short name T379
Test name
Test status
Simulation time 5567703688 ps
CPU time 8.55 seconds
Started Mar 19 03:10:36 PM PDT 24
Finished Mar 19 03:10:45 PM PDT 24
Peak memory 200076 kb
Host smart-20b6d224-29e4-4c93-bfa7-ad33185ea1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791627678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2791627678
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3404727937
Short name T774
Test name
Test status
Simulation time 287471122645 ps
CPU time 114.74 seconds
Started Mar 19 03:10:44 PM PDT 24
Finished Mar 19 03:12:39 PM PDT 24
Peak memory 200176 kb
Host smart-e58d85df-0763-4b6e-aca9-ec6557d1d9e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404727937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3404727937
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1212822206
Short name T1010
Test name
Test status
Simulation time 58658837884 ps
CPU time 547.12 seconds
Started Mar 19 03:10:48 PM PDT 24
Finished Mar 19 03:19:56 PM PDT 24
Peak memory 212788 kb
Host smart-9d8fc1c4-d680-408f-a657-e227eb2fb16d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212822206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1212822206
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.4249144761
Short name T1084
Test name
Test status
Simulation time 1253340070 ps
CPU time 2.92 seconds
Started Mar 19 03:10:45 PM PDT 24
Finished Mar 19 03:10:48 PM PDT 24
Peak memory 198504 kb
Host smart-6401ed85-8142-4df6-8892-6e2bc9d4083b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249144761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4249144761
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2994385446
Short name T764
Test name
Test status
Simulation time 23153843348 ps
CPU time 36.69 seconds
Started Mar 19 03:10:33 PM PDT 24
Finished Mar 19 03:11:10 PM PDT 24
Peak memory 200076 kb
Host smart-745d0418-8dab-4ecb-8c09-86419ebd97c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994385446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2994385446
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1676500037
Short name T794
Test name
Test status
Simulation time 101833469924 ps
CPU time 120.49 seconds
Started Mar 19 03:13:34 PM PDT 24
Finished Mar 19 03:15:35 PM PDT 24
Peak memory 200188 kb
Host smart-62effe11-95ed-474c-a81d-252761669e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676500037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1676500037
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3476361816
Short name T2
Test name
Test status
Simulation time 14889662696 ps
CPU time 7.91 seconds
Started Mar 19 03:13:36 PM PDT 24
Finished Mar 19 03:13:44 PM PDT 24
Peak memory 199884 kb
Host smart-13ba3727-2241-417d-b188-9ae432815a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476361816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3476361816
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1517222813
Short name T183
Test name
Test status
Simulation time 251771427409 ps
CPU time 89.65 seconds
Started Mar 19 03:13:34 PM PDT 24
Finished Mar 19 03:15:04 PM PDT 24
Peak memory 200208 kb
Host smart-1f791470-eacf-4322-bbb4-b5f5a4c8332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517222813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1517222813
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1125392190
Short name T212
Test name
Test status
Simulation time 38617539873 ps
CPU time 16.74 seconds
Started Mar 19 03:13:33 PM PDT 24
Finished Mar 19 03:13:50 PM PDT 24
Peak memory 200108 kb
Host smart-30effe53-d1ce-4917-a55b-4e20b8dabbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125392190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1125392190
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1157981480
Short name T302
Test name
Test status
Simulation time 395218442921 ps
CPU time 55.74 seconds
Started Mar 19 03:13:50 PM PDT 24
Finished Mar 19 03:14:45 PM PDT 24
Peak memory 198940 kb
Host smart-44eafb90-6ff2-4004-a08d-3c04d23f25b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157981480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1157981480
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.4086150574
Short name T227
Test name
Test status
Simulation time 31420792078 ps
CPU time 45.53 seconds
Started Mar 19 03:13:47 PM PDT 24
Finished Mar 19 03:14:33 PM PDT 24
Peak memory 200236 kb
Host smart-f09069a0-c9d3-48f8-b6ec-070481914a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086150574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.4086150574
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3906417840
Short name T293
Test name
Test status
Simulation time 34738178941 ps
CPU time 33.61 seconds
Started Mar 19 03:13:46 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 200224 kb
Host smart-ca90038d-d1eb-4891-a845-65bb4330e739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906417840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3906417840
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1661354923
Short name T209
Test name
Test status
Simulation time 88505115777 ps
CPU time 282.84 seconds
Started Mar 19 03:13:46 PM PDT 24
Finished Mar 19 03:18:29 PM PDT 24
Peak memory 200212 kb
Host smart-102b7065-00d4-4951-8e93-14673e6696d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661354923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1661354923
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1505094125
Short name T61
Test name
Test status
Simulation time 35799342 ps
CPU time 0.53 seconds
Started Mar 19 03:10:45 PM PDT 24
Finished Mar 19 03:10:46 PM PDT 24
Peak memory 194612 kb
Host smart-f59e9d4f-2dfb-4790-bb01-a687b4ca557d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505094125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1505094125
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2479110351
Short name T702
Test name
Test status
Simulation time 182379953836 ps
CPU time 346.42 seconds
Started Mar 19 03:10:50 PM PDT 24
Finished Mar 19 03:16:37 PM PDT 24
Peak memory 200208 kb
Host smart-acb6e05b-762e-42a7-9f00-049818049a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479110351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2479110351
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3221138308
Short name T48
Test name
Test status
Simulation time 18508895827 ps
CPU time 9.18 seconds
Started Mar 19 03:10:49 PM PDT 24
Finished Mar 19 03:10:58 PM PDT 24
Peak memory 200096 kb
Host smart-0db92807-bfbc-4574-b396-5c1dc83470fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221138308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3221138308
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1538347442
Short name T920
Test name
Test status
Simulation time 7719378569 ps
CPU time 13.03 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:11:00 PM PDT 24
Peak memory 200148 kb
Host smart-557ef417-c029-444a-82a8-f2675140e3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538347442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1538347442
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1793293144
Short name T494
Test name
Test status
Simulation time 14118188776 ps
CPU time 5.51 seconds
Started Mar 19 03:10:45 PM PDT 24
Finished Mar 19 03:10:51 PM PDT 24
Peak memory 199612 kb
Host smart-f14e1dfa-e3fb-49a7-b61c-a62b4f4104e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793293144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1793293144
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2930889969
Short name T632
Test name
Test status
Simulation time 134039381849 ps
CPU time 143.28 seconds
Started Mar 19 03:10:49 PM PDT 24
Finished Mar 19 03:13:14 PM PDT 24
Peak memory 200180 kb
Host smart-dbae0385-74d8-4dd2-b2b0-f104f01a5c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930889969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2930889969
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4243232464
Short name T491
Test name
Test status
Simulation time 1327512738 ps
CPU time 1.84 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:10:49 PM PDT 24
Peak memory 196316 kb
Host smart-5970e8ec-d1d1-498e-8f2d-aa8daee9f1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243232464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4243232464
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2684106633
Short name T400
Test name
Test status
Simulation time 142781475848 ps
CPU time 65.83 seconds
Started Mar 19 03:10:50 PM PDT 24
Finished Mar 19 03:11:57 PM PDT 24
Peak memory 208524 kb
Host smart-5c7cfa94-dcfe-492e-8a18-4d715a6b6a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684106633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2684106633
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2397600746
Short name T434
Test name
Test status
Simulation time 3629909303 ps
CPU time 89.26 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:12:16 PM PDT 24
Peak memory 200232 kb
Host smart-3cacbee3-9f35-4c02-8b5d-4186c27915a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397600746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2397600746
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.806945183
Short name T448
Test name
Test status
Simulation time 3055573359 ps
CPU time 23.98 seconds
Started Mar 19 03:10:45 PM PDT 24
Finished Mar 19 03:11:09 PM PDT 24
Peak memory 198316 kb
Host smart-05c5e997-ca51-44b0-aef8-c8df5b1d028d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806945183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.806945183
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.4278116104
Short name T812
Test name
Test status
Simulation time 220950327081 ps
CPU time 58.94 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:11:46 PM PDT 24
Peak memory 200220 kb
Host smart-e9fad58c-64f9-4ad5-a159-2b5bc5f95abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278116104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4278116104
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2547590512
Short name T828
Test name
Test status
Simulation time 4479957316 ps
CPU time 1.46 seconds
Started Mar 19 03:10:43 PM PDT 24
Finished Mar 19 03:10:44 PM PDT 24
Peak memory 196288 kb
Host smart-7b38b951-057c-4b45-85b4-a26900163e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547590512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2547590512
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1471447027
Short name T738
Test name
Test status
Simulation time 604824508 ps
CPU time 2.56 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:10:49 PM PDT 24
Peak memory 198460 kb
Host smart-7342a31c-4350-4e27-9655-abc308c4d903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471447027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1471447027
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2842083738
Short name T170
Test name
Test status
Simulation time 276782249467 ps
CPU time 132.17 seconds
Started Mar 19 03:10:48 PM PDT 24
Finished Mar 19 03:13:00 PM PDT 24
Peak memory 200216 kb
Host smart-21d4313a-dc7d-4640-b1dc-801750e5687e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842083738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2842083738
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3683731824
Short name T580
Test name
Test status
Simulation time 921399044 ps
CPU time 2.55 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:10:50 PM PDT 24
Peak memory 198744 kb
Host smart-d68e8041-5e65-448c-b9c1-870d939664d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683731824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3683731824
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2924425254
Short name T92
Test name
Test status
Simulation time 10156756519 ps
CPU time 9.37 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:10:56 PM PDT 24
Peak memory 200124 kb
Host smart-735218c9-ace3-443f-8912-99402b7fdf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924425254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2924425254
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.679238540
Short name T219
Test name
Test status
Simulation time 152880811675 ps
CPU time 86.53 seconds
Started Mar 19 03:13:47 PM PDT 24
Finished Mar 19 03:15:14 PM PDT 24
Peak memory 200208 kb
Host smart-4c630806-ee26-4dc6-874c-9974a40576fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679238540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.679238540
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3684225201
Short name T808
Test name
Test status
Simulation time 46400014316 ps
CPU time 31.43 seconds
Started Mar 19 03:13:46 PM PDT 24
Finished Mar 19 03:14:18 PM PDT 24
Peak memory 200004 kb
Host smart-8c50ce62-2058-40d1-9b47-5dcc8a467d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684225201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3684225201
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1672388415
Short name T639
Test name
Test status
Simulation time 197224632855 ps
CPU time 146.85 seconds
Started Mar 19 03:13:46 PM PDT 24
Finished Mar 19 03:16:13 PM PDT 24
Peak memory 200228 kb
Host smart-c5dc4f9b-3bb8-4852-afcc-8faaba9aaa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672388415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1672388415
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1622216535
Short name T855
Test name
Test status
Simulation time 59837900744 ps
CPU time 26.32 seconds
Started Mar 19 03:13:47 PM PDT 24
Finished Mar 19 03:14:14 PM PDT 24
Peak memory 200248 kb
Host smart-44113188-6ae5-4aa4-b565-944d7c1e4472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622216535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1622216535
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3450994695
Short name T780
Test name
Test status
Simulation time 157146544707 ps
CPU time 140.05 seconds
Started Mar 19 03:13:45 PM PDT 24
Finished Mar 19 03:16:06 PM PDT 24
Peak memory 200188 kb
Host smart-673f9cd9-85c7-4ac6-9edd-1fabe7b6eb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450994695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3450994695
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1138988745
Short name T917
Test name
Test status
Simulation time 85232445447 ps
CPU time 43.29 seconds
Started Mar 19 03:13:44 PM PDT 24
Finished Mar 19 03:14:28 PM PDT 24
Peak memory 200152 kb
Host smart-47b475e0-b03a-45ef-839e-e4e7ae1fd148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138988745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1138988745
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3277394728
Short name T288
Test name
Test status
Simulation time 76885668639 ps
CPU time 32.12 seconds
Started Mar 19 03:13:47 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 200252 kb
Host smart-0be2d855-b70b-4b57-aafe-87df5500ddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277394728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3277394728
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.427232963
Short name T238
Test name
Test status
Simulation time 23434566146 ps
CPU time 36.17 seconds
Started Mar 19 03:13:50 PM PDT 24
Finished Mar 19 03:14:26 PM PDT 24
Peak memory 200108 kb
Host smart-699eb978-a7c5-4377-a020-cbf112f3e559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427232963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.427232963
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4047173518
Short name T975
Test name
Test status
Simulation time 37400314480 ps
CPU time 59.16 seconds
Started Mar 19 03:13:48 PM PDT 24
Finished Mar 19 03:14:48 PM PDT 24
Peak memory 200200 kb
Host smart-fad512be-91aa-4025-9765-bb8b98bb7342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047173518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4047173518
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.897801358
Short name T435
Test name
Test status
Simulation time 12286091 ps
CPU time 0.59 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:09:28 PM PDT 24
Peak memory 195656 kb
Host smart-7c23a478-23fb-449d-996a-7863431f5a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897801358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.897801358
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1194679329
Short name T1103
Test name
Test status
Simulation time 47506027782 ps
CPU time 21.65 seconds
Started Mar 19 03:09:29 PM PDT 24
Finished Mar 19 03:09:51 PM PDT 24
Peak memory 199812 kb
Host smart-3a548aff-56bc-4040-b562-817a23fc7e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194679329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1194679329
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.619909814
Short name T453
Test name
Test status
Simulation time 65506993375 ps
CPU time 23.63 seconds
Started Mar 19 03:09:32 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 200100 kb
Host smart-0e9f423c-db10-4edd-9187-9835a269f840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619909814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.619909814
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.120021860
Short name T1027
Test name
Test status
Simulation time 37764265803 ps
CPU time 36.34 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 200216 kb
Host smart-1d584980-5866-4b8b-80fc-f19889d65518
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120021860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.120021860
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.792063245
Short name T1072
Test name
Test status
Simulation time 232653065433 ps
CPU time 333.56 seconds
Started Mar 19 03:09:28 PM PDT 24
Finished Mar 19 03:15:02 PM PDT 24
Peak memory 200180 kb
Host smart-f93ac1be-70c5-4411-94e8-9ff092caadaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792063245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.792063245
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1432962764
Short name T489
Test name
Test status
Simulation time 1684391836 ps
CPU time 3.5 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:09:28 PM PDT 24
Peak memory 198224 kb
Host smart-b9a3ad77-ae63-4859-b7b0-7f0edebe275a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432962764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1432962764
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3226741247
Short name T648
Test name
Test status
Simulation time 266335894422 ps
CPU time 53.14 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:10:23 PM PDT 24
Peak memory 200244 kb
Host smart-bf33fe5e-123b-42b1-bbda-8b1c9b6de7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226741247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3226741247
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2730180211
Short name T91
Test name
Test status
Simulation time 12099512982 ps
CPU time 586.41 seconds
Started Mar 19 03:09:28 PM PDT 24
Finished Mar 19 03:19:15 PM PDT 24
Peak memory 200176 kb
Host smart-e4edb177-66ea-4dd7-85cb-999c87258a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730180211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2730180211
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.891850000
Short name T14
Test name
Test status
Simulation time 6287295157 ps
CPU time 4.43 seconds
Started Mar 19 03:09:25 PM PDT 24
Finished Mar 19 03:09:30 PM PDT 24
Peak memory 198400 kb
Host smart-fdc89ab6-df4a-45f1-9c91-75f0f8da9c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891850000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.891850000
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4199289429
Short name T134
Test name
Test status
Simulation time 19402968278 ps
CPU time 32.86 seconds
Started Mar 19 03:09:28 PM PDT 24
Finished Mar 19 03:10:02 PM PDT 24
Peak memory 200064 kb
Host smart-f2e6cd4f-d357-46fe-92a9-9c435966dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199289429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4199289429
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2388746932
Short name T1058
Test name
Test status
Simulation time 1925308731 ps
CPU time 3.4 seconds
Started Mar 19 03:09:29 PM PDT 24
Finished Mar 19 03:09:33 PM PDT 24
Peak memory 195912 kb
Host smart-cdd8b10c-802c-423d-baf9-57e29af5f88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388746932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2388746932
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2056573120
Short name T33
Test name
Test status
Simulation time 157952184 ps
CPU time 0.76 seconds
Started Mar 19 03:09:31 PM PDT 24
Finished Mar 19 03:09:32 PM PDT 24
Peak memory 218584 kb
Host smart-05f85af1-89c2-425b-ac47-96995cda9c43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056573120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2056573120
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2958828343
Short name T369
Test name
Test status
Simulation time 314606594 ps
CPU time 0.92 seconds
Started Mar 19 03:09:32 PM PDT 24
Finished Mar 19 03:09:33 PM PDT 24
Peak memory 198480 kb
Host smart-59e164c4-0040-4e3e-ae18-a7800ba32ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958828343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2958828343
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1527775752
Short name T1080
Test name
Test status
Simulation time 76828766701 ps
CPU time 212.8 seconds
Started Mar 19 03:09:25 PM PDT 24
Finished Mar 19 03:12:58 PM PDT 24
Peak memory 209536 kb
Host smart-94dd1caf-97bd-4058-88a3-013b06e3c6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527775752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1527775752
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.832630231
Short name T248
Test name
Test status
Simulation time 55648876666 ps
CPU time 769.69 seconds
Started Mar 19 03:09:20 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 216296 kb
Host smart-166570a4-fe19-4224-bc3d-d16133ff3ee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832630231 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.832630231
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3299162838
Short name T754
Test name
Test status
Simulation time 7125503893 ps
CPU time 1.56 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:09:29 PM PDT 24
Peak memory 199104 kb
Host smart-bb3f3d4a-e933-4fca-9b21-b2859beab45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299162838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3299162838
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2321173702
Short name T281
Test name
Test status
Simulation time 44243876037 ps
CPU time 36.57 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 200072 kb
Host smart-1f59ce43-bc8c-47a1-aab0-ecf67f08fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321173702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2321173702
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1278428635
Short name T659
Test name
Test status
Simulation time 12949205 ps
CPU time 0.54 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:10:48 PM PDT 24
Peak memory 195584 kb
Host smart-4de28f2c-1fad-4877-94fd-3d223114034c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278428635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1278428635
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1971462015
Short name T507
Test name
Test status
Simulation time 20411772468 ps
CPU time 28.9 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:11:15 PM PDT 24
Peak memory 200188 kb
Host smart-cc0d787f-9d25-472a-8ff9-a30e7a52bb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971462015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1971462015
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2461612618
Short name T641
Test name
Test status
Simulation time 88411288620 ps
CPU time 86.73 seconds
Started Mar 19 03:10:50 PM PDT 24
Finished Mar 19 03:12:18 PM PDT 24
Peak memory 200180 kb
Host smart-d9df453e-4549-4c24-84f1-ba22808ead03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461612618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2461612618
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1228965957
Short name T1036
Test name
Test status
Simulation time 113457350753 ps
CPU time 99.15 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:12:27 PM PDT 24
Peak memory 200148 kb
Host smart-eecb51a3-1861-4780-a68c-10f79408fc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228965957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1228965957
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1240439931
Short name T22
Test name
Test status
Simulation time 84795694791 ps
CPU time 29.19 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:11:16 PM PDT 24
Peak memory 199556 kb
Host smart-122a91b8-9bfa-4afe-b9e5-fb5aff29ddb9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240439931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1240439931
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1689483199
Short name T1003
Test name
Test status
Simulation time 90372110130 ps
CPU time 380.17 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:17:07 PM PDT 24
Peak memory 199852 kb
Host smart-acdf4865-9697-47e7-a801-8d6822fc482e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689483199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1689483199
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2133840083
Short name T587
Test name
Test status
Simulation time 1087935754 ps
CPU time 2.43 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:10:50 PM PDT 24
Peak memory 196468 kb
Host smart-5bb10929-c8db-4c48-a05e-b00905537172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133840083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2133840083
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.847360092
Short name T1042
Test name
Test status
Simulation time 12786880528 ps
CPU time 10.92 seconds
Started Mar 19 03:10:44 PM PDT 24
Finished Mar 19 03:10:55 PM PDT 24
Peak memory 195196 kb
Host smart-48d60694-cbae-42c6-ab37-9b547e744ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847360092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.847360092
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.4231180091
Short name T898
Test name
Test status
Simulation time 14701769145 ps
CPU time 578.46 seconds
Started Mar 19 03:10:50 PM PDT 24
Finished Mar 19 03:20:29 PM PDT 24
Peak memory 200140 kb
Host smart-35e4b9d1-59f0-400e-8a2a-e1a8493cbc69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231180091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4231180091
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4081815989
Short name T395
Test name
Test status
Simulation time 3709299363 ps
CPU time 27.73 seconds
Started Mar 19 03:10:49 PM PDT 24
Finished Mar 19 03:11:17 PM PDT 24
Peak memory 198532 kb
Host smart-57c5ab4f-ec9f-4dc6-a3d6-a438e802745e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081815989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4081815989
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1732802938
Short name T130
Test name
Test status
Simulation time 165909527735 ps
CPU time 28.82 seconds
Started Mar 19 03:10:50 PM PDT 24
Finished Mar 19 03:11:20 PM PDT 24
Peak memory 200176 kb
Host smart-60794ed8-f60a-4600-b3e2-3b55053b73af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732802938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1732802938
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2159097855
Short name T290
Test name
Test status
Simulation time 40516298697 ps
CPU time 29.37 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:11:15 PM PDT 24
Peak memory 195960 kb
Host smart-29a6a362-f44f-43fc-9e47-bc18c7973971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159097855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2159097855
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1830489804
Short name T809
Test name
Test status
Simulation time 299245132 ps
CPU time 1.41 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:10:47 PM PDT 24
Peak memory 198588 kb
Host smart-78191a71-e4cc-41b5-ad54-e2f60bebe2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830489804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1830489804
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2826769484
Short name T516
Test name
Test status
Simulation time 239302389925 ps
CPU time 452.14 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:18:19 PM PDT 24
Peak memory 200200 kb
Host smart-1b0e32ce-dd3d-4318-a1c8-db87aa02e7cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826769484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2826769484
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1435395059
Short name T4
Test name
Test status
Simulation time 3099742063 ps
CPU time 1.39 seconds
Started Mar 19 03:10:45 PM PDT 24
Finished Mar 19 03:10:47 PM PDT 24
Peak memory 198904 kb
Host smart-24763133-fd6d-488f-9925-aefc9fb8acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435395059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1435395059
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.296007526
Short name T89
Test name
Test status
Simulation time 192334782932 ps
CPU time 73.37 seconds
Started Mar 19 03:10:50 PM PDT 24
Finished Mar 19 03:12:04 PM PDT 24
Peak memory 200124 kb
Host smart-ec9f762f-d065-48bb-963a-07f74870118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296007526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.296007526
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3765113846
Short name T573
Test name
Test status
Simulation time 20645110 ps
CPU time 0.52 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:11:00 PM PDT 24
Peak memory 194604 kb
Host smart-55d54f7f-de06-4537-91de-96abbdbb139a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765113846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3765113846
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.94144469
Short name T525
Test name
Test status
Simulation time 163441530267 ps
CPU time 137.85 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:13:05 PM PDT 24
Peak memory 200160 kb
Host smart-0ec5a56f-e195-4660-a405-19bc38954557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94144469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.94144469
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1311532324
Short name T873
Test name
Test status
Simulation time 159521448567 ps
CPU time 241.63 seconds
Started Mar 19 03:10:45 PM PDT 24
Finished Mar 19 03:14:47 PM PDT 24
Peak memory 200064 kb
Host smart-478b4f59-f968-43f3-b7b9-f40e3400d3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311532324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1311532324
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.267479352
Short name T207
Test name
Test status
Simulation time 38515321018 ps
CPU time 33.38 seconds
Started Mar 19 03:10:48 PM PDT 24
Finished Mar 19 03:11:21 PM PDT 24
Peak memory 200188 kb
Host smart-38cf5ff4-1d83-4acb-a118-b47522a26053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267479352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.267479352
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.407054315
Short name T581
Test name
Test status
Simulation time 191511665546 ps
CPU time 23.69 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:11:10 PM PDT 24
Peak memory 198204 kb
Host smart-30d5eaab-4740-4633-8259-4abf9c4de1fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407054315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.407054315
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.829049689
Short name T947
Test name
Test status
Simulation time 71733401307 ps
CPU time 680.32 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 200092 kb
Host smart-26ec5b1c-1a56-4097-a93b-7157a38671d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829049689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.829049689
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2879992745
Short name T667
Test name
Test status
Simulation time 11433243495 ps
CPU time 21.28 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:11:08 PM PDT 24
Peak memory 200124 kb
Host smart-4724ad9b-1cdd-4a62-bec1-b48207050556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879992745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2879992745
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.776372249
Short name T915
Test name
Test status
Simulation time 63383628723 ps
CPU time 31.16 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:11:18 PM PDT 24
Peak memory 199124 kb
Host smart-be75e628-88ec-4c91-92a7-a6f69fcecc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776372249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.776372249
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1788961467
Short name T981
Test name
Test status
Simulation time 17285271248 ps
CPU time 828.19 seconds
Started Mar 19 03:10:49 PM PDT 24
Finished Mar 19 03:24:37 PM PDT 24
Peak memory 200200 kb
Host smart-e4276114-af3d-4e44-b575-f0113940b4da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788961467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1788961467
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2598265150
Short name T335
Test name
Test status
Simulation time 1708495611 ps
CPU time 2.89 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:10:49 PM PDT 24
Peak memory 198140 kb
Host smart-5777cfaa-707c-4669-bb44-898406c48ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598265150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2598265150
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1802384968
Short name T893
Test name
Test status
Simulation time 11199405046 ps
CPU time 19.9 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:11:06 PM PDT 24
Peak memory 200220 kb
Host smart-a83cad70-52bd-4b58-b5a9-f00d29b7d49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802384968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1802384968
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.170122449
Short name T109
Test name
Test status
Simulation time 2763558671 ps
CPU time 1.39 seconds
Started Mar 19 03:10:47 PM PDT 24
Finished Mar 19 03:10:49 PM PDT 24
Peak memory 195976 kb
Host smart-a897cb81-0879-4a48-aaa8-30d6bad4f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170122449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.170122449
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1480631205
Short name T768
Test name
Test status
Simulation time 250803535 ps
CPU time 1.22 seconds
Started Mar 19 03:10:49 PM PDT 24
Finished Mar 19 03:10:50 PM PDT 24
Peak memory 198256 kb
Host smart-fbe73417-2f96-46da-aefd-b19d0b88a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480631205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1480631205
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2733617752
Short name T697
Test name
Test status
Simulation time 152567624245 ps
CPU time 139.14 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:13:17 PM PDT 24
Peak memory 216676 kb
Host smart-be007e39-9326-4902-88eb-f6310dfcb02d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733617752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2733617752
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.4072448892
Short name T419
Test name
Test status
Simulation time 2106827084 ps
CPU time 1.93 seconds
Started Mar 19 03:10:48 PM PDT 24
Finished Mar 19 03:10:50 PM PDT 24
Peak memory 198388 kb
Host smart-edaf46b8-24da-46c2-b30b-d0ee9a478601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072448892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.4072448892
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3601119079
Short name T1093
Test name
Test status
Simulation time 29319866069 ps
CPU time 35.95 seconds
Started Mar 19 03:10:46 PM PDT 24
Finished Mar 19 03:11:22 PM PDT 24
Peak memory 200188 kb
Host smart-95c7be3d-4978-4a45-b474-7e8799484355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601119079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3601119079
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1544216764
Short name T640
Test name
Test status
Simulation time 43074509 ps
CPU time 0.54 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:10:59 PM PDT 24
Peak memory 195664 kb
Host smart-9f4f6cd2-4fa1-40f1-be29-293f7b7f0b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544216764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1544216764
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3189627389
Short name T405
Test name
Test status
Simulation time 31422039814 ps
CPU time 27.62 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:11:24 PM PDT 24
Peak memory 200160 kb
Host smart-8a593bf7-05a5-40ae-bca1-041087b703e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189627389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3189627389
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2021455850
Short name T139
Test name
Test status
Simulation time 54929225340 ps
CPU time 94.43 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:12:31 PM PDT 24
Peak memory 199804 kb
Host smart-65e9d3a9-8d19-4f26-a220-791975c959f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021455850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2021455850
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1959133400
Short name T464
Test name
Test status
Simulation time 27491379239 ps
CPU time 32.71 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:11:32 PM PDT 24
Peak memory 200148 kb
Host smart-fe21c7c0-0540-480c-8d4d-94bcba3e6970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959133400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1959133400
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1354140247
Short name T291
Test name
Test status
Simulation time 13814525027 ps
CPU time 12.56 seconds
Started Mar 19 03:11:03 PM PDT 24
Finished Mar 19 03:11:16 PM PDT 24
Peak memory 200144 kb
Host smart-1dbcfb5c-92e8-4ce0-9bf6-6ddf8f5725c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354140247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1354140247
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2202887058
Short name T832
Test name
Test status
Simulation time 63704618143 ps
CPU time 157.41 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:13:34 PM PDT 24
Peak memory 200168 kb
Host smart-2bffcbc8-474e-48fc-b11d-56e1f10e0f53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202887058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2202887058
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.38350482
Short name T817
Test name
Test status
Simulation time 8664747183 ps
CPU time 17.28 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:11:15 PM PDT 24
Peak memory 198216 kb
Host smart-af259e13-62a9-4217-bec6-d9cababc1f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38350482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.38350482
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1851092285
Short name T1053
Test name
Test status
Simulation time 178256783869 ps
CPU time 104.44 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:12:42 PM PDT 24
Peak memory 208476 kb
Host smart-a2a8acc9-59e3-408b-be70-37c752653407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851092285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1851092285
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3444973069
Short name T953
Test name
Test status
Simulation time 6569045463 ps
CPU time 164.11 seconds
Started Mar 19 03:10:55 PM PDT 24
Finished Mar 19 03:13:40 PM PDT 24
Peak memory 200200 kb
Host smart-e8e19903-30d6-4b61-b0fc-587f97f1de78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444973069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3444973069
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3150373756
Short name T345
Test name
Test status
Simulation time 3352275375 ps
CPU time 22.99 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:11:21 PM PDT 24
Peak memory 198344 kb
Host smart-493fb77f-8822-4ddf-9ea4-4a24f6ed0bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150373756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3150373756
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.672112608
Short name T157
Test name
Test status
Simulation time 39599185116 ps
CPU time 17.23 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:11:17 PM PDT 24
Peak memory 200176 kb
Host smart-c4cb289a-a776-4626-a29b-8936fbbe80ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672112608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.672112608
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3483531397
Short name T630
Test name
Test status
Simulation time 2539767779 ps
CPU time 4.83 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:11:03 PM PDT 24
Peak memory 196004 kb
Host smart-b6fe6d0e-11c7-4fc7-8106-a04d0cc701dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483531397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3483531397
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.124636697
Short name T771
Test name
Test status
Simulation time 649915554 ps
CPU time 1.78 seconds
Started Mar 19 03:11:03 PM PDT 24
Finished Mar 19 03:11:05 PM PDT 24
Peak memory 200024 kb
Host smart-e1c9886b-b5c7-4a32-92a9-b5158bb34c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124636697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.124636697
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2327337923
Short name T792
Test name
Test status
Simulation time 717028536955 ps
CPU time 197.14 seconds
Started Mar 19 03:11:02 PM PDT 24
Finished Mar 19 03:14:20 PM PDT 24
Peak memory 208000 kb
Host smart-59628710-ff68-40bf-8c6f-c441e34f8792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327337923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2327337923
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3437546782
Short name T35
Test name
Test status
Simulation time 9240278122 ps
CPU time 112.88 seconds
Started Mar 19 03:11:00 PM PDT 24
Finished Mar 19 03:12:54 PM PDT 24
Peak memory 208584 kb
Host smart-b3015909-28c9-45eb-b083-8e8c56804a93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437546782 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3437546782
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1310089709
Short name T368
Test name
Test status
Simulation time 1485981048 ps
CPU time 1.4 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:10:57 PM PDT 24
Peak memory 198160 kb
Host smart-fc5d151b-bda3-4706-9817-9b3cb0b5cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310089709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1310089709
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.607079024
Short name T414
Test name
Test status
Simulation time 15974339902 ps
CPU time 16.24 seconds
Started Mar 19 03:11:04 PM PDT 24
Finished Mar 19 03:11:20 PM PDT 24
Peak memory 200184 kb
Host smart-f757b56f-cae6-4ec3-b028-94a7c0254f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607079024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.607079024
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.4129607381
Short name T719
Test name
Test status
Simulation time 15318187 ps
CPU time 0.54 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:10:59 PM PDT 24
Peak memory 195608 kb
Host smart-166577da-3497-4518-8b9f-6eb61656152d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129607381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.4129607381
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.804871608
Short name T255
Test name
Test status
Simulation time 34560031599 ps
CPU time 49.31 seconds
Started Mar 19 03:11:04 PM PDT 24
Finished Mar 19 03:11:53 PM PDT 24
Peak memory 199760 kb
Host smart-09debba2-a4b4-4c6a-b591-0fb010f81cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804871608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.804871608
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2018003398
Short name T589
Test name
Test status
Simulation time 42435512810 ps
CPU time 32.61 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:11:32 PM PDT 24
Peak memory 200128 kb
Host smart-027a8c62-c05b-484b-9be4-fa471e310024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018003398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2018003398
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.4131025255
Short name T324
Test name
Test status
Simulation time 57200640880 ps
CPU time 43.64 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 200076 kb
Host smart-551804d7-b1d3-4a26-8bce-34d72fd613de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131025255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.4131025255
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.369922004
Short name T287
Test name
Test status
Simulation time 152920532263 ps
CPU time 1398.36 seconds
Started Mar 19 03:11:00 PM PDT 24
Finished Mar 19 03:34:19 PM PDT 24
Peak memory 200204 kb
Host smart-ebceb9ca-9c5d-48c9-8853-eb998fc3b825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369922004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.369922004
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2339762801
Short name T749
Test name
Test status
Simulation time 8596210685 ps
CPU time 5.34 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:11:02 PM PDT 24
Peak memory 198940 kb
Host smart-9deff06a-9612-4b02-bc09-0452cc3375a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339762801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2339762801
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2939009929
Short name T998
Test name
Test status
Simulation time 174695958399 ps
CPU time 41.49 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:11:39 PM PDT 24
Peak memory 200336 kb
Host smart-1e19050f-f645-42e8-920b-7caec09cbc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939009929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2939009929
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.859839636
Short name T315
Test name
Test status
Simulation time 15948220680 ps
CPU time 131.09 seconds
Started Mar 19 03:11:00 PM PDT 24
Finished Mar 19 03:13:12 PM PDT 24
Peak memory 200176 kb
Host smart-bcd4b8e1-528a-4d0d-a4de-fbe132cc310b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859839636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.859839636
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2942837524
Short name T595
Test name
Test status
Simulation time 2417391764 ps
CPU time 14.1 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:11:12 PM PDT 24
Peak memory 198276 kb
Host smart-425ed1ff-d3b0-4e8e-a8d3-d7ae8be6079c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942837524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2942837524
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.650388502
Short name T402
Test name
Test status
Simulation time 30274517248 ps
CPU time 27.5 seconds
Started Mar 19 03:11:00 PM PDT 24
Finished Mar 19 03:11:28 PM PDT 24
Peak memory 200116 kb
Host smart-a781ce48-70ab-485b-8310-b34aebbe836b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650388502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.650388502
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2498126183
Short name T355
Test name
Test status
Simulation time 4822495203 ps
CPU time 7.72 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:11:05 PM PDT 24
Peak memory 196572 kb
Host smart-9df31497-2298-4b2e-89ce-8d9ae6cfc464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498126183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2498126183
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3465391247
Short name T60
Test name
Test status
Simulation time 443850744 ps
CPU time 1.2 seconds
Started Mar 19 03:11:02 PM PDT 24
Finished Mar 19 03:11:04 PM PDT 24
Peak memory 198224 kb
Host smart-7f56a285-4314-4813-8b48-6b767460b8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465391247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3465391247
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3991779204
Short name T681
Test name
Test status
Simulation time 219372334895 ps
CPU time 82.06 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:12:21 PM PDT 24
Peak memory 200216 kb
Host smart-cda604ec-1f91-4bf1-816c-48387182af20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991779204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3991779204
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.18141956
Short name T406
Test name
Test status
Simulation time 6219772988 ps
CPU time 21.1 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:11:20 PM PDT 24
Peak memory 200156 kb
Host smart-061971e0-cda0-4552-b12a-462819a37368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18141956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.18141956
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2394695266
Short name T275
Test name
Test status
Simulation time 62760167969 ps
CPU time 122.95 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:12:59 PM PDT 24
Peak memory 200232 kb
Host smart-148c130e-e370-401a-9b30-ac4e89a6b127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394695266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2394695266
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3999764561
Short name T429
Test name
Test status
Simulation time 110156558 ps
CPU time 0.54 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:11:00 PM PDT 24
Peak memory 195668 kb
Host smart-0589eb0e-b168-412e-877f-097277ebdcd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999764561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3999764561
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1147128583
Short name T889
Test name
Test status
Simulation time 230195823358 ps
CPU time 623.07 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 200128 kb
Host smart-4bd37808-814a-4bbf-bc0b-1da66a095f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147128583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1147128583
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2073533193
Short name T531
Test name
Test status
Simulation time 54770145330 ps
CPU time 98.46 seconds
Started Mar 19 03:11:00 PM PDT 24
Finished Mar 19 03:12:39 PM PDT 24
Peak memory 200140 kb
Host smart-3fed4b2f-3295-4db1-adcd-4e8097f6c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073533193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2073533193
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.257545576
Short name T830
Test name
Test status
Simulation time 74814004763 ps
CPU time 32.15 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:11:32 PM PDT 24
Peak memory 200204 kb
Host smart-f1c08af1-bce5-4c9e-9c3c-cb5c59e0bd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257545576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.257545576
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2646761118
Short name T684
Test name
Test status
Simulation time 32020019435 ps
CPU time 30.26 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:11:28 PM PDT 24
Peak memory 198092 kb
Host smart-d792a60c-a245-4f01-b78b-37a4ea98f5c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646761118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2646761118
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.705192757
Short name T952
Test name
Test status
Simulation time 77071594196 ps
CPU time 417.82 seconds
Started Mar 19 03:11:04 PM PDT 24
Finished Mar 19 03:18:02 PM PDT 24
Peak memory 200200 kb
Host smart-70823d1d-d00c-4d40-a920-3e7effa03f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705192757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.705192757
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.397997157
Short name T359
Test name
Test status
Simulation time 6795128729 ps
CPU time 13.83 seconds
Started Mar 19 03:10:54 PM PDT 24
Finished Mar 19 03:11:09 PM PDT 24
Peak memory 199580 kb
Host smart-175e188f-d1b8-4027-b9bd-47e5e0880655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397997157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.397997157
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2363995146
Short name T376
Test name
Test status
Simulation time 79760503068 ps
CPU time 69.89 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:12:09 PM PDT 24
Peak memory 199620 kb
Host smart-8b534d06-3c58-4100-9aae-2468fb46f368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363995146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2363995146
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2452681496
Short name T524
Test name
Test status
Simulation time 7241962178 ps
CPU time 147.27 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:13:24 PM PDT 24
Peak memory 200228 kb
Host smart-7e6c2727-cdcf-4aff-bdb4-a2379956b583
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452681496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2452681496
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.80821314
Short name T378
Test name
Test status
Simulation time 5875305762 ps
CPU time 4.26 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:11:01 PM PDT 24
Peak memory 198300 kb
Host smart-2533668d-0e52-438a-bfbc-adc5c43b19ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80821314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.80821314
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2512927286
Short name T835
Test name
Test status
Simulation time 89354426508 ps
CPU time 102.62 seconds
Started Mar 19 03:10:56 PM PDT 24
Finished Mar 19 03:12:39 PM PDT 24
Peak memory 200200 kb
Host smart-4a95f1f8-19d9-44d7-9506-c0cb996021b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512927286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2512927286
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3392099966
Short name T105
Test name
Test status
Simulation time 2971650188 ps
CPU time 5.7 seconds
Started Mar 19 03:11:02 PM PDT 24
Finished Mar 19 03:11:08 PM PDT 24
Peak memory 196576 kb
Host smart-ff5c4808-f071-421d-96ae-8bdf05dac6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392099966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3392099966
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1429829632
Short name T1006
Test name
Test status
Simulation time 535293878 ps
CPU time 1.34 seconds
Started Mar 19 03:10:59 PM PDT 24
Finished Mar 19 03:11:01 PM PDT 24
Peak memory 198960 kb
Host smart-2cd7f154-e6a5-4f44-aad5-ee7c15ee98d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429829632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1429829632
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.306425861
Short name T918
Test name
Test status
Simulation time 519635838700 ps
CPU time 529.44 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:19:48 PM PDT 24
Peak memory 208480 kb
Host smart-cdcb6b75-8366-4d48-aff2-9de5c88599e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306425861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.306425861
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1991301052
Short name T463
Test name
Test status
Simulation time 2248836727 ps
CPU time 2.03 seconds
Started Mar 19 03:10:58 PM PDT 24
Finished Mar 19 03:11:01 PM PDT 24
Peak memory 198488 kb
Host smart-d72c1b1e-aad4-400a-ae41-597412a0a84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991301052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1991301052
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2186190108
Short name T760
Test name
Test status
Simulation time 82861821944 ps
CPU time 57.12 seconds
Started Mar 19 03:11:01 PM PDT 24
Finished Mar 19 03:11:58 PM PDT 24
Peak memory 200176 kb
Host smart-e0d0bde7-7fcf-4601-a6f3-0727dca85528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186190108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2186190108
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2734280204
Short name T104
Test name
Test status
Simulation time 51992384 ps
CPU time 0.56 seconds
Started Mar 19 03:11:16 PM PDT 24
Finished Mar 19 03:11:17 PM PDT 24
Peak memory 195592 kb
Host smart-30f70fb4-008e-4b24-8190-198d2b34214c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734280204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2734280204
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.293831785
Short name T270
Test name
Test status
Simulation time 21800282406 ps
CPU time 37.81 seconds
Started Mar 19 03:11:15 PM PDT 24
Finished Mar 19 03:11:53 PM PDT 24
Peak memory 200144 kb
Host smart-848ee1bd-e596-4c08-91b1-ecde266e471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293831785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.293831785
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3742247457
Short name T311
Test name
Test status
Simulation time 107021428250 ps
CPU time 81.81 seconds
Started Mar 19 03:11:16 PM PDT 24
Finished Mar 19 03:12:38 PM PDT 24
Peak memory 200192 kb
Host smart-b918e875-d51e-49e9-8a59-ecb24c66767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742247457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3742247457
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3981393935
Short name T493
Test name
Test status
Simulation time 53171134884 ps
CPU time 13.29 seconds
Started Mar 19 03:11:13 PM PDT 24
Finished Mar 19 03:11:27 PM PDT 24
Peak memory 200152 kb
Host smart-8dbefa2f-bb12-4b14-810c-41d56b9cc489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981393935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3981393935
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3718776397
Short name T765
Test name
Test status
Simulation time 4813995279 ps
CPU time 9.74 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:11:24 PM PDT 24
Peak memory 199940 kb
Host smart-bb17de77-41b6-42d8-82f8-c7603b4f4d64
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718776397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3718776397
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.945195176
Short name T495
Test name
Test status
Simulation time 117375957565 ps
CPU time 242.37 seconds
Started Mar 19 03:11:16 PM PDT 24
Finished Mar 19 03:15:19 PM PDT 24
Peak memory 200200 kb
Host smart-6c15255a-d467-4246-b063-8a1d8d24fb66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945195176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.945195176
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.944706323
Short name T349
Test name
Test status
Simulation time 8955397060 ps
CPU time 8.58 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:11:24 PM PDT 24
Peak memory 199388 kb
Host smart-440ad591-71d5-4bc4-96cb-0481c431ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944706323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.944706323
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.4109823054
Short name T805
Test name
Test status
Simulation time 72204758656 ps
CPU time 65.71 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:12:20 PM PDT 24
Peak memory 200280 kb
Host smart-e40d8d8d-621c-4e6a-b138-2852d7797514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109823054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.4109823054
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.578360080
Short name T1059
Test name
Test status
Simulation time 14129950668 ps
CPU time 147.58 seconds
Started Mar 19 03:11:16 PM PDT 24
Finished Mar 19 03:13:44 PM PDT 24
Peak memory 199684 kb
Host smart-fa0338fc-62a8-4222-acdd-a21178af0174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578360080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.578360080
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3540098670
Short name T530
Test name
Test status
Simulation time 1528889531 ps
CPU time 0.87 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:11:15 PM PDT 24
Peak memory 195760 kb
Host smart-979e87ca-7881-4887-991b-59cd82ba3e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3540098670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3540098670
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2733623156
Short name T24
Test name
Test status
Simulation time 21728607465 ps
CPU time 35.2 seconds
Started Mar 19 03:11:17 PM PDT 24
Finished Mar 19 03:11:52 PM PDT 24
Peak memory 200220 kb
Host smart-b336e5ab-6d3d-419a-9e48-b12fb99cd93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733623156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2733623156
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2173523683
Short name T365
Test name
Test status
Simulation time 1703530853 ps
CPU time 3.25 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:11:18 PM PDT 24
Peak memory 195988 kb
Host smart-d9ea62af-d1d8-4335-aaea-84862c4be510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173523683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2173523683
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3499350571
Short name T1087
Test name
Test status
Simulation time 5887110786 ps
CPU time 18.7 seconds
Started Mar 19 03:10:57 PM PDT 24
Finished Mar 19 03:11:16 PM PDT 24
Peak memory 199856 kb
Host smart-e14602ea-7bd4-4b05-a775-eed8aac69538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499350571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3499350571
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1481623599
Short name T113
Test name
Test status
Simulation time 92829398207 ps
CPU time 112.52 seconds
Started Mar 19 03:11:18 PM PDT 24
Finished Mar 19 03:13:10 PM PDT 24
Peak memory 200160 kb
Host smart-f9e89814-1a1a-483a-8692-cfb8c9905e8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481623599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1481623599
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1657907356
Short name T1106
Test name
Test status
Simulation time 857379378 ps
CPU time 4.16 seconds
Started Mar 19 03:11:15 PM PDT 24
Finished Mar 19 03:11:19 PM PDT 24
Peak memory 200048 kb
Host smart-22dac5d2-1d9f-420a-94f5-01b41392cbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657907356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1657907356
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2215298225
Short name T847
Test name
Test status
Simulation time 25975514775 ps
CPU time 27.09 seconds
Started Mar 19 03:11:04 PM PDT 24
Finished Mar 19 03:11:32 PM PDT 24
Peak memory 200132 kb
Host smart-04210fc7-318e-4181-9a37-d185a5505730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215298225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2215298225
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3686727407
Short name T745
Test name
Test status
Simulation time 35845086 ps
CPU time 0.56 seconds
Started Mar 19 03:11:18 PM PDT 24
Finished Mar 19 03:11:18 PM PDT 24
Peak memory 195664 kb
Host smart-d4a6d5ef-537f-42e1-949d-547aaae15c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686727407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3686727407
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2059254743
Short name T332
Test name
Test status
Simulation time 13845420947 ps
CPU time 20.58 seconds
Started Mar 19 03:11:17 PM PDT 24
Finished Mar 19 03:11:38 PM PDT 24
Peak memory 200168 kb
Host smart-06dab3ca-a009-4025-8e87-4f03ecec3339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059254743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2059254743
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3827937348
Short name T887
Test name
Test status
Simulation time 193652016947 ps
CPU time 123.49 seconds
Started Mar 19 03:11:17 PM PDT 24
Finished Mar 19 03:13:20 PM PDT 24
Peak memory 200184 kb
Host smart-a6d4581a-86c1-4269-a63a-97954f6e89d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827937348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3827937348
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2972032729
Short name T677
Test name
Test status
Simulation time 17461525155 ps
CPU time 29.05 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:11:43 PM PDT 24
Peak memory 200112 kb
Host smart-854321d1-76b2-4688-bb15-623c3391dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972032729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2972032729
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1237822115
Short name T896
Test name
Test status
Simulation time 28505277440 ps
CPU time 18.23 seconds
Started Mar 19 03:11:17 PM PDT 24
Finished Mar 19 03:11:36 PM PDT 24
Peak memory 200176 kb
Host smart-7b4c6f3a-18ab-4c53-a9b1-a0233bbe8aaf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237822115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1237822115
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.781396760
Short name T383
Test name
Test status
Simulation time 129515361199 ps
CPU time 756.58 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:23:51 PM PDT 24
Peak memory 200076 kb
Host smart-8d8326f5-0df6-4efa-8b90-472fdae820b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781396760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.781396760
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3290646508
Short name T995
Test name
Test status
Simulation time 8098353908 ps
CPU time 4.5 seconds
Started Mar 19 03:11:15 PM PDT 24
Finished Mar 19 03:11:21 PM PDT 24
Peak memory 198568 kb
Host smart-69f14d86-3ae4-40e1-b0fc-195c3993e947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290646508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3290646508
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3609552515
Short name T390
Test name
Test status
Simulation time 67982486791 ps
CPU time 67.94 seconds
Started Mar 19 03:11:15 PM PDT 24
Finished Mar 19 03:12:24 PM PDT 24
Peak memory 216128 kb
Host smart-dba84680-6098-4eaf-a814-0adf4ed373aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609552515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3609552515
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1889040401
Short name T565
Test name
Test status
Simulation time 19127918157 ps
CPU time 266.69 seconds
Started Mar 19 03:11:16 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 200140 kb
Host smart-cb396bf1-d248-4cd0-a1f8-aa07f61f50bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889040401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1889040401
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1439661272
Short name T1104
Test name
Test status
Simulation time 1271803949 ps
CPU time 2.87 seconds
Started Mar 19 03:11:15 PM PDT 24
Finished Mar 19 03:11:18 PM PDT 24
Peak memory 198352 kb
Host smart-dd819d4c-0254-4187-8ee4-1f9803693d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439661272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1439661272
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2862525714
Short name T309
Test name
Test status
Simulation time 377346685680 ps
CPU time 93.77 seconds
Started Mar 19 03:11:16 PM PDT 24
Finished Mar 19 03:12:50 PM PDT 24
Peak memory 200220 kb
Host smart-1c282e5d-3ff7-48d7-8531-5aeb744f795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862525714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2862525714
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2326449302
Short name T575
Test name
Test status
Simulation time 38663836660 ps
CPU time 28.73 seconds
Started Mar 19 03:11:13 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 196284 kb
Host smart-683cd1e5-ca39-474b-845b-5b62a63783b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326449302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2326449302
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1985757068
Short name T318
Test name
Test status
Simulation time 275220921 ps
CPU time 1.65 seconds
Started Mar 19 03:11:17 PM PDT 24
Finished Mar 19 03:11:19 PM PDT 24
Peak memory 198768 kb
Host smart-39ee020c-37d9-45b6-a5a8-cc0ffa540657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985757068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1985757068
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1117771320
Short name T985
Test name
Test status
Simulation time 1646296139 ps
CPU time 1.77 seconds
Started Mar 19 03:11:18 PM PDT 24
Finished Mar 19 03:11:20 PM PDT 24
Peak memory 198540 kb
Host smart-0bc50221-5fea-4656-8993-30cc65faeea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117771320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1117771320
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.762485770
Short name T1085
Test name
Test status
Simulation time 26854771541 ps
CPU time 28.48 seconds
Started Mar 19 03:11:16 PM PDT 24
Finished Mar 19 03:11:45 PM PDT 24
Peak memory 200104 kb
Host smart-5513e8aa-91ff-4071-b6a0-c474bd9c7348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762485770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.762485770
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1262056053
Short name T354
Test name
Test status
Simulation time 25616589 ps
CPU time 0.52 seconds
Started Mar 19 03:11:30 PM PDT 24
Finished Mar 19 03:11:32 PM PDT 24
Peak memory 194600 kb
Host smart-c8dfafaa-585f-4f8e-8864-ddb9488d84bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262056053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1262056053
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.961875989
Short name T879
Test name
Test status
Simulation time 41762784626 ps
CPU time 63.05 seconds
Started Mar 19 03:11:16 PM PDT 24
Finished Mar 19 03:12:19 PM PDT 24
Peak memory 200092 kb
Host smart-3dec78b4-a008-47f8-8ff9-2cd207409f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961875989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.961875989
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.187448680
Short name T510
Test name
Test status
Simulation time 78758363185 ps
CPU time 140.05 seconds
Started Mar 19 03:11:18 PM PDT 24
Finished Mar 19 03:13:38 PM PDT 24
Peak memory 200204 kb
Host smart-563c0b88-1d74-48e1-97f2-3224c6036cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187448680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.187448680
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.2530783961
Short name T1023
Test name
Test status
Simulation time 60284550148 ps
CPU time 51.14 seconds
Started Mar 19 03:11:14 PM PDT 24
Finished Mar 19 03:12:05 PM PDT 24
Peak memory 199404 kb
Host smart-d12697aa-0aaa-4d9a-b96f-50ec2a6da21d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530783961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2530783961
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3968241641
Short name T426
Test name
Test status
Simulation time 125325689448 ps
CPU time 804.34 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:24:54 PM PDT 24
Peak memory 200104 kb
Host smart-ff09842d-f67c-40d9-bd68-d14882fc2f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968241641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3968241641
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3332644727
Short name T599
Test name
Test status
Simulation time 7197825771 ps
CPU time 12.11 seconds
Started Mar 19 03:11:27 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 199120 kb
Host smart-38863d8e-24ba-4d75-b9da-8c81568258dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332644727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3332644727
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.351565997
Short name T695
Test name
Test status
Simulation time 294487919406 ps
CPU time 247.15 seconds
Started Mar 19 03:11:17 PM PDT 24
Finished Mar 19 03:15:24 PM PDT 24
Peak memory 216652 kb
Host smart-d95ebc24-3a7f-4f2d-bb54-604081ba1ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351565997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.351565997
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4129117028
Short name T55
Test name
Test status
Simulation time 26591182855 ps
CPU time 171.11 seconds
Started Mar 19 03:11:30 PM PDT 24
Finished Mar 19 03:14:23 PM PDT 24
Peak memory 200144 kb
Host smart-4ef925e9-bf6f-4da6-a36d-034980a416f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129117028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4129117028
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2153838826
Short name T594
Test name
Test status
Simulation time 2018243888 ps
CPU time 12.56 seconds
Started Mar 19 03:11:17 PM PDT 24
Finished Mar 19 03:11:30 PM PDT 24
Peak memory 198680 kb
Host smart-b98ceda6-d679-492f-b460-f111b6fed38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2153838826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2153838826
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3222447396
Short name T611
Test name
Test status
Simulation time 9854612222 ps
CPU time 8.97 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:11:39 PM PDT 24
Peak memory 199844 kb
Host smart-9bbbf041-6487-46f8-8135-5ffcc79c0d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222447396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3222447396
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.80420936
Short name T609
Test name
Test status
Simulation time 4270357980 ps
CPU time 2.22 seconds
Started Mar 19 03:11:15 PM PDT 24
Finished Mar 19 03:11:17 PM PDT 24
Peak memory 196248 kb
Host smart-af6d6672-556d-4c0d-9430-17eddfc15803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80420936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.80420936
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3823430856
Short name T733
Test name
Test status
Simulation time 5650225469 ps
CPU time 13.28 seconds
Started Mar 19 03:11:15 PM PDT 24
Finished Mar 19 03:11:29 PM PDT 24
Peak memory 200040 kb
Host smart-943dcfc7-b975-49a1-a8f7-ea665c5d01e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823430856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3823430856
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1401326677
Short name T679
Test name
Test status
Simulation time 255464647035 ps
CPU time 1011.09 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:28:22 PM PDT 24
Peak memory 200228 kb
Host smart-e915bd27-262e-4067-a867-d1a1c5189bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401326677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1401326677
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1907101585
Short name T36
Test name
Test status
Simulation time 71127589012 ps
CPU time 123.39 seconds
Started Mar 19 03:11:32 PM PDT 24
Finished Mar 19 03:13:36 PM PDT 24
Peak memory 208348 kb
Host smart-94b9d976-1b3a-4e29-986d-6834b5cd1c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907101585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1907101585
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1836353916
Short name T1113
Test name
Test status
Simulation time 7158768931 ps
CPU time 17.05 seconds
Started Mar 19 03:11:31 PM PDT 24
Finished Mar 19 03:11:50 PM PDT 24
Peak memory 199720 kb
Host smart-d8980b0e-15f6-4fe7-a233-3729bcb3ba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836353916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1836353916
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2099750165
Short name T294
Test name
Test status
Simulation time 22597379733 ps
CPU time 32.45 seconds
Started Mar 19 03:11:17 PM PDT 24
Finished Mar 19 03:11:49 PM PDT 24
Peak memory 200112 kb
Host smart-21251733-096a-405d-a73c-0dbc73630297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099750165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2099750165
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.698542351
Short name T418
Test name
Test status
Simulation time 14557455 ps
CPU time 0.62 seconds
Started Mar 19 03:11:27 PM PDT 24
Finished Mar 19 03:11:30 PM PDT 24
Peak memory 195640 kb
Host smart-2f9fb84c-3be4-41f3-93df-3121fcc2bc1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698542351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.698542351
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.793114747
Short name T903
Test name
Test status
Simulation time 188171662047 ps
CPU time 132.8 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:13:42 PM PDT 24
Peak memory 200152 kb
Host smart-835b1318-8121-499e-8d03-3493386941e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793114747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.793114747
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3382233923
Short name T724
Test name
Test status
Simulation time 193734405944 ps
CPU time 300.72 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:16:31 PM PDT 24
Peak memory 199900 kb
Host smart-ac67e4da-6423-4ae6-a311-f3a6bd3662c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382233923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3382233923
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.622523190
Short name T196
Test name
Test status
Simulation time 113127327601 ps
CPU time 217.53 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:15:07 PM PDT 24
Peak memory 200052 kb
Host smart-46a5fba4-03d1-42a5-8872-a03f745b4128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622523190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.622523190
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2670687124
Short name T461
Test name
Test status
Simulation time 5078567093 ps
CPU time 1.19 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:11:32 PM PDT 24
Peak memory 197040 kb
Host smart-35bcfe5a-137c-480a-83be-2ae065b410c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670687124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2670687124
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1287642451
Short name T956
Test name
Test status
Simulation time 64853050115 ps
CPU time 455.87 seconds
Started Mar 19 03:11:26 PM PDT 24
Finished Mar 19 03:19:04 PM PDT 24
Peak memory 200184 kb
Host smart-ebcabd57-b50b-481e-876c-b634bc2e045f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287642451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1287642451
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4008878781
Short name T473
Test name
Test status
Simulation time 4727589124 ps
CPU time 6.15 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:11:37 PM PDT 24
Peak memory 200180 kb
Host smart-a970692c-c79f-458a-8055-ef70444e728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008878781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4008878781
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1990812648
Short name T818
Test name
Test status
Simulation time 6438943202 ps
CPU time 11.6 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:11:43 PM PDT 24
Peak memory 195112 kb
Host smart-2fa85258-bf69-4b04-b62e-a6d29fc01b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990812648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1990812648
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.505179114
Short name T553
Test name
Test status
Simulation time 25698340459 ps
CPU time 496.47 seconds
Started Mar 19 03:11:26 PM PDT 24
Finished Mar 19 03:19:44 PM PDT 24
Peak memory 200164 kb
Host smart-5e6d1cac-afbe-45d6-8e18-93d81cc948c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505179114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.505179114
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.932273483
Short name T1019
Test name
Test status
Simulation time 4548250278 ps
CPU time 9.95 seconds
Started Mar 19 03:11:27 PM PDT 24
Finished Mar 19 03:11:38 PM PDT 24
Peak memory 198276 kb
Host smart-a12d7246-244e-49fc-a6a3-cf9b324d375b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932273483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.932273483
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2904500817
Short name T707
Test name
Test status
Simulation time 340986692249 ps
CPU time 103.9 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:13:16 PM PDT 24
Peak memory 200132 kb
Host smart-9d0abc19-74cd-4694-bdc7-44504ab47be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904500817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2904500817
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2961917016
Short name T979
Test name
Test status
Simulation time 3092125706 ps
CPU time 5.52 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:11:37 PM PDT 24
Peak memory 196272 kb
Host smart-34db23fc-7dda-4b80-bc98-2c0f807646a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961917016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2961917016
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2146066040
Short name T703
Test name
Test status
Simulation time 512826105 ps
CPU time 1.71 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:11:33 PM PDT 24
Peak memory 198924 kb
Host smart-dd8eeb15-6f31-4c74-b98f-edbeab0bd640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146066040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2146066040
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2706491291
Short name T364
Test name
Test status
Simulation time 3238215321 ps
CPU time 1.75 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:11:33 PM PDT 24
Peak memory 199432 kb
Host smart-bd35a158-864c-4be2-aa79-ab86e7d2b946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706491291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2706491291
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2709258190
Short name T786
Test name
Test status
Simulation time 73686371971 ps
CPU time 34.08 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:12:05 PM PDT 24
Peak memory 200120 kb
Host smart-2d461074-c101-4be9-a578-91d6d3dc2503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709258190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2709258190
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3759951766
Short name T367
Test name
Test status
Simulation time 12139958 ps
CPU time 0.55 seconds
Started Mar 19 03:11:30 PM PDT 24
Finished Mar 19 03:11:32 PM PDT 24
Peak memory 194632 kb
Host smart-703e3ca1-05a5-41f4-b701-b642c59047e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759951766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3759951766
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2864108669
Short name T486
Test name
Test status
Simulation time 41641033997 ps
CPU time 35.03 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:12:07 PM PDT 24
Peak memory 200200 kb
Host smart-ff87e29b-b9e3-4886-8fec-1c3d1605f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864108669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2864108669
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2565916696
Short name T708
Test name
Test status
Simulation time 24423716573 ps
CPU time 9.37 seconds
Started Mar 19 03:11:32 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 200020 kb
Host smart-089ba602-5303-428e-ad9f-7477941b8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565916696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2565916696
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2273908097
Short name T1046
Test name
Test status
Simulation time 136399388061 ps
CPU time 75.29 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:12:47 PM PDT 24
Peak memory 200064 kb
Host smart-19b6c9e8-1e89-4e44-b2fe-1843ccf56d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273908097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2273908097
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1036735111
Short name T1013
Test name
Test status
Simulation time 521691573545 ps
CPU time 686.13 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:22:58 PM PDT 24
Peak memory 199232 kb
Host smart-b35a2a65-08d9-4b0d-9527-aec0953b5f98
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036735111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1036735111
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2251588745
Short name T347
Test name
Test status
Simulation time 58895436310 ps
CPU time 102.63 seconds
Started Mar 19 03:11:33 PM PDT 24
Finished Mar 19 03:13:16 PM PDT 24
Peak memory 200172 kb
Host smart-0764bd15-9461-408b-862d-29855e7471a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251588745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2251588745
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2753301074
Short name T1054
Test name
Test status
Simulation time 736123090 ps
CPU time 1.71 seconds
Started Mar 19 03:11:30 PM PDT 24
Finished Mar 19 03:11:34 PM PDT 24
Peak memory 195728 kb
Host smart-6d842d65-4c5f-4e1b-867b-6174acad88e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753301074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2753301074
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2166543230
Short name T661
Test name
Test status
Simulation time 368869286848 ps
CPU time 172.21 seconds
Started Mar 19 03:11:31 PM PDT 24
Finished Mar 19 03:14:24 PM PDT 24
Peak memory 208504 kb
Host smart-a02998ab-c81a-494c-9b6e-dad6771c76fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166543230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2166543230
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.773725616
Short name T1091
Test name
Test status
Simulation time 8856912986 ps
CPU time 434.76 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 200104 kb
Host smart-c892dbf5-1c0d-4af9-aa47-0470eda4fdeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773725616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.773725616
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.213015769
Short name T902
Test name
Test status
Simulation time 2561925803 ps
CPU time 3.8 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:11:33 PM PDT 24
Peak memory 198576 kb
Host smart-a4d2d8ec-5bec-469f-92cd-8b6d973a35f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213015769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.213015769
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4038541892
Short name T742
Test name
Test status
Simulation time 105521130132 ps
CPU time 124.86 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:13:37 PM PDT 24
Peak memory 200204 kb
Host smart-660f5699-63f1-41a3-abd3-02667add7b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038541892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4038541892
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2210341885
Short name T820
Test name
Test status
Simulation time 1864028613 ps
CPU time 2.02 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:11:33 PM PDT 24
Peak memory 194852 kb
Host smart-2088a513-1612-416f-8a15-794d12357503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210341885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2210341885
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1063917896
Short name T865
Test name
Test status
Simulation time 494184066 ps
CPU time 1.34 seconds
Started Mar 19 03:11:28 PM PDT 24
Finished Mar 19 03:11:32 PM PDT 24
Peak memory 199136 kb
Host smart-1356ecfa-3dd0-4130-8cb2-a5446acee32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063917896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1063917896
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2162301312
Short name T452
Test name
Test status
Simulation time 266148576954 ps
CPU time 656.1 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:22:31 PM PDT 24
Peak memory 200196 kb
Host smart-3dbfdb96-5c5e-42b9-a68e-e7dd410625a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162301312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2162301312
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.806322138
Short name T272
Test name
Test status
Simulation time 909398390 ps
CPU time 2.39 seconds
Started Mar 19 03:11:32 PM PDT 24
Finished Mar 19 03:11:35 PM PDT 24
Peak memory 198580 kb
Host smart-ecbb914a-7e10-4be9-90be-44c66b0f06ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806322138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.806322138
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.70194187
Short name T404
Test name
Test status
Simulation time 41876950215 ps
CPU time 19.99 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:11:52 PM PDT 24
Peak memory 200200 kb
Host smart-021c64a7-841e-4279-92ad-6374c5cae331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70194187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.70194187
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.238707082
Short name T110
Test name
Test status
Simulation time 11336475 ps
CPU time 0.59 seconds
Started Mar 19 03:09:25 PM PDT 24
Finished Mar 19 03:09:25 PM PDT 24
Peak memory 195668 kb
Host smart-9e07bfb7-4138-4cb5-90f0-32e0c9f0ea41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238707082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.238707082
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2842853207
Short name T838
Test name
Test status
Simulation time 131247413441 ps
CPU time 96.83 seconds
Started Mar 19 03:09:22 PM PDT 24
Finished Mar 19 03:10:59 PM PDT 24
Peak memory 200172 kb
Host smart-e74be11d-f102-4883-9b19-16c5feb39f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842853207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2842853207
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1767481021
Short name T957
Test name
Test status
Simulation time 17580188219 ps
CPU time 47.86 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:10:21 PM PDT 24
Peak memory 200164 kb
Host smart-21a77815-9880-40b9-ab5b-7cbf9f1b6e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767481021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1767481021
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3425864556
Short name T327
Test name
Test status
Simulation time 102329619478 ps
CPU time 140.77 seconds
Started Mar 19 03:09:34 PM PDT 24
Finished Mar 19 03:11:56 PM PDT 24
Peak memory 200080 kb
Host smart-f60fa430-596a-49c4-a403-64969ccb2af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425864556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3425864556
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3183364748
Short name T13
Test name
Test status
Simulation time 49995324310 ps
CPU time 43.86 seconds
Started Mar 19 03:09:35 PM PDT 24
Finished Mar 19 03:10:20 PM PDT 24
Peak memory 199124 kb
Host smart-655175c6-a117-4979-8f4c-16b51779bfa7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183364748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3183364748
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.242997027
Short name T1094
Test name
Test status
Simulation time 62796346117 ps
CPU time 522.04 seconds
Started Mar 19 03:09:35 PM PDT 24
Finished Mar 19 03:18:18 PM PDT 24
Peak memory 200156 kb
Host smart-50abfd53-2a0d-4b63-b3d7-2cc38109ef0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242997027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.242997027
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1476183262
Short name T633
Test name
Test status
Simulation time 6516737353 ps
CPU time 11.38 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:09:39 PM PDT 24
Peak memory 199960 kb
Host smart-c7f9e4c0-55f0-4cd4-9f42-c33a1fa00a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476183262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1476183262
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2814361525
Short name T666
Test name
Test status
Simulation time 27964878038 ps
CPU time 49.68 seconds
Started Mar 19 03:09:32 PM PDT 24
Finished Mar 19 03:10:22 PM PDT 24
Peak memory 198908 kb
Host smart-f0b784ae-dbe8-461a-830a-40577342c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814361525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2814361525
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2505353927
Short name T407
Test name
Test status
Simulation time 6175975172 ps
CPU time 375.03 seconds
Started Mar 19 03:09:29 PM PDT 24
Finished Mar 19 03:15:45 PM PDT 24
Peak memory 200140 kb
Host smart-df238333-7973-40bb-9c40-486e4efa0610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505353927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2505353927
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2298679195
Short name T802
Test name
Test status
Simulation time 3489774952 ps
CPU time 27.77 seconds
Started Mar 19 03:09:26 PM PDT 24
Finished Mar 19 03:09:55 PM PDT 24
Peak memory 198096 kb
Host smart-140168b8-7084-4c02-af18-1431241d6a5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2298679195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2298679195
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.163513190
Short name T806
Test name
Test status
Simulation time 87520908889 ps
CPU time 138.03 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:11:45 PM PDT 24
Peak memory 200200 kb
Host smart-d277c2df-29a3-435b-a0dd-91c8db8d5278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163513190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.163513190
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1712045868
Short name T869
Test name
Test status
Simulation time 33895425411 ps
CPU time 28.44 seconds
Started Mar 19 03:09:28 PM PDT 24
Finished Mar 19 03:09:57 PM PDT 24
Peak memory 196256 kb
Host smart-4b3786d3-9d83-451b-a08c-a703160feea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712045868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1712045868
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.951164444
Short name T87
Test name
Test status
Simulation time 366075161 ps
CPU time 0.8 seconds
Started Mar 19 03:09:24 PM PDT 24
Finished Mar 19 03:09:25 PM PDT 24
Peak memory 218568 kb
Host smart-91b14133-4c48-4cee-9066-7feb40f967ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951164444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.951164444
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1053304717
Short name T319
Test name
Test status
Simulation time 912181094 ps
CPU time 2.18 seconds
Started Mar 19 03:09:26 PM PDT 24
Finished Mar 19 03:09:29 PM PDT 24
Peak memory 198868 kb
Host smart-9c1a233d-924c-4b36-9934-1d91a5be9ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053304717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1053304717
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1776369936
Short name T955
Test name
Test status
Simulation time 386876094251 ps
CPU time 318.4 seconds
Started Mar 19 03:09:29 PM PDT 24
Finished Mar 19 03:14:47 PM PDT 24
Peak memory 208716 kb
Host smart-85fce093-6911-4480-aca5-ead551d93b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776369936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1776369936
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.730201139
Short name T394
Test name
Test status
Simulation time 13882639126 ps
CPU time 14.7 seconds
Started Mar 19 03:09:35 PM PDT 24
Finished Mar 19 03:09:51 PM PDT 24
Peak memory 200104 kb
Host smart-745a6f35-74a8-4da3-b93b-d20b410f5254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730201139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.730201139
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2264915515
Short name T468
Test name
Test status
Simulation time 105102027033 ps
CPU time 15.8 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:09:46 PM PDT 24
Peak memory 200068 kb
Host smart-f90ef108-6bd8-4ab8-9267-923d78ed9f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264915515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2264915515
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3131157954
Short name T872
Test name
Test status
Simulation time 17685349 ps
CPU time 0.56 seconds
Started Mar 19 03:11:33 PM PDT 24
Finished Mar 19 03:11:34 PM PDT 24
Peak memory 195664 kb
Host smart-9c5805e9-f050-4eef-9171-8694616d6411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131157954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3131157954
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3822872218
Short name T46
Test name
Test status
Simulation time 20383333617 ps
CPU time 54.43 seconds
Started Mar 19 03:11:30 PM PDT 24
Finished Mar 19 03:12:26 PM PDT 24
Peak memory 200132 kb
Host smart-3a5b9fd8-e5a6-4283-a720-2171c28bb280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822872218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3822872218
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.983281975
Short name T796
Test name
Test status
Simulation time 22247928787 ps
CPU time 41.19 seconds
Started Mar 19 03:11:31 PM PDT 24
Finished Mar 19 03:12:13 PM PDT 24
Peak memory 200096 kb
Host smart-3419463a-76e7-4109-a23d-64748efce207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983281975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.983281975
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.4006612291
Short name T146
Test name
Test status
Simulation time 7219929453 ps
CPU time 10.09 seconds
Started Mar 19 03:11:31 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 200204 kb
Host smart-9b2e551a-9789-4422-ad94-5c4bc73a73fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006612291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.4006612291
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2100214157
Short name T732
Test name
Test status
Simulation time 30531394263 ps
CPU time 49.67 seconds
Started Mar 19 03:11:31 PM PDT 24
Finished Mar 19 03:12:22 PM PDT 24
Peak memory 200084 kb
Host smart-6a4658d8-fdf3-4026-aab6-2f58a946d8b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100214157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2100214157
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1578012900
Short name T1032
Test name
Test status
Simulation time 138897094495 ps
CPU time 406.2 seconds
Started Mar 19 03:11:33 PM PDT 24
Finished Mar 19 03:18:20 PM PDT 24
Peak memory 200216 kb
Host smart-a7a84d50-b22a-49c7-b969-56ca58b27557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578012900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1578012900
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.682181401
Short name T748
Test name
Test status
Simulation time 8279752052 ps
CPU time 13.42 seconds
Started Mar 19 03:11:32 PM PDT 24
Finished Mar 19 03:11:46 PM PDT 24
Peak memory 199996 kb
Host smart-3d55e6cc-9389-424a-a934-eb3646e6a418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682181401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.682181401
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.194604429
Short name T716
Test name
Test status
Simulation time 54223585836 ps
CPU time 52.77 seconds
Started Mar 19 03:11:33 PM PDT 24
Finished Mar 19 03:12:26 PM PDT 24
Peak memory 200328 kb
Host smart-85d5ba0d-0629-479d-8d19-e25be8b46da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194604429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.194604429
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3018782377
Short name T268
Test name
Test status
Simulation time 11499117587 ps
CPU time 300.37 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:16:35 PM PDT 24
Peak memory 200144 kb
Host smart-f381c58d-0d1c-4e1e-a006-978e016177c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018782377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3018782377
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1597986619
Short name T456
Test name
Test status
Simulation time 5378638280 ps
CPU time 44.81 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:12:19 PM PDT 24
Peak memory 198244 kb
Host smart-04cb0fc1-8dd0-411a-a68e-502dd687254c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597986619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1597986619
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3459182215
Short name T539
Test name
Test status
Simulation time 121649849165 ps
CPU time 49.88 seconds
Started Mar 19 03:11:32 PM PDT 24
Finished Mar 19 03:12:23 PM PDT 24
Peak memory 200176 kb
Host smart-01d0ff9a-021a-4aa2-b940-722977b185d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459182215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3459182215
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2199180977
Short name T410
Test name
Test status
Simulation time 5030719614 ps
CPU time 2.64 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:11:37 PM PDT 24
Peak memory 196260 kb
Host smart-19666adb-5841-4c8f-9bd0-518f3380a882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199180977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2199180977
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1081579344
Short name T691
Test name
Test status
Simulation time 5451649459 ps
CPU time 15.21 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:11:50 PM PDT 24
Peak memory 200128 kb
Host smart-66dfb752-2563-4c26-84d3-c02827d97e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081579344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1081579344
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.63164183
Short name T1090
Test name
Test status
Simulation time 145121893420 ps
CPU time 31.44 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:12:05 PM PDT 24
Peak memory 200092 kb
Host smart-6a6e4efe-2830-4f7a-b599-1b56fdd11221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63164183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.63164183
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3196469367
Short name T393
Test name
Test status
Simulation time 526342206 ps
CPU time 1.8 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:11:34 PM PDT 24
Peak memory 198692 kb
Host smart-649b6cd2-cec1-4f58-a32e-3575d75830f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196469367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3196469367
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2950801745
Short name T471
Test name
Test status
Simulation time 47812100867 ps
CPU time 149 seconds
Started Mar 19 03:11:29 PM PDT 24
Finished Mar 19 03:14:01 PM PDT 24
Peak memory 200176 kb
Host smart-f9387699-5202-411d-a1b7-9bf6e3e821b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950801745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2950801745
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3841457499
Short name T662
Test name
Test status
Simulation time 39569943 ps
CPU time 0.54 seconds
Started Mar 19 03:11:37 PM PDT 24
Finished Mar 19 03:11:37 PM PDT 24
Peak memory 195152 kb
Host smart-c0eec004-d78c-487a-950e-1babe7d1f70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841457499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3841457499
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1721981782
Short name T1004
Test name
Test status
Simulation time 16073061748 ps
CPU time 29.09 seconds
Started Mar 19 03:11:33 PM PDT 24
Finished Mar 19 03:12:03 PM PDT 24
Peak memory 200120 kb
Host smart-adc88452-253d-4ca2-a381-47e3a2d384ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721981782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1721981782
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.709170095
Short name T946
Test name
Test status
Simulation time 97662960995 ps
CPU time 14.23 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:11:49 PM PDT 24
Peak memory 199460 kb
Host smart-93d323e9-977f-4380-96e5-04abd7b684f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709170095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.709170095
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3132539068
Short name T523
Test name
Test status
Simulation time 63155501080 ps
CPU time 28.94 seconds
Started Mar 19 03:11:30 PM PDT 24
Finished Mar 19 03:12:01 PM PDT 24
Peak memory 200052 kb
Host smart-19e2977e-2f0d-4183-b878-f3f27a616c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132539068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3132539068
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1697947208
Short name T445
Test name
Test status
Simulation time 29342183091 ps
CPU time 28.23 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:12:07 PM PDT 24
Peak memory 199572 kb
Host smart-74207daf-87bf-435c-b6a0-dc70bfa7d41c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697947208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1697947208
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3497057962
Short name T56
Test name
Test status
Simulation time 39030775507 ps
CPU time 171.58 seconds
Started Mar 19 03:11:41 PM PDT 24
Finished Mar 19 03:14:32 PM PDT 24
Peak memory 200180 kb
Host smart-a15be019-b25e-45f7-9a08-4113762b8804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497057962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3497057962
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.993997638
Short name T842
Test name
Test status
Simulation time 8456293342 ps
CPU time 4.03 seconds
Started Mar 19 03:11:37 PM PDT 24
Finished Mar 19 03:11:41 PM PDT 24
Peak memory 199184 kb
Host smart-533dd535-f397-49c0-bd08-209f2154f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993997638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.993997638
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.53475901
Short name T714
Test name
Test status
Simulation time 119690760194 ps
CPU time 38.38 seconds
Started Mar 19 03:11:30 PM PDT 24
Finished Mar 19 03:12:10 PM PDT 24
Peak memory 200344 kb
Host smart-a7c4a460-18f9-4b3f-9666-037457cd6443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53475901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.53475901
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2801314978
Short name T261
Test name
Test status
Simulation time 3767516592 ps
CPU time 49 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:12:28 PM PDT 24
Peak memory 200176 kb
Host smart-dfc11b03-da17-4e77-9321-52d43110fb50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801314978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2801314978
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2513478891
Short name T874
Test name
Test status
Simulation time 4223035450 ps
CPU time 26.08 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:12:04 PM PDT 24
Peak memory 198556 kb
Host smart-f44f2016-aed1-499e-9b91-047d4ad80b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513478891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2513478891
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.125941876
Short name T750
Test name
Test status
Simulation time 40762999831 ps
CPU time 7.56 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:11:46 PM PDT 24
Peak memory 200164 kb
Host smart-0ff0de55-febc-46b6-a922-c2bd17a1ed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125941876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.125941876
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3009543080
Short name T884
Test name
Test status
Simulation time 1883118921 ps
CPU time 1.39 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:11:35 PM PDT 24
Peak memory 195900 kb
Host smart-592267f3-ee01-4c70-8988-fff8e488452c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009543080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3009543080
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2484903720
Short name T689
Test name
Test status
Simulation time 11109703784 ps
CPU time 35.45 seconds
Started Mar 19 03:11:32 PM PDT 24
Finished Mar 19 03:12:08 PM PDT 24
Peak memory 200012 kb
Host smart-d0181a21-a264-4d41-b1d0-c80bcff565e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484903720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2484903720
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1609356332
Short name T301
Test name
Test status
Simulation time 272287434526 ps
CPU time 475.66 seconds
Started Mar 19 03:11:41 PM PDT 24
Finished Mar 19 03:19:37 PM PDT 24
Peak memory 200180 kb
Host smart-9310630d-cacb-4dec-a625-66a27438df46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609356332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1609356332
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2410873287
Short name T26
Test name
Test status
Simulation time 94458538224 ps
CPU time 319.45 seconds
Started Mar 19 03:11:40 PM PDT 24
Finished Mar 19 03:16:59 PM PDT 24
Peak memory 215348 kb
Host smart-be7f3876-4146-47b4-814d-f750be54900b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410873287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2410873287
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3822240101
Short name T582
Test name
Test status
Simulation time 411469656 ps
CPU time 1.49 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:11:40 PM PDT 24
Peak memory 198176 kb
Host smart-c9ca7d1b-8445-493d-957e-ae1cd681c579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822240101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3822240101
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2556088954
Short name T931
Test name
Test status
Simulation time 23386042566 ps
CPU time 40.49 seconds
Started Mar 19 03:11:34 PM PDT 24
Finished Mar 19 03:12:15 PM PDT 24
Peak memory 200084 kb
Host smart-1f946aae-34eb-404b-8081-3068e1e35762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556088954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2556088954
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1122735779
Short name T598
Test name
Test status
Simulation time 18631838 ps
CPU time 0.56 seconds
Started Mar 19 03:11:40 PM PDT 24
Finished Mar 19 03:11:41 PM PDT 24
Peak memory 195628 kb
Host smart-192a7436-423d-4688-a813-7c1dc047a05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122735779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1122735779
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1557617395
Short name T757
Test name
Test status
Simulation time 36383696591 ps
CPU time 18.81 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:11:56 PM PDT 24
Peak memory 200172 kb
Host smart-d795bf4c-8382-42af-b8a8-fe3ce9acdc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557617395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1557617395
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.4227554553
Short name T466
Test name
Test status
Simulation time 127387580381 ps
CPU time 23.53 seconds
Started Mar 19 03:11:42 PM PDT 24
Finished Mar 19 03:12:06 PM PDT 24
Peak memory 200132 kb
Host smart-b13db5cf-5871-4ae3-985b-99bd36e3b72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227554553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.4227554553
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2412879857
Short name T174
Test name
Test status
Simulation time 184222457505 ps
CPU time 451.12 seconds
Started Mar 19 03:11:45 PM PDT 24
Finished Mar 19 03:19:16 PM PDT 24
Peak memory 200124 kb
Host smart-d9b76e6f-f59e-466e-a393-5d86ded5b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412879857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2412879857
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1503340750
Short name T42
Test name
Test status
Simulation time 304928827680 ps
CPU time 129.17 seconds
Started Mar 19 03:11:41 PM PDT 24
Finished Mar 19 03:13:51 PM PDT 24
Peak memory 199600 kb
Host smart-ee6e8dcc-304f-448e-8171-9040e44e1426
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503340750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1503340750
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3372263305
Short name T736
Test name
Test status
Simulation time 30504407511 ps
CPU time 136.9 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:13:55 PM PDT 24
Peak memory 200196 kb
Host smart-f6b15de0-ed41-48d0-9568-6c65f31c6354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372263305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3372263305
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2105847263
Short name T997
Test name
Test status
Simulation time 6624331841 ps
CPU time 7.04 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:11:45 PM PDT 24
Peak memory 200156 kb
Host smart-c3eca10d-98e3-4175-98c1-d2ffe2d5c85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105847263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2105847263
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2989600215
Short name T992
Test name
Test status
Simulation time 140617377156 ps
CPU time 62.67 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:12:41 PM PDT 24
Peak memory 208152 kb
Host smart-8bd24079-919b-4158-8a3d-95e1fd46d2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989600215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2989600215
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2783650829
Short name T343
Test name
Test status
Simulation time 5733764325 ps
CPU time 88.17 seconds
Started Mar 19 03:11:41 PM PDT 24
Finished Mar 19 03:13:09 PM PDT 24
Peak memory 199724 kb
Host smart-850b6fae-6a07-4ab3-a1ca-f40997fff7c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783650829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2783650829
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1411525782
Short name T9
Test name
Test status
Simulation time 2640368120 ps
CPU time 13 seconds
Started Mar 19 03:11:46 PM PDT 24
Finished Mar 19 03:11:59 PM PDT 24
Peak memory 199160 kb
Host smart-da385988-1ec6-421e-8660-ea88a4e5057c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411525782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1411525782
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3671381271
Short name T999
Test name
Test status
Simulation time 133249016239 ps
CPU time 59.24 seconds
Started Mar 19 03:11:41 PM PDT 24
Finished Mar 19 03:12:40 PM PDT 24
Peak memory 200144 kb
Host smart-65ba6c32-61f4-4f23-8ec4-fab4cb90ebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671381271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3671381271
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.994844179
Short name T839
Test name
Test status
Simulation time 3463764871 ps
CPU time 3.12 seconds
Started Mar 19 03:11:43 PM PDT 24
Finished Mar 19 03:11:46 PM PDT 24
Peak memory 196288 kb
Host smart-26baee97-5f99-4a28-a184-c932e42caee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994844179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.994844179
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1257924050
Short name T939
Test name
Test status
Simulation time 607732567 ps
CPU time 2.51 seconds
Started Mar 19 03:11:37 PM PDT 24
Finished Mar 19 03:11:40 PM PDT 24
Peak memory 198460 kb
Host smart-1b08a2c8-8de2-474e-8345-61ecb0e4c10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257924050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1257924050
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2412353047
Short name T421
Test name
Test status
Simulation time 46391616546 ps
CPU time 80.4 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:13:00 PM PDT 24
Peak memory 200352 kb
Host smart-848c3239-5a49-4c86-8482-9c81f64b8b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412353047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2412353047
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.847181763
Short name T1110
Test name
Test status
Simulation time 365052013356 ps
CPU time 373.79 seconds
Started Mar 19 03:11:41 PM PDT 24
Finished Mar 19 03:17:55 PM PDT 24
Peak memory 216652 kb
Host smart-d71ac1b1-f7a9-4808-88c9-9a4f4d2a67a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847181763 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.847181763
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.378837383
Short name T798
Test name
Test status
Simulation time 6380473025 ps
CPU time 26.86 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:12:06 PM PDT 24
Peak memory 200124 kb
Host smart-6a287872-6296-4ad9-a581-e9f81845bd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378837383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.378837383
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3369290600
Short name T1052
Test name
Test status
Simulation time 34746186994 ps
CPU time 23.54 seconds
Started Mar 19 03:11:43 PM PDT 24
Finished Mar 19 03:12:06 PM PDT 24
Peak memory 200160 kb
Host smart-c4022b98-21da-41b4-844a-1a1ddb1f901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369290600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3369290600
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.141584296
Short name T415
Test name
Test status
Simulation time 42908413 ps
CPU time 0.57 seconds
Started Mar 19 03:11:42 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 195124 kb
Host smart-f67de0dc-591a-47f5-8f70-576d5abb527d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141584296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.141584296
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1418466493
Short name T597
Test name
Test status
Simulation time 6341078060 ps
CPU time 9.65 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:11:49 PM PDT 24
Peak memory 198708 kb
Host smart-0af783a3-9d53-421b-aaae-b17299c453c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418466493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1418466493
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.4225613028
Short name T54
Test name
Test status
Simulation time 57796506862 ps
CPU time 209.23 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:15:09 PM PDT 24
Peak memory 200112 kb
Host smart-b4bbffb1-d3b8-471e-b2ab-de05133e7d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225613028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.4225613028
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3500905354
Short name T141
Test name
Test status
Simulation time 76566719313 ps
CPU time 27.53 seconds
Started Mar 19 03:11:43 PM PDT 24
Finished Mar 19 03:12:10 PM PDT 24
Peak memory 200112 kb
Host smart-a9b6b7ee-94a1-4cbc-a373-8866f2e1a457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500905354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3500905354
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2794230766
Short name T259
Test name
Test status
Simulation time 285383114104 ps
CPU time 124.01 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:13:43 PM PDT 24
Peak memory 199988 kb
Host smart-3f02327b-9c0e-41ab-94d5-a01d1f6a7c2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794230766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2794230766
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.324419414
Short name T465
Test name
Test status
Simulation time 175572461492 ps
CPU time 141.75 seconds
Started Mar 19 03:11:40 PM PDT 24
Finished Mar 19 03:14:02 PM PDT 24
Peak memory 200204 kb
Host smart-49018ba4-64ab-4b27-b2c0-fa9cc54c9ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324419414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.324419414
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1160880014
Short name T989
Test name
Test status
Simulation time 451790113 ps
CPU time 1.09 seconds
Started Mar 19 03:11:40 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 197900 kb
Host smart-e94509c1-832a-446a-a6c8-6029559af46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160880014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1160880014
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2652292170
Short name T967
Test name
Test status
Simulation time 23089625986 ps
CPU time 19.85 seconds
Started Mar 19 03:11:47 PM PDT 24
Finished Mar 19 03:12:06 PM PDT 24
Peak memory 196612 kb
Host smart-7231b8da-a176-4a8a-9169-3120b84c1353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652292170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2652292170
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3615897007
Short name T929
Test name
Test status
Simulation time 4864063075 ps
CPU time 266.43 seconds
Started Mar 19 03:11:43 PM PDT 24
Finished Mar 19 03:16:10 PM PDT 24
Peak memory 200140 kb
Host smart-9f14efbe-5798-413a-917a-eaf41b32f6ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615897007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3615897007
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.271602438
Short name T536
Test name
Test status
Simulation time 6192195254 ps
CPU time 12.99 seconds
Started Mar 19 03:11:41 PM PDT 24
Finished Mar 19 03:11:54 PM PDT 24
Peak memory 198184 kb
Host smart-b8f8942f-7625-4fca-873f-5ef835f0dfab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271602438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.271602438
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3606929020
Short name T556
Test name
Test status
Simulation time 137973901473 ps
CPU time 62.17 seconds
Started Mar 19 03:11:42 PM PDT 24
Finished Mar 19 03:12:44 PM PDT 24
Peak memory 200236 kb
Host smart-331e53d3-04ff-4764-8f41-2656d02ea8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606929020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3606929020
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2119532445
Short name T444
Test name
Test status
Simulation time 47193784182 ps
CPU time 37.55 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:12:16 PM PDT 24
Peak memory 196552 kb
Host smart-7c72b093-2b40-42cc-826c-de9a2d46bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119532445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2119532445
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1322180423
Short name T624
Test name
Test status
Simulation time 713286465 ps
CPU time 2.89 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:11:42 PM PDT 24
Peak memory 198984 kb
Host smart-95586fc8-c974-4c34-a714-aadeb5659f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322180423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1322180423
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.777037118
Short name T554
Test name
Test status
Simulation time 239274745633 ps
CPU time 314.82 seconds
Started Mar 19 03:11:40 PM PDT 24
Finished Mar 19 03:16:55 PM PDT 24
Peak memory 200184 kb
Host smart-68576f8f-ba8d-474c-8d25-cfa5c48b3bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777037118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.777037118
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.908039377
Short name T720
Test name
Test status
Simulation time 12841947600 ps
CPU time 22.54 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:12:00 PM PDT 24
Peak memory 200152 kb
Host smart-6ee9082b-feac-4680-a7eb-7f57c552617d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908039377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.908039377
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2865605992
Short name T574
Test name
Test status
Simulation time 73796108261 ps
CPU time 34.18 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:12:14 PM PDT 24
Peak memory 200236 kb
Host smart-7e322b61-a0e7-4434-a6b8-264e5b1b9afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865605992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2865605992
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.216120789
Short name T1105
Test name
Test status
Simulation time 11568622 ps
CPU time 0.57 seconds
Started Mar 19 03:11:42 PM PDT 24
Finished Mar 19 03:11:43 PM PDT 24
Peak memory 195664 kb
Host smart-668ba9c2-4b01-4519-8837-63facfbb7939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216120789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.216120789
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.496574298
Short name T658
Test name
Test status
Simulation time 113908181015 ps
CPU time 50.75 seconds
Started Mar 19 03:11:43 PM PDT 24
Finished Mar 19 03:12:33 PM PDT 24
Peak memory 200148 kb
Host smart-a727fbd2-9f2e-4e95-befb-7ae2359826a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496574298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.496574298
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.790963678
Short name T398
Test name
Test status
Simulation time 41774003776 ps
CPU time 20.28 seconds
Started Mar 19 03:11:45 PM PDT 24
Finished Mar 19 03:12:05 PM PDT 24
Peak memory 200080 kb
Host smart-42e94901-a2ae-40a8-8a32-f6efab95a86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790963678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.790963678
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3208250687
Short name T852
Test name
Test status
Simulation time 103439875382 ps
CPU time 50.93 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:12:30 PM PDT 24
Peak memory 200072 kb
Host smart-f690e455-9399-4d5a-9402-856c33617e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208250687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3208250687
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1292016316
Short name T278
Test name
Test status
Simulation time 49390607046 ps
CPU time 42.41 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:12:22 PM PDT 24
Peak memory 200188 kb
Host smart-de5d0df9-9e1b-4df0-abeb-a14fb735ac13
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292016316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1292016316
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.698485576
Short name T567
Test name
Test status
Simulation time 52915606872 ps
CPU time 538.82 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:20:38 PM PDT 24
Peak memory 200204 kb
Host smart-8b3c750d-98c0-4067-a7e5-87bb588d1bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=698485576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.698485576
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.734684489
Short name T1067
Test name
Test status
Simulation time 7911095236 ps
CPU time 9.67 seconds
Started Mar 19 03:11:40 PM PDT 24
Finished Mar 19 03:11:50 PM PDT 24
Peak memory 199088 kb
Host smart-d72d8845-a773-4f0f-bd9e-62469de015c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734684489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.734684489
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1159157659
Short name T807
Test name
Test status
Simulation time 82367354998 ps
CPU time 139.48 seconds
Started Mar 19 03:11:39 PM PDT 24
Finished Mar 19 03:13:59 PM PDT 24
Peak memory 208596 kb
Host smart-cd5f1a58-d096-47d0-8f5d-83173d1c9001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159157659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1159157659
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3029678427
Short name T362
Test name
Test status
Simulation time 10362877209 ps
CPU time 283.5 seconds
Started Mar 19 03:11:42 PM PDT 24
Finished Mar 19 03:16:26 PM PDT 24
Peak memory 200180 kb
Host smart-32700f68-929c-4f66-a04e-b206f63f3384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029678427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3029678427
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2030525073
Short name T932
Test name
Test status
Simulation time 3162926059 ps
CPU time 6.04 seconds
Started Mar 19 03:11:42 PM PDT 24
Finished Mar 19 03:11:48 PM PDT 24
Peak memory 198356 kb
Host smart-3bdf8cfd-3642-490f-94a8-bb7827403a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030525073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2030525073
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.691873670
Short name T133
Test name
Test status
Simulation time 50994560911 ps
CPU time 38.79 seconds
Started Mar 19 03:11:40 PM PDT 24
Finished Mar 19 03:12:19 PM PDT 24
Peak memory 199660 kb
Host smart-0195a6cf-8977-44da-84e6-6699c7efbae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691873670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.691873670
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2130611252
Short name T513
Test name
Test status
Simulation time 79735989539 ps
CPU time 63.15 seconds
Started Mar 19 03:11:45 PM PDT 24
Finished Mar 19 03:12:48 PM PDT 24
Peak memory 195964 kb
Host smart-99c3550a-23ec-4521-81e5-aeb87581466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130611252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2130611252
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.798269178
Short name T927
Test name
Test status
Simulation time 887401696 ps
CPU time 3.71 seconds
Started Mar 19 03:11:42 PM PDT 24
Finished Mar 19 03:11:45 PM PDT 24
Peak memory 199980 kb
Host smart-6c2eeeca-81a3-4caf-82c0-abb22b026bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798269178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.798269178
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2171699189
Short name T266
Test name
Test status
Simulation time 223070611834 ps
CPU time 395.66 seconds
Started Mar 19 03:11:45 PM PDT 24
Finished Mar 19 03:18:21 PM PDT 24
Peak memory 208840 kb
Host smart-361b52dc-ed30-46f8-bfbf-f6f137052464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171699189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2171699189
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.781342415
Short name T826
Test name
Test status
Simulation time 8375896016 ps
CPU time 13.31 seconds
Started Mar 19 03:11:38 PM PDT 24
Finished Mar 19 03:11:52 PM PDT 24
Peak memory 200172 kb
Host smart-2dea8beb-0d18-446c-9bab-452ce4be4a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781342415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.781342415
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.4002300766
Short name T654
Test name
Test status
Simulation time 38279279822 ps
CPU time 15.19 seconds
Started Mar 19 03:11:47 PM PDT 24
Finished Mar 19 03:12:03 PM PDT 24
Peak memory 197856 kb
Host smart-bbc086b1-455d-46ae-bea2-c8925e67c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002300766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4002300766
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1938359423
Short name T344
Test name
Test status
Simulation time 19603010 ps
CPU time 0.57 seconds
Started Mar 19 03:11:51 PM PDT 24
Finished Mar 19 03:11:51 PM PDT 24
Peak memory 195644 kb
Host smart-3e7670ce-4459-42d0-bdfc-cf2cc40edb63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938359423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1938359423
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2935009276
Short name T111
Test name
Test status
Simulation time 131252620497 ps
CPU time 193.91 seconds
Started Mar 19 03:11:44 PM PDT 24
Finished Mar 19 03:14:58 PM PDT 24
Peak memory 200168 kb
Host smart-84a1724d-d03a-4e08-8c07-12de8e643141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935009276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2935009276
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1137047941
Short name T165
Test name
Test status
Simulation time 19284040009 ps
CPU time 30.63 seconds
Started Mar 19 03:11:36 PM PDT 24
Finished Mar 19 03:12:07 PM PDT 24
Peak memory 200212 kb
Host smart-7a1b4b26-5b12-4163-95b5-274df494b36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137047941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1137047941
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.707620708
Short name T58
Test name
Test status
Simulation time 17971511432 ps
CPU time 33.82 seconds
Started Mar 19 03:11:45 PM PDT 24
Finished Mar 19 03:12:19 PM PDT 24
Peak memory 200128 kb
Host smart-6df359d4-b309-462c-87f6-f72056f984fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707620708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.707620708
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1650400105
Short name T972
Test name
Test status
Simulation time 137300149065 ps
CPU time 235.26 seconds
Started Mar 19 03:11:43 PM PDT 24
Finished Mar 19 03:15:39 PM PDT 24
Peak memory 199244 kb
Host smart-63cc8daa-66d5-43ab-85fc-af5f4e2f17c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650400105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1650400105
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.607267945
Short name T258
Test name
Test status
Simulation time 67957076821 ps
CPU time 389.05 seconds
Started Mar 19 03:11:52 PM PDT 24
Finished Mar 19 03:18:21 PM PDT 24
Peak memory 200232 kb
Host smart-cf0ccca7-f6b6-4a49-bac9-7c0435babb28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607267945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.607267945
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.932580995
Short name T340
Test name
Test status
Simulation time 5514783990 ps
CPU time 10.52 seconds
Started Mar 19 03:11:50 PM PDT 24
Finished Mar 19 03:12:01 PM PDT 24
Peak memory 197760 kb
Host smart-decca2dc-9ae3-4671-aac6-b7aee9054f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932580995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.932580995
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3002038200
Short name T384
Test name
Test status
Simulation time 73965169527 ps
CPU time 43.37 seconds
Started Mar 19 03:11:47 PM PDT 24
Finished Mar 19 03:12:30 PM PDT 24
Peak memory 199548 kb
Host smart-e4f18b52-c085-4598-b3a7-7b9b60299932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002038200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3002038200
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.4178252192
Short name T868
Test name
Test status
Simulation time 13750508203 ps
CPU time 777.19 seconds
Started Mar 19 03:11:54 PM PDT 24
Finished Mar 19 03:24:51 PM PDT 24
Peak memory 200160 kb
Host smart-43d2b52e-063a-442b-84e5-8126fe306045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178252192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4178252192
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2738461496
Short name T357
Test name
Test status
Simulation time 4954912791 ps
CPU time 43.57 seconds
Started Mar 19 03:11:47 PM PDT 24
Finished Mar 19 03:12:31 PM PDT 24
Peak memory 197976 kb
Host smart-0b852c9a-c1d0-4b78-b05c-ede81cc17d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738461496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2738461496
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3692087266
Short name T563
Test name
Test status
Simulation time 61544490231 ps
CPU time 78.31 seconds
Started Mar 19 03:11:46 PM PDT 24
Finished Mar 19 03:13:05 PM PDT 24
Peak memory 200112 kb
Host smart-3877efbb-a451-444d-b0b9-558d2b4bd9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692087266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3692087266
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3631640210
Short name T540
Test name
Test status
Simulation time 4722275383 ps
CPU time 8.54 seconds
Started Mar 19 03:11:46 PM PDT 24
Finished Mar 19 03:11:55 PM PDT 24
Peak memory 196208 kb
Host smart-601533f5-3a3d-4e4c-94df-dde7774c981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631640210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3631640210
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2480078439
Short name T1005
Test name
Test status
Simulation time 11060089813 ps
CPU time 23.22 seconds
Started Mar 19 03:11:41 PM PDT 24
Finished Mar 19 03:12:04 PM PDT 24
Peak memory 199964 kb
Host smart-bb935122-c00f-4ab4-b3b6-2ef44e6f88d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480078439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2480078439
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2050453261
Short name T797
Test name
Test status
Simulation time 66632200951 ps
CPU time 274.98 seconds
Started Mar 19 03:11:49 PM PDT 24
Finished Mar 19 03:16:24 PM PDT 24
Peak memory 200192 kb
Host smart-17ab9d9e-e9b0-4bdd-abc7-0f97a5790d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050453261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2050453261
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1630140150
Short name T388
Test name
Test status
Simulation time 491364527 ps
CPU time 1.07 seconds
Started Mar 19 03:11:51 PM PDT 24
Finished Mar 19 03:11:52 PM PDT 24
Peak memory 197192 kb
Host smart-168abce5-b031-40d9-be17-b85ceedc678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630140150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1630140150
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3887092921
Short name T655
Test name
Test status
Simulation time 129183515539 ps
CPU time 49.69 seconds
Started Mar 19 03:11:42 PM PDT 24
Finished Mar 19 03:12:32 PM PDT 24
Peak memory 200180 kb
Host smart-9e0d56cd-e29b-4f54-b16b-c45c6d74fdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887092921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3887092921
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3104759736
Short name T965
Test name
Test status
Simulation time 12969606 ps
CPU time 0.54 seconds
Started Mar 19 03:11:50 PM PDT 24
Finished Mar 19 03:11:51 PM PDT 24
Peak memory 195660 kb
Host smart-6bb76037-a246-4e62-a93f-891eeacf46b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104759736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3104759736
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3663334356
Short name T1048
Test name
Test status
Simulation time 17000397542 ps
CPU time 15.92 seconds
Started Mar 19 03:11:54 PM PDT 24
Finished Mar 19 03:12:10 PM PDT 24
Peak memory 200148 kb
Host smart-610cbea5-6639-49f7-8d76-4e3050dd1dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663334356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3663334356
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2460671354
Short name T432
Test name
Test status
Simulation time 134515504581 ps
CPU time 292.81 seconds
Started Mar 19 03:11:54 PM PDT 24
Finished Mar 19 03:16:47 PM PDT 24
Peak memory 200196 kb
Host smart-456c73c2-f861-4260-ab81-e05be820b979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460671354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2460671354
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.139449962
Short name T430
Test name
Test status
Simulation time 76579743415 ps
CPU time 50.22 seconds
Started Mar 19 03:11:53 PM PDT 24
Finished Mar 19 03:12:43 PM PDT 24
Peak memory 200148 kb
Host smart-1cabf604-9afb-4fb8-b8b1-37bc49c85ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139449962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.139449962
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3166152635
Short name T541
Test name
Test status
Simulation time 7943745397 ps
CPU time 6.87 seconds
Started Mar 19 03:11:50 PM PDT 24
Finished Mar 19 03:11:57 PM PDT 24
Peak memory 196948 kb
Host smart-64205457-7394-41fd-a4fc-4c1820db5da5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166152635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3166152635
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1520449125
Short name T1063
Test name
Test status
Simulation time 81785399965 ps
CPU time 454.34 seconds
Started Mar 19 03:11:51 PM PDT 24
Finished Mar 19 03:19:25 PM PDT 24
Peak memory 200032 kb
Host smart-1aa673e4-dd84-45b5-a520-9856a3d0c946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520449125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1520449125
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.422186218
Short name T1086
Test name
Test status
Simulation time 5050143236 ps
CPU time 6 seconds
Started Mar 19 03:11:53 PM PDT 24
Finished Mar 19 03:11:59 PM PDT 24
Peak memory 199816 kb
Host smart-75760bf5-7f92-459c-9409-94835fdfc3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422186218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.422186218
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3209126327
Short name T672
Test name
Test status
Simulation time 1199150827 ps
CPU time 0.98 seconds
Started Mar 19 03:11:56 PM PDT 24
Finished Mar 19 03:11:57 PM PDT 24
Peak memory 195940 kb
Host smart-f8487748-06d4-4708-b608-dcd9d5051842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209126327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3209126327
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3897102505
Short name T616
Test name
Test status
Simulation time 16646947314 ps
CPU time 387.48 seconds
Started Mar 19 03:11:51 PM PDT 24
Finished Mar 19 03:18:19 PM PDT 24
Peak memory 200044 kb
Host smart-b579bbdb-dbfd-49e1-888b-7aec7762bce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897102505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3897102505
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2493110396
Short name T1064
Test name
Test status
Simulation time 6086565661 ps
CPU time 49.49 seconds
Started Mar 19 03:11:56 PM PDT 24
Finished Mar 19 03:12:46 PM PDT 24
Peak memory 199352 kb
Host smart-e2c3d6db-5e40-47c5-a509-4d59ac2807ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493110396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2493110396
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3559804065
Short name T790
Test name
Test status
Simulation time 17261079101 ps
CPU time 25.53 seconds
Started Mar 19 03:11:56 PM PDT 24
Finished Mar 19 03:12:21 PM PDT 24
Peak memory 199716 kb
Host smart-8d889e38-eb75-4b27-855b-1b175e7462dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559804065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3559804065
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1411804759
Short name T911
Test name
Test status
Simulation time 1606908110 ps
CPU time 2.98 seconds
Started Mar 19 03:11:51 PM PDT 24
Finished Mar 19 03:11:54 PM PDT 24
Peak memory 195700 kb
Host smart-ebed1749-c496-471d-9a69-10d98f79d525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411804759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1411804759
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4050763044
Short name T919
Test name
Test status
Simulation time 613303803 ps
CPU time 1.9 seconds
Started Mar 19 03:11:50 PM PDT 24
Finished Mar 19 03:11:52 PM PDT 24
Peak memory 198516 kb
Host smart-98ebe98f-f5a3-45e7-9dd0-b1198fbd04a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050763044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4050763044
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1286260941
Short name T247
Test name
Test status
Simulation time 87319198020 ps
CPU time 1736.47 seconds
Started Mar 19 03:11:49 PM PDT 24
Finished Mar 19 03:40:46 PM PDT 24
Peak memory 216652 kb
Host smart-866948ff-cc04-46e2-9d2e-7200e1ba2b14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286260941 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1286260941
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2573496761
Short name T682
Test name
Test status
Simulation time 1758002107 ps
CPU time 2.02 seconds
Started Mar 19 03:11:52 PM PDT 24
Finished Mar 19 03:11:55 PM PDT 24
Peak memory 198596 kb
Host smart-60bbd34c-5aa7-45a5-b794-b247081b14f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573496761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2573496761
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.4013075922
Short name T503
Test name
Test status
Simulation time 37292544120 ps
CPU time 32.81 seconds
Started Mar 19 03:11:50 PM PDT 24
Finished Mar 19 03:12:23 PM PDT 24
Peak memory 200120 kb
Host smart-b180d231-ed04-4427-92d9-f34bb373e0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013075922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.4013075922
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3463245502
Short name T454
Test name
Test status
Simulation time 20522800 ps
CPU time 0.56 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:12:06 PM PDT 24
Peak memory 195644 kb
Host smart-d173fe99-e1d8-40fd-9bfa-6b229b584535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463245502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3463245502
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.539639224
Short name T1001
Test name
Test status
Simulation time 214812559414 ps
CPU time 252.79 seconds
Started Mar 19 03:11:49 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 200232 kb
Host smart-caebc7d5-9d70-4de5-9ef4-5718ac024e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539639224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.539639224
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.177636778
Short name T1079
Test name
Test status
Simulation time 228478145546 ps
CPU time 152.49 seconds
Started Mar 19 03:11:54 PM PDT 24
Finished Mar 19 03:14:27 PM PDT 24
Peak memory 200224 kb
Host smart-95ac1e17-1471-46b1-80e5-e117f4edd57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177636778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.177636778
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2517699555
Short name T187
Test name
Test status
Simulation time 135231935156 ps
CPU time 195.01 seconds
Started Mar 19 03:11:52 PM PDT 24
Finished Mar 19 03:15:07 PM PDT 24
Peak memory 200260 kb
Host smart-bf8de0a2-52c5-4f9a-813c-97b3c60c65b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517699555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2517699555
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3504324121
Short name T256
Test name
Test status
Simulation time 12830742396 ps
CPU time 26.93 seconds
Started Mar 19 03:11:53 PM PDT 24
Finished Mar 19 03:12:20 PM PDT 24
Peak memory 200200 kb
Host smart-88befc33-3726-49c1-9ccd-282602d524ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504324121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3504324121
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2055121768
Short name T411
Test name
Test status
Simulation time 127973763028 ps
CPU time 259.5 seconds
Started Mar 19 03:11:59 PM PDT 24
Finished Mar 19 03:16:19 PM PDT 24
Peak memory 200176 kb
Host smart-addc935c-272f-4316-aedc-54fe7a4b14b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055121768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2055121768
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.4067137907
Short name T885
Test name
Test status
Simulation time 6458056868 ps
CPU time 11.68 seconds
Started Mar 19 03:11:58 PM PDT 24
Finished Mar 19 03:12:10 PM PDT 24
Peak memory 197728 kb
Host smart-040d1ad2-905b-4e24-883d-c74a5a84575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067137907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.4067137907
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.441277294
Short name T1065
Test name
Test status
Simulation time 33150000639 ps
CPU time 63.28 seconds
Started Mar 19 03:11:50 PM PDT 24
Finished Mar 19 03:12:53 PM PDT 24
Peak memory 200592 kb
Host smart-71787803-ecc9-4bb5-b0aa-1aa959e6caa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441277294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.441277294
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1258960779
Short name T312
Test name
Test status
Simulation time 2712045497 ps
CPU time 65.75 seconds
Started Mar 19 03:11:58 PM PDT 24
Finished Mar 19 03:13:04 PM PDT 24
Peak memory 200224 kb
Host smart-0b5570d4-7245-4c94-874e-19c3087d7ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258960779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1258960779
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.822211407
Short name T382
Test name
Test status
Simulation time 2896780589 ps
CPU time 2.58 seconds
Started Mar 19 03:11:52 PM PDT 24
Finished Mar 19 03:11:55 PM PDT 24
Peak memory 198272 kb
Host smart-99c99dc2-0be0-40b7-93c3-cac1ec0d4995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822211407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.822211407
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.177840331
Short name T950
Test name
Test status
Simulation time 220663243973 ps
CPU time 29.57 seconds
Started Mar 19 03:11:56 PM PDT 24
Finished Mar 19 03:12:26 PM PDT 24
Peak memory 200152 kb
Host smart-0e2e7bdf-f0af-4fa2-bece-991183c5ff9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177840331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.177840331
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.440686598
Short name T861
Test name
Test status
Simulation time 32509622028 ps
CPU time 41.06 seconds
Started Mar 19 03:11:51 PM PDT 24
Finished Mar 19 03:12:32 PM PDT 24
Peak memory 195964 kb
Host smart-6a5bbb3a-6813-4ec5-a508-cbe5cea7db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440686598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.440686598
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4182327926
Short name T653
Test name
Test status
Simulation time 635216323 ps
CPU time 2.08 seconds
Started Mar 19 03:11:50 PM PDT 24
Finished Mar 19 03:11:52 PM PDT 24
Peak memory 200008 kb
Host smart-37d9cc05-3da9-4208-a107-19016940fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182327926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4182327926
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2984185807
Short name T1020
Test name
Test status
Simulation time 395257232 ps
CPU time 1.42 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:12:08 PM PDT 24
Peak memory 198624 kb
Host smart-9dc144b7-a1af-4940-b567-31aa375ffa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984185807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2984185807
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1130684995
Short name T1026
Test name
Test status
Simulation time 19298720719 ps
CPU time 29.49 seconds
Started Mar 19 03:11:52 PM PDT 24
Finished Mar 19 03:12:21 PM PDT 24
Peak memory 200148 kb
Host smart-da39b278-de8f-421e-85ea-aedca582bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130684995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1130684995
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.506824699
Short name T29
Test name
Test status
Simulation time 14467842 ps
CPU time 0.53 seconds
Started Mar 19 03:12:05 PM PDT 24
Finished Mar 19 03:12:05 PM PDT 24
Peak memory 195664 kb
Host smart-e4989f60-0a0d-4c5b-ad9c-df2b7603f738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506824699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.506824699
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2603740167
Short name T674
Test name
Test status
Simulation time 97837693356 ps
CPU time 246.24 seconds
Started Mar 19 03:11:56 PM PDT 24
Finished Mar 19 03:16:03 PM PDT 24
Peak memory 200172 kb
Host smart-698fd853-a54e-495f-8ec1-519f7c85730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603740167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2603740167
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.657680876
Short name T660
Test name
Test status
Simulation time 52361160660 ps
CPU time 101.28 seconds
Started Mar 19 03:11:57 PM PDT 24
Finished Mar 19 03:13:39 PM PDT 24
Peak memory 200184 kb
Host smart-cb671295-7e33-49fd-83e8-f19f1cf3e0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657680876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.657680876
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.60303600
Short name T206
Test name
Test status
Simulation time 98656304092 ps
CPU time 16.21 seconds
Started Mar 19 03:12:04 PM PDT 24
Finished Mar 19 03:12:20 PM PDT 24
Peak memory 200128 kb
Host smart-41382522-f8e7-4ab1-8e9d-a98ef730c26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60303600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.60303600
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1485103240
Short name T787
Test name
Test status
Simulation time 60287102026 ps
CPU time 111.29 seconds
Started Mar 19 03:11:58 PM PDT 24
Finished Mar 19 03:13:50 PM PDT 24
Peak memory 200244 kb
Host smart-fc44581f-f93a-4f42-8c5d-c931c13f62bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485103240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1485103240
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3795535312
Short name T734
Test name
Test status
Simulation time 75497829785 ps
CPU time 195.91 seconds
Started Mar 19 03:12:02 PM PDT 24
Finished Mar 19 03:15:18 PM PDT 24
Peak memory 200192 kb
Host smart-ea157b58-be3c-451c-becd-108abdc95d3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795535312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3795535312
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1420666773
Short name T558
Test name
Test status
Simulation time 9015333458 ps
CPU time 13.17 seconds
Started Mar 19 03:11:59 PM PDT 24
Finished Mar 19 03:12:12 PM PDT 24
Peak memory 200176 kb
Host smart-14212c9e-24e5-4617-bef2-95bacf8e45d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420666773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1420666773
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2659005838
Short name T685
Test name
Test status
Simulation time 153488483056 ps
CPU time 109.7 seconds
Started Mar 19 03:11:56 PM PDT 24
Finished Mar 19 03:13:46 PM PDT 24
Peak memory 216176 kb
Host smart-f3448adf-1f4d-4c0d-b61d-e0dd17e00701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659005838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2659005838
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.566392687
Short name T459
Test name
Test status
Simulation time 16586127396 ps
CPU time 167.97 seconds
Started Mar 19 03:12:04 PM PDT 24
Finished Mar 19 03:14:52 PM PDT 24
Peak memory 200180 kb
Host smart-21a026fb-b36b-44d9-9c26-69979a7d11ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=566392687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.566392687
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.423137837
Short name T1040
Test name
Test status
Simulation time 6725052633 ps
CPU time 13.91 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:12:21 PM PDT 24
Peak memory 199304 kb
Host smart-4cf9e498-124b-4404-abd4-2ed0383e9f8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423137837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.423137837
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1858883977
Short name T926
Test name
Test status
Simulation time 119891027451 ps
CPU time 104.63 seconds
Started Mar 19 03:11:58 PM PDT 24
Finished Mar 19 03:13:42 PM PDT 24
Peak memory 200156 kb
Host smart-0eac87b4-145f-406e-9365-a81748542c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858883977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1858883977
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1113666282
Short name T603
Test name
Test status
Simulation time 4298686516 ps
CPU time 3.99 seconds
Started Mar 19 03:12:07 PM PDT 24
Finished Mar 19 03:12:11 PM PDT 24
Peak memory 196532 kb
Host smart-ae112190-eb3e-4ec1-a208-dfd1d1b96a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113666282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1113666282
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3094258761
Short name T606
Test name
Test status
Simulation time 6048258431 ps
CPU time 9.67 seconds
Started Mar 19 03:11:57 PM PDT 24
Finished Mar 19 03:12:07 PM PDT 24
Peak memory 200000 kb
Host smart-042d852b-464d-43dd-ae03-d7d1467425b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094258761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3094258761
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1432557828
Short name T322
Test name
Test status
Simulation time 38470932586 ps
CPU time 48.82 seconds
Started Mar 19 03:11:58 PM PDT 24
Finished Mar 19 03:12:47 PM PDT 24
Peak memory 200064 kb
Host smart-87bd8295-2b05-49fa-9236-d3e134cfa19a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432557828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1432557828
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.4267136570
Short name T916
Test name
Test status
Simulation time 1164969821 ps
CPU time 2.33 seconds
Started Mar 19 03:11:58 PM PDT 24
Finished Mar 19 03:12:01 PM PDT 24
Peak memory 198616 kb
Host smart-34c1cf23-3388-4bc3-b522-ce211af99a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267136570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4267136570
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.4150550214
Short name T93
Test name
Test status
Simulation time 83956025771 ps
CPU time 15.27 seconds
Started Mar 19 03:11:59 PM PDT 24
Finished Mar 19 03:12:14 PM PDT 24
Peak memory 197388 kb
Host smart-a6575cb0-9d01-4cff-a95c-179656c7497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150550214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.4150550214
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.326139554
Short name T600
Test name
Test status
Simulation time 33833026 ps
CPU time 0.57 seconds
Started Mar 19 03:12:07 PM PDT 24
Finished Mar 19 03:12:08 PM PDT 24
Peak memory 195576 kb
Host smart-311c12ee-abb6-4fbb-9e7c-6280bc2bd233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326139554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.326139554
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3880570898
Short name T815
Test name
Test status
Simulation time 85748074503 ps
CPU time 35.28 seconds
Started Mar 19 03:12:01 PM PDT 24
Finished Mar 19 03:12:36 PM PDT 24
Peak memory 200148 kb
Host smart-110ac710-ae2a-4772-bdf1-c35990e01fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880570898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3880570898
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1208961924
Short name T57
Test name
Test status
Simulation time 117344803415 ps
CPU time 198.41 seconds
Started Mar 19 03:12:02 PM PDT 24
Finished Mar 19 03:15:21 PM PDT 24
Peak memory 200012 kb
Host smart-8c7718f6-7c05-4395-948f-09f78281b8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208961924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1208961924
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.1602598602
Short name T298
Test name
Test status
Simulation time 181541014796 ps
CPU time 78.53 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:13:25 PM PDT 24
Peak memory 200120 kb
Host smart-6598b1cd-e6aa-4b6e-90bb-4dce63377b12
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602598602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1602598602
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1973943515
Short name T508
Test name
Test status
Simulation time 93587059427 ps
CPU time 282.46 seconds
Started Mar 19 03:12:08 PM PDT 24
Finished Mar 19 03:16:51 PM PDT 24
Peak memory 200132 kb
Host smart-a240c7a1-01e8-47a7-8042-035a26ad5041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973943515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1973943515
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2614312044
Short name T342
Test name
Test status
Simulation time 1072630655 ps
CPU time 1.4 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:12:08 PM PDT 24
Peak memory 198312 kb
Host smart-f45e580a-ff0a-4243-bee2-18d5e45e5d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614312044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2614312044
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.4186265132
Short name T944
Test name
Test status
Simulation time 124308028633 ps
CPU time 205.05 seconds
Started Mar 19 03:11:56 PM PDT 24
Finished Mar 19 03:15:22 PM PDT 24
Peak memory 199388 kb
Host smart-f5318284-e32e-4133-ac3b-80f8826020eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186265132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.4186265132
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1793358648
Short name T726
Test name
Test status
Simulation time 3998713810 ps
CPU time 56.46 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:13:03 PM PDT 24
Peak memory 200116 kb
Host smart-4b42831f-d1a1-4a67-aab1-2cb45a964932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793358648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1793358648
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2821808319
Short name T1092
Test name
Test status
Simulation time 1589686570 ps
CPU time 3.38 seconds
Started Mar 19 03:12:08 PM PDT 24
Finished Mar 19 03:12:11 PM PDT 24
Peak memory 198092 kb
Host smart-8634cf0d-7cca-43c2-8b18-593adbce1702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821808319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2821808319
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1512270880
Short name T741
Test name
Test status
Simulation time 66797682587 ps
CPU time 16.56 seconds
Started Mar 19 03:11:59 PM PDT 24
Finished Mar 19 03:12:16 PM PDT 24
Peak memory 200160 kb
Host smart-d4d2369a-c3b8-4638-98e6-ce08b9451718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512270880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1512270880
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.4105552087
Short name T5
Test name
Test status
Simulation time 514551918 ps
CPU time 1 seconds
Started Mar 19 03:11:57 PM PDT 24
Finished Mar 19 03:11:58 PM PDT 24
Peak memory 195648 kb
Host smart-7fcb58bd-c6e4-44a5-ba49-00cb22e0d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105552087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.4105552087
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.4010561815
Short name T688
Test name
Test status
Simulation time 290163021 ps
CPU time 0.99 seconds
Started Mar 19 03:12:01 PM PDT 24
Finished Mar 19 03:12:02 PM PDT 24
Peak memory 198792 kb
Host smart-183ba9b1-47f1-4ade-935b-0f3d0e6a70f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010561815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.4010561815
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.582940326
Short name T1078
Test name
Test status
Simulation time 311206310642 ps
CPU time 169.61 seconds
Started Mar 19 03:12:07 PM PDT 24
Finished Mar 19 03:14:57 PM PDT 24
Peak memory 200176 kb
Host smart-0426cefd-4f09-45b3-9e85-ea4548e6094b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582940326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.582940326
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1958849787
Short name T550
Test name
Test status
Simulation time 721357028 ps
CPU time 2.43 seconds
Started Mar 19 03:12:01 PM PDT 24
Finished Mar 19 03:12:03 PM PDT 24
Peak memory 198780 kb
Host smart-f75d724f-bd96-4128-b82b-62fb9e75fe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958849787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1958849787
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3340949525
Short name T853
Test name
Test status
Simulation time 189841380018 ps
CPU time 165.29 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:14:51 PM PDT 24
Peak memory 200164 kb
Host smart-ee75cf31-3495-4004-90c0-688aad3bc288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340949525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3340949525
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.237352892
Short name T535
Test name
Test status
Simulation time 44436837 ps
CPU time 0.6 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:09:34 PM PDT 24
Peak memory 195000 kb
Host smart-d58d7e6b-0d0e-43a0-b237-86759116e62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237352892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.237352892
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1508143574
Short name T59
Test name
Test status
Simulation time 26354195463 ps
CPU time 42.65 seconds
Started Mar 19 03:09:31 PM PDT 24
Finished Mar 19 03:10:14 PM PDT 24
Peak memory 200212 kb
Host smart-06591ea5-4351-4408-968f-8538ed3d6b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508143574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1508143574
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3006754790
Short name T758
Test name
Test status
Simulation time 39824884580 ps
CPU time 66.6 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:10:36 PM PDT 24
Peak memory 200176 kb
Host smart-97d3f8ba-332b-40f2-9e30-5343a010ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006754790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3006754790
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3065046843
Short name T925
Test name
Test status
Simulation time 17896763051 ps
CPU time 35.02 seconds
Started Mar 19 03:09:28 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 200128 kb
Host smart-c494017c-1d53-44a3-81ec-ef139ffa57f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065046843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3065046843
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2964742989
Short name T474
Test name
Test status
Simulation time 6784292937 ps
CPU time 11.93 seconds
Started Mar 19 03:09:29 PM PDT 24
Finished Mar 19 03:09:42 PM PDT 24
Peak memory 197272 kb
Host smart-5fc41772-7424-4ff3-8d9d-1fbe9e251ced
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964742989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2964742989
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.526829771
Short name T423
Test name
Test status
Simulation time 178149173979 ps
CPU time 487.61 seconds
Started Mar 19 03:09:29 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 200136 kb
Host smart-00eabb53-8663-4ba9-9b13-15872accb489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526829771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.526829771
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.423091212
Short name T592
Test name
Test status
Simulation time 7215451650 ps
CPU time 4.64 seconds
Started Mar 19 03:09:28 PM PDT 24
Finished Mar 19 03:09:32 PM PDT 24
Peak memory 199788 kb
Host smart-2765e42a-0868-40cc-918b-fd9893b6a8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423091212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.423091212
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2021622633
Short name T547
Test name
Test status
Simulation time 42113238699 ps
CPU time 36.83 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 199328 kb
Host smart-7735dbc9-0899-499f-be1a-60455f0718d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021622633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2021622633
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3212957884
Short name T669
Test name
Test status
Simulation time 17502425161 ps
CPU time 277.3 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:14:05 PM PDT 24
Peak memory 200152 kb
Host smart-6997262e-7caa-4d50-8ff2-537e0f82526a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212957884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3212957884
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.369619804
Short name T1073
Test name
Test status
Simulation time 1682788788 ps
CPU time 6.08 seconds
Started Mar 19 03:09:25 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 198260 kb
Host smart-23c50cf8-5b35-4417-bfc2-573ec9738268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369619804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.369619804
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3561112838
Short name T1088
Test name
Test status
Simulation time 52695741521 ps
CPU time 73.89 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:10:41 PM PDT 24
Peak memory 200224 kb
Host smart-e5360823-7633-41ba-9551-710c2c8461a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561112838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3561112838
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4023588147
Short name T566
Test name
Test status
Simulation time 3436553099 ps
CPU time 1.18 seconds
Started Mar 19 03:09:25 PM PDT 24
Finished Mar 19 03:09:26 PM PDT 24
Peak memory 196312 kb
Host smart-6de688ec-b75a-465f-ab42-763ccd8abfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023588147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4023588147
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2861264590
Short name T397
Test name
Test status
Simulation time 122861998 ps
CPU time 0.76 seconds
Started Mar 19 03:09:28 PM PDT 24
Finished Mar 19 03:09:29 PM PDT 24
Peak memory 197320 kb
Host smart-c488454b-0392-4ab5-a903-7abbd7a371ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861264590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2861264590
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3998235190
Short name T670
Test name
Test status
Simulation time 574188825 ps
CPU time 2.97 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:09:33 PM PDT 24
Peak memory 199248 kb
Host smart-f79d9e28-9e35-41c0-ba74-d4996943b66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998235190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3998235190
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3406741349
Short name T1034
Test name
Test status
Simulation time 379029576266 ps
CPU time 76.55 seconds
Started Mar 19 03:09:47 PM PDT 24
Finished Mar 19 03:11:03 PM PDT 24
Peak memory 200148 kb
Host smart-eeb6cba2-0452-422f-99e3-b31dadc581a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406741349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3406741349
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1265795357
Short name T740
Test name
Test status
Simulation time 81025283301 ps
CPU time 64.94 seconds
Started Mar 19 03:12:08 PM PDT 24
Finished Mar 19 03:13:14 PM PDT 24
Peak memory 200140 kb
Host smart-241af518-4997-418c-bd95-421df1dbc1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265795357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1265795357
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2901912474
Short name T617
Test name
Test status
Simulation time 23412700005 ps
CPU time 41.94 seconds
Started Mar 19 03:12:11 PM PDT 24
Finished Mar 19 03:12:53 PM PDT 24
Peak memory 200128 kb
Host smart-a9cb09a5-24c0-4bb4-864f-38b23416b03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901912474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2901912474
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.887447480
Short name T751
Test name
Test status
Simulation time 8772616034 ps
CPU time 16.86 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:12:23 PM PDT 24
Peak memory 200224 kb
Host smart-3186f15b-68b0-44d8-b89c-68f4c17da02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887447480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.887447480
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3978284953
Short name T614
Test name
Test status
Simulation time 105803479020 ps
CPU time 28.6 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:12:35 PM PDT 24
Peak memory 200072 kb
Host smart-a5410287-52c9-4f39-9fbe-316db95ec04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978284953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3978284953
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2057273656
Short name T333
Test name
Test status
Simulation time 81310320301 ps
CPU time 30.26 seconds
Started Mar 19 03:12:10 PM PDT 24
Finished Mar 19 03:12:40 PM PDT 24
Peak memory 200228 kb
Host smart-e7c23b9f-f751-434e-8488-56b0573a8b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057273656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2057273656
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3642216772
Short name T899
Test name
Test status
Simulation time 101399745531 ps
CPU time 174.5 seconds
Started Mar 19 03:12:07 PM PDT 24
Finished Mar 19 03:15:02 PM PDT 24
Peak memory 200100 kb
Host smart-914ffe42-581c-455b-977d-91dc87497ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642216772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3642216772
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3185268678
Short name T223
Test name
Test status
Simulation time 79902453232 ps
CPU time 36.29 seconds
Started Mar 19 03:12:11 PM PDT 24
Finished Mar 19 03:12:47 PM PDT 24
Peak memory 200144 kb
Host smart-265795a0-b53d-490d-a470-553a4305b6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185268678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3185268678
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2676433151
Short name T1100
Test name
Test status
Simulation time 57531874320 ps
CPU time 47.25 seconds
Started Mar 19 03:12:10 PM PDT 24
Finished Mar 19 03:12:58 PM PDT 24
Peak memory 199820 kb
Host smart-b556fd5f-e940-4ef9-aea2-47952fc255a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676433151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2676433151
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.204353829
Short name T793
Test name
Test status
Simulation time 64328268437 ps
CPU time 357.79 seconds
Started Mar 19 03:12:09 PM PDT 24
Finished Mar 19 03:18:07 PM PDT 24
Peak memory 216648 kb
Host smart-1bd7b616-28f5-4af7-be0b-a6f8b537738d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204353829 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.204353829
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2060565875
Short name T949
Test name
Test status
Simulation time 89617172171 ps
CPU time 73.04 seconds
Started Mar 19 03:12:07 PM PDT 24
Finished Mar 19 03:13:20 PM PDT 24
Peak memory 200200 kb
Host smart-f48a6f2c-aeb3-4fb6-90b9-9166dbf8d32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060565875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2060565875
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.301634786
Short name T39
Test name
Test status
Simulation time 90791064305 ps
CPU time 478.52 seconds
Started Mar 19 03:12:06 PM PDT 24
Finished Mar 19 03:20:05 PM PDT 24
Peak memory 212528 kb
Host smart-f4ace30d-59ac-4b3b-bdcc-ed60cf53973f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301634786 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.301634786
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.843429780
Short name T321
Test name
Test status
Simulation time 99922890902 ps
CPU time 127.97 seconds
Started Mar 19 03:12:07 PM PDT 24
Finished Mar 19 03:14:15 PM PDT 24
Peak memory 200032 kb
Host smart-17690823-550d-4fae-944b-e7a624a26dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843429780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.843429780
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.498786176
Short name T350
Test name
Test status
Simulation time 12825005 ps
CPU time 0.57 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:09:34 PM PDT 24
Peak memory 195576 kb
Host smart-f66397e3-8732-4ead-9c29-9eacf9ba7537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498786176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.498786176
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.4150686809
Short name T1033
Test name
Test status
Simulation time 39212917876 ps
CPU time 14.47 seconds
Started Mar 19 03:09:26 PM PDT 24
Finished Mar 19 03:09:41 PM PDT 24
Peak memory 199120 kb
Host smart-5d7ba231-c8de-405a-beff-e62935dd8a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150686809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4150686809
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.4214230249
Short name T772
Test name
Test status
Simulation time 40364732615 ps
CPU time 19.6 seconds
Started Mar 19 03:09:34 PM PDT 24
Finished Mar 19 03:09:54 PM PDT 24
Peak memory 199976 kb
Host smart-550b4b75-39f0-4ab1-bc7c-09c041194122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214230249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4214230249
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.1217953244
Short name T252
Test name
Test status
Simulation time 28382405052 ps
CPU time 27.04 seconds
Started Mar 19 03:09:31 PM PDT 24
Finished Mar 19 03:09:58 PM PDT 24
Peak memory 199364 kb
Host smart-6692c372-fa89-4c98-a50b-f6e1e4f422d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217953244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1217953244
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1798011926
Short name T375
Test name
Test status
Simulation time 61110451185 ps
CPU time 207.66 seconds
Started Mar 19 03:09:38 PM PDT 24
Finished Mar 19 03:13:06 PM PDT 24
Peak memory 200180 kb
Host smart-e696d99f-ea1d-4bf2-b461-02932e66aa4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798011926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1798011926
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2577055548
Short name T864
Test name
Test status
Simulation time 1768128050 ps
CPU time 1.28 seconds
Started Mar 19 03:09:34 PM PDT 24
Finished Mar 19 03:09:36 PM PDT 24
Peak memory 197736 kb
Host smart-1064cc7b-72d4-4c60-b38b-7d454eb4c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577055548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2577055548
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1156304893
Short name T1077
Test name
Test status
Simulation time 24575865850 ps
CPU time 37.71 seconds
Started Mar 19 03:09:29 PM PDT 24
Finished Mar 19 03:10:08 PM PDT 24
Peak memory 196780 kb
Host smart-a49cf8ae-cc76-4d7f-ab01-a2e51e0eb46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156304893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1156304893
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3370948288
Short name T694
Test name
Test status
Simulation time 21726065534 ps
CPU time 246.59 seconds
Started Mar 19 03:09:35 PM PDT 24
Finished Mar 19 03:13:43 PM PDT 24
Peak memory 200236 kb
Host smart-db060af9-57ab-42b7-bb1d-47f696edb5be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370948288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3370948288
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1143795212
Short name T928
Test name
Test status
Simulation time 7719985262 ps
CPU time 9.49 seconds
Started Mar 19 03:09:31 PM PDT 24
Finished Mar 19 03:09:40 PM PDT 24
Peak memory 199048 kb
Host smart-20936b6b-731f-4ee6-beaa-4d076208e77d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143795212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1143795212
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2249356568
Short name T829
Test name
Test status
Simulation time 82065287972 ps
CPU time 142.18 seconds
Started Mar 19 03:09:34 PM PDT 24
Finished Mar 19 03:11:57 PM PDT 24
Peak memory 200164 kb
Host smart-c1964731-5451-4753-9f7e-6aa681c65039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249356568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2249356568
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1410317638
Short name T795
Test name
Test status
Simulation time 27705917907 ps
CPU time 41.94 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:10:15 PM PDT 24
Peak memory 196256 kb
Host smart-3ac4d399-2575-437e-83d3-6fbfecb8fcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410317638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1410317638
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1080263423
Short name T800
Test name
Test status
Simulation time 266161760 ps
CPU time 1.46 seconds
Started Mar 19 03:09:31 PM PDT 24
Finished Mar 19 03:09:32 PM PDT 24
Peak memory 200104 kb
Host smart-542b2df9-56c4-4f38-8a0b-8dcba1728329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080263423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1080263423
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1937628891
Short name T17
Test name
Test status
Simulation time 102179017680 ps
CPU time 88.32 seconds
Started Mar 19 03:09:38 PM PDT 24
Finished Mar 19 03:11:07 PM PDT 24
Peak memory 200172 kb
Host smart-3cd5687f-95c3-4481-b025-8d662d5287a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937628891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1937628891
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1916499593
Short name T723
Test name
Test status
Simulation time 611492950 ps
CPU time 2.11 seconds
Started Mar 19 03:09:36 PM PDT 24
Finished Mar 19 03:09:39 PM PDT 24
Peak memory 198856 kb
Host smart-afad4580-739a-4b90-9a18-d4ddbebdc61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916499593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1916499593
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2212364139
Short name T625
Test name
Test status
Simulation time 29880926845 ps
CPU time 56.03 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:10:27 PM PDT 24
Peak memory 200208 kb
Host smart-2feca246-c5ab-4d43-b2cd-72da3f0bd0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212364139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2212364139
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.504668363
Short name T602
Test name
Test status
Simulation time 24731883150 ps
CPU time 10.63 seconds
Started Mar 19 03:12:19 PM PDT 24
Finished Mar 19 03:12:30 PM PDT 24
Peak memory 200168 kb
Host smart-5d1b8a97-dfb9-4cf1-9191-bbc7724fdec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504668363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.504668363
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.788481552
Short name T988
Test name
Test status
Simulation time 63809756773 ps
CPU time 23.92 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:12:39 PM PDT 24
Peak memory 200164 kb
Host smart-d7d127a5-418e-42f1-8407-9628ebec4301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788481552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.788481552
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.643266547
Short name T722
Test name
Test status
Simulation time 36365541497 ps
CPU time 78.7 seconds
Started Mar 19 03:12:19 PM PDT 24
Finished Mar 19 03:13:38 PM PDT 24
Peak memory 200188 kb
Host smart-3f429b00-1d54-443d-ae62-f0650d733e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643266547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.643266547
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2508441224
Short name T52
Test name
Test status
Simulation time 117115187815 ps
CPU time 1134.98 seconds
Started Mar 19 03:12:16 PM PDT 24
Finished Mar 19 03:31:11 PM PDT 24
Peak memory 216676 kb
Host smart-87ee8706-d0c7-4614-b434-11993f715b24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508441224 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2508441224
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3384890428
Short name T526
Test name
Test status
Simulation time 34697009791 ps
CPU time 39.5 seconds
Started Mar 19 03:12:17 PM PDT 24
Finished Mar 19 03:12:57 PM PDT 24
Peak memory 200132 kb
Host smart-3a033a62-666d-480c-af3e-96ad72c877fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384890428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3384890428
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.793678172
Short name T718
Test name
Test status
Simulation time 104235726437 ps
CPU time 188.64 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:15:24 PM PDT 24
Peak memory 200140 kb
Host smart-34450fe9-2369-4145-9995-7834d69f0c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793678172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.793678172
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.4114401935
Short name T150
Test name
Test status
Simulation time 80379484273 ps
CPU time 16.74 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:12:32 PM PDT 24
Peak memory 200108 kb
Host smart-700f40d2-159c-4fd0-a5d1-6b4af10ffd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114401935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4114401935
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2657878445
Short name T277
Test name
Test status
Simulation time 17219220391 ps
CPU time 43.61 seconds
Started Mar 19 03:12:17 PM PDT 24
Finished Mar 19 03:13:01 PM PDT 24
Peak memory 200160 kb
Host smart-28d37693-d457-474a-9614-488c470261ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657878445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2657878445
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3875774604
Short name T40
Test name
Test status
Simulation time 145169511730 ps
CPU time 660.65 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:23:15 PM PDT 24
Peak memory 216688 kb
Host smart-dce708a6-6ede-4cab-bf31-76d7e7b61c57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875774604 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3875774604
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3820839521
Short name T890
Test name
Test status
Simulation time 202480318961 ps
CPU time 57.63 seconds
Started Mar 19 03:12:16 PM PDT 24
Finished Mar 19 03:13:14 PM PDT 24
Peak memory 200128 kb
Host smart-9f23ddc1-eb60-4cac-91f4-af610befffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820839521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3820839521
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3799771942
Short name T505
Test name
Test status
Simulation time 27373195 ps
CPU time 0.58 seconds
Started Mar 19 03:09:32 PM PDT 24
Finished Mar 19 03:09:33 PM PDT 24
Peak memory 195664 kb
Host smart-709d7a2b-43bd-43e7-9a7d-333d7ca992c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799771942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3799771942
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.834864287
Short name T831
Test name
Test status
Simulation time 141006112739 ps
CPU time 285.68 seconds
Started Mar 19 03:09:40 PM PDT 24
Finished Mar 19 03:14:25 PM PDT 24
Peak memory 200164 kb
Host smart-d472c543-dcca-458a-981a-c4b6dcbc8808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834864287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.834864287
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3702823632
Short name T253
Test name
Test status
Simulation time 126835640121 ps
CPU time 20.51 seconds
Started Mar 19 03:09:43 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 200132 kb
Host smart-2eb2b774-7fbb-400e-af7a-1e56c3723c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702823632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3702823632
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1833626916
Short name T804
Test name
Test status
Simulation time 96074494077 ps
CPU time 151.71 seconds
Started Mar 19 03:09:37 PM PDT 24
Finished Mar 19 03:12:09 PM PDT 24
Peak memory 200128 kb
Host smart-8c24266e-44f3-42be-9865-1e34d7305d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833626916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1833626916
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3944482561
Short name T431
Test name
Test status
Simulation time 28925103015 ps
CPU time 28.72 seconds
Started Mar 19 03:09:36 PM PDT 24
Finished Mar 19 03:10:05 PM PDT 24
Peak memory 200128 kb
Host smart-098718a0-a0d1-43ca-8d49-5251b38a0ba7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944482561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3944482561
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.269843600
Short name T458
Test name
Test status
Simulation time 105877083187 ps
CPU time 1172.19 seconds
Started Mar 19 03:09:35 PM PDT 24
Finished Mar 19 03:29:09 PM PDT 24
Peak memory 200164 kb
Host smart-f251639c-71f5-4ec0-9b6f-f2fabcf9f72f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=269843600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.269843600
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.4103956313
Short name T891
Test name
Test status
Simulation time 7002856122 ps
CPU time 7.5 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:09:41 PM PDT 24
Peak memory 200044 kb
Host smart-dbc2c0e1-5b40-4f3a-8d06-4407c82c72fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103956313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.4103956313
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3035079402
Short name T509
Test name
Test status
Simulation time 107931102960 ps
CPU time 224.84 seconds
Started Mar 19 03:09:38 PM PDT 24
Finished Mar 19 03:13:24 PM PDT 24
Peak memory 200176 kb
Host smart-0f79ec38-2a59-42c6-bdd1-39be9d8e0ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035079402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3035079402
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2242772160
Short name T552
Test name
Test status
Simulation time 17224436003 ps
CPU time 918.25 seconds
Started Mar 19 03:09:43 PM PDT 24
Finished Mar 19 03:25:02 PM PDT 24
Peak memory 200108 kb
Host smart-b390f0eb-9367-404b-b670-b44fcddf5491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242772160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2242772160
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.334073579
Short name T686
Test name
Test status
Simulation time 4506522858 ps
CPU time 34.37 seconds
Started Mar 19 03:09:43 PM PDT 24
Finished Mar 19 03:10:18 PM PDT 24
Peak memory 199376 kb
Host smart-c2d24409-6fda-4f7f-85f8-67d67136f1a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334073579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.334073579
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2647941770
Short name T160
Test name
Test status
Simulation time 63433218390 ps
CPU time 24.17 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:09:57 PM PDT 24
Peak memory 200200 kb
Host smart-d1762c18-2084-4934-a317-5fc760bc87c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647941770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2647941770
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3754656847
Short name T789
Test name
Test status
Simulation time 3242538619 ps
CPU time 3.09 seconds
Started Mar 19 03:09:34 PM PDT 24
Finished Mar 19 03:09:38 PM PDT 24
Peak memory 196320 kb
Host smart-1453543a-cea1-4e02-81e0-6c8dee4eca21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754656847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3754656847
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.4262679325
Short name T519
Test name
Test status
Simulation time 5571413909 ps
CPU time 8.63 seconds
Started Mar 19 03:09:37 PM PDT 24
Finished Mar 19 03:09:46 PM PDT 24
Peak memory 200112 kb
Host smart-0696e202-8c69-43cd-bab7-569195246d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262679325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4262679325
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.4178252831
Short name T217
Test name
Test status
Simulation time 87008348384 ps
CPU time 145.18 seconds
Started Mar 19 03:09:47 PM PDT 24
Finished Mar 19 03:12:13 PM PDT 24
Peak memory 200216 kb
Host smart-60d38e5e-12b4-4024-9ebe-3fe9bdbf3a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178252831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.4178252831
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1675346483
Short name T34
Test name
Test status
Simulation time 130279557138 ps
CPU time 380.98 seconds
Started Mar 19 03:09:44 PM PDT 24
Finished Mar 19 03:16:05 PM PDT 24
Peak memory 216628 kb
Host smart-c6d5aa4b-25ae-48ad-b45a-08d3438e4423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675346483 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1675346483
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2487697110
Short name T725
Test name
Test status
Simulation time 3159563632 ps
CPU time 1.65 seconds
Started Mar 19 03:09:36 PM PDT 24
Finished Mar 19 03:09:38 PM PDT 24
Peak memory 198904 kb
Host smart-911dad41-bc6e-489a-b917-d6509b44223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487697110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2487697110
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2979069751
Short name T1000
Test name
Test status
Simulation time 22129678750 ps
CPU time 10.82 seconds
Started Mar 19 03:09:38 PM PDT 24
Finished Mar 19 03:09:49 PM PDT 24
Peak memory 200060 kb
Host smart-349ef672-ecd1-4ed8-9632-53d636233c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979069751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2979069751
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1272830770
Short name T500
Test name
Test status
Simulation time 72600393921 ps
CPU time 29.21 seconds
Started Mar 19 03:12:16 PM PDT 24
Finished Mar 19 03:12:45 PM PDT 24
Peak memory 200112 kb
Host smart-78196cc2-daec-4f89-a79d-ec371b779b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272830770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1272830770
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2722315925
Short name T199
Test name
Test status
Simulation time 56954442859 ps
CPU time 47.05 seconds
Started Mar 19 03:12:16 PM PDT 24
Finished Mar 19 03:13:03 PM PDT 24
Peak memory 200156 kb
Host smart-6a9a2b2b-50d0-4733-b788-33275bf7f037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722315925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2722315925
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1584780454
Short name T197
Test name
Test status
Simulation time 17938756943 ps
CPU time 32.44 seconds
Started Mar 19 03:12:16 PM PDT 24
Finished Mar 19 03:12:49 PM PDT 24
Peak memory 200204 kb
Host smart-666b6230-4071-4d1e-8780-877eedbbbdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584780454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1584780454
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1840876831
Short name T413
Test name
Test status
Simulation time 42184301528 ps
CPU time 20.18 seconds
Started Mar 19 03:12:19 PM PDT 24
Finished Mar 19 03:12:39 PM PDT 24
Peak memory 200148 kb
Host smart-800f83f5-6934-45e0-b3a4-49aeb48c729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840876831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1840876831
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2856474068
Short name T214
Test name
Test status
Simulation time 24653324765 ps
CPU time 17.86 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:12:33 PM PDT 24
Peak memory 199972 kb
Host smart-59894439-b959-4bbe-af28-278cbd8e858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856474068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2856474068
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1936925994
Short name T136
Test name
Test status
Simulation time 51527783909 ps
CPU time 136.17 seconds
Started Mar 19 03:12:19 PM PDT 24
Finished Mar 19 03:14:35 PM PDT 24
Peak memory 200136 kb
Host smart-527fdd21-8d34-42af-aa1f-4bd664e1aea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936925994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1936925994
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3533683195
Short name T833
Test name
Test status
Simulation time 9189252755 ps
CPU time 17.67 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:12:33 PM PDT 24
Peak memory 200204 kb
Host smart-33a130ea-d918-4043-b3f8-99e0c31e6b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533683195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3533683195
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1428465308
Short name T959
Test name
Test status
Simulation time 502479984932 ps
CPU time 1223.57 seconds
Started Mar 19 03:12:14 PM PDT 24
Finished Mar 19 03:32:38 PM PDT 24
Peak memory 224988 kb
Host smart-b237570f-1fd0-4e42-b0ae-1f1309ba8646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428465308 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1428465308
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4247961890
Short name T330
Test name
Test status
Simulation time 219674884023 ps
CPU time 320.48 seconds
Started Mar 19 03:12:16 PM PDT 24
Finished Mar 19 03:17:37 PM PDT 24
Peak memory 200188 kb
Host smart-2caad027-b7b1-48cd-b6d0-f15c9ad1c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247961890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4247961890
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.514411474
Short name T825
Test name
Test status
Simulation time 230506385922 ps
CPU time 1112.81 seconds
Started Mar 19 03:12:15 PM PDT 24
Finished Mar 19 03:30:48 PM PDT 24
Peak memory 216776 kb
Host smart-8418383d-da42-490b-b7d5-c148b8a417cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514411474 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.514411474
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2994029919
Short name T940
Test name
Test status
Simulation time 110711493235 ps
CPU time 44.61 seconds
Started Mar 19 03:12:16 PM PDT 24
Finished Mar 19 03:13:01 PM PDT 24
Peak memory 200052 kb
Host smart-8c0a3059-8b27-4f0d-b8ce-e4afeccea70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994029919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2994029919
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.559119243
Short name T264
Test name
Test status
Simulation time 56684195315 ps
CPU time 24.98 seconds
Started Mar 19 03:12:29 PM PDT 24
Finished Mar 19 03:12:54 PM PDT 24
Peak memory 199952 kb
Host smart-f049c0db-a6da-4e03-b49e-4b442398e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559119243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.559119243
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2010172505
Short name T767
Test name
Test status
Simulation time 18217534 ps
CPU time 0.6 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 195688 kb
Host smart-02cf2389-2936-41db-9217-75d7d2e89114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010172505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2010172505
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3495891206
Short name T854
Test name
Test status
Simulation time 77116790172 ps
CPU time 75.28 seconds
Started Mar 19 03:09:35 PM PDT 24
Finished Mar 19 03:10:51 PM PDT 24
Peak memory 200172 kb
Host smart-fc8f11bc-5067-4119-8519-49ae5f76a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495891206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3495891206
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.446114330
Short name T53
Test name
Test status
Simulation time 63966181455 ps
CPU time 96.78 seconds
Started Mar 19 03:09:31 PM PDT 24
Finished Mar 19 03:11:08 PM PDT 24
Peak memory 200176 kb
Host smart-9f706aca-74ed-473b-87af-134bd8cfc739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446114330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.446114330
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.952289463
Short name T164
Test name
Test status
Simulation time 70753743126 ps
CPU time 30.17 seconds
Started Mar 19 03:09:34 PM PDT 24
Finished Mar 19 03:10:06 PM PDT 24
Peak memory 200100 kb
Host smart-1afe4917-9b0f-41b4-ad63-737ec40d32dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952289463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.952289463
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3757740151
Short name T991
Test name
Test status
Simulation time 11785822323 ps
CPU time 18.95 seconds
Started Mar 19 03:09:40 PM PDT 24
Finished Mar 19 03:09:59 PM PDT 24
Peak memory 196912 kb
Host smart-dc0397be-fa71-40e4-a502-cad013248cd5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757740151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3757740151
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2922804689
Short name T544
Test name
Test status
Simulation time 57693365458 ps
CPU time 155.53 seconds
Started Mar 19 03:09:38 PM PDT 24
Finished Mar 19 03:12:14 PM PDT 24
Peak memory 200144 kb
Host smart-c731644e-2e8a-46a9-af68-599a7af8c85a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922804689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2922804689
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2248846341
Short name T346
Test name
Test status
Simulation time 6893749107 ps
CPU time 6.31 seconds
Started Mar 19 03:09:42 PM PDT 24
Finished Mar 19 03:09:48 PM PDT 24
Peak memory 199020 kb
Host smart-9126c16e-7783-4e87-a6b3-dc838d7f5f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248846341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2248846341
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1383275081
Short name T987
Test name
Test status
Simulation time 33160128054 ps
CPU time 66.98 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:10:40 PM PDT 24
Peak memory 200312 kb
Host smart-c086c647-e3e5-4c23-a204-c5e85c33a784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383275081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1383275081
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.518403800
Short name T377
Test name
Test status
Simulation time 22789886819 ps
CPU time 254.48 seconds
Started Mar 19 03:09:36 PM PDT 24
Finished Mar 19 03:13:51 PM PDT 24
Peak memory 200212 kb
Host smart-8f4f208e-c02d-43ac-ae2d-8743a12f38de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518403800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.518403800
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1968453435
Short name T107
Test name
Test status
Simulation time 2630626675 ps
CPU time 19.98 seconds
Started Mar 19 03:09:47 PM PDT 24
Finished Mar 19 03:10:07 PM PDT 24
Peak memory 198532 kb
Host smart-e6208afd-1f77-4e86-88f1-03e5b92cc146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968453435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1968453435
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4056373125
Short name T963
Test name
Test status
Simulation time 39723312757 ps
CPU time 17.84 seconds
Started Mar 19 03:09:47 PM PDT 24
Finished Mar 19 03:10:05 PM PDT 24
Peak memory 199888 kb
Host smart-386d1f97-bd26-4abc-90e2-8d82e5c0de82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056373125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4056373125
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2132174155
Short name T1022
Test name
Test status
Simulation time 2146752422 ps
CPU time 1.68 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:09:35 PM PDT 24
Peak memory 195616 kb
Host smart-9e3126dc-f95c-483b-ae54-e121efedad6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132174155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2132174155
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.118544581
Short name T676
Test name
Test status
Simulation time 483458194 ps
CPU time 1.11 seconds
Started Mar 19 03:09:30 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 198640 kb
Host smart-1d8c8cf1-aa03-4edb-8f61-750763080c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118544581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.118544581
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2684528257
Short name T329
Test name
Test status
Simulation time 324947931839 ps
CPU time 226.64 seconds
Started Mar 19 03:09:36 PM PDT 24
Finished Mar 19 03:13:23 PM PDT 24
Peak memory 208532 kb
Host smart-6421f506-f50f-49da-a4c4-1e0966fa328b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684528257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2684528257
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.464254423
Short name T848
Test name
Test status
Simulation time 1236745444 ps
CPU time 2.41 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:09:36 PM PDT 24
Peak memory 200048 kb
Host smart-7cee12b7-3adc-45fd-a6b0-abeb6e4c9b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464254423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.464254423
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.214528069
Short name T313
Test name
Test status
Simulation time 156247135311 ps
CPU time 22.37 seconds
Started Mar 19 03:09:37 PM PDT 24
Finished Mar 19 03:10:00 PM PDT 24
Peak memory 200120 kb
Host smart-1842b036-78a5-4983-bc45-529c7ef74930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214528069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.214528069
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1676333909
Short name T246
Test name
Test status
Simulation time 20747714796 ps
CPU time 29.21 seconds
Started Mar 19 03:12:27 PM PDT 24
Finished Mar 19 03:12:56 PM PDT 24
Peak memory 200164 kb
Host smart-38220a64-17d3-48e2-bccc-3b9257dcc1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676333909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1676333909
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.4245277238
Short name T151
Test name
Test status
Simulation time 39997050453 ps
CPU time 32.28 seconds
Started Mar 19 03:12:28 PM PDT 24
Finished Mar 19 03:13:00 PM PDT 24
Peak memory 200220 kb
Host smart-725ed794-8e4a-4188-92e2-609f15255f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245277238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4245277238
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.915561378
Short name T1056
Test name
Test status
Simulation time 112308453949 ps
CPU time 15.48 seconds
Started Mar 19 03:12:26 PM PDT 24
Finished Mar 19 03:12:42 PM PDT 24
Peak memory 200184 kb
Host smart-6d7fe8e1-0ffa-44bb-8a5a-6ad8cedf0d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915561378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.915561378
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.4054098976
Short name T1074
Test name
Test status
Simulation time 185337988007 ps
CPU time 45.33 seconds
Started Mar 19 03:12:27 PM PDT 24
Finished Mar 19 03:13:13 PM PDT 24
Peak memory 200164 kb
Host smart-545e1d04-74fc-4387-9436-cf552031a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054098976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4054098976
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2696009580
Short name T282
Test name
Test status
Simulation time 120552273950 ps
CPU time 45.95 seconds
Started Mar 19 03:12:26 PM PDT 24
Finished Mar 19 03:13:13 PM PDT 24
Peak memory 200096 kb
Host smart-3a341d48-52a9-440f-86e2-6f6240e54c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696009580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2696009580
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3583943193
Short name T235
Test name
Test status
Simulation time 37617065709 ps
CPU time 15.79 seconds
Started Mar 19 03:12:29 PM PDT 24
Finished Mar 19 03:12:46 PM PDT 24
Peak memory 200112 kb
Host smart-0d94d1e4-0098-4102-95b4-1744c54d213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583943193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3583943193
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1615289186
Short name T840
Test name
Test status
Simulation time 13798799126 ps
CPU time 146.1 seconds
Started Mar 19 03:12:27 PM PDT 24
Finished Mar 19 03:14:53 PM PDT 24
Peak memory 208580 kb
Host smart-941f8b0e-121d-407a-9ba2-9209da396ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615289186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1615289186
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2029248230
Short name T222
Test name
Test status
Simulation time 81018063114 ps
CPU time 149.9 seconds
Started Mar 19 03:12:27 PM PDT 24
Finished Mar 19 03:14:57 PM PDT 24
Peak memory 200124 kb
Host smart-77af87e9-d5fb-4449-9f07-ffef7e04006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029248230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2029248230
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1935439565
Short name T265
Test name
Test status
Simulation time 88237003058 ps
CPU time 75.9 seconds
Started Mar 19 03:12:27 PM PDT 24
Finished Mar 19 03:13:43 PM PDT 24
Peak memory 200180 kb
Host smart-1fc4184d-44ee-4711-a161-c4d3172eeed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935439565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1935439565
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2187626636
Short name T897
Test name
Test status
Simulation time 53200173333 ps
CPU time 31.63 seconds
Started Mar 19 03:12:26 PM PDT 24
Finished Mar 19 03:12:58 PM PDT 24
Peak memory 200192 kb
Host smart-461851a7-8100-4597-8ec3-3ae4c37697ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187626636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2187626636
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1099511686
Short name T608
Test name
Test status
Simulation time 122603694482 ps
CPU time 64.44 seconds
Started Mar 19 03:12:30 PM PDT 24
Finished Mar 19 03:13:34 PM PDT 24
Peak memory 200120 kb
Host smart-3356851a-e08b-4a44-9e77-3d9bc4bd57a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099511686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1099511686
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.747318413
Short name T542
Test name
Test status
Simulation time 37662963 ps
CPU time 0.58 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:09:50 PM PDT 24
Peak memory 195664 kb
Host smart-81de9721-953c-489f-8f66-20ee17931bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747318413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.747318413
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.415239095
Short name T814
Test name
Test status
Simulation time 99462905620 ps
CPU time 16.15 seconds
Started Mar 19 03:09:38 PM PDT 24
Finished Mar 19 03:09:54 PM PDT 24
Peak memory 200024 kb
Host smart-a7d6e2d7-0753-4c47-810a-852c0ef17f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415239095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.415239095
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.681157404
Short name T878
Test name
Test status
Simulation time 58981886380 ps
CPU time 95.8 seconds
Started Mar 19 03:09:44 PM PDT 24
Finished Mar 19 03:11:20 PM PDT 24
Peak memory 200136 kb
Host smart-b87dd78b-f17a-43f4-aa58-e7eff5b94b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681157404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.681157404
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3001360641
Short name T202
Test name
Test status
Simulation time 22762647742 ps
CPU time 19.34 seconds
Started Mar 19 03:09:37 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 200164 kb
Host smart-c93b137a-0875-4eb6-aaff-72ed389c5955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001360641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3001360641
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2024213780
Short name T304
Test name
Test status
Simulation time 530292099175 ps
CPU time 466.54 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:17:20 PM PDT 24
Peak memory 200172 kb
Host smart-fc6ee31a-57f8-4ce5-ae52-9f0976ef201a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024213780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2024213780
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.428022312
Short name T45
Test name
Test status
Simulation time 88817992834 ps
CPU time 484.19 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:17:53 PM PDT 24
Peak memory 200156 kb
Host smart-2773781f-a024-4de6-8fea-61f98d5ae823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428022312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.428022312
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.495667264
Short name T576
Test name
Test status
Simulation time 5010021191 ps
CPU time 11.04 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:10:00 PM PDT 24
Peak memory 200000 kb
Host smart-94aa672b-7144-4e25-bda2-d38d7fd786b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495667264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.495667264
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3048149598
Short name T387
Test name
Test status
Simulation time 39821480671 ps
CPU time 37.67 seconds
Started Mar 19 03:09:36 PM PDT 24
Finished Mar 19 03:10:14 PM PDT 24
Peak memory 200300 kb
Host smart-75413297-c8b0-4292-85c1-4586083ad590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048149598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3048149598
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1573903025
Short name T683
Test name
Test status
Simulation time 20359812078 ps
CPU time 1183.89 seconds
Started Mar 19 03:09:48 PM PDT 24
Finished Mar 19 03:29:33 PM PDT 24
Peak memory 200128 kb
Host smart-76a1b139-269a-4c0a-ad40-c66be8f711f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573903025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1573903025
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4272389452
Short name T813
Test name
Test status
Simulation time 3918664553 ps
CPU time 29.16 seconds
Started Mar 19 03:09:31 PM PDT 24
Finished Mar 19 03:10:01 PM PDT 24
Peak memory 198544 kb
Host smart-297cb52e-eff8-41a5-95a7-7f9cd87c765b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272389452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4272389452
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.4014385578
Short name T620
Test name
Test status
Simulation time 83606778659 ps
CPU time 86.26 seconds
Started Mar 19 03:09:33 PM PDT 24
Finished Mar 19 03:11:01 PM PDT 24
Peak memory 200172 kb
Host smart-a3415976-5687-47f7-b99d-16316777ad29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014385578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4014385578
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2449070098
Short name T668
Test name
Test status
Simulation time 3682323895 ps
CPU time 2.19 seconds
Started Mar 19 03:09:39 PM PDT 24
Finished Mar 19 03:09:42 PM PDT 24
Peak memory 196276 kb
Host smart-bac76904-7b8b-4836-9ddf-22ae91c4e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449070098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2449070098
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1638572887
Short name T584
Test name
Test status
Simulation time 96422544 ps
CPU time 0.84 seconds
Started Mar 19 03:09:39 PM PDT 24
Finished Mar 19 03:09:40 PM PDT 24
Peak memory 197244 kb
Host smart-bf70150c-a23f-4a64-8137-58d41bde4ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638572887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1638572887
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2975102266
Short name T1101
Test name
Test status
Simulation time 6535368920 ps
CPU time 16.07 seconds
Started Mar 19 03:09:51 PM PDT 24
Finished Mar 19 03:10:09 PM PDT 24
Peak memory 199568 kb
Host smart-c9daba4a-a571-4201-ad10-e40bafb3132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975102266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2975102266
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2223636472
Short name T447
Test name
Test status
Simulation time 155840521246 ps
CPU time 38.92 seconds
Started Mar 19 03:09:38 PM PDT 24
Finished Mar 19 03:10:18 PM PDT 24
Peak memory 200136 kb
Host smart-07b411ab-8aac-4287-97c1-45815dae3549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223636472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2223636472
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2739186791
Short name T276
Test name
Test status
Simulation time 103009258845 ps
CPU time 42.19 seconds
Started Mar 19 03:12:29 PM PDT 24
Finished Mar 19 03:13:12 PM PDT 24
Peak memory 200204 kb
Host smart-716c4177-5159-43e0-959a-8dd4deb3df80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739186791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2739186791
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1636377462
Short name T98
Test name
Test status
Simulation time 50445907461 ps
CPU time 516.32 seconds
Started Mar 19 03:12:29 PM PDT 24
Finished Mar 19 03:21:06 PM PDT 24
Peak memory 225760 kb
Host smart-e9d3059b-fa72-475f-8735-2cf7339be37b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636377462 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1636377462
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1475711041
Short name T562
Test name
Test status
Simulation time 18179829544 ps
CPU time 229.43 seconds
Started Mar 19 03:12:26 PM PDT 24
Finished Mar 19 03:16:16 PM PDT 24
Peak memory 211524 kb
Host smart-f39565d7-d5a0-4a1d-ac82-d4429a813ca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475711041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1475711041
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1096139282
Short name T226
Test name
Test status
Simulation time 88730657847 ps
CPU time 154.6 seconds
Started Mar 19 03:12:29 PM PDT 24
Finished Mar 19 03:15:04 PM PDT 24
Peak memory 200172 kb
Host smart-387ccdd0-1ba0-47ca-9d55-f6ea009f133a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096139282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1096139282
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1840960791
Short name T971
Test name
Test status
Simulation time 16270413901 ps
CPU time 12.26 seconds
Started Mar 19 03:12:27 PM PDT 24
Finished Mar 19 03:12:40 PM PDT 24
Peak memory 200044 kb
Host smart-cbba1753-504c-4b11-8c55-cde776227fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840960791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1840960791
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.861406879
Short name T154
Test name
Test status
Simulation time 56263341054 ps
CPU time 24.83 seconds
Started Mar 19 03:12:27 PM PDT 24
Finished Mar 19 03:12:52 PM PDT 24
Peak memory 200176 kb
Host smart-4a484788-5b7b-4d98-8e5a-e86be79e1dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861406879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.861406879
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.642520160
Short name T100
Test name
Test status
Simulation time 60814591716 ps
CPU time 304.32 seconds
Started Mar 19 03:12:26 PM PDT 24
Finished Mar 19 03:17:30 PM PDT 24
Peak memory 215328 kb
Host smart-d44c8989-8b4b-4dde-875e-01c8019421fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642520160 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.642520160
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3415023913
Short name T709
Test name
Test status
Simulation time 125489490612 ps
CPU time 115.1 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:14:36 PM PDT 24
Peak memory 200180 kb
Host smart-d32f4142-31e1-4801-a221-f665419e7c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415023913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3415023913
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3761360941
Short name T99
Test name
Test status
Simulation time 1386984716170 ps
CPU time 832.92 seconds
Started Mar 19 03:12:39 PM PDT 24
Finished Mar 19 03:26:33 PM PDT 24
Peak memory 224944 kb
Host smart-541e8499-b36f-4fb8-be87-087c88f8b67b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761360941 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3761360941
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3774786590
Short name T704
Test name
Test status
Simulation time 93980154407 ps
CPU time 199.72 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 200132 kb
Host smart-a5f0fa64-8924-43d5-8ade-9080da853918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774786590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3774786590
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.844934442
Short name T1014
Test name
Test status
Simulation time 12139559645 ps
CPU time 21.51 seconds
Started Mar 19 03:12:41 PM PDT 24
Finished Mar 19 03:13:03 PM PDT 24
Peak memory 200172 kb
Host smart-c52ef0f9-e586-41ca-9c99-cdfe4a33d412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844934442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.844934442
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1617864637
Short name T3
Test name
Test status
Simulation time 96577375207 ps
CPU time 18.42 seconds
Started Mar 19 03:12:42 PM PDT 24
Finished Mar 19 03:13:00 PM PDT 24
Peak memory 200048 kb
Host smart-1829ce74-b048-4a58-abd8-f24d6df96657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617864637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1617864637
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2941054194
Short name T779
Test name
Test status
Simulation time 218537211795 ps
CPU time 776.35 seconds
Started Mar 19 03:12:43 PM PDT 24
Finished Mar 19 03:25:40 PM PDT 24
Peak memory 216576 kb
Host smart-8b2f4786-fc40-4581-8854-d4faae5cd6b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941054194 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2941054194
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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