Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	91052	1			T1	2		T2	5		T3	9
all_values[1]	91052	1			T1	2		T2	5		T3	9
all_values[2]	91052	1			T1	2		T2	5		T3	9
all_values[3]	91052	1			T1	2		T2	5		T3	9
all_values[4]	91052	1			T1	2		T2	5		T3	9
all_values[5]	91052	1			T1	2		T2	5		T3	9
all_values[6]	91052	1			T1	2		T2	5		T3	9
all_values[7]	91052	1			T1	2		T2	5		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

353309

1

T1

16

T2

28

T3

22

auto[1]

375107

1

T2

12

T3

50

T4

162

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682947

1

T1

13

T2

37

T3

65

auto[1]

45469

1

T1

3

T2

3

T3

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	28489	1			T2	1		T4	27		T21	79
all_values[0]	auto[0]	auto[1]	20123	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	26785	1			T2	2		T3	4		T8	2
all_values[0]	auto[1]	auto[1]	15655	1			T3	3		T4	2		T6	12
all_values[1]	auto[0]	auto[0]	40045	1			T1	2		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	1408	1			T6	2		T9	7		T11	13
all_values[1]	auto[1]	auto[0]	47950	1			T2	2		T3	7		T4	37
all_values[1]	auto[1]	auto[1]	1649	1			T8	4		T125	23		T25	42
all_values[2]	auto[0]	auto[0]	42641	1			T1	1		T2	4		T4	23
all_values[2]	auto[0]	auto[1]	2455	1			T1	1		T2	1		T4	3
all_values[2]	auto[1]	auto[0]	43905	1			T3	7		T4	17		T6	2
all_values[2]	auto[1]	auto[1]	2051	1			T3	2		T4	5		T8	4
all_values[3]	auto[0]	auto[0]	40816	1			T1	2		T2	4		T3	9
all_values[3]	auto[0]	auto[1]	235	1			T16	1		T118	3		T17	1
all_values[3]	auto[1]	auto[0]	49779	1			T2	1		T6	2		T7	1
all_values[3]	auto[1]	auto[1]	222	1			T11	1		T12	2		T13	1
all_values[4]	auto[0]	auto[0]	43695	1			T1	2		T2	5		T4	46
all_values[4]	auto[0]	auto[1]	390	1			T26	2		T16	2		T18	5
all_values[4]	auto[1]	auto[0]	46701	1			T3	9		T4	2		T6	13
all_values[4]	auto[1]	auto[1]	266	1			T26	3		T16	4		T17	4
all_values[5]	auto[0]	auto[0]	44721	1			T1	2		T2	3		T4	17
all_values[5]	auto[0]	auto[1]	104	1			T16	1		T28	1		T29	4
all_values[5]	auto[1]	auto[0]	46120	1			T2	2		T3	9		T4	31
all_values[5]	auto[1]	auto[1]	107	1			T16	2		T28	3		T29	2
all_values[6]	auto[0]	auto[0]	42123	1			T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	126	1			T16	2		T29	4		T38	1
all_values[6]	auto[1]	auto[0]	48655	1			T2	2		T3	7		T4	33
all_values[6]	auto[1]	auto[1]	148	1			T16	3		T28	3		T29	1
all_values[7]	auto[0]	auto[0]	45641	1			T1	2		T2	2		T3	7
all_values[7]	auto[0]	auto[1]	297	1			T16	3		T18	4		T106	7
all_values[7]	auto[1]	auto[0]	44881	1			T2	3		T3	2		T4	35
all_values[7]	auto[1]	auto[1]	233	1			T20	6		T16	4		T94	3