Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2038

1

T1

1

T2

1

T3

1

auto[UartRx]

2038

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3934	1			T1	2		T2	2		T3	2
values[1]	24	1			T27	1		T29	2		T39	1
values[2]	10	1			T38	1		T39	1		T43	1
values[3]	11	1			T37	1		T38	1		T111	1
values[4]	7	1			T27	1		T300	2		T251	3
values[5]	19	1			T27	1		T28	2		T29	2
values[6]	11	1			T29	2		T40	1		T42	1
values[7]	8	1			T27	1		T28	1		T37	3
values[8]	14	1			T28	1		T37	1		T39	1
values[9]	16	1			T29	1		T37	1		T38	1
values[10]	14	1			T27	1		T28	1		T40	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2004	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	8	1			T40	1		T300	1		T251	3
auto[UartTx]	values[2]	1	1			T43	1		-	-		-	-
auto[UartTx]	values[3]	1	1			T178	1		-	-		-	-
auto[UartTx]	values[4]	3	1			T300	1		T251	2		-	-
auto[UartTx]	values[5]	5	1			T28	1		T43	1		T303	1
auto[UartTx]	values[6]	3	1			T29	1		T303	1		T304	1
auto[UartTx]	values[7]	1	1			T37	1		-	-		-	-
auto[UartTx]	values[8]	2	1			T39	1		T224	1		-	-
auto[UartTx]	values[9]	5	1			T42	2		T295	1		T305	1
auto[UartTx]	values[10]	4	1			T27	1		T40	1		T175	1
auto[UartRx]	values[0]	1930	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	16	1			T27	1		T29	2		T39	1
auto[UartRx]	values[2]	9	1			T38	1		T39	1		T300	1
auto[UartRx]	values[3]	10	1			T37	1		T38	1		T111	1
auto[UartRx]	values[4]	4	1			T27	1		T300	1		T251	1
auto[UartRx]	values[5]	14	1			T27	1		T28	1		T29	2
auto[UartRx]	values[6]	8	1			T29	1		T40	1		T42	1
auto[UartRx]	values[7]	7	1			T27	1		T28	1		T37	2
auto[UartRx]	values[8]	12	1			T28	1		T37	1		T41	1
auto[UartRx]	values[9]	11	1			T29	1		T37	1		T38	1
auto[UartRx]	values[10]	10	1			T28	1		T41	2		T43	1