Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1967	1			T4	4		T6	1		T7	10
auto[BaudRate115200]	1641	1			T1	1		T2	1		T3	1
auto[BaudRate230400]	1645	1			T2	2		T3	3		T4	1
auto[BaudRate128Kbps]	1549	1			T2	1		T4	1		T5	1
auto[BaudRate256Kbps]	1794	1			T1	1		T5	1		T8	1
auto[BaudRate1Mbps]	1391	1			T3	1		T4	2		T9	1
auto[BaudRate1p5Mbps]	1077	1			T2	1		T3	1		T4	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	953	1			T126	6		T12	7		T35	6
freqs[25]	899	1			T16	42		T123	10		T94	10
freqs[48]	384	1			T2	5		T306	17		T252	6
freqs[50]	652	1			T6	5		T44	9		T148	7
freqs[100]	1185	1			T36	10		T276	2		T258	14

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	139	1			T126	2		T19	2		T50	1
auto[BaudRate9600]	freqs[25]	146	1			T16	1		T123	2		T94	2
auto[BaudRate9600]	freqs[48]	64	1			T306	17		T307	7		T308	1
auto[BaudRate9600]	freqs[50]	97	1			T6	1		T148	2		T146	2
auto[BaudRate9600]	freqs[100]	226	1			T36	1		T258	2		T260	1
auto[BaudRate115200]	freqs[24]	164	1			T126	1		T12	1		T35	2
auto[BaudRate115200]	freqs[25]	144	1			T16	4		T123	2		T162	1
auto[BaudRate115200]	freqs[48]	37	1			T2	1		T252	1		T309	1
auto[BaudRate115200]	freqs[50]	97	1			T6	1		T44	2		T148	2
auto[BaudRate115200]	freqs[100]	170	1			T36	2		T258	2		T143	1
auto[BaudRate230400]	freqs[24]	125	1			T12	1		T26	8		T50	1
auto[BaudRate230400]	freqs[25]	154	1			T16	6		T123	2		T93	1
auto[BaudRate230400]	freqs[48]	53	1			T2	2		T252	1		T310	1
auto[BaudRate230400]	freqs[50]	84	1			T148	1		T146	2		T292	3
auto[BaudRate230400]	freqs[100]	189	1			T143	1		T260	2		T254	2
auto[BaudRate128Kbps]	freqs[24]	119	1			T12	1		T35	2		T26	5
auto[BaudRate128Kbps]	freqs[25]	120	1			T16	6		T123	3		T94	2
auto[BaudRate128Kbps]	freqs[48]	50	1			T2	1		T308	3		T311	1
auto[BaudRate128Kbps]	freqs[50]	101	1			T6	1		T44	2		T146	1
auto[BaudRate128Kbps]	freqs[100]	143	1			T36	1		T276	2		T258	2
auto[BaudRate256Kbps]	freqs[24]	160	1			T126	1		T12	2		T26	8
auto[BaudRate256Kbps]	freqs[25]	152	1			T16	7		T123	1		T129	2
auto[BaudRate256Kbps]	freqs[48]	46	1			T252	1		T312	2		T313	1
auto[BaudRate256Kbps]	freqs[50]	93	1			T44	1		T148	1		T146	1
auto[BaudRate256Kbps]	freqs[100]	155	1			T258	3		T143	1		T314	1
auto[BaudRate1Mbps]	freqs[24]	148	1			T126	2		T12	2		T35	2
auto[BaudRate1Mbps]	freqs[25]	122	1			T16	12		T94	5		T129	2
auto[BaudRate1Mbps]	freqs[48]	75	1			T252	2		T310	1		T315	6
auto[BaudRate1Mbps]	freqs[50]	100	1			T44	2		T146	2		T156	2
auto[BaudRate1Mbps]	freqs[100]	153	1			T36	2		T258	3		T314	5
auto[BaudRate1p5Mbps]	freqs[25]	61	1			T16	6		T94	1		T129	1
auto[BaudRate1p5Mbps]	freqs[48]	59	1			T2	1		T252	1		T309	1
auto[BaudRate1p5Mbps]	freqs[50]	80	1			T6	2		T44	2		T148	1
auto[BaudRate1p5Mbps]	freqs[100]	149	1			T36	4		T258	2		T143	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded