Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28016167	1			T2	21		T3	31		T4	734
all_levels[1]	166583	1			T3	1		T4	19		T6	1
all_levels[2]	2394	1			T4	1		T8	1		T21	2
all_levels[3]	980	1			T8	2		T9	1		T11	4
all_levels[4]	696	1			T9	2		T11	2		T137	3
all_levels[5]	519	1			T9	1		T25	1		T36	3
all_levels[6]	408	1			T8	4		T9	5		T125	1
all_levels[7]	337	1			T3	1		T6	1		T8	3
all_levels[8]	276	1			T3	1		T6	1		T137	1
all_levels[9]	260	1			T3	1		T8	2		T11	1
all_levels[10]	198	1			T138	4		T27	2		T47	1
all_levels[11]	202	1			T3	1		T6	1		T8	2
all_levels[12]	146	1			T3	1		T9	1		T25	2
all_levels[13]	140	1			T8	2		T137	1		T25	1
all_levels[14]	114	1			T6	1		T8	2		T9	1
all_levels[15]	120	1			T8	4		T9	1		T25	1
all_levels[16]	140	1			T3	2		T8	2		T25	2
all_levels[17]	123	1			T8	2		T9	1		T139	2
all_levels[18]	99	1			T3	1		T6	1		T139	2
all_levels[19]	85	1			T8	1		T9	1		T25	1
all_levels[20]	79	1			T9	1		T139	1		T49	1
all_levels[21]	53	1			T9	1		T140	4		T49	2
all_levels[22]	56	1			T25	1		T49	1		T13	1
all_levels[23]	54	1			T6	1		T11	1		T141	1
all_levels[24]	51	1			T6	1		T25	1		T13	1
all_levels[25]	39	1			T6	2		T48	3		T18	1
all_levels[26]	35	1			T49	1		T13	1		T110	1
all_levels[27]	58	1			T126	1		T142	1		T13	1
all_levels[28]	44	1			T142	1		T16	1		T123	1
all_levels[29]	35	1			T49	1		T16	1		T107	3
all_levels[30]	31	1			T51	2		T143	2		T144	1
all_levels[31]	31	1			T16	1		T145	1		T146	2
all_levels[32]	26	1			T106	1		T145	1		T147	2
all_levels[33]	35	1			T49	2		T94	1		T148	1
all_levels[34]	20	1			T125	2		T50	1		T16	1
all_levels[35]	29	1			T6	1		T29	1		T144	2
all_levels[36]	17	1			T2	1		T139	1		T29	1
all_levels[37]	21	1			T149	2		T37	1		T150	1
all_levels[38]	16	1			T25	3		T50	1		T145	1
all_levels[39]	23	1			T45	1		T148	1		T18	1
all_levels[40]	18	1			T151	1		T152	1		T153	1
all_levels[41]	20	1			T25	1		T51	1		T45	1
all_levels[42]	19	1			T25	1		T123	3		T154	3
all_levels[43]	15	1			T105	1		T37	1		T155	1
all_levels[44]	12	1			T51	1		T45	1		T29	1
all_levels[45]	11	1			T145	1		T156	1		T157	1
all_levels[46]	20	1			T20	1		T141	1		T106	1
all_levels[47]	4	1			T158	1		T159	1		T160	1
all_levels[48]	11	1			T28	1		T37	1		T43	1
all_levels[49]	12	1			T138	1		T149	1		T161	1
all_levels[50]	17	1			T49	2		T119	1		T162	2
all_levels[51]	5	1			T18	1		T37	1		T163	1
all_levels[52]	6	1			T45	2		T38	1		T164	1
all_levels[53]	10	1			T45	1		T129	1		T145	2
all_levels[54]	9	1			T16	1		T165	3		T166	1
all_levels[55]	18	1			T16	1		T156	1		T37	1
all_levels[56]	11	1			T107	3		T37	1		T111	1
all_levels[57]	15	1			T48	3		T167	3		T168	2
all_levels[58]	9	1			T169	2		T170	1		T171	2
all_levels[59]	12	1			T50	1		T38	1		T171	1
all_levels[60]	5	1			T119	1		T172	1		T173	1
all_levels[61]	10	1			T174	1		T37	1		T175	1
all_levels[62]	4	1			T176	2		T177	1		T178	1
all_levels[63]	3	1			T124	1		T106	1		T179	1
all_levels[64]	83	1			T11	1		T118	4		T129	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28187314

1

T2

18

T3

34

T4

754

auto[1]

3785

1

T2

4

T3

6

T7

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[26]]	[auto[1]]	0	1	1
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[47] , all_levels[48] , all_levels[49]]	[auto[1]]	--	--	3
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[59] , all_levels[60]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28012830	1			T2	17		T3	25		T4	734
all_levels[0]	auto[1]	3337	1			T2	4		T3	6		T7	1
all_levels[1]	auto[0]	166501	1			T3	1		T4	19		T6	1
all_levels[1]	auto[1]	82	1			T125	1		T13	2		T110	1
all_levels[2]	auto[0]	2376	1			T4	1		T8	1		T21	2
all_levels[2]	auto[1]	18	1			T180	1		T160	2		T181	3
all_levels[3]	auto[0]	962	1			T8	2		T9	1		T11	4
all_levels[3]	auto[1]	18	1			T110	2		T182	2		T160	2
all_levels[4]	auto[0]	681	1			T9	2		T11	2		T137	3
all_levels[4]	auto[1]	15	1			T139	1		T13	1		T151	1
all_levels[5]	auto[0]	485	1			T9	1		T25	1		T36	3
all_levels[5]	auto[1]	34	1			T106	2		T151	2		T147	1
all_levels[6]	auto[0]	391	1			T8	2		T9	2		T125	1
all_levels[6]	auto[1]	17	1			T8	2		T9	3		T151	1
all_levels[7]	auto[0]	327	1			T3	1		T6	1		T8	3
all_levels[7]	auto[1]	10	1			T145	1		T183	1		T184	4
all_levels[8]	auto[0]	273	1			T3	1		T6	1		T137	1
all_levels[8]	auto[1]	3	1			T185	1		T186	2		-	-
all_levels[9]	auto[0]	246	1			T3	1		T8	2		T11	1
all_levels[9]	auto[1]	14	1			T187	1		T188	2		T189	1
all_levels[10]	auto[0]	181	1			T138	2		T27	2		T47	1
all_levels[10]	auto[1]	17	1			T138	2		T76	6		T190	1
all_levels[11]	auto[0]	187	1			T3	1		T6	1		T8	2
all_levels[11]	auto[1]	15	1			T25	1		T27	1		T191	2
all_levels[12]	auto[0]	138	1			T3	1		T9	1		T25	2
all_levels[12]	auto[1]	8	1			T139	1		T162	2		T192	1
all_levels[13]	auto[0]	133	1			T8	2		T137	1		T25	1
all_levels[13]	auto[1]	7	1			T35	2		T145	1		T193	2
all_levels[14]	auto[0]	102	1			T6	1		T8	2		T9	1
all_levels[14]	auto[1]	12	1			T25	1		T13	2		T194	1
all_levels[15]	auto[0]	111	1			T8	3		T9	1		T25	1
all_levels[15]	auto[1]	9	1			T8	1		T49	1		T195	1
all_levels[16]	auto[0]	125	1			T3	2		T8	2		T25	2
all_levels[16]	auto[1]	15	1			T123	2		T158	2		T196	4
all_levels[17]	auto[0]	112	1			T8	2		T9	1		T139	2
all_levels[17]	auto[1]	11	1			T197	1		T75	1		T198	1
all_levels[18]	auto[0]	87	1			T3	1		T6	1		T139	1
all_levels[18]	auto[1]	12	1			T139	1		T199	2		T200	1
all_levels[19]	auto[0]	79	1			T8	1		T9	1		T25	1
all_levels[19]	auto[1]	6	1			T159	1		T201	1		T202	1
all_levels[20]	auto[0]	74	1			T9	1		T139	1		T49	1
all_levels[20]	auto[1]	5	1			T150	1		T203	1		T204	2
all_levels[21]	auto[0]	46	1			T9	1		T140	1		T49	2
all_levels[21]	auto[1]	7	1			T140	3		T194	1		T205	1
all_levels[22]	auto[0]	51	1			T25	1		T49	1		T13	1
all_levels[22]	auto[1]	5	1			T37	1		T198	1		T206	1
all_levels[23]	auto[0]	49	1			T6	1		T11	1		T141	1
all_levels[23]	auto[1]	5	1			T207	1		T208	1		T209	1
all_levels[24]	auto[0]	45	1			T6	1		T25	1		T13	1
all_levels[24]	auto[1]	6	1			T185	1		T173	1		T210	2
all_levels[25]	auto[0]	35	1			T6	2		T48	1		T18	1
all_levels[25]	auto[1]	4	1			T48	2		T211	1		T212	1
all_levels[26]	auto[0]	35	1			T49	1		T13	1		T110	1
all_levels[27]	auto[0]	53	1			T126	1		T142	1		T13	1
all_levels[27]	auto[1]	5	1			T213	1		T214	1		T215	1
all_levels[28]	auto[0]	37	1			T142	1		T16	1		T123	1
all_levels[28]	auto[1]	7	1			T216	1		T217	1		T218	4
all_levels[29]	auto[0]	29	1			T49	1		T16	1		T107	1
all_levels[29]	auto[1]	6	1			T107	2		T219	1		T220	1
all_levels[30]	auto[0]	27	1			T51	2		T143	1		T144	1
all_levels[30]	auto[1]	4	1			T143	1		T157	1		T221	2
all_levels[31]	auto[0]	24	1			T16	1		T145	1		T146	1
all_levels[31]	auto[1]	7	1			T146	1		T222	1		T202	1
all_levels[32]	auto[0]	22	1			T106	1		T145	1		T147	1
all_levels[32]	auto[1]	4	1			T147	1		T223	1		T224	1
all_levels[33]	auto[0]	30	1			T49	2		T94	1		T148	1
all_levels[33]	auto[1]	5	1			T156	1		T225	4		-	-
all_levels[34]	auto[0]	19	1			T125	2		T50	1		T16	1
all_levels[34]	auto[1]	1	1			T131	1		-	-		-	-
all_levels[35]	auto[0]	25	1			T6	1		T29	1		T144	2
all_levels[35]	auto[1]	4	1			T226	2		T227	1		T228	1
all_levels[36]	auto[0]	17	1			T2	1		T139	1		T29	1
all_levels[37]	auto[0]	20	1			T149	1		T37	1		T150	1
all_levels[37]	auto[1]	1	1			T149	1		-	-		-	-
all_levels[38]	auto[0]	14	1			T25	1		T50	1		T145	1
all_levels[38]	auto[1]	2	1			T25	2		-	-		-	-
all_levels[39]	auto[0]	19	1			T45	1		T148	1		T18	1
all_levels[39]	auto[1]	4	1			T166	1		T224	1		T212	1
all_levels[40]	auto[0]	18	1			T151	1		T152	1		T153	1
all_levels[41]	auto[0]	18	1			T25	1		T51	1		T45	1
all_levels[41]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[42]	auto[0]	13	1			T25	1		T123	1		T154	1
all_levels[42]	auto[1]	6	1			T123	2		T154	2		T231	2
all_levels[43]	auto[0]	15	1			T105	1		T37	1		T155	1
all_levels[44]	auto[0]	11	1			T51	1		T45	1		T29	1
all_levels[44]	auto[1]	1	1			T160	1		-	-		-	-
all_levels[45]	auto[0]	11	1			T145	1		T156	1		T157	1
all_levels[46]	auto[0]	17	1			T20	1		T141	1		T106	1
all_levels[46]	auto[1]	3	1			T232	2		T233	1		-	-
all_levels[47]	auto[0]	4	1			T158	1		T159	1		T160	1
all_levels[48]	auto[0]	11	1			T28	1		T37	1		T43	1
all_levels[49]	auto[0]	12	1			T138	1		T149	1		T161	1
all_levels[50]	auto[0]	14	1			T49	1		T119	1		T162	1
all_levels[50]	auto[1]	3	1			T49	1		T162	1		T163	1
all_levels[51]	auto[0]	5	1			T18	1		T37	1		T163	1
all_levels[52]	auto[0]	6	1			T45	2		T38	1		T164	1
all_levels[53]	auto[0]	9	1			T45	1		T129	1		T145	1
all_levels[53]	auto[1]	1	1			T145	1		-	-		-	-
all_levels[54]	auto[0]	7	1			T16	1		T165	1		T166	1
all_levels[54]	auto[1]	2	1			T165	2		-	-		-	-
all_levels[55]	auto[0]	15	1			T16	1		T156	1		T37	1
all_levels[55]	auto[1]	3	1			T234	1		T235	2		-	-
all_levels[56]	auto[0]	9	1			T107	1		T37	1		T111	1
all_levels[56]	auto[1]	2	1			T107	2		-	-		-	-
all_levels[57]	auto[0]	10	1			T48	1		T167	1		T168	2
all_levels[57]	auto[1]	5	1			T48	2		T167	2		T236	1
all_levels[58]	auto[0]	7	1			T169	1		T170	1		T171	1
all_levels[58]	auto[1]	2	1			T169	1		T171	1		-	-
all_levels[59]	auto[0]	12	1			T50	1		T38	1		T171	1
all_levels[60]	auto[0]	5	1			T119	1		T172	1		T173	1
all_levels[61]	auto[0]	8	1			T174	1		T37	1		T175	1
all_levels[61]	auto[1]	2	1			T237	2		-	-		-	-
all_levels[62]	auto[0]	3	1			T176	1		T177	1		T178	1
all_levels[62]	auto[1]	1	1			T176	1		-	-		-	-
all_levels[63]	auto[0]	3	1			T124	1		T106	1		T179	1
all_levels[64]	auto[0]	73	1			T11	1		T118	2		T129	2
all_levels[64]	auto[1]	10	1			T118	2		T238	2		T239	1