Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	91052	1			T1	2		T2	5		T3	9
all_pins[1]	91052	1			T1	2		T2	5		T3	9
all_pins[2]	91052	1			T1	2		T2	5		T3	9
all_pins[3]	91052	1			T1	2		T2	5		T3	9
all_pins[4]	91052	1			T1	2		T2	5		T3	9
all_pins[5]	91052	1			T1	2		T2	5		T3	9
all_pins[6]	91052	1			T1	2		T2	5		T3	9
all_pins[7]	91052	1			T1	2		T2	5		T3	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	707339	1			T1	16		T2	40		T3	67
values[0x1]	21077	1			T3	5		T4	7		T6	15
transitions[0x0=>0x1]	20189	1			T3	5		T4	7		T6	15
transitions[0x1=>0x0]	19749	1			T3	5		T4	6		T6	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	75344	1			T1	2		T2	5		T3	6
all_pins[0]	values[0x1]	15708	1			T3	3		T4	2		T6	12
all_pins[0]	transitions[0x0=>0x1]	15260	1			T3	3		T4	2		T6	12
all_pins[0]	transitions[0x1=>0x0]	1200	1			T125	23		T25	24		T138	1
all_pins[1]	values[0x0]	89404	1			T1	2		T2	5		T3	9
all_pins[1]	values[0x1]	1648	1			T8	4		T125	23		T25	42
all_pins[1]	transitions[0x0=>0x1]	1525	1			T8	4		T125	23		T25	42
all_pins[1]	transitions[0x1=>0x0]	1979	1			T3	2		T4	5		T8	4
all_pins[2]	values[0x0]	88950	1			T1	2		T2	5		T3	7
all_pins[2]	values[0x1]	2102	1			T3	2		T4	5		T8	4
all_pins[2]	transitions[0x0=>0x1]	2051	1			T3	2		T4	5		T8	4
all_pins[2]	transitions[0x1=>0x0]	171	1			T11	1		T12	2		T13	1
all_pins[3]	values[0x0]	90830	1			T1	2		T2	5		T3	9
all_pins[3]	values[0x1]	222	1			T11	1		T12	2		T13	1
all_pins[3]	transitions[0x0=>0x1]	196	1			T11	1		T12	2		T13	1
all_pins[3]	transitions[0x1=>0x0]	240	1			T26	3		T16	1		T17	4
all_pins[4]	values[0x0]	90786	1			T1	2		T2	5		T3	9
all_pins[4]	values[0x1]	266	1			T26	3		T16	4		T17	4
all_pins[4]	transitions[0x0=>0x1]	230	1			T26	3		T16	3		T17	3
all_pins[4]	transitions[0x1=>0x0]	106	1			T16	1		T18	1		T24	1
all_pins[5]	values[0x0]	90910	1			T1	2		T2	5		T3	9
all_pins[5]	values[0x1]	142	1			T16	2		T17	1		T18	1
all_pins[5]	transitions[0x0=>0x1]	106	1			T16	1		T17	1		T18	1
all_pins[5]	transitions[0x1=>0x0]	720	1			T6	3		T8	2		T126	1
all_pins[6]	values[0x0]	90296	1			T1	2		T2	5		T3	9
all_pins[6]	values[0x1]	756	1			T6	3		T8	2		T126	1
all_pins[6]	transitions[0x0=>0x1]	702	1			T6	3		T8	2		T126	1
all_pins[6]	transitions[0x1=>0x0]	179	1			T20	5		T16	4		T94	3
all_pins[7]	values[0x0]	90819	1			T1	2		T2	5		T3	9
all_pins[7]	values[0x1]	233	1			T20	6		T16	4		T94	3
all_pins[7]	transitions[0x0=>0x1]	119	1			T20	2		T16	1		T94	3
all_pins[7]	transitions[0x1=>0x0]	15154	1			T3	3		T4	1		T6	12