Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6622040	1			T2	3		T3	18		T4	8
all_levels[1]	1117037	1			T2	3		T3	3		T4	3
all_levels[2]	709200	1			T4	32		T6	4		T21	1
all_levels[3]	287931	1			T6	3		T8	2		T21	5
all_levels[4]	236525	1			T3	1		T21	4		T125	4
all_levels[5]	174014	1			T3	2		T4	2		T8	10
all_levels[6]	358593	1			T4	1		T125	3		T126	7
all_levels[7]	702107	1			T4	1		T11	1		T125	4
all_levels[8]	395019	1			T6	1		T125	3		T25	101
all_levels[9]	258611	1			T4	265		T125	4		T25	84
all_levels[10]	211632	1			T3	4		T4	2		T125	4
all_levels[11]	166881	1			T4	128		T125	8		T12	1
all_levels[12]	156493	1			T3	1		T4	14		T11	2
all_levels[13]	195334	1			T4	51		T21	2		T125	3
all_levels[14]	418198	1			T3	1		T125	6		T12	1
all_levels[15]	178883	1			T4	5		T21	5		T125	2
all_levels[16]	350458	1			T3	1		T125	5		T25	105
all_levels[17]	147386	1			T3	1		T4	2		T6	1
all_levels[18]	168750	1			T21	41		T125	2		T25	114
all_levels[19]	250068	1			T2	1		T21	6		T125	6
all_levels[20]	439658	1			T125	4		T25	106		T139	1
all_levels[21]	223793	1			T21	3		T125	8		T25	101
all_levels[22]	258326	1			T3	1		T125	4		T25	99
all_levels[23]	215465	1			T125	6		T126	5		T12	1
all_levels[24]	154807	1			T3	1		T125	1		T25	105
all_levels[25]	348752	1			T125	1		T25	99		T243	60
all_levels[26]	298276	1			T125	2		T25	99		T139	1
all_levels[27]	133337	1			T21	2		T125	5		T25	110
all_levels[28]	126108	1			T2	6		T21	134		T125	5
all_levels[29]	159655	1			T4	10		T21	4		T12	3
all_levels[30]	129097	1			T25	104		T243	55		T26	55
all_levels[31]	589270	1			T21	47		T12	1		T25	2603
all_levels[32]	12009196	1			T2	9		T3	7		T4	230

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28187314

1

T2

18

T3

34

T4

754

auto[1]

3586

1

T2

4

T3

7

T8

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6620153	1			T2	2		T3	13		T4	8
all_levels[0]	auto[1]	1887	1			T2	1		T3	5		T8	4
all_levels[1]	auto[0]	1116801	1			T2	2		T3	3		T4	3
all_levels[1]	auto[1]	236	1			T2	1		T35	2		T27	2
all_levels[2]	auto[0]	709165	1			T4	32		T6	4		T21	1
all_levels[2]	auto[1]	35	1			T53	1		T48	1		T107	2
all_levels[3]	auto[0]	287787	1			T6	3		T8	2		T21	5
all_levels[3]	auto[1]	144	1			T44	2		T151	2		T302	2
all_levels[4]	auto[0]	236500	1			T3	1		T21	4		T125	4
all_levels[4]	auto[1]	25	1			T182	1		T269	1		T160	1
all_levels[5]	auto[0]	173977	1			T3	2		T4	2		T8	8
all_levels[5]	auto[1]	37	1			T8	2		T141	2		T122	3
all_levels[6]	auto[0]	358576	1			T4	1		T125	3		T126	7
all_levels[6]	auto[1]	17	1			T141	2		T131	2		T320	1
all_levels[7]	auto[0]	701996	1			T4	1		T11	1		T125	4
all_levels[7]	auto[1]	111	1			T140	2		T149	3		T131	1
all_levels[8]	auto[0]	394996	1			T6	1		T125	3		T25	101
all_levels[8]	auto[1]	23	1			T162	1		T161	1		T222	1
all_levels[9]	auto[0]	258582	1			T4	265		T125	4		T25	84
all_levels[9]	auto[1]	29	1			T107	1		T187	1		T150	3
all_levels[10]	auto[0]	211594	1			T3	4		T4	2		T125	4
all_levels[10]	auto[1]	38	1			T139	1		T241	1		T60	1
all_levels[11]	auto[0]	166835	1			T4	128		T125	8		T12	1
all_levels[11]	auto[1]	46	1			T139	2		T13	1		T107	2
all_levels[12]	auto[0]	156469	1			T3	1		T4	14		T11	2
all_levels[12]	auto[1]	24	1			T280	1		T321	1		T111	2
all_levels[13]	auto[0]	195304	1			T4	51		T21	2		T125	3
all_levels[13]	auto[1]	30	1			T26	1		T49	1		T130	1
all_levels[14]	auto[0]	418173	1			T3	1		T125	6		T12	1
all_levels[14]	auto[1]	25	1			T123	2		T146	2		T322	1
all_levels[15]	auto[0]	178809	1			T4	5		T21	5		T125	2
all_levels[15]	auto[1]	74	1			T49	1		T130	1		T323	1
all_levels[16]	auto[0]	350442	1			T3	1		T125	5		T25	105
all_levels[16]	auto[1]	16	1			T13	1		T107	1		T262	2
all_levels[17]	auto[0]	147362	1			T3	1		T4	2		T6	1
all_levels[17]	auto[1]	24	1			T324	6		T325	1		T326	4
all_levels[18]	auto[0]	168734	1			T21	41		T125	2		T25	114
all_levels[18]	auto[1]	16	1			T327	1		T328	1		T190	1
all_levels[19]	auto[0]	250049	1			T2	1		T21	6		T125	6
all_levels[19]	auto[1]	19	1			T107	1		T302	2		T285	1
all_levels[20]	auto[0]	439624	1			T125	4		T25	106		T139	1
all_levels[20]	auto[1]	34	1			T16	1		T146	1		T75	2
all_levels[21]	auto[0]	223772	1			T21	3		T125	8		T25	101
all_levels[21]	auto[1]	21	1			T123	3		T145	1		T299	1
all_levels[22]	auto[0]	258315	1			T3	1		T125	4		T25	99
all_levels[22]	auto[1]	11	1			T47	1		T162	1		T329	1
all_levels[23]	auto[0]	215439	1			T125	6		T126	5		T12	1
all_levels[23]	auto[1]	26	1			T137	3		T139	1		T208	3
all_levels[24]	auto[0]	154784	1			T3	1		T125	1		T25	105
all_levels[24]	auto[1]	23	1			T169	2		T167	1		T330	1
all_levels[25]	auto[0]	348737	1			T125	1		T25	99		T243	60
all_levels[25]	auto[1]	15	1			T302	1		T154	1		T319	1
all_levels[26]	auto[0]	298251	1			T125	2		T25	99		T139	1
all_levels[26]	auto[1]	25	1			T107	1		T145	1		T262	1
all_levels[27]	auto[0]	133322	1			T21	2		T125	5		T25	110
all_levels[27]	auto[1]	15	1			T18	1		T330	1		T226	2
all_levels[28]	auto[0]	126086	1			T2	5		T21	133		T125	5
all_levels[28]	auto[1]	22	1			T2	1		T21	1		T331	1
all_levels[29]	auto[0]	159628	1			T4	10		T21	4		T12	3
all_levels[29]	auto[1]	27	1			T145	2		T146	1		T181	1
all_levels[30]	auto[0]	129083	1			T25	104		T243	55		T26	55
all_levels[30]	auto[1]	14	1			T191	1		T110	1		T223	1
all_levels[31]	auto[0]	589255	1			T21	47		T12	1		T25	2603
all_levels[31]	auto[1]	15	1			T131	1		T180	2		T161	1
all_levels[32]	auto[0]	12008714	1			T2	8		T3	5		T4	230
all_levels[32]	auto[1]	482	1			T2	1		T3	2		T9	3