Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	506	1			T16	7		T28	7		T29	11
all_values[1]	506	1			T16	7		T28	7		T29	11
all_values[2]	506	1			T16	7		T28	7		T29	11
all_values[3]	506	1			T16	7		T28	7		T29	11
all_values[4]	506	1			T16	7		T28	7		T29	11
all_values[5]	506	1			T16	7		T28	7		T29	11
all_values[6]	506	1			T16	7		T28	7		T29	11
all_values[7]	506	1			T16	7		T28	7		T29	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2177

1

T16

23

T28

24

T29

51

auto[1]

1871

1

T16

33

T28

32

T29

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1435

1

T16

22

T28

11

T29

38

auto[1]

2613

1

T16

34

T28

45

T29

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2351

1

T16

30

T28

23

T29

60

auto[1]

1697

1

T16

26

T28

33

T29

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	151	1			T16	1		T29	6		T38	5
all_values[0]	auto[0]	auto[1]	auto[1]	130	1			T16	1		T28	1		T29	3
all_values[0]	auto[1]	auto[0]	auto[1]	114	1			T16	1		T28	1		T40	2
all_values[0]	auto[1]	auto[1]	auto[1]	111	1			T16	4		T28	5		T29	2
all_values[1]	auto[0]	auto[0]	auto[0]	161	1			T16	3		T28	2		T29	3
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T16	2		T28	1		T29	6
all_values[1]	auto[1]	auto[0]	auto[1]	98	1			T16	1		T28	1		T38	2
all_values[1]	auto[1]	auto[1]	auto[1]	108	1			T16	1		T28	3		T29	2
all_values[2]	auto[0]	auto[0]	auto[0]	90	1			T16	1		T29	2		T38	3
all_values[2]	auto[0]	auto[0]	auto[1]	52	1			T29	1		T38	2		T41	1
all_values[2]	auto[0]	auto[1]	auto[0]	84	1			T16	3		T29	2		T38	1
all_values[2]	auto[0]	auto[1]	auto[1]	59	1			T28	1		T29	1		T40	1
all_values[2]	auto[1]	auto[0]	auto[1]	128	1			T16	1		T28	3		T29	5
all_values[2]	auto[1]	auto[1]	auto[1]	93	1			T16	2		T28	3		T40	2
all_values[3]	auto[0]	auto[0]	auto[0]	116	1			T16	2		T28	1		T29	4
all_values[3]	auto[0]	auto[0]	auto[1]	48	1			T29	1		T41	2		T42	2
all_values[3]	auto[0]	auto[1]	auto[0]	81	1			T29	1		T38	2		T40	1
all_values[3]	auto[0]	auto[1]	auto[1]	52	1			T16	2		T28	2		T29	1
all_values[3]	auto[1]	auto[0]	auto[1]	106	1			T16	1		T28	2		T29	2
all_values[3]	auto[1]	auto[1]	auto[1]	103	1			T16	2		T28	2		T29	2
all_values[4]	auto[0]	auto[0]	auto[0]	110	1			T29	4		T38	1		T40	3
all_values[4]	auto[0]	auto[0]	auto[1]	56	1			T28	3		T38	2		T41	3
all_values[4]	auto[0]	auto[1]	auto[0]	78	1			T16	1		T29	3		T42	1
all_values[4]	auto[0]	auto[1]	auto[1]	51	1			T16	2		T28	1		T38	2
all_values[4]	auto[1]	auto[0]	auto[1]	114	1			T28	2		T29	1		T38	4
all_values[4]	auto[1]	auto[1]	auto[1]	97	1			T16	4		T28	1		T29	3
all_values[5]	auto[0]	auto[0]	auto[0]	133	1			T16	2		T28	1		T29	1
all_values[5]	auto[0]	auto[0]	auto[1]	42	1			T29	3		T40	1		T41	2
all_values[5]	auto[0]	auto[1]	auto[0]	94	1			T16	2		T29	3		T38	3
all_values[5]	auto[0]	auto[1]	auto[1]	48	1			T28	2		T29	1		T40	1
all_values[5]	auto[1]	auto[0]	auto[1]	100	1			T16	1		T28	2		T29	1
all_values[5]	auto[1]	auto[1]	auto[1]	89	1			T16	2		T28	2		T29	2
all_values[6]	auto[0]	auto[0]	auto[0]	98	1			T16	2		T29	4		T38	2
all_values[6]	auto[0]	auto[0]	auto[1]	56	1			T16	1		T29	2		T38	2
all_values[6]	auto[0]	auto[1]	auto[0]	80	1			T28	2		T29	2		T38	4
all_values[6]	auto[0]	auto[1]	auto[1]	62	1			T16	1		T28	2		T40	2
all_values[6]	auto[1]	auto[0]	auto[1]	122	1			T16	2		T29	3		T38	1
all_values[6]	auto[1]	auto[1]	auto[1]	88	1			T16	1		T28	3		T38	2
all_values[7]	auto[0]	auto[0]	auto[0]	96	1			T16	3		T28	3		T29	3
all_values[7]	auto[0]	auto[0]	auto[1]	57	1			T29	1		T38	3		T41	1
all_values[7]	auto[0]	auto[1]	auto[0]	75	1			T16	1		T28	1		T40	2
all_values[7]	auto[0]	auto[1]	auto[1]	52	1			T29	2		T41	1		T42	2
all_values[7]	auto[1]	auto[0]	auto[1]	129	1			T16	1		T28	3		T29	4
all_values[7]	auto[1]	auto[1]	auto[1]	97	1			T16	2		T29	1		T38	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal