Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.27 97.90 100.00 98.80 100.00 99.52


Total test records in report: 1250
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T1034 /workspace/coverage/default/183.uart_fifo_reset.3209506475 Mar 21 01:58:24 PM PDT 24 Mar 21 01:58:56 PM PDT 24 42726178418 ps
T1035 /workspace/coverage/default/14.uart_tx_ovrd.4048665538 Mar 21 01:54:18 PM PDT 24 Mar 21 01:54:22 PM PDT 24 1426047919 ps
T1036 /workspace/coverage/default/49.uart_tx_ovrd.2755412267 Mar 21 01:57:15 PM PDT 24 Mar 21 01:57:33 PM PDT 24 6119148158 ps
T1037 /workspace/coverage/default/21.uart_rx_oversample.4197956861 Mar 21 01:54:42 PM PDT 24 Mar 21 01:54:55 PM PDT 24 3241976597 ps
T1038 /workspace/coverage/default/1.uart_perf.3645057389 Mar 21 01:52:49 PM PDT 24 Mar 21 02:04:52 PM PDT 24 14204853945 ps
T1039 /workspace/coverage/default/44.uart_tx_ovrd.204872334 Mar 21 01:56:41 PM PDT 24 Mar 21 01:56:44 PM PDT 24 467950246 ps
T1040 /workspace/coverage/default/40.uart_tx_ovrd.358452105 Mar 21 01:56:24 PM PDT 24 Mar 21 01:56:27 PM PDT 24 3161165718 ps
T1041 /workspace/coverage/default/31.uart_fifo_full.4186670109 Mar 21 01:55:26 PM PDT 24 Mar 21 01:57:24 PM PDT 24 221706190831 ps
T1042 /workspace/coverage/default/15.uart_rx_start_bit_filter.1803078500 Mar 21 01:54:12 PM PDT 24 Mar 21 01:54:18 PM PDT 24 3051095892 ps
T1043 /workspace/coverage/default/41.uart_fifo_overflow.3988361583 Mar 21 01:56:23 PM PDT 24 Mar 21 01:57:23 PM PDT 24 72074887325 ps
T1044 /workspace/coverage/default/7.uart_fifo_full.411243101 Mar 21 01:53:11 PM PDT 24 Mar 21 01:54:17 PM PDT 24 67132853589 ps
T1045 /workspace/coverage/default/27.uart_intr.3340690932 Mar 21 01:55:17 PM PDT 24 Mar 21 02:01:02 PM PDT 24 423063182666 ps
T1046 /workspace/coverage/default/250.uart_fifo_reset.3795105289 Mar 21 01:58:57 PM PDT 24 Mar 21 01:59:25 PM PDT 24 87338442804 ps
T1047 /workspace/coverage/default/155.uart_fifo_reset.794471588 Mar 21 01:58:11 PM PDT 24 Mar 21 01:59:49 PM PDT 24 143510047748 ps
T1048 /workspace/coverage/default/5.uart_fifo_overflow.4116428518 Mar 21 01:53:03 PM PDT 24 Mar 21 01:54:05 PM PDT 24 167172807847 ps
T1049 /workspace/coverage/default/11.uart_rx_parity_err.11579616 Mar 21 01:54:04 PM PDT 24 Mar 21 01:55:00 PM PDT 24 113965462595 ps
T1050 /workspace/coverage/default/145.uart_fifo_reset.2034119505 Mar 21 01:58:11 PM PDT 24 Mar 21 02:00:30 PM PDT 24 79808657286 ps
T1051 /workspace/coverage/default/150.uart_fifo_reset.806862530 Mar 21 01:58:11 PM PDT 24 Mar 21 01:58:27 PM PDT 24 66465415451 ps
T1052 /workspace/coverage/default/3.uart_noise_filter.549485609 Mar 21 01:52:57 PM PDT 24 Mar 21 01:53:18 PM PDT 24 13001415882 ps
T1053 /workspace/coverage/default/191.uart_fifo_reset.4110099708 Mar 21 01:58:23 PM PDT 24 Mar 21 01:59:10 PM PDT 24 261010629295 ps
T1054 /workspace/coverage/default/45.uart_perf.3752764722 Mar 21 01:56:51 PM PDT 24 Mar 21 02:06:58 PM PDT 24 46201452997 ps
T1055 /workspace/coverage/default/107.uart_fifo_reset.3559060625 Mar 21 01:57:59 PM PDT 24 Mar 21 02:02:12 PM PDT 24 151561679098 ps
T1056 /workspace/coverage/default/32.uart_noise_filter.104584944 Mar 21 01:55:42 PM PDT 24 Mar 21 01:56:21 PM PDT 24 23499923630 ps
T1057 /workspace/coverage/default/147.uart_fifo_reset.3582537971 Mar 21 01:58:10 PM PDT 24 Mar 21 02:01:32 PM PDT 24 109717359380 ps
T1058 /workspace/coverage/default/0.uart_tx_ovrd.2377905666 Mar 21 01:52:37 PM PDT 24 Mar 21 01:53:16 PM PDT 24 12881650113 ps
T1059 /workspace/coverage/default/154.uart_fifo_reset.2293411486 Mar 21 01:58:11 PM PDT 24 Mar 21 01:58:33 PM PDT 24 14343263361 ps
T1060 /workspace/coverage/default/7.uart_smoke.3876602619 Mar 21 01:53:18 PM PDT 24 Mar 21 01:53:20 PM PDT 24 848981871 ps
T1061 /workspace/coverage/default/208.uart_fifo_reset.1803645470 Mar 21 01:58:42 PM PDT 24 Mar 21 01:59:11 PM PDT 24 74404402269 ps
T1062 /workspace/coverage/default/254.uart_fifo_reset.1798428876 Mar 21 01:58:55 PM PDT 24 Mar 21 02:00:15 PM PDT 24 206375138083 ps
T1063 /workspace/coverage/default/196.uart_fifo_reset.1643580429 Mar 21 01:58:23 PM PDT 24 Mar 21 02:00:08 PM PDT 24 95899443733 ps
T1064 /workspace/coverage/default/44.uart_fifo_full.4105350770 Mar 21 01:56:36 PM PDT 24 Mar 21 01:59:04 PM PDT 24 92383738023 ps
T1065 /workspace/coverage/default/248.uart_fifo_reset.2463039983 Mar 21 01:58:56 PM PDT 24 Mar 21 01:59:53 PM PDT 24 38399777141 ps
T178 /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2499730120 Mar 21 01:55:44 PM PDT 24 Mar 21 02:06:59 PM PDT 24 719397826242 ps
T1066 /workspace/coverage/default/118.uart_fifo_reset.4243830138 Mar 21 01:57:57 PM PDT 24 Mar 21 01:58:55 PM PDT 24 94081465514 ps
T1067 /workspace/coverage/default/14.uart_long_xfer_wo_dly.1268674256 Mar 21 01:54:17 PM PDT 24 Mar 21 01:59:47 PM PDT 24 99651234505 ps
T1068 /workspace/coverage/default/30.uart_noise_filter.2317140793 Mar 21 01:55:24 PM PDT 24 Mar 21 01:56:07 PM PDT 24 27287722948 ps
T1069 /workspace/coverage/default/31.uart_alert_test.3740161206 Mar 21 01:55:41 PM PDT 24 Mar 21 01:55:42 PM PDT 24 11608655 ps
T1070 /workspace/coverage/default/276.uart_fifo_reset.2224587581 Mar 21 01:59:10 PM PDT 24 Mar 21 01:59:37 PM PDT 24 30482469333 ps
T1071 /workspace/coverage/default/9.uart_perf.1501676554 Mar 21 01:53:43 PM PDT 24 Mar 21 01:57:46 PM PDT 24 4039671540 ps
T1072 /workspace/coverage/default/76.uart_fifo_reset.2597565840 Mar 21 01:57:28 PM PDT 24 Mar 21 01:57:47 PM PDT 24 77152911317 ps
T1073 /workspace/coverage/default/43.uart_loopback.3892237919 Mar 21 01:56:36 PM PDT 24 Mar 21 01:56:40 PM PDT 24 2706891234 ps
T1074 /workspace/coverage/default/35.uart_smoke.676521577 Mar 21 01:55:57 PM PDT 24 Mar 21 01:56:06 PM PDT 24 5636412970 ps
T1075 /workspace/coverage/default/47.uart_stress_all.462831035 Mar 21 01:57:04 PM PDT 24 Mar 21 02:09:31 PM PDT 24 393134410366 ps
T1076 /workspace/coverage/default/6.uart_smoke.2052414543 Mar 21 01:53:20 PM PDT 24 Mar 21 01:53:22 PM PDT 24 428005641 ps
T1077 /workspace/coverage/default/17.uart_perf.692291163 Mar 21 01:54:29 PM PDT 24 Mar 21 02:00:56 PM PDT 24 25396119202 ps
T1078 /workspace/coverage/default/11.uart_long_xfer_wo_dly.2088526239 Mar 21 01:54:00 PM PDT 24 Mar 21 02:05:32 PM PDT 24 87426986001 ps
T1079 /workspace/coverage/default/30.uart_tx_ovrd.1014171373 Mar 21 01:55:25 PM PDT 24 Mar 21 01:55:29 PM PDT 24 1088906666 ps
T1080 /workspace/coverage/default/24.uart_tx_ovrd.2911365240 Mar 21 01:54:51 PM PDT 24 Mar 21 01:54:53 PM PDT 24 974221195 ps
T1081 /workspace/coverage/default/7.uart_alert_test.275969523 Mar 21 01:53:20 PM PDT 24 Mar 21 01:53:20 PM PDT 24 11404911 ps
T1082 /workspace/coverage/default/31.uart_intr.409257791 Mar 21 01:55:24 PM PDT 24 Mar 21 01:56:03 PM PDT 24 62697438940 ps
T1083 /workspace/coverage/default/31.uart_rx_oversample.980416780 Mar 21 01:55:32 PM PDT 24 Mar 21 01:55:49 PM PDT 24 3688137173 ps
T236 /workspace/coverage/default/91.uart_fifo_reset.2180016947 Mar 21 01:57:39 PM PDT 24 Mar 21 01:57:50 PM PDT 24 21327946363 ps
T1084 /workspace/coverage/default/43.uart_rx_start_bit_filter.1788038712 Mar 21 01:56:36 PM PDT 24 Mar 21 01:56:44 PM PDT 24 3956078316 ps
T1085 /workspace/coverage/default/5.uart_rx_parity_err.3413556605 Mar 21 01:53:08 PM PDT 24 Mar 21 01:55:54 PM PDT 24 304754806107 ps
T1086 /workspace/coverage/default/79.uart_fifo_reset.1436481035 Mar 21 01:57:27 PM PDT 24 Mar 21 01:58:13 PM PDT 24 26510979335 ps
T1087 /workspace/coverage/default/100.uart_fifo_reset.3296811337 Mar 21 01:57:56 PM PDT 24 Mar 21 01:58:13 PM PDT 24 16383202773 ps
T1088 /workspace/coverage/default/20.uart_tx_rx.621215546 Mar 21 01:54:38 PM PDT 24 Mar 21 01:55:32 PM PDT 24 30332794686 ps
T1089 /workspace/coverage/default/1.uart_loopback.2805812965 Mar 21 01:52:49 PM PDT 24 Mar 21 01:52:53 PM PDT 24 3964977265 ps
T230 /workspace/coverage/default/258.uart_fifo_reset.3890364626 Mar 21 01:58:55 PM PDT 24 Mar 21 01:59:28 PM PDT 24 17503012005 ps
T1090 /workspace/coverage/default/23.uart_loopback.1167127825 Mar 21 01:54:50 PM PDT 24 Mar 21 01:54:54 PM PDT 24 10668726474 ps
T1091 /workspace/coverage/default/18.uart_fifo_reset.280688003 Mar 21 01:54:23 PM PDT 24 Mar 21 01:57:54 PM PDT 24 93116274973 ps
T1092 /workspace/coverage/default/39.uart_tx_rx.2975680016 Mar 21 01:56:10 PM PDT 24 Mar 21 01:56:57 PM PDT 24 54473416047 ps
T1093 /workspace/coverage/default/44.uart_perf.1893766365 Mar 21 01:56:37 PM PDT 24 Mar 21 02:09:25 PM PDT 24 16288813982 ps
T1094 /workspace/coverage/default/30.uart_smoke.2746439129 Mar 21 01:55:25 PM PDT 24 Mar 21 01:55:26 PM PDT 24 287632681 ps
T1095 /workspace/coverage/default/226.uart_fifo_reset.1427729741 Mar 21 01:58:44 PM PDT 24 Mar 21 01:58:59 PM PDT 24 106545908346 ps
T1096 /workspace/coverage/default/45.uart_rx_oversample.339063356 Mar 21 01:56:49 PM PDT 24 Mar 21 01:56:50 PM PDT 24 2082759946 ps
T1097 /workspace/coverage/default/39.uart_loopback.4194447128 Mar 21 01:56:23 PM PDT 24 Mar 21 01:56:26 PM PDT 24 3340655273 ps
T1098 /workspace/coverage/default/9.uart_fifo_overflow.1070248578 Mar 21 01:53:45 PM PDT 24 Mar 21 01:54:17 PM PDT 24 21286848685 ps
T1099 /workspace/coverage/default/1.uart_intr.400598317 Mar 21 01:52:50 PM PDT 24 Mar 21 01:53:36 PM PDT 24 28169004033 ps
T1100 /workspace/coverage/default/5.uart_perf.4242940256 Mar 21 01:53:09 PM PDT 24 Mar 21 01:59:36 PM PDT 24 8491222512 ps
T1101 /workspace/coverage/default/39.uart_alert_test.2658145692 Mar 21 01:56:24 PM PDT 24 Mar 21 01:56:24 PM PDT 24 44744851 ps
T1102 /workspace/coverage/default/1.uart_long_xfer_wo_dly.731052735 Mar 21 01:52:47 PM PDT 24 Mar 21 01:56:22 PM PDT 24 64496955742 ps
T1103 /workspace/coverage/default/59.uart_fifo_reset.1568293905 Mar 21 01:57:19 PM PDT 24 Mar 21 01:58:21 PM PDT 24 67237651391 ps
T1104 /workspace/coverage/default/44.uart_stress_all.2182211452 Mar 21 01:56:51 PM PDT 24 Mar 21 02:23:10 PM PDT 24 576644012403 ps
T1105 /workspace/coverage/default/40.uart_rx_parity_err.203221791 Mar 21 01:56:24 PM PDT 24 Mar 21 01:56:31 PM PDT 24 10173756257 ps
T1106 /workspace/coverage/default/25.uart_stress_all.1482471164 Mar 21 01:54:59 PM PDT 24 Mar 21 01:57:30 PM PDT 24 222318617094 ps
T1107 /workspace/coverage/default/4.uart_fifo_full.3256496939 Mar 21 01:52:59 PM PDT 24 Mar 21 02:00:12 PM PDT 24 205014656428 ps
T1108 /workspace/coverage/default/21.uart_fifo_reset.2389593927 Mar 21 01:54:36 PM PDT 24 Mar 21 01:56:05 PM PDT 24 96667610675 ps
T1109 /workspace/coverage/default/287.uart_fifo_reset.4126112956 Mar 21 01:59:09 PM PDT 24 Mar 21 02:00:04 PM PDT 24 22205467663 ps
T1110 /workspace/coverage/default/19.uart_tx_rx.3555037207 Mar 21 01:54:39 PM PDT 24 Mar 21 01:55:36 PM PDT 24 106611305748 ps
T1111 /workspace/coverage/default/42.uart_noise_filter.2089932027 Mar 21 01:56:36 PM PDT 24 Mar 21 01:59:45 PM PDT 24 90340419738 ps
T1112 /workspace/coverage/default/119.uart_fifo_reset.4217318777 Mar 21 01:57:58 PM PDT 24 Mar 21 01:58:31 PM PDT 24 159655122708 ps
T1113 /workspace/coverage/default/39.uart_stress_all.2896880859 Mar 21 01:56:32 PM PDT 24 Mar 21 01:59:02 PM PDT 24 200694304787 ps
T1114 /workspace/coverage/default/262.uart_fifo_reset.1739605116 Mar 21 01:58:57 PM PDT 24 Mar 21 01:59:14 PM PDT 24 20790328725 ps
T1115 /workspace/coverage/default/207.uart_fifo_reset.1183186467 Mar 21 01:58:43 PM PDT 24 Mar 21 02:03:58 PM PDT 24 56127515375 ps
T85 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1982927515 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 193304080 ps
T114 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3900792093 Mar 21 03:11:15 PM PDT 24 Mar 21 03:11:17 PM PDT 24 317943279 ps
T86 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3455055409 Mar 21 03:11:51 PM PDT 24 Mar 21 03:11:53 PM PDT 24 42475392 ps
T1116 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4183118228 Mar 21 03:10:59 PM PDT 24 Mar 21 03:11:01 PM PDT 24 190762614 ps
T1117 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.486068776 Mar 21 03:11:17 PM PDT 24 Mar 21 03:11:19 PM PDT 24 70869531 ps
T1118 /workspace/coverage/cover_reg_top/20.uart_intr_test.243336253 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:43 PM PDT 24 18910485 ps
T1119 /workspace/coverage/cover_reg_top/35.uart_intr_test.3370942462 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 39101634 ps
T87 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1343817696 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 20261645 ps
T1120 /workspace/coverage/cover_reg_top/18.uart_intr_test.2963602668 Mar 21 03:11:43 PM PDT 24 Mar 21 03:11:44 PM PDT 24 27811685 ps
T88 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2728068380 Mar 21 03:11:17 PM PDT 24 Mar 21 03:11:18 PM PDT 24 47074469 ps
T1121 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2656796580 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:27 PM PDT 24 181796968 ps
T66 /workspace/coverage/cover_reg_top/13.uart_csr_rw.761933802 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:24 PM PDT 24 42746227 ps
T1122 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4285800580 Mar 21 03:11:30 PM PDT 24 Mar 21 03:11:31 PM PDT 24 22764320 ps
T1123 /workspace/coverage/cover_reg_top/44.uart_intr_test.2341404161 Mar 21 03:11:51 PM PDT 24 Mar 21 03:11:54 PM PDT 24 33068415 ps
T1124 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.15575340 Mar 21 03:11:08 PM PDT 24 Mar 21 03:11:09 PM PDT 24 11858750 ps
T67 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3016074094 Mar 21 03:10:59 PM PDT 24 Mar 21 03:11:00 PM PDT 24 56583668 ps
T89 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3375974731 Mar 21 03:11:01 PM PDT 24 Mar 21 03:11:02 PM PDT 24 93280603 ps
T1125 /workspace/coverage/cover_reg_top/8.uart_intr_test.4154986594 Mar 21 03:11:16 PM PDT 24 Mar 21 03:11:17 PM PDT 24 44377050 ps
T90 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1328131563 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:24 PM PDT 24 180501824 ps
T1126 /workspace/coverage/cover_reg_top/37.uart_intr_test.2826709444 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:40 PM PDT 24 54035346 ps
T1127 /workspace/coverage/cover_reg_top/34.uart_intr_test.737886649 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 60852567 ps
T1128 /workspace/coverage/cover_reg_top/0.uart_csr_rw.350782078 Mar 21 03:11:05 PM PDT 24 Mar 21 03:11:06 PM PDT 24 56389156 ps
T1129 /workspace/coverage/cover_reg_top/6.uart_intr_test.2414165675 Mar 21 03:11:11 PM PDT 24 Mar 21 03:11:12 PM PDT 24 35227720 ps
T1130 /workspace/coverage/cover_reg_top/21.uart_intr_test.2691637061 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 192097829 ps
T1131 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.473851008 Mar 21 03:11:01 PM PDT 24 Mar 21 03:11:01 PM PDT 24 13861320 ps
T1132 /workspace/coverage/cover_reg_top/19.uart_intr_test.1753436100 Mar 21 03:11:43 PM PDT 24 Mar 21 03:11:44 PM PDT 24 22359395 ps
T1133 /workspace/coverage/cover_reg_top/43.uart_intr_test.954928114 Mar 21 03:11:52 PM PDT 24 Mar 21 03:11:55 PM PDT 24 42402975 ps
T1134 /workspace/coverage/cover_reg_top/25.uart_intr_test.459874802 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:40 PM PDT 24 80191398 ps
T95 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1462456813 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:42 PM PDT 24 88229008 ps
T1135 /workspace/coverage/cover_reg_top/15.uart_intr_test.3255300829 Mar 21 03:11:39 PM PDT 24 Mar 21 03:11:40 PM PDT 24 16819210 ps
T1136 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.976153935 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:09 PM PDT 24 18194643 ps
T1137 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2053664211 Mar 21 03:10:59 PM PDT 24 Mar 21 03:11:01 PM PDT 24 73881662 ps
T91 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4233847048 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:24 PM PDT 24 59770084 ps
T1138 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.211659736 Mar 21 03:10:59 PM PDT 24 Mar 21 03:11:00 PM PDT 24 48807367 ps
T68 /workspace/coverage/cover_reg_top/4.uart_csr_rw.911861162 Mar 21 03:11:10 PM PDT 24 Mar 21 03:11:11 PM PDT 24 46292696 ps
T92 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3505589170 Mar 21 03:11:08 PM PDT 24 Mar 21 03:11:09 PM PDT 24 42386263 ps
T96 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.326603084 Mar 21 03:11:16 PM PDT 24 Mar 21 03:11:17 PM PDT 24 131419038 ps
T69 /workspace/coverage/cover_reg_top/9.uart_csr_rw.13352520 Mar 21 03:11:30 PM PDT 24 Mar 21 03:11:31 PM PDT 24 76906908 ps
T1139 /workspace/coverage/cover_reg_top/12.uart_intr_test.1200602361 Mar 21 03:11:25 PM PDT 24 Mar 21 03:11:25 PM PDT 24 24495728 ps
T1140 /workspace/coverage/cover_reg_top/48.uart_intr_test.2588643938 Mar 21 03:11:51 PM PDT 24 Mar 21 03:11:54 PM PDT 24 44135084 ps
T1141 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2023865226 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 21878351 ps
T1142 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.48230942 Mar 21 03:11:12 PM PDT 24 Mar 21 03:11:13 PM PDT 24 14613191 ps
T1143 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4113327791 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:25 PM PDT 24 15929198 ps
T1144 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4138903124 Mar 21 03:11:22 PM PDT 24 Mar 21 03:11:23 PM PDT 24 29345503 ps
T1145 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1174072598 Mar 21 03:11:08 PM PDT 24 Mar 21 03:11:09 PM PDT 24 25810033 ps
T1146 /workspace/coverage/cover_reg_top/41.uart_intr_test.2506938939 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:42 PM PDT 24 161757021 ps
T1147 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3168533961 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 46009254 ps
T1148 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.579035905 Mar 21 03:11:11 PM PDT 24 Mar 21 03:11:13 PM PDT 24 171353223 ps
T1149 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2422896070 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:24 PM PDT 24 20675946 ps
T97 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.307293775 Mar 21 03:11:07 PM PDT 24 Mar 21 03:11:08 PM PDT 24 93588955 ps
T1150 /workspace/coverage/cover_reg_top/1.uart_intr_test.2951109497 Mar 21 03:10:59 PM PDT 24 Mar 21 03:10:59 PM PDT 24 32633876 ps
T1151 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3940991016 Mar 21 03:10:59 PM PDT 24 Mar 21 03:10:59 PM PDT 24 62353144 ps
T1152 /workspace/coverage/cover_reg_top/14.uart_intr_test.257199795 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:25 PM PDT 24 27977582 ps
T1153 /workspace/coverage/cover_reg_top/45.uart_intr_test.4065836282 Mar 21 03:11:51 PM PDT 24 Mar 21 03:11:54 PM PDT 24 12623710 ps
T1154 /workspace/coverage/cover_reg_top/27.uart_intr_test.3657739633 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 19153087 ps
T1155 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3685381804 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 15147871 ps
T1156 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3308410460 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 74066849 ps
T1157 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1520962524 Mar 21 03:10:59 PM PDT 24 Mar 21 03:11:00 PM PDT 24 104153425 ps
T70 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1748731207 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:24 PM PDT 24 67374429 ps
T1158 /workspace/coverage/cover_reg_top/16.uart_intr_test.2793532147 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 14245964 ps
T1159 /workspace/coverage/cover_reg_top/33.uart_intr_test.4213893584 Mar 21 03:11:39 PM PDT 24 Mar 21 03:11:40 PM PDT 24 99609546 ps
T1160 /workspace/coverage/cover_reg_top/17.uart_intr_test.2945781102 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:43 PM PDT 24 13347177 ps
T1161 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2188119172 Mar 21 03:11:11 PM PDT 24 Mar 21 03:11:11 PM PDT 24 16820913 ps
T71 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.349708617 Mar 21 03:10:59 PM PDT 24 Mar 21 03:10:59 PM PDT 24 190860223 ps
T1162 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3148208220 Mar 21 03:11:22 PM PDT 24 Mar 21 03:11:24 PM PDT 24 89012009 ps
T99 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3562457412 Mar 21 03:11:30 PM PDT 24 Mar 21 03:11:31 PM PDT 24 46302255 ps
T1163 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1049862823 Mar 21 03:11:03 PM PDT 24 Mar 21 03:11:04 PM PDT 24 150850517 ps
T1164 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4215943082 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 124858153 ps
T100 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3633341865 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:26 PM PDT 24 92083988 ps
T1165 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2005306915 Mar 21 03:11:15 PM PDT 24 Mar 21 03:11:16 PM PDT 24 102650483 ps
T1166 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1239812278 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:43 PM PDT 24 181753233 ps
T1167 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.584577483 Mar 21 03:11:13 PM PDT 24 Mar 21 03:11:14 PM PDT 24 81658013 ps
T72 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3744746720 Mar 21 03:11:30 PM PDT 24 Mar 21 03:11:31 PM PDT 24 58906784 ps
T1168 /workspace/coverage/cover_reg_top/17.uart_tl_errors.385432516 Mar 21 03:11:45 PM PDT 24 Mar 21 03:11:48 PM PDT 24 285873740 ps
T1169 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3743834215 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:25 PM PDT 24 556837463 ps
T101 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.4034676837 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 195927206 ps
T1170 /workspace/coverage/cover_reg_top/40.uart_intr_test.1412318556 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:42 PM PDT 24 22409025 ps
T1171 /workspace/coverage/cover_reg_top/32.uart_intr_test.1138883657 Mar 21 03:11:44 PM PDT 24 Mar 21 03:11:45 PM PDT 24 16258381 ps
T1172 /workspace/coverage/cover_reg_top/30.uart_intr_test.2592328716 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:43 PM PDT 24 15157392 ps
T1173 /workspace/coverage/cover_reg_top/19.uart_tl_errors.378103129 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:42 PM PDT 24 401850458 ps
T1174 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.4208173663 Mar 21 03:11:02 PM PDT 24 Mar 21 03:11:03 PM PDT 24 24322880 ps
T1175 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4288598195 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 91615386 ps
T1176 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3288692472 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:24 PM PDT 24 151377676 ps
T1177 /workspace/coverage/cover_reg_top/47.uart_intr_test.3169534559 Mar 21 03:11:51 PM PDT 24 Mar 21 03:11:52 PM PDT 24 16938599 ps
T1178 /workspace/coverage/cover_reg_top/24.uart_intr_test.408709301 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:42 PM PDT 24 13369904 ps
T1179 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3408427712 Mar 21 03:11:00 PM PDT 24 Mar 21 03:11:01 PM PDT 24 65041881 ps
T1180 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2198810727 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:11 PM PDT 24 23646191 ps
T1181 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3276710447 Mar 21 03:11:03 PM PDT 24 Mar 21 03:11:04 PM PDT 24 120273807 ps
T1182 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3675122288 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:25 PM PDT 24 49675701 ps
T1183 /workspace/coverage/cover_reg_top/39.uart_intr_test.3396451182 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 21410813 ps
T98 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3083424317 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:44 PM PDT 24 340917291 ps
T1184 /workspace/coverage/cover_reg_top/1.uart_csr_rw.4196832644 Mar 21 03:10:58 PM PDT 24 Mar 21 03:10:59 PM PDT 24 16712561 ps
T1185 /workspace/coverage/cover_reg_top/28.uart_intr_test.2246210863 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 28299043 ps
T1186 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1062805501 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:25 PM PDT 24 118716863 ps
T1187 /workspace/coverage/cover_reg_top/26.uart_intr_test.3181242591 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 36497510 ps
T1188 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2565304299 Mar 21 03:11:22 PM PDT 24 Mar 21 03:11:25 PM PDT 24 59993323 ps
T1189 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1132152095 Mar 21 03:11:02 PM PDT 24 Mar 21 03:11:03 PM PDT 24 14092393 ps
T1190 /workspace/coverage/cover_reg_top/7.uart_intr_test.908217330 Mar 21 03:11:10 PM PDT 24 Mar 21 03:11:10 PM PDT 24 40357828 ps
T1191 /workspace/coverage/cover_reg_top/22.uart_intr_test.1024953705 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:41 PM PDT 24 36562387 ps
T1192 /workspace/coverage/cover_reg_top/4.uart_tl_errors.454801176 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:11 PM PDT 24 65140013 ps
T1193 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3986718091 Mar 21 03:11:21 PM PDT 24 Mar 21 03:11:22 PM PDT 24 350092924 ps
T1194 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3824882772 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:42 PM PDT 24 68169130 ps
T1195 /workspace/coverage/cover_reg_top/42.uart_intr_test.2661246413 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:43 PM PDT 24 43412871 ps
T1196 /workspace/coverage/cover_reg_top/36.uart_intr_test.3483782126 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:41 PM PDT 24 24834129 ps
T1197 /workspace/coverage/cover_reg_top/46.uart_intr_test.4036927645 Mar 21 03:11:54 PM PDT 24 Mar 21 03:11:56 PM PDT 24 15116544 ps
T1198 /workspace/coverage/cover_reg_top/15.uart_tl_errors.4248097064 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:26 PM PDT 24 69243558 ps
T73 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4111907873 Mar 21 03:10:59 PM PDT 24 Mar 21 03:11:02 PM PDT 24 259249791 ps
T1199 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.571282770 Mar 21 03:11:01 PM PDT 24 Mar 21 03:11:03 PM PDT 24 313187123 ps
T1200 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3247586971 Mar 21 03:11:22 PM PDT 24 Mar 21 03:11:23 PM PDT 24 17488717 ps
T1201 /workspace/coverage/cover_reg_top/5.uart_intr_test.573430271 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 66686181 ps
T1202 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1131406184 Mar 21 03:11:02 PM PDT 24 Mar 21 03:11:03 PM PDT 24 32791223 ps
T1203 /workspace/coverage/cover_reg_top/29.uart_intr_test.2623072102 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 44362248 ps
T1204 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1785689891 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 49685536 ps
T1205 /workspace/coverage/cover_reg_top/3.uart_intr_test.3545941611 Mar 21 03:11:00 PM PDT 24 Mar 21 03:11:00 PM PDT 24 61749942 ps
T1206 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1388289132 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:43 PM PDT 24 44569194 ps
T1207 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3421527170 Mar 21 03:11:10 PM PDT 24 Mar 21 03:11:11 PM PDT 24 13743956 ps
T83 /workspace/coverage/cover_reg_top/17.uart_csr_rw.191828907 Mar 21 03:11:44 PM PDT 24 Mar 21 03:11:45 PM PDT 24 15174238 ps
T1208 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2122956694 Mar 21 03:11:10 PM PDT 24 Mar 21 03:11:10 PM PDT 24 30685984 ps
T1209 /workspace/coverage/cover_reg_top/0.uart_tl_errors.4249662778 Mar 21 03:11:01 PM PDT 24 Mar 21 03:11:02 PM PDT 24 89123977 ps
T74 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1216057054 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 67719687 ps
T1210 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2266732007 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 30878904 ps
T1211 /workspace/coverage/cover_reg_top/2.uart_intr_test.8317779 Mar 21 03:11:03 PM PDT 24 Mar 21 03:11:04 PM PDT 24 19120023 ps
T1212 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1421785956 Mar 21 03:11:06 PM PDT 24 Mar 21 03:11:07 PM PDT 24 31800303 ps
T135 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.834948943 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:26 PM PDT 24 169712467 ps
T1213 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.445259629 Mar 21 03:11:16 PM PDT 24 Mar 21 03:11:17 PM PDT 24 54842172 ps
T1214 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3592911839 Mar 21 03:10:59 PM PDT 24 Mar 21 03:11:00 PM PDT 24 165021460 ps
T1215 /workspace/coverage/cover_reg_top/11.uart_intr_test.4208288403 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:25 PM PDT 24 50549189 ps
T136 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3083637627 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:25 PM PDT 24 625411765 ps
T1216 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2666702155 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:42 PM PDT 24 91278372 ps
T1217 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.157639249 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:43 PM PDT 24 54175429 ps
T1218 /workspace/coverage/cover_reg_top/3.uart_tl_errors.379552035 Mar 21 03:11:03 PM PDT 24 Mar 21 03:11:06 PM PDT 24 208005845 ps
T1219 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1986882558 Mar 21 03:11:40 PM PDT 24 Mar 21 03:11:41 PM PDT 24 20162528 ps
T1220 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.874368706 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:24 PM PDT 24 20077280 ps
T134 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2930696831 Mar 21 03:11:10 PM PDT 24 Mar 21 03:11:11 PM PDT 24 252252390 ps
T1221 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3563033243 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 27977629 ps
T1222 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1655537680 Mar 21 03:11:05 PM PDT 24 Mar 21 03:11:07 PM PDT 24 64735328 ps
T1223 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1946772921 Mar 21 03:11:00 PM PDT 24 Mar 21 03:11:02 PM PDT 24 130393707 ps
T1224 /workspace/coverage/cover_reg_top/49.uart_intr_test.2664377726 Mar 21 03:11:53 PM PDT 24 Mar 21 03:11:55 PM PDT 24 24017682 ps
T1225 /workspace/coverage/cover_reg_top/31.uart_intr_test.887313890 Mar 21 03:11:43 PM PDT 24 Mar 21 03:11:43 PM PDT 24 97034442 ps
T1226 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1972902077 Mar 21 03:11:16 PM PDT 24 Mar 21 03:11:17 PM PDT 24 319122359 ps
T1227 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.542728817 Mar 21 03:11:21 PM PDT 24 Mar 21 03:11:23 PM PDT 24 86141894 ps
T1228 /workspace/coverage/cover_reg_top/10.uart_intr_test.635542899 Mar 21 03:11:22 PM PDT 24 Mar 21 03:11:24 PM PDT 24 31064927 ps
T1229 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.276650801 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 30770242 ps
T1230 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1421925832 Mar 21 03:11:08 PM PDT 24 Mar 21 03:11:10 PM PDT 24 97788992 ps
T1231 /workspace/coverage/cover_reg_top/0.uart_intr_test.3768591698 Mar 21 03:11:11 PM PDT 24 Mar 21 03:11:12 PM PDT 24 25259735 ps
T1232 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2958523972 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 14939906 ps
T1233 /workspace/coverage/cover_reg_top/4.uart_intr_test.2809659802 Mar 21 03:11:16 PM PDT 24 Mar 21 03:11:16 PM PDT 24 14289108 ps
T1234 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3760020873 Mar 21 03:11:30 PM PDT 24 Mar 21 03:11:31 PM PDT 24 138989574 ps
T1235 /workspace/coverage/cover_reg_top/9.uart_intr_test.1798822532 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:24 PM PDT 24 23868210 ps
T1236 /workspace/coverage/cover_reg_top/38.uart_intr_test.898808535 Mar 21 03:11:43 PM PDT 24 Mar 21 03:11:43 PM PDT 24 34642736 ps
T1237 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3272113033 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 71001308 ps
T84 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1954395614 Mar 21 03:11:39 PM PDT 24 Mar 21 03:11:40 PM PDT 24 11897548 ps
T1238 /workspace/coverage/cover_reg_top/6.uart_tl_errors.597756434 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 18694795 ps
T1239 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4104047372 Mar 21 03:11:16 PM PDT 24 Mar 21 03:11:18 PM PDT 24 165799259 ps
T1240 /workspace/coverage/cover_reg_top/7.uart_tl_errors.859711094 Mar 21 03:11:16 PM PDT 24 Mar 21 03:11:18 PM PDT 24 2283702052 ps
T1241 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.753226940 Mar 21 03:11:41 PM PDT 24 Mar 21 03:11:42 PM PDT 24 699547304 ps
T1242 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2911753034 Mar 21 03:11:22 PM PDT 24 Mar 21 03:11:23 PM PDT 24 77883097 ps
T1243 /workspace/coverage/cover_reg_top/23.uart_intr_test.3158398450 Mar 21 03:11:42 PM PDT 24 Mar 21 03:11:42 PM PDT 24 35242880 ps
T1244 /workspace/coverage/cover_reg_top/13.uart_intr_test.440013205 Mar 21 03:11:23 PM PDT 24 Mar 21 03:11:24 PM PDT 24 12917624 ps
T1245 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4217264839 Mar 21 03:11:11 PM PDT 24 Mar 21 03:11:12 PM PDT 24 19312469 ps
T1246 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.699613646 Mar 21 03:11:03 PM PDT 24 Mar 21 03:11:05 PM PDT 24 142309276 ps
T1247 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1387614664 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 91631325 ps
T1248 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2167313293 Mar 21 03:11:24 PM PDT 24 Mar 21 03:11:25 PM PDT 24 21079840 ps
T1249 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4172339574 Mar 21 03:11:09 PM PDT 24 Mar 21 03:11:10 PM PDT 24 80436066 ps
T1250 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3270846892 Mar 21 03:11:21 PM PDT 24 Mar 21 03:11:24 PM PDT 24 324513809 ps

Test location /workspace/coverage/default/227.uart_fifo_reset.3146872182
Short name T2
Test name
Test status
Simulation time 17818708350 ps
CPU time 15.69 seconds
Started Mar 21 01:58:45 PM PDT 24
Finished Mar 21 01:59:01 PM PDT 24
Peak memory 200452 kb
Host smart-58192f40-27f9-42a6-81cf-da328dc44e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146872182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3146872182
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.836048972
Short name T28
Test name
Test status
Simulation time 120879367659 ps
CPU time 526.07 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 02:06:02 PM PDT 24
Peak memory 216760 kb
Host smart-045b083a-a656-4c27-b1b2-52f11a4bf67a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836048972 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.836048972
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.2862734411
Short name T25
Test name
Test status
Simulation time 538332627373 ps
CPU time 1249.12 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 02:14:03 PM PDT 24
Peak memory 200432 kb
Host smart-629b228f-614e-4c5a-90dc-91664ec945a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862734411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2862734411
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all.3197981226
Short name T18
Test name
Test status
Simulation time 421660030042 ps
CPU time 1638.32 seconds
Started Mar 21 01:55:13 PM PDT 24
Finished Mar 21 02:22:32 PM PDT 24
Peak memory 200408 kb
Host smart-47fba07a-2b34-4119-8d80-f8bf2a593e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197981226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3197981226
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all.3649103066
Short name T106
Test name
Test status
Simulation time 423170802583 ps
CPU time 1396.29 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 02:18:41 PM PDT 24
Peak memory 200420 kb
Host smart-8cc33178-f55f-4fe2-8f56-f7b61264b7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649103066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3649103066
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3044833764
Short name T145
Test name
Test status
Simulation time 248979364315 ps
CPU time 90.84 seconds
Started Mar 21 01:56:26 PM PDT 24
Finished Mar 21 01:57:57 PM PDT 24
Peak memory 200412 kb
Host smart-119e5eca-d1df-4568-9c76-b8cc5515b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044833764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3044833764
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.1751900551
Short name T16
Test name
Test status
Simulation time 160667797424 ps
CPU time 156.4 seconds
Started Mar 21 01:54:23 PM PDT 24
Finished Mar 21 01:56:59 PM PDT 24
Peak memory 200428 kb
Host smart-f912eb18-424a-4cae-90f3-3c9284cb8115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751900551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1751900551
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all.3017105342
Short name T21
Test name
Test status
Simulation time 130537446043 ps
CPU time 213.47 seconds
Started Mar 21 01:53:49 PM PDT 24
Finished Mar 21 01:57:23 PM PDT 24
Peak memory 200620 kb
Host smart-9f466a25-16dc-4472-97d8-e5bbef0464b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017105342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3017105342
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.942749498
Short name T37
Test name
Test status
Simulation time 119294621663 ps
CPU time 507.02 seconds
Started Mar 21 01:56:35 PM PDT 24
Finished Mar 21 02:05:05 PM PDT 24
Peak memory 216852 kb
Host smart-f6320f15-74bc-4d40-be8f-138543c6b080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942749498 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.942749498
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3043386380
Short name T32
Test name
Test status
Simulation time 255426754 ps
CPU time 0.8 seconds
Started Mar 21 01:52:59 PM PDT 24
Finished Mar 21 01:53:00 PM PDT 24
Peak memory 218480 kb
Host smart-c0ddba10-d226-4e9f-ba05-f549cda718e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043386380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3043386380
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2919525917
Short name T52
Test name
Test status
Simulation time 45742644905 ps
CPU time 337.73 seconds
Started Mar 21 01:56:39 PM PDT 24
Finished Mar 21 02:02:18 PM PDT 24
Peak memory 200392 kb
Host smart-0935b126-2479-40f3-8768-2e629065c3b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919525917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2919525917
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.541842410
Short name T42
Test name
Test status
Simulation time 638788837540 ps
CPU time 595.84 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 02:07:11 PM PDT 24
Peak memory 214412 kb
Host smart-5edd7b70-63c9-4caa-b330-20a8ba3f981d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541842410 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.541842410
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.2134198311
Short name T107
Test name
Test status
Simulation time 814639517023 ps
CPU time 322.72 seconds
Started Mar 21 01:56:44 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 208736 kb
Host smart-8dc69cd9-f6f1-4fd1-a132-652d92bfba10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134198311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2134198311
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1327138765
Short name T127
Test name
Test status
Simulation time 121068154130 ps
CPU time 347.01 seconds
Started Mar 21 01:57:12 PM PDT 24
Finished Mar 21 02:02:59 PM PDT 24
Peak memory 200324 kb
Host smart-5c458ef2-f039-4799-b6c7-22a16200167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327138765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1327138765
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1998349858
Short name T167
Test name
Test status
Simulation time 181856741340 ps
CPU time 353.15 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 02:05:05 PM PDT 24
Peak memory 200332 kb
Host smart-5dc25af6-9b27-4ab4-8542-cd94d9a51b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998349858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1998349858
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3083424317
Short name T98
Test name
Test status
Simulation time 340917291 ps
CPU time 1.3 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:44 PM PDT 24
Peak memory 199740 kb
Host smart-cf3c8000-45dd-4c5e-93d9-a2a7cae1bed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083424317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3083424317
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.125637060
Short name T260
Test name
Test status
Simulation time 113630851767 ps
CPU time 164.32 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:57:03 PM PDT 24
Peak memory 200320 kb
Host smart-e2a3cfaa-f598-4f0a-bc79-940c1d29b6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125637060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.125637060
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.306937125
Short name T38
Test name
Test status
Simulation time 186552498692 ps
CPU time 337.49 seconds
Started Mar 21 01:57:27 PM PDT 24
Finished Mar 21 02:03:05 PM PDT 24
Peak memory 226480 kb
Host smart-8ed9a976-0069-446a-8d9e-d291d026c486
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306937125 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.306937125
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.67922830
Short name T334
Test name
Test status
Simulation time 95373329 ps
CPU time 0.57 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:54:27 PM PDT 24
Peak memory 195464 kb
Host smart-986a83a0-1180-40b4-9785-b52c96686bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67922830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.67922830
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.4211486230
Short name T248
Test name
Test status
Simulation time 148901123591 ps
CPU time 264.07 seconds
Started Mar 21 01:56:57 PM PDT 24
Finished Mar 21 02:01:21 PM PDT 24
Peak memory 200476 kb
Host smart-ab739a65-5684-49c8-9c43-960c9fb1ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211486230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4211486230
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1456247473
Short name T162
Test name
Test status
Simulation time 52917445067 ps
CPU time 57.71 seconds
Started Mar 21 01:58:23 PM PDT 24
Finished Mar 21 01:59:21 PM PDT 24
Peak memory 200324 kb
Host smart-f81928bb-6b22-4727-97bf-0be8c8cbcb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456247473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1456247473
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3014977369
Short name T9
Test name
Test status
Simulation time 32871570236 ps
CPU time 56.37 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:59 PM PDT 24
Peak memory 200248 kb
Host smart-00f4f566-88f3-447a-9b53-fe19a92188e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014977369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3014977369
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3993012558
Short name T295
Test name
Test status
Simulation time 404320684081 ps
CPU time 543.03 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 02:05:16 PM PDT 24
Peak memory 217256 kb
Host smart-f685a33f-afda-4570-986a-a18c00a854ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993012558 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3993012558
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1593725547
Short name T300
Test name
Test status
Simulation time 81366961828 ps
CPU time 853.71 seconds
Started Mar 21 01:57:15 PM PDT 24
Finished Mar 21 02:11:28 PM PDT 24
Peak memory 228004 kb
Host smart-98539e57-cf73-47a7-9202-b79adac4c149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593725547 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1593725547
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3016074094
Short name T67
Test name
Test status
Simulation time 56583668 ps
CPU time 0.8 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:00 PM PDT 24
Peak memory 197116 kb
Host smart-7ffdff08-e2ed-4c61-a81d-e6f66b437243
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016074094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3016074094
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4233847048
Short name T91
Test name
Test status
Simulation time 59770084 ps
CPU time 0.73 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 197340 kb
Host smart-27a5a61d-7628-42ea-b180-569394cc35ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233847048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.4233847048
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/3.uart_stress_all.479546973
Short name T159
Test name
Test status
Simulation time 240509888981 ps
CPU time 278.45 seconds
Started Mar 21 01:53:04 PM PDT 24
Finished Mar 21 01:57:43 PM PDT 24
Peak memory 200432 kb
Host smart-df96be66-674b-412c-b006-1c26b53dabaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479546973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.479546973
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all.3119133663
Short name T131
Test name
Test status
Simulation time 139069467153 ps
CPU time 209.6 seconds
Started Mar 21 01:56:42 PM PDT 24
Finished Mar 21 02:00:13 PM PDT 24
Peak memory 200448 kb
Host smart-f2b8a4a5-af90-483a-ad1d-be3428cfae41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119133663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3119133663
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_fifo_full.867967527
Short name T266
Test name
Test status
Simulation time 121552988665 ps
CPU time 166.35 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:57:38 PM PDT 24
Peak memory 200376 kb
Host smart-556b9501-ca02-4099-ad07-18739c7018de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867967527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.867967527
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1229565533
Short name T62
Test name
Test status
Simulation time 253904049411 ps
CPU time 41.58 seconds
Started Mar 21 01:52:36 PM PDT 24
Finished Mar 21 01:53:18 PM PDT 24
Peak memory 200404 kb
Host smart-d7af9c5f-ae00-4c3e-b3ea-5ce22fc08738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229565533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1229565533
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3490316278
Short name T256
Test name
Test status
Simulation time 150632909515 ps
CPU time 363.19 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 02:00:08 PM PDT 24
Peak memory 200408 kb
Host smart-df13f54d-65bb-44db-9d47-abad20552bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490316278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3490316278
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.365956999
Short name T138
Test name
Test status
Simulation time 30322826924 ps
CPU time 16.06 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 01:59:12 PM PDT 24
Peak memory 200380 kb
Host smart-4e4bc99c-7079-440e-8e39-400f22363568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365956999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.365956999
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.2530671336
Short name T269
Test name
Test status
Simulation time 154552663896 ps
CPU time 394.48 seconds
Started Mar 21 01:55:00 PM PDT 24
Finished Mar 21 02:01:35 PM PDT 24
Peak memory 216540 kb
Host smart-4301c550-f308-4ad6-bd86-4a53baea3c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530671336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2530671336
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.301540692
Short name T202
Test name
Test status
Simulation time 50668200772 ps
CPU time 21.3 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 01:59:33 PM PDT 24
Peak memory 200460 kb
Host smart-315f1719-3f07-4690-932c-84f296f94906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301540692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.301540692
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1679771843
Short name T119
Test name
Test status
Simulation time 199333959087 ps
CPU time 132.32 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:58:25 PM PDT 24
Peak memory 200436 kb
Host smart-71d43e8a-9dc3-48a1-9b9c-a27ed753ea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679771843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1679771843
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3708212795
Short name T181
Test name
Test status
Simulation time 135194185137 ps
CPU time 67.37 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 01:59:31 PM PDT 24
Peak memory 200416 kb
Host smart-a3bf1852-688f-4e9f-bfcb-eb5126080c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708212795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3708212795
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3702931494
Short name T137
Test name
Test status
Simulation time 151565660735 ps
CPU time 16.67 seconds
Started Mar 21 01:59:08 PM PDT 24
Finished Mar 21 01:59:25 PM PDT 24
Peak memory 200268 kb
Host smart-43ca7c43-a65a-4623-93d5-c6b101b4f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702931494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3702931494
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.2237418032
Short name T582
Test name
Test status
Simulation time 230340570312 ps
CPU time 134.46 seconds
Started Mar 21 01:55:41 PM PDT 24
Finished Mar 21 01:57:56 PM PDT 24
Peak memory 200432 kb
Host smart-09dbe40b-41d6-4174-85ab-6622923ae512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237418032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2237418032
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2756184679
Short name T47
Test name
Test status
Simulation time 134770082553 ps
CPU time 44.2 seconds
Started Mar 21 01:56:35 PM PDT 24
Finished Mar 21 01:57:20 PM PDT 24
Peak memory 200372 kb
Host smart-f662c6ad-dc2e-4f8e-8c6f-107a1c1d7613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756184679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2756184679
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3127191194
Short name T486
Test name
Test status
Simulation time 64526056189 ps
CPU time 56.32 seconds
Started Mar 21 01:53:25 PM PDT 24
Finished Mar 21 01:54:21 PM PDT 24
Peak memory 200312 kb
Host smart-ba7c83ad-c922-4f8d-989c-105160e368e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127191194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3127191194
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.4181897328
Short name T218
Test name
Test status
Simulation time 18014967766 ps
CPU time 19.03 seconds
Started Mar 21 01:58:23 PM PDT 24
Finished Mar 21 01:58:42 PM PDT 24
Peak memory 200372 kb
Host smart-28e4581a-3788-40cb-be8c-62015c09fa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181897328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.4181897328
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1843040824
Short name T65
Test name
Test status
Simulation time 344032209649 ps
CPU time 654.27 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 02:05:33 PM PDT 24
Peak memory 225264 kb
Host smart-3ea068ef-7db8-411f-9dcd-cbaa1736c43e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843040824 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1843040824
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1668631933
Short name T211
Test name
Test status
Simulation time 108264585410 ps
CPU time 430.15 seconds
Started Mar 21 01:58:55 PM PDT 24
Finished Mar 21 02:06:05 PM PDT 24
Peak memory 200356 kb
Host smart-b8917e52-a720-43d3-98dc-0165145b690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668631933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1668631933
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1657322809
Short name T123
Test name
Test status
Simulation time 86788588474 ps
CPU time 41.99 seconds
Started Mar 21 01:59:10 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 200456 kb
Host smart-7bdab1eb-3a85-40e2-a8e7-e2b2a509eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657322809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1657322809
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2499730120
Short name T178
Test name
Test status
Simulation time 719397826242 ps
CPU time 675.65 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 02:06:59 PM PDT 24
Peak memory 225280 kb
Host smart-274eb317-59b8-410f-b829-1ba697506846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499730120 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2499730120
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2751891088
Short name T185
Test name
Test status
Simulation time 41192166216 ps
CPU time 19.79 seconds
Started Mar 21 01:58:27 PM PDT 24
Finished Mar 21 01:58:46 PM PDT 24
Peak memory 200352 kb
Host smart-7caa7bcf-c1f7-4172-8f85-d65db0c8862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751891088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2751891088
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1094771563
Short name T8
Test name
Test status
Simulation time 36042917308 ps
CPU time 58.25 seconds
Started Mar 21 01:58:55 PM PDT 24
Finished Mar 21 01:59:53 PM PDT 24
Peak memory 200444 kb
Host smart-cbd1b36d-ad14-43c4-b51b-2f5c8f3c0eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094771563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1094771563
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.598365648
Short name T110
Test name
Test status
Simulation time 42731521888 ps
CPU time 36.04 seconds
Started Mar 21 01:58:57 PM PDT 24
Finished Mar 21 01:59:34 PM PDT 24
Peak memory 200372 kb
Host smart-fb48159f-89bb-4a02-9aba-1237c7cbecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598365648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.598365648
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.717543640
Short name T224
Test name
Test status
Simulation time 29169369092 ps
CPU time 144.42 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:59:27 PM PDT 24
Peak memory 215880 kb
Host smart-de501cea-5ae9-4d99-ad74-2cd42d94d629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717543640 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.717543640
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3083637627
Short name T136
Test name
Test status
Simulation time 625411765 ps
CPU time 1.38 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 199992 kb
Host smart-012f13dc-039f-4bff-a87e-502e854f6082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083637627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3083637627
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_smoke.1081821715
Short name T310
Test name
Test status
Simulation time 295552248 ps
CPU time 1.18 seconds
Started Mar 21 01:52:33 PM PDT 24
Finished Mar 21 01:52:34 PM PDT 24
Peak memory 200388 kb
Host smart-0d5255e6-4b4b-4ef9-8c84-5d3e9b4d24fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081821715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1081821715
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.821673957
Short name T169
Test name
Test status
Simulation time 55521758729 ps
CPU time 108.48 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:59:48 PM PDT 24
Peak memory 200348 kb
Host smart-0cc7eabb-50ba-4879-a47d-740c040bf757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821673957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.821673957
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.999560143
Short name T603
Test name
Test status
Simulation time 57205915325 ps
CPU time 94.74 seconds
Started Mar 21 01:57:57 PM PDT 24
Finished Mar 21 01:59:32 PM PDT 24
Peak memory 200396 kb
Host smart-c204c26a-d9f8-4edd-b4e5-8e4aa03bff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999560143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.999560143
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.844454550
Short name T189
Test name
Test status
Simulation time 58740260753 ps
CPU time 115.39 seconds
Started Mar 21 01:57:57 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 200376 kb
Host smart-80004038-5f8f-416c-bad3-414cfb8f8226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844454550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.844454550
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1076505784
Short name T736
Test name
Test status
Simulation time 58663410164 ps
CPU time 25.74 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:58:25 PM PDT 24
Peak memory 200368 kb
Host smart-fc9f3f9a-ba42-4a0f-a849-fd7cf110b8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076505784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1076505784
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.4124129551
Short name T221
Test name
Test status
Simulation time 126093920914 ps
CPU time 246.23 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 02:02:06 PM PDT 24
Peak memory 200468 kb
Host smart-4fed6d04-b09e-4afd-a9ee-4b1e9fc6b35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124129551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.4124129551
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2355068986
Short name T227
Test name
Test status
Simulation time 100770404603 ps
CPU time 219.82 seconds
Started Mar 21 01:57:57 PM PDT 24
Finished Mar 21 02:01:39 PM PDT 24
Peak memory 200424 kb
Host smart-4571e9a3-d47b-4d9e-8c9e-60da270befef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355068986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2355068986
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1516150883
Short name T203
Test name
Test status
Simulation time 184568530547 ps
CPU time 185.69 seconds
Started Mar 21 01:58:03 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 200428 kb
Host smart-f70c960a-4d8d-4479-97b8-5e90e1d3adc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516150883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1516150883
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1785648296
Short name T531
Test name
Test status
Simulation time 91856682035 ps
CPU time 139.32 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 01:56:36 PM PDT 24
Peak memory 200448 kb
Host smart-b6760d61-dd5c-4303-8b02-967ce7c4b2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785648296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1785648296
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3546881186
Short name T27
Test name
Test status
Simulation time 36329753271 ps
CPU time 335.34 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 217076 kb
Host smart-28875161-3829-4979-8654-94dc583ea792
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546881186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3546881186
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3257423387
Short name T156
Test name
Test status
Simulation time 110486919916 ps
CPU time 91.27 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 01:59:56 PM PDT 24
Peak memory 200320 kb
Host smart-b68e739f-4688-4e61-822c-2b260e7d4b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257423387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3257423387
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1354429979
Short name T229
Test name
Test status
Simulation time 120656385792 ps
CPU time 92 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 02:00:28 PM PDT 24
Peak memory 200416 kb
Host smart-8c03e291-d33b-421a-aeb6-ae813e3c84ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354429979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1354429979
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4249545013
Short name T235
Test name
Test status
Simulation time 67529816061 ps
CPU time 55.6 seconds
Started Mar 21 01:58:54 PM PDT 24
Finished Mar 21 01:59:49 PM PDT 24
Peak memory 200208 kb
Host smart-78c6920a-eb20-48c4-8669-437e6b2ec677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249545013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4249545013
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2002398114
Short name T932
Test name
Test status
Simulation time 21958715891 ps
CPU time 33.86 seconds
Started Mar 21 01:58:57 PM PDT 24
Finished Mar 21 01:59:31 PM PDT 24
Peak memory 200384 kb
Host smart-86cbeb86-dff3-496c-9882-d5101dd9ae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002398114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2002398114
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.682691485
Short name T237
Test name
Test status
Simulation time 57223272295 ps
CPU time 87.3 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 02:00:23 PM PDT 24
Peak memory 200312 kb
Host smart-d864c08c-baf1-42d1-9786-e581db527239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682691485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.682691485
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1233878860
Short name T233
Test name
Test status
Simulation time 117264686190 ps
CPU time 36.86 seconds
Started Mar 21 01:55:13 PM PDT 24
Finished Mar 21 01:55:50 PM PDT 24
Peak memory 200444 kb
Host smart-ade31ae8-3f65-42b3-926f-2fafd43080be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233878860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1233878860
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.701137003
Short name T43
Test name
Test status
Simulation time 260214085358 ps
CPU time 727.7 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 02:07:22 PM PDT 24
Peak memory 225256 kb
Host smart-743329f0-59fc-438d-8dc4-21d5fdb30784
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701137003 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.701137003
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2359547618
Short name T304
Test name
Test status
Simulation time 25778799209 ps
CPU time 609.86 seconds
Started Mar 21 01:56:25 PM PDT 24
Finished Mar 21 02:06:36 PM PDT 24
Peak memory 208768 kb
Host smart-b215999b-dfe1-4664-a99b-36b4c8eea97d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359547618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2359547618
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3522116597
Short name T165
Test name
Test status
Simulation time 275689103967 ps
CPU time 108.28 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:58:50 PM PDT 24
Peak memory 200436 kb
Host smart-30ae08c1-8b28-4849-a922-1dbbb110bdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522116597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3522116597
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.310734313
Short name T149
Test name
Test status
Simulation time 70258667208 ps
CPU time 106.29 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 01:59:02 PM PDT 24
Peak memory 200336 kb
Host smart-895912fd-fbd8-4a6d-b681-9b5745bc13ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310734313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.310734313
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3282010745
Short name T160
Test name
Test status
Simulation time 107067238244 ps
CPU time 186.34 seconds
Started Mar 21 01:57:15 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 200468 kb
Host smart-04d9aa39-1fca-47fb-b06c-fc573fc9fffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282010745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3282010745
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2459736571
Short name T176
Test name
Test status
Simulation time 155768734666 ps
CPU time 182.38 seconds
Started Mar 21 01:57:27 PM PDT 24
Finished Mar 21 02:00:30 PM PDT 24
Peak memory 200332 kb
Host smart-c8235015-4164-4d94-a263-c4a1e037c749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459736571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2459736571
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4183118228
Short name T1116
Test name
Test status
Simulation time 190762614 ps
CPU time 1.57 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:01 PM PDT 24
Peak memory 198452 kb
Host smart-83607a0e-cf32-42be-9076-53d87c6aad77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183118228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4183118228
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.349708617
Short name T71
Test name
Test status
Simulation time 190860223 ps
CPU time 0.61 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:10:59 PM PDT 24
Peak memory 195816 kb
Host smart-f6a96af6-d2e0-4418-9da3-49a3c73c8ed0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349708617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.349708617
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1131406184
Short name T1202
Test name
Test status
Simulation time 32791223 ps
CPU time 0.98 seconds
Started Mar 21 03:11:02 PM PDT 24
Finished Mar 21 03:11:03 PM PDT 24
Peak memory 200252 kb
Host smart-bf4118f0-43c2-4bb2-9ef5-53eabcc2f581
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131406184 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1131406184
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.350782078
Short name T1128
Test name
Test status
Simulation time 56389156 ps
CPU time 0.62 seconds
Started Mar 21 03:11:05 PM PDT 24
Finished Mar 21 03:11:06 PM PDT 24
Peak memory 195788 kb
Host smart-9b5e464c-ff0e-41da-a4e1-ebcbda050a27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350782078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.350782078
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3768591698
Short name T1231
Test name
Test status
Simulation time 25259735 ps
CPU time 0.55 seconds
Started Mar 21 03:11:11 PM PDT 24
Finished Mar 21 03:11:12 PM PDT 24
Peak memory 194836 kb
Host smart-38744a31-3325-4e5b-834e-ad89d314438b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768591698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3768591698
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3276710447
Short name T1181
Test name
Test status
Simulation time 120273807 ps
CPU time 0.79 seconds
Started Mar 21 03:11:03 PM PDT 24
Finished Mar 21 03:11:04 PM PDT 24
Peak memory 197932 kb
Host smart-2a8ba091-328f-4aa8-94eb-262e5919275e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276710447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3276710447
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.4249662778
Short name T1209
Test name
Test status
Simulation time 89123977 ps
CPU time 1.06 seconds
Started Mar 21 03:11:01 PM PDT 24
Finished Mar 21 03:11:02 PM PDT 24
Peak memory 199120 kb
Host smart-a80f988e-36e4-4787-9e98-772bf3084e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249662778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4249662778
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3408427712
Short name T1179
Test name
Test status
Simulation time 65041881 ps
CPU time 1.25 seconds
Started Mar 21 03:11:00 PM PDT 24
Finished Mar 21 03:11:01 PM PDT 24
Peak memory 199712 kb
Host smart-358bb171-15de-43c3-a0bf-2c815a58add5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408427712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3408427712
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3940991016
Short name T1151
Test name
Test status
Simulation time 62353144 ps
CPU time 0.69 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:10:59 PM PDT 24
Peak memory 195848 kb
Host smart-b8685b7b-7d5d-4b78-ad35-89a436df5614
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940991016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3940991016
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.699613646
Short name T1246
Test name
Test status
Simulation time 142309276 ps
CPU time 2.22 seconds
Started Mar 21 03:11:03 PM PDT 24
Finished Mar 21 03:11:05 PM PDT 24
Peak memory 198060 kb
Host smart-d085dba0-62ef-4338-8db6-fd30eed95a47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699613646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.699613646
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1421785956
Short name T1212
Test name
Test status
Simulation time 31800303 ps
CPU time 0.61 seconds
Started Mar 21 03:11:06 PM PDT 24
Finished Mar 21 03:11:07 PM PDT 24
Peak memory 195784 kb
Host smart-0ab09f0f-a02d-447e-a5ba-6f0d6f3dbfc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421785956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1421785956
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1655537680
Short name T1222
Test name
Test status
Simulation time 64735328 ps
CPU time 1.1 seconds
Started Mar 21 03:11:05 PM PDT 24
Finished Mar 21 03:11:07 PM PDT 24
Peak memory 200264 kb
Host smart-e0b7db88-5f21-4544-b2cb-cedb6b830914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655537680 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1655537680
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.4196832644
Short name T1184
Test name
Test status
Simulation time 16712561 ps
CPU time 0.59 seconds
Started Mar 21 03:10:58 PM PDT 24
Finished Mar 21 03:10:59 PM PDT 24
Peak memory 195932 kb
Host smart-87e30385-5596-4d98-92c9-d4b60d204465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196832644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.4196832644
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2951109497
Short name T1150
Test name
Test status
Simulation time 32633876 ps
CPU time 0.58 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:10:59 PM PDT 24
Peak memory 194880 kb
Host smart-ed86c151-bff5-4170-990f-0cf9747df6d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951109497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2951109497
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.4208173663
Short name T1174
Test name
Test status
Simulation time 24322880 ps
CPU time 0.74 seconds
Started Mar 21 03:11:02 PM PDT 24
Finished Mar 21 03:11:03 PM PDT 24
Peak memory 197312 kb
Host smart-2a170bc6-0419-4422-9a73-f389c5af42d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208173663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.4208173663
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1520962524
Short name T1157
Test name
Test status
Simulation time 104153425 ps
CPU time 1.26 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:00 PM PDT 24
Peak memory 200512 kb
Host smart-c5032c42-fa03-4ea2-9ec3-6d2a5cd34816
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520962524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1520962524
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.571282770
Short name T1199
Test name
Test status
Simulation time 313187123 ps
CPU time 1.37 seconds
Started Mar 21 03:11:01 PM PDT 24
Finished Mar 21 03:11:03 PM PDT 24
Peak memory 199880 kb
Host smart-6eb1ee2b-1c08-42b5-be6e-510aca4c9b70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571282770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.571282770
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4138903124
Short name T1144
Test name
Test status
Simulation time 29345503 ps
CPU time 0.8 seconds
Started Mar 21 03:11:22 PM PDT 24
Finished Mar 21 03:11:23 PM PDT 24
Peak memory 198980 kb
Host smart-645e3bd1-6c0f-401f-a54e-c5424851ee13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138903124 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4138903124
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1748731207
Short name T70
Test name
Test status
Simulation time 67374429 ps
CPU time 0.64 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 195896 kb
Host smart-2ce17b16-88df-4213-9628-408850e9e02e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748731207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1748731207
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.635542899
Short name T1228
Test name
Test status
Simulation time 31064927 ps
CPU time 0.64 seconds
Started Mar 21 03:11:22 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 194780 kb
Host smart-76c7ee90-6a0f-4d76-a585-9ca546b56efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635542899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.635542899
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3288692472
Short name T1176
Test name
Test status
Simulation time 151377676 ps
CPU time 0.64 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 196272 kb
Host smart-d5f3eaa5-55bb-4ab2-8df5-883361bd0ff6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288692472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3288692472
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2565304299
Short name T1188
Test name
Test status
Simulation time 59993323 ps
CPU time 1.21 seconds
Started Mar 21 03:11:22 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 200484 kb
Host smart-ce36ff9a-3fce-487c-a54b-053ad70c2227
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565304299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2565304299
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3633341865
Short name T100
Test name
Test status
Simulation time 92083988 ps
CPU time 1.41 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:26 PM PDT 24
Peak memory 199852 kb
Host smart-53eee162-cec6-4c70-9118-c85b7e78b6d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633341865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3633341865
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4113327791
Short name T1143
Test name
Test status
Simulation time 15929198 ps
CPU time 0.71 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 197916 kb
Host smart-7aca7dff-2cd0-4a43-adc8-93780f3d68bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113327791 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4113327791
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3247586971
Short name T1200
Test name
Test status
Simulation time 17488717 ps
CPU time 0.6 seconds
Started Mar 21 03:11:22 PM PDT 24
Finished Mar 21 03:11:23 PM PDT 24
Peak memory 195824 kb
Host smart-48d57c9f-6d83-4126-a9cc-5896845bbb74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247586971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3247586971
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4208288403
Short name T1215
Test name
Test status
Simulation time 50549189 ps
CPU time 0.58 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 194752 kb
Host smart-4b3b8f16-ecd1-4c2b-acdd-e7c03981388c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208288403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4208288403
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3760020873
Short name T1234
Test name
Test status
Simulation time 138989574 ps
CPU time 0.65 seconds
Started Mar 21 03:11:30 PM PDT 24
Finished Mar 21 03:11:31 PM PDT 24
Peak memory 195976 kb
Host smart-516fb0ae-a81f-45f3-950a-9652f836b015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760020873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3760020873
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1062805501
Short name T1186
Test name
Test status
Simulation time 118716863 ps
CPU time 1.35 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 200528 kb
Host smart-806773ec-ab68-4f34-ad95-94b2230a2226
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062805501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1062805501
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3743834215
Short name T1169
Test name
Test status
Simulation time 556837463 ps
CPU time 1.11 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 199548 kb
Host smart-e6ddca9a-faf1-4f3d-bf76-cab0d2982159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743834215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3743834215
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3675122288
Short name T1182
Test name
Test status
Simulation time 49675701 ps
CPU time 0.79 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 199616 kb
Host smart-13a5df5d-c93b-4a69-9a3d-6ac2816a87d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675122288 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3675122288
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3744746720
Short name T72
Test name
Test status
Simulation time 58906784 ps
CPU time 0.65 seconds
Started Mar 21 03:11:30 PM PDT 24
Finished Mar 21 03:11:31 PM PDT 24
Peak memory 196224 kb
Host smart-6e68042a-fcfd-44f4-9955-4b3220b5884e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744746720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3744746720
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1200602361
Short name T1139
Test name
Test status
Simulation time 24495728 ps
CPU time 0.58 seconds
Started Mar 21 03:11:25 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 194788 kb
Host smart-ecf269a6-7389-4db8-81ee-d2217a83b7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200602361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1200602361
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2656796580
Short name T1121
Test name
Test status
Simulation time 181796968 ps
CPU time 2.5 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:27 PM PDT 24
Peak memory 200548 kb
Host smart-2d7abd6b-7c45-489b-84a5-c734917ceabe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656796580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2656796580
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2911753034
Short name T1242
Test name
Test status
Simulation time 77883097 ps
CPU time 0.72 seconds
Started Mar 21 03:11:22 PM PDT 24
Finished Mar 21 03:11:23 PM PDT 24
Peak memory 198752 kb
Host smart-95d9c495-6ba4-45d0-82a0-631222c3a3f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911753034 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2911753034
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.761933802
Short name T66
Test name
Test status
Simulation time 42746227 ps
CPU time 0.6 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 195828 kb
Host smart-e2939c24-2a62-4825-9e28-ab83264636b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761933802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.761933802
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.440013205
Short name T1244
Test name
Test status
Simulation time 12917624 ps
CPU time 0.6 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 194828 kb
Host smart-1c336e5d-af27-4d59-8033-568dca736d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440013205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.440013205
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1328131563
Short name T90
Test name
Test status
Simulation time 180501824 ps
CPU time 0.75 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 197464 kb
Host smart-e7f17beb-cf7f-4411-bfac-085c67df4845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328131563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1328131563
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2167313293
Short name T1248
Test name
Test status
Simulation time 21079840 ps
CPU time 1.06 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 200524 kb
Host smart-1461b8c3-82af-468e-86f4-30b0e4dca38c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167313293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2167313293
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.834948943
Short name T135
Test name
Test status
Simulation time 169712467 ps
CPU time 1.37 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:26 PM PDT 24
Peak memory 199764 kb
Host smart-5e6cc3e6-942e-4274-9837-6f4470c004e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834948943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.834948943
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3986718091
Short name T1193
Test name
Test status
Simulation time 350092924 ps
CPU time 0.77 seconds
Started Mar 21 03:11:21 PM PDT 24
Finished Mar 21 03:11:22 PM PDT 24
Peak memory 198660 kb
Host smart-1010e377-696d-499f-9dfe-e8ad0d96c756
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986718091 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3986718091
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2422896070
Short name T1149
Test name
Test status
Simulation time 20675946 ps
CPU time 0.62 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 195952 kb
Host smart-41048c49-8361-4396-8098-8c6f4fd6d3b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422896070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2422896070
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.257199795
Short name T1152
Test name
Test status
Simulation time 27977582 ps
CPU time 0.59 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:25 PM PDT 24
Peak memory 194852 kb
Host smart-1d92fad3-8698-47ff-ba5a-53d546bf5df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257199795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.257199795
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3148208220
Short name T1162
Test name
Test status
Simulation time 89012009 ps
CPU time 0.66 seconds
Started Mar 21 03:11:22 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 196324 kb
Host smart-fe5b7367-cb22-4489-abf8-be44d06ceb4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148208220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3148208220
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3270846892
Short name T1250
Test name
Test status
Simulation time 324513809 ps
CPU time 1.72 seconds
Started Mar 21 03:11:21 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 200544 kb
Host smart-0f4b3c75-538b-4b44-b584-c29ee631e388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270846892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3270846892
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3562457412
Short name T99
Test name
Test status
Simulation time 46302255 ps
CPU time 0.98 seconds
Started Mar 21 03:11:30 PM PDT 24
Finished Mar 21 03:11:31 PM PDT 24
Peak memory 199360 kb
Host smart-1b876be1-c79a-48ac-9fbc-258d2a6c7541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562457412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3562457412
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3563033243
Short name T1221
Test name
Test status
Simulation time 27977629 ps
CPU time 0.89 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 200276 kb
Host smart-8466b5c8-dc69-41e1-a930-e342277cdff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563033243 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3563033243
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1388289132
Short name T1206
Test name
Test status
Simulation time 44569194 ps
CPU time 0.6 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 195784 kb
Host smart-08e5adf2-9298-4a08-90fc-4964d3c5e1af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388289132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1388289132
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3255300829
Short name T1135
Test name
Test status
Simulation time 16819210 ps
CPU time 0.58 seconds
Started Mar 21 03:11:39 PM PDT 24
Finished Mar 21 03:11:40 PM PDT 24
Peak memory 194780 kb
Host smart-9b976d28-b2b5-4680-a4b4-c10fd8f32b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255300829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3255300829
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1986882558
Short name T1219
Test name
Test status
Simulation time 20162528 ps
CPU time 0.64 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 196188 kb
Host smart-348fba47-5271-464b-acc8-56ccd9afd423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986882558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1986882558
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4248097064
Short name T1198
Test name
Test status
Simulation time 69243558 ps
CPU time 1.74 seconds
Started Mar 21 03:11:24 PM PDT 24
Finished Mar 21 03:11:26 PM PDT 24
Peak memory 200492 kb
Host smart-9d495726-8573-450a-8636-8b952fb27745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248097064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4248097064
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2666702155
Short name T1216
Test name
Test status
Simulation time 91278372 ps
CPU time 1.39 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 199756 kb
Host smart-51d460f4-f70c-4509-9e74-4ba34a640c25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666702155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2666702155
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4288598195
Short name T1175
Test name
Test status
Simulation time 91615386 ps
CPU time 1.28 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 200516 kb
Host smart-52719776-70d2-49cb-b434-2d2fac7ab0b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288598195 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4288598195
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1954395614
Short name T84
Test name
Test status
Simulation time 11897548 ps
CPU time 0.62 seconds
Started Mar 21 03:11:39 PM PDT 24
Finished Mar 21 03:11:40 PM PDT 24
Peak memory 196132 kb
Host smart-7697576c-3330-4a84-8653-03d4c2fe9335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954395614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1954395614
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2793532147
Short name T1158
Test name
Test status
Simulation time 14245964 ps
CPU time 0.62 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 194788 kb
Host smart-3cdf012b-259f-412f-b0a7-832a7702ac1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793532147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2793532147
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.157639249
Short name T1217
Test name
Test status
Simulation time 54175429 ps
CPU time 0.75 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 197928 kb
Host smart-220ae900-0533-4e6d-8d6a-b42a5501aff7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157639249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.157639249
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3824882772
Short name T1194
Test name
Test status
Simulation time 68169130 ps
CPU time 2.23 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 200548 kb
Host smart-6eeb63dc-448c-426a-ac97-2debbdb236e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824882772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3824882772
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.753226940
Short name T1241
Test name
Test status
Simulation time 699547304 ps
CPU time 1.42 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 199860 kb
Host smart-dbbefb83-0da3-47bd-a3b1-4e94a2e247d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753226940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.753226940
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4215943082
Short name T1164
Test name
Test status
Simulation time 124858153 ps
CPU time 0.78 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 199084 kb
Host smart-40d5cd29-28c5-4455-967c-ff53673d106b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215943082 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4215943082
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.191828907
Short name T83
Test name
Test status
Simulation time 15174238 ps
CPU time 0.59 seconds
Started Mar 21 03:11:44 PM PDT 24
Finished Mar 21 03:11:45 PM PDT 24
Peak memory 195836 kb
Host smart-609b7823-2cb7-4061-b53b-76f39baaf724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191828907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.191828907
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2945781102
Short name T1160
Test name
Test status
Simulation time 13347177 ps
CPU time 0.59 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 194856 kb
Host smart-6349f283-f980-4036-ae81-ff848ca70ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945781102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2945781102
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2958523972
Short name T1232
Test name
Test status
Simulation time 14939906 ps
CPU time 0.63 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 194920 kb
Host smart-1e039244-7a00-4ceb-9fff-32fa0cce8b7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958523972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2958523972
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.385432516
Short name T1168
Test name
Test status
Simulation time 285873740 ps
CPU time 2.16 seconds
Started Mar 21 03:11:45 PM PDT 24
Finished Mar 21 03:11:48 PM PDT 24
Peak memory 200544 kb
Host smart-5bf83cb4-a3b4-4d62-b7ec-43e7db5948c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385432516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.385432516
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1462456813
Short name T95
Test name
Test status
Simulation time 88229008 ps
CPU time 1.38 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 200000 kb
Host smart-80984341-777f-474b-8d83-192b7cc14d02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462456813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1462456813
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3685381804
Short name T1155
Test name
Test status
Simulation time 15147871 ps
CPU time 0.75 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 198428 kb
Host smart-62a74115-cfd8-4b6f-b824-170241ceea80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685381804 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3685381804
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3455055409
Short name T86
Test name
Test status
Simulation time 42475392 ps
CPU time 0.59 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:11:53 PM PDT 24
Peak memory 195920 kb
Host smart-adc0d717-0c02-4929-8856-16dfa3a2323e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455055409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3455055409
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2963602668
Short name T1120
Test name
Test status
Simulation time 27811685 ps
CPU time 0.6 seconds
Started Mar 21 03:11:43 PM PDT 24
Finished Mar 21 03:11:44 PM PDT 24
Peak memory 194804 kb
Host smart-709e7012-9c95-4930-887d-400537a75c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963602668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2963602668
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1343817696
Short name T87
Test name
Test status
Simulation time 20261645 ps
CPU time 0.69 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 196256 kb
Host smart-d168d6d2-7388-42b3-b58e-e768b18f8c99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343817696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1343817696
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1239812278
Short name T1166
Test name
Test status
Simulation time 181753233 ps
CPU time 1.14 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 200540 kb
Host smart-261b41eb-291d-4974-9be7-ecc3427de603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239812278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1239812278
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.4034676837
Short name T101
Test name
Test status
Simulation time 195927206 ps
CPU time 1.36 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 199740 kb
Host smart-7b7c463e-e11d-42f9-b83f-e5d3a27bd427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034676837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.4034676837
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3308410460
Short name T1156
Test name
Test status
Simulation time 74066849 ps
CPU time 0.76 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 199640 kb
Host smart-9b11c059-c002-4685-a422-419e774a5bf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308410460 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3308410460
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3168533961
Short name T1147
Test name
Test status
Simulation time 46009254 ps
CPU time 0.64 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 195924 kb
Host smart-9b75d2ce-7422-4021-8cff-b85ed0c61265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168533961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3168533961
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1753436100
Short name T1132
Test name
Test status
Simulation time 22359395 ps
CPU time 0.57 seconds
Started Mar 21 03:11:43 PM PDT 24
Finished Mar 21 03:11:44 PM PDT 24
Peak memory 194816 kb
Host smart-80a86330-8610-46d8-a76c-57380a8e7e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753436100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1753436100
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.276650801
Short name T1229
Test name
Test status
Simulation time 30770242 ps
CPU time 0.81 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 196588 kb
Host smart-6602e94a-aa96-4c2d-9477-f1e7d64fc487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276650801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.276650801
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.378103129
Short name T1173
Test name
Test status
Simulation time 401850458 ps
CPU time 2.32 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 200608 kb
Host smart-17cb677e-4bc6-429d-afdf-984f843066c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378103129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.378103129
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1049862823
Short name T1163
Test name
Test status
Simulation time 150850517 ps
CPU time 0.68 seconds
Started Mar 21 03:11:03 PM PDT 24
Finished Mar 21 03:11:04 PM PDT 24
Peak memory 195812 kb
Host smart-98a0be20-a32d-4643-ae4f-d1fde5e6999a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049862823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1049862823
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4111907873
Short name T73
Test name
Test status
Simulation time 259249791 ps
CPU time 2.7 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:02 PM PDT 24
Peak memory 197976 kb
Host smart-4736ce95-3200-4727-95d2-f1fe299f6751
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111907873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4111907873
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.473851008
Short name T1131
Test name
Test status
Simulation time 13861320 ps
CPU time 0.61 seconds
Started Mar 21 03:11:01 PM PDT 24
Finished Mar 21 03:11:01 PM PDT 24
Peak memory 195788 kb
Host smart-c4ae9be3-4482-4d30-829f-c468f67bee64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473851008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.473851008
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.211659736
Short name T1138
Test name
Test status
Simulation time 48807367 ps
CPU time 0.7 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:00 PM PDT 24
Peak memory 198432 kb
Host smart-c971c87d-f3fa-47dc-a97b-2135b2d08d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211659736 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.211659736
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1132152095
Short name T1189
Test name
Test status
Simulation time 14092393 ps
CPU time 0.63 seconds
Started Mar 21 03:11:02 PM PDT 24
Finished Mar 21 03:11:03 PM PDT 24
Peak memory 195904 kb
Host smart-69d780e0-93d2-4379-9dce-1677f01c4877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132152095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1132152095
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.8317779
Short name T1211
Test name
Test status
Simulation time 19120023 ps
CPU time 0.58 seconds
Started Mar 21 03:11:03 PM PDT 24
Finished Mar 21 03:11:04 PM PDT 24
Peak memory 194792 kb
Host smart-6ec8231c-40ac-4c88-8e17-dc722eb63195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8317779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.8317779
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3375974731
Short name T89
Test name
Test status
Simulation time 93280603 ps
CPU time 0.76 seconds
Started Mar 21 03:11:01 PM PDT 24
Finished Mar 21 03:11:02 PM PDT 24
Peak memory 197324 kb
Host smart-ed45d29b-fd97-495a-83fa-386602033299
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375974731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3375974731
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2053664211
Short name T1137
Test name
Test status
Simulation time 73881662 ps
CPU time 1.61 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:01 PM PDT 24
Peak memory 200524 kb
Host smart-ba86736f-c67e-43e6-8005-5c70b86bc34e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053664211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2053664211
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1946772921
Short name T1223
Test name
Test status
Simulation time 130393707 ps
CPU time 1.01 seconds
Started Mar 21 03:11:00 PM PDT 24
Finished Mar 21 03:11:02 PM PDT 24
Peak memory 199504 kb
Host smart-2b1effe1-6d20-41b3-9042-f66736990c18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946772921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1946772921
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.243336253
Short name T1118
Test name
Test status
Simulation time 18910485 ps
CPU time 0.6 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 194764 kb
Host smart-4bf80f57-76ff-4205-86c6-726edf6a50da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243336253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.243336253
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2691637061
Short name T1130
Test name
Test status
Simulation time 192097829 ps
CPU time 0.58 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 194824 kb
Host smart-535c7640-261d-49e9-bced-435859d99919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691637061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2691637061
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1024953705
Short name T1191
Test name
Test status
Simulation time 36562387 ps
CPU time 0.6 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 194832 kb
Host smart-65d9cacf-c91b-42bf-9565-e5ca5a89b9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024953705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1024953705
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3158398450
Short name T1243
Test name
Test status
Simulation time 35242880 ps
CPU time 0.56 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 194832 kb
Host smart-2308bc16-9425-40f1-9318-8d45c896c964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158398450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3158398450
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.408709301
Short name T1178
Test name
Test status
Simulation time 13369904 ps
CPU time 0.59 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 194796 kb
Host smart-e14e72c2-db15-4c7c-9b63-9457c6218052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408709301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.408709301
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.459874802
Short name T1134
Test name
Test status
Simulation time 80191398 ps
CPU time 0.58 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:40 PM PDT 24
Peak memory 194760 kb
Host smart-52f3a3d6-c40d-4aec-a169-498de41bd3fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459874802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.459874802
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3181242591
Short name T1187
Test name
Test status
Simulation time 36497510 ps
CPU time 0.57 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 194860 kb
Host smart-8a73c59c-df7e-4dd1-bf6a-835d6d757be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181242591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3181242591
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3657739633
Short name T1154
Test name
Test status
Simulation time 19153087 ps
CPU time 0.56 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 194812 kb
Host smart-748ecd3a-2cce-48c1-a5aa-2df8e365ca55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657739633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3657739633
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2246210863
Short name T1185
Test name
Test status
Simulation time 28299043 ps
CPU time 0.6 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 194752 kb
Host smart-f41f6771-ad58-45e8-b91e-5a4a0e1ff889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246210863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2246210863
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2623072102
Short name T1203
Test name
Test status
Simulation time 44362248 ps
CPU time 0.58 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 194812 kb
Host smart-a938c5f8-2d00-44f2-913d-ce39a3f60e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623072102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2623072102
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.445259629
Short name T1213
Test name
Test status
Simulation time 54842172 ps
CPU time 0.81 seconds
Started Mar 21 03:11:16 PM PDT 24
Finished Mar 21 03:11:17 PM PDT 24
Peak memory 196756 kb
Host smart-fe3df672-ca25-485d-ad3b-d7923941c97a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445259629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.445259629
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.579035905
Short name T1148
Test name
Test status
Simulation time 171353223 ps
CPU time 2.41 seconds
Started Mar 21 03:11:11 PM PDT 24
Finished Mar 21 03:11:13 PM PDT 24
Peak memory 198116 kb
Host smart-0f90cd2c-809a-4eba-838f-ffb4edab9dba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579035905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.579035905
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.15575340
Short name T1124
Test name
Test status
Simulation time 11858750 ps
CPU time 0.59 seconds
Started Mar 21 03:11:08 PM PDT 24
Finished Mar 21 03:11:09 PM PDT 24
Peak memory 195816 kb
Host smart-44a97b47-2802-47ce-ada5-09315eb8e374
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.15575340
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.976153935
Short name T1136
Test name
Test status
Simulation time 18194643 ps
CPU time 0.7 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:09 PM PDT 24
Peak memory 198332 kb
Host smart-056bde68-76d5-47d9-a678-f209ababff77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976153935 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.976153935
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2023865226
Short name T1141
Test name
Test status
Simulation time 21878351 ps
CPU time 0.62 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 195872 kb
Host smart-ee3de792-1c76-483f-9ab2-0e76809745f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023865226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2023865226
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3545941611
Short name T1205
Test name
Test status
Simulation time 61749942 ps
CPU time 0.57 seconds
Started Mar 21 03:11:00 PM PDT 24
Finished Mar 21 03:11:00 PM PDT 24
Peak memory 194844 kb
Host smart-19532ce3-4ad7-4cb5-9929-25ec56a1128d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545941611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3545941611
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.584577483
Short name T1167
Test name
Test status
Simulation time 81658013 ps
CPU time 0.75 seconds
Started Mar 21 03:11:13 PM PDT 24
Finished Mar 21 03:11:14 PM PDT 24
Peak memory 198080 kb
Host smart-44b6bbf4-d014-47b3-af9c-8ef9b744654d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584577483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.584577483
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.379552035
Short name T1218
Test name
Test status
Simulation time 208005845 ps
CPU time 2.41 seconds
Started Mar 21 03:11:03 PM PDT 24
Finished Mar 21 03:11:06 PM PDT 24
Peak memory 200524 kb
Host smart-5c8b55e6-bc80-4eca-9b9a-da9de9b48418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379552035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.379552035
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3592911839
Short name T1214
Test name
Test status
Simulation time 165021460 ps
CPU time 0.96 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:00 PM PDT 24
Peak memory 199512 kb
Host smart-b9fb4e2f-fbd2-482c-8623-4b9c97b589d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592911839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3592911839
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2592328716
Short name T1172
Test name
Test status
Simulation time 15157392 ps
CPU time 0.58 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 194852 kb
Host smart-437db0df-5918-4d66-87ff-3fa106be0d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592328716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2592328716
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.887313890
Short name T1225
Test name
Test status
Simulation time 97034442 ps
CPU time 0.57 seconds
Started Mar 21 03:11:43 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 194868 kb
Host smart-49b5d8bb-f9c5-4405-b08d-6d50354f4f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887313890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.887313890
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1138883657
Short name T1171
Test name
Test status
Simulation time 16258381 ps
CPU time 0.57 seconds
Started Mar 21 03:11:44 PM PDT 24
Finished Mar 21 03:11:45 PM PDT 24
Peak memory 194796 kb
Host smart-fee9695d-2fbf-4ade-a2f7-b2d5f7365e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138883657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1138883657
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4213893584
Short name T1159
Test name
Test status
Simulation time 99609546 ps
CPU time 0.58 seconds
Started Mar 21 03:11:39 PM PDT 24
Finished Mar 21 03:11:40 PM PDT 24
Peak memory 194792 kb
Host smart-7a1fc49c-6463-467c-9e5a-1af70840de58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213893584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4213893584
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.737886649
Short name T1127
Test name
Test status
Simulation time 60852567 ps
CPU time 0.59 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 194768 kb
Host smart-62c499ea-001a-4233-9539-33faab6dec1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737886649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.737886649
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3370942462
Short name T1119
Test name
Test status
Simulation time 39101634 ps
CPU time 0.55 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 194748 kb
Host smart-b302c049-9624-499e-8edb-d379b6bdf3c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370942462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3370942462
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3483782126
Short name T1196
Test name
Test status
Simulation time 24834129 ps
CPU time 0.6 seconds
Started Mar 21 03:11:41 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 194812 kb
Host smart-d9c63a1a-6282-432a-bbfb-e053058c2d8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483782126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3483782126
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2826709444
Short name T1126
Test name
Test status
Simulation time 54035346 ps
CPU time 0.57 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:40 PM PDT 24
Peak memory 194804 kb
Host smart-30875b74-534c-4ffd-8804-b1f8e45b3a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826709444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2826709444
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.898808535
Short name T1236
Test name
Test status
Simulation time 34642736 ps
CPU time 0.58 seconds
Started Mar 21 03:11:43 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 194820 kb
Host smart-febb6b59-c980-453e-bd74-825c76a88b96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898808535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.898808535
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3396451182
Short name T1183
Test name
Test status
Simulation time 21410813 ps
CPU time 0.6 seconds
Started Mar 21 03:11:40 PM PDT 24
Finished Mar 21 03:11:41 PM PDT 24
Peak memory 194768 kb
Host smart-4a836efd-2d14-4b22-be82-37e2ac268d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396451182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3396451182
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1972902077
Short name T1226
Test name
Test status
Simulation time 319122359 ps
CPU time 0.79 seconds
Started Mar 21 03:11:16 PM PDT 24
Finished Mar 21 03:11:17 PM PDT 24
Peak memory 196580 kb
Host smart-b492e7b1-d6e6-488e-b148-a94dd4845975
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972902077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1972902077
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.486068776
Short name T1117
Test name
Test status
Simulation time 70869531 ps
CPU time 1.44 seconds
Started Mar 21 03:11:17 PM PDT 24
Finished Mar 21 03:11:19 PM PDT 24
Peak memory 198120 kb
Host smart-599116b1-9080-4928-accb-a53ff28cf0c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486068776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.486068776
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2122956694
Short name T1208
Test name
Test status
Simulation time 30685984 ps
CPU time 0.56 seconds
Started Mar 21 03:11:10 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 195836 kb
Host smart-991db8b6-9eab-4aab-8755-4bd130b709b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122956694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2122956694
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4217264839
Short name T1245
Test name
Test status
Simulation time 19312469 ps
CPU time 0.66 seconds
Started Mar 21 03:11:11 PM PDT 24
Finished Mar 21 03:11:12 PM PDT 24
Peak memory 198000 kb
Host smart-0c960d3e-b8b9-40c0-adab-7688d47a4e91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217264839 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4217264839
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.911861162
Short name T68
Test name
Test status
Simulation time 46292696 ps
CPU time 0.61 seconds
Started Mar 21 03:11:10 PM PDT 24
Finished Mar 21 03:11:11 PM PDT 24
Peak memory 195808 kb
Host smart-8bd4a029-1a7d-49e4-88ee-dc31ce9117f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911861162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.911861162
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2809659802
Short name T1233
Test name
Test status
Simulation time 14289108 ps
CPU time 0.57 seconds
Started Mar 21 03:11:16 PM PDT 24
Finished Mar 21 03:11:16 PM PDT 24
Peak memory 194856 kb
Host smart-58e8248b-f4d1-4fb8-8e3f-1f357ffbb5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809659802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2809659802
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2266732007
Short name T1210
Test name
Test status
Simulation time 30878904 ps
CPU time 0.74 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 197292 kb
Host smart-7d5da99b-04b0-4912-8111-be0c5451e0c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266732007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2266732007
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.454801176
Short name T1192
Test name
Test status
Simulation time 65140013 ps
CPU time 1.48 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:11 PM PDT 24
Peak memory 200448 kb
Host smart-cf087b4e-42b3-4b07-b00d-c8187c82ca9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454801176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.454801176
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1387614664
Short name T1247
Test name
Test status
Simulation time 91631325 ps
CPU time 1.36 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 199828 kb
Host smart-ac0aabb2-e86b-4e78-a952-8fab805a4fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387614664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1387614664
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1412318556
Short name T1170
Test name
Test status
Simulation time 22409025 ps
CPU time 0.59 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 194788 kb
Host smart-03afc211-df8f-4023-8805-347b6613c845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412318556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1412318556
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2506938939
Short name T1146
Test name
Test status
Simulation time 161757021 ps
CPU time 0.58 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:42 PM PDT 24
Peak memory 194800 kb
Host smart-315c2a59-685f-4690-8774-5df8f9be5b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506938939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2506938939
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2661246413
Short name T1195
Test name
Test status
Simulation time 43412871 ps
CPU time 0.59 seconds
Started Mar 21 03:11:42 PM PDT 24
Finished Mar 21 03:11:43 PM PDT 24
Peak memory 194820 kb
Host smart-c52efbd6-ab50-4781-9c52-53a1f13e9d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661246413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2661246413
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.954928114
Short name T1133
Test name
Test status
Simulation time 42402975 ps
CPU time 0.59 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:11:55 PM PDT 24
Peak memory 194824 kb
Host smart-14e18e6a-b445-4196-8e76-6eaf1fa90cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954928114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.954928114
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2341404161
Short name T1123
Test name
Test status
Simulation time 33068415 ps
CPU time 0.56 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:11:54 PM PDT 24
Peak memory 194800 kb
Host smart-8462db2f-0df4-4bdf-a4a2-f8cc9a47aab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341404161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2341404161
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.4065836282
Short name T1153
Test name
Test status
Simulation time 12623710 ps
CPU time 0.58 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:11:54 PM PDT 24
Peak memory 194792 kb
Host smart-32004046-55d2-44da-8998-d22c2cb2467f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065836282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.4065836282
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.4036927645
Short name T1197
Test name
Test status
Simulation time 15116544 ps
CPU time 0.59 seconds
Started Mar 21 03:11:54 PM PDT 24
Finished Mar 21 03:11:56 PM PDT 24
Peak memory 194848 kb
Host smart-c380eaa2-ee6a-4b70-be39-f0eba064ae8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036927645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4036927645
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3169534559
Short name T1177
Test name
Test status
Simulation time 16938599 ps
CPU time 0.58 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:11:52 PM PDT 24
Peak memory 194872 kb
Host smart-9b5793cd-e60f-4008-afa7-857b703036ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169534559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3169534559
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2588643938
Short name T1140
Test name
Test status
Simulation time 44135084 ps
CPU time 0.64 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:11:54 PM PDT 24
Peak memory 194836 kb
Host smart-13d786c2-37cd-48f1-8a00-da4f88a2f0b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588643938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2588643938
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2664377726
Short name T1224
Test name
Test status
Simulation time 24017682 ps
CPU time 0.58 seconds
Started Mar 21 03:11:53 PM PDT 24
Finished Mar 21 03:11:55 PM PDT 24
Peak memory 194876 kb
Host smart-cff05be7-60c3-4045-903b-bcc790f38451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664377726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2664377726
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3272113033
Short name T1237
Test name
Test status
Simulation time 71001308 ps
CPU time 1.03 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 200288 kb
Host smart-7caf2864-9b2c-445e-a528-40949cda4711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272113033 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3272113033
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1216057054
Short name T74
Test name
Test status
Simulation time 67719687 ps
CPU time 0.59 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 195816 kb
Host smart-5c69a76f-84f7-4785-bc6f-5592f89b3701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216057054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1216057054
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.573430271
Short name T1201
Test name
Test status
Simulation time 66686181 ps
CPU time 0.58 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 194784 kb
Host smart-944b6568-7b92-4bb1-b2a9-7f763deef875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573430271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.573430271
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1982927515
Short name T85
Test name
Test status
Simulation time 193304080 ps
CPU time 0.65 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 196996 kb
Host smart-b0870c49-5d6e-4c75-b71d-1f68ac4e30a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982927515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1982927515
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3900792093
Short name T114
Test name
Test status
Simulation time 317943279 ps
CPU time 1.44 seconds
Started Mar 21 03:11:15 PM PDT 24
Finished Mar 21 03:11:17 PM PDT 24
Peak memory 200480 kb
Host smart-05ec9824-2af4-4967-9a62-fb345f9a50fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900792093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3900792093
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2930696831
Short name T134
Test name
Test status
Simulation time 252252390 ps
CPU time 1.36 seconds
Started Mar 21 03:11:10 PM PDT 24
Finished Mar 21 03:11:11 PM PDT 24
Peak memory 199964 kb
Host smart-8d4acc02-07c9-40b9-8f2b-0ecdfa9aeb23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930696831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2930696831
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2188119172
Short name T1161
Test name
Test status
Simulation time 16820913 ps
CPU time 0.69 seconds
Started Mar 21 03:11:11 PM PDT 24
Finished Mar 21 03:11:11 PM PDT 24
Peak memory 198492 kb
Host smart-ddc9a8bf-1957-44f6-879d-8196ebefae8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188119172 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2188119172
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2728068380
Short name T88
Test name
Test status
Simulation time 47074469 ps
CPU time 0.59 seconds
Started Mar 21 03:11:17 PM PDT 24
Finished Mar 21 03:11:18 PM PDT 24
Peak memory 195816 kb
Host smart-8cdd3de2-19ca-47b9-b1b1-19aceaac456c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728068380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2728068380
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2414165675
Short name T1129
Test name
Test status
Simulation time 35227720 ps
CPU time 0.6 seconds
Started Mar 21 03:11:11 PM PDT 24
Finished Mar 21 03:11:12 PM PDT 24
Peak memory 194816 kb
Host smart-369cb3f9-9bd1-4d69-b43c-6cba9d207849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414165675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2414165675
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.48230942
Short name T1142
Test name
Test status
Simulation time 14613191 ps
CPU time 0.66 seconds
Started Mar 21 03:11:12 PM PDT 24
Finished Mar 21 03:11:13 PM PDT 24
Peak memory 196104 kb
Host smart-01fcc655-db73-4fa3-9072-11e7ad460f3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48230942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_o
utstanding.48230942
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.597756434
Short name T1238
Test name
Test status
Simulation time 18694795 ps
CPU time 0.83 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 199672 kb
Host smart-597f0a2a-e741-46a2-9e4e-c2de4a8dc80b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597756434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.597756434
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.307293775
Short name T97
Test name
Test status
Simulation time 93588955 ps
CPU time 1.45 seconds
Started Mar 21 03:11:07 PM PDT 24
Finished Mar 21 03:11:08 PM PDT 24
Peak memory 199856 kb
Host smart-02a6a7de-9173-476e-ae08-419d226bba8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307293775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.307293775
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4172339574
Short name T1249
Test name
Test status
Simulation time 80436066 ps
CPU time 1.04 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 200300 kb
Host smart-d7096c5b-dc3e-4955-96e5-e3f1cf6c5125
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172339574 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.4172339574
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1174072598
Short name T1145
Test name
Test status
Simulation time 25810033 ps
CPU time 0.63 seconds
Started Mar 21 03:11:08 PM PDT 24
Finished Mar 21 03:11:09 PM PDT 24
Peak memory 196056 kb
Host smart-a1da3e87-7cd2-4ba8-bb30-8fa73478016b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174072598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1174072598
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.908217330
Short name T1190
Test name
Test status
Simulation time 40357828 ps
CPU time 0.58 seconds
Started Mar 21 03:11:10 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 194820 kb
Host smart-09789889-5388-4949-b84e-fb1b34d85664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908217330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.908217330
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3421527170
Short name T1207
Test name
Test status
Simulation time 13743956 ps
CPU time 0.62 seconds
Started Mar 21 03:11:10 PM PDT 24
Finished Mar 21 03:11:11 PM PDT 24
Peak memory 196072 kb
Host smart-d85b91b6-58a6-4c46-bb26-3568c71f77fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421527170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3421527170
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.859711094
Short name T1240
Test name
Test status
Simulation time 2283702052 ps
CPU time 2.05 seconds
Started Mar 21 03:11:16 PM PDT 24
Finished Mar 21 03:11:18 PM PDT 24
Peak memory 200604 kb
Host smart-162c5e04-f203-4ca4-8d87-da6a42205da6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859711094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.859711094
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4104047372
Short name T1239
Test name
Test status
Simulation time 165799259 ps
CPU time 1.39 seconds
Started Mar 21 03:11:16 PM PDT 24
Finished Mar 21 03:11:18 PM PDT 24
Peak memory 199960 kb
Host smart-62f45c9e-61f3-4168-b743-52e45f554175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104047372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4104047372
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1785689891
Short name T1204
Test name
Test status
Simulation time 49685536 ps
CPU time 0.85 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 200256 kb
Host smart-f0ca2a20-9e34-4beb-9739-9aa994f2bd38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785689891 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1785689891
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3505589170
Short name T92
Test name
Test status
Simulation time 42386263 ps
CPU time 0.63 seconds
Started Mar 21 03:11:08 PM PDT 24
Finished Mar 21 03:11:09 PM PDT 24
Peak memory 195752 kb
Host smart-4d0ef8aa-c2bc-466a-94bb-ddff940c3415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505589170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3505589170
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.4154986594
Short name T1125
Test name
Test status
Simulation time 44377050 ps
CPU time 0.57 seconds
Started Mar 21 03:11:16 PM PDT 24
Finished Mar 21 03:11:17 PM PDT 24
Peak memory 194796 kb
Host smart-d23bca3c-acb9-4916-b06a-b103e84dc9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154986594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4154986594
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2005306915
Short name T1165
Test name
Test status
Simulation time 102650483 ps
CPU time 0.81 seconds
Started Mar 21 03:11:15 PM PDT 24
Finished Mar 21 03:11:16 PM PDT 24
Peak memory 196496 kb
Host smart-2f0bf142-e288-4191-8361-9f2417f5bd85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005306915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2005306915
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2198810727
Short name T1180
Test name
Test status
Simulation time 23646191 ps
CPU time 1.18 seconds
Started Mar 21 03:11:09 PM PDT 24
Finished Mar 21 03:11:11 PM PDT 24
Peak memory 200540 kb
Host smart-14b9a75a-374b-4209-9862-e84b3ea5cba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198810727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2198810727
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.326603084
Short name T96
Test name
Test status
Simulation time 131419038 ps
CPU time 1.23 seconds
Started Mar 21 03:11:16 PM PDT 24
Finished Mar 21 03:11:17 PM PDT 24
Peak memory 199936 kb
Host smart-fbdc89ed-af41-447c-b0c9-677c8b595506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326603084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.326603084
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4285800580
Short name T1122
Test name
Test status
Simulation time 22764320 ps
CPU time 0.78 seconds
Started Mar 21 03:11:30 PM PDT 24
Finished Mar 21 03:11:31 PM PDT 24
Peak memory 199576 kb
Host smart-d33cd3f0-20f1-443f-9a1b-93523c77ac2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285800580 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.4285800580
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.13352520
Short name T69
Test name
Test status
Simulation time 76906908 ps
CPU time 0.59 seconds
Started Mar 21 03:11:30 PM PDT 24
Finished Mar 21 03:11:31 PM PDT 24
Peak memory 195840 kb
Host smart-b3ce1d50-551f-4076-948f-95436ace6980
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13352520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.13352520
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1798822532
Short name T1235
Test name
Test status
Simulation time 23868210 ps
CPU time 0.58 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 194760 kb
Host smart-b70a1737-f5db-478a-b393-c43e40accac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798822532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1798822532
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.874368706
Short name T1220
Test name
Test status
Simulation time 20077280 ps
CPU time 0.68 seconds
Started Mar 21 03:11:23 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 196296 kb
Host smart-ec0bb70b-6c2c-4a36-8150-bc8b581333c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874368706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.874368706
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1421925832
Short name T1230
Test name
Test status
Simulation time 97788992 ps
CPU time 1.54 seconds
Started Mar 21 03:11:08 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 200592 kb
Host smart-167110d5-7aef-4980-a73e-37513b3a2f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421925832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1421925832
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.542728817
Short name T1227
Test name
Test status
Simulation time 86141894 ps
CPU time 1.35 seconds
Started Mar 21 03:11:21 PM PDT 24
Finished Mar 21 03:11:23 PM PDT 24
Peak memory 199816 kb
Host smart-9a89a787-78d3-496b-ac25-27c760fe3a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542728817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.542728817
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1398916417
Short name T493
Test name
Test status
Simulation time 15036996 ps
CPU time 0.56 seconds
Started Mar 21 01:52:37 PM PDT 24
Finished Mar 21 01:52:38 PM PDT 24
Peak memory 195288 kb
Host smart-1c15565c-df58-4258-b5af-de9b39b376bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398916417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1398916417
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2249621782
Short name T168
Test name
Test status
Simulation time 94227909057 ps
CPU time 37 seconds
Started Mar 21 01:52:37 PM PDT 24
Finished Mar 21 01:53:14 PM PDT 24
Peak memory 200412 kb
Host smart-08451db0-b5ea-4e1b-92d6-106a1a59c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249621782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2249621782
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2203776815
Short name T6
Test name
Test status
Simulation time 12423589673 ps
CPU time 14 seconds
Started Mar 21 01:52:35 PM PDT 24
Finished Mar 21 01:52:49 PM PDT 24
Peak memory 200372 kb
Host smart-b6441af9-25d6-4798-b978-1712eb070538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203776815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2203776815
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.219510474
Short name T838
Test name
Test status
Simulation time 29656128457 ps
CPU time 37.82 seconds
Started Mar 21 01:52:37 PM PDT 24
Finished Mar 21 01:53:15 PM PDT 24
Peak memory 200424 kb
Host smart-bec86a78-45ac-4fce-b2bc-64c0d26ba192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219510474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.219510474
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.709323946
Short name T455
Test name
Test status
Simulation time 274301843227 ps
CPU time 116.89 seconds
Started Mar 21 01:52:38 PM PDT 24
Finished Mar 21 01:54:35 PM PDT 24
Peak memory 200288 kb
Host smart-961d5053-2036-49e9-b0bd-f9fc50ecb7db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709323946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.709323946
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1072899141
Short name T488
Test name
Test status
Simulation time 99182372552 ps
CPU time 189.8 seconds
Started Mar 21 01:52:36 PM PDT 24
Finished Mar 21 01:55:46 PM PDT 24
Peak memory 200400 kb
Host smart-6258aa45-ae3e-4fc4-8198-edd978b0f879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072899141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1072899141
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1331008126
Short name T429
Test name
Test status
Simulation time 3297616301 ps
CPU time 9.82 seconds
Started Mar 21 01:52:36 PM PDT 24
Finished Mar 21 01:52:46 PM PDT 24
Peak memory 199152 kb
Host smart-2612862a-27b1-47c0-92f6-718a68e6c93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331008126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1331008126
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.885373108
Short name T331
Test name
Test status
Simulation time 54814532261 ps
CPU time 80.9 seconds
Started Mar 21 01:52:35 PM PDT 24
Finished Mar 21 01:53:56 PM PDT 24
Peak memory 200736 kb
Host smart-162aa0f8-31d5-4cad-b48f-94fa86ad7b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885373108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.885373108
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2088226457
Short name T863
Test name
Test status
Simulation time 11341484270 ps
CPU time 160.86 seconds
Started Mar 21 01:52:36 PM PDT 24
Finished Mar 21 01:55:17 PM PDT 24
Peak memory 200336 kb
Host smart-18f6c6f5-439d-4a23-bbe5-93365a8abfca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088226457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2088226457
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1007703178
Short name T599
Test name
Test status
Simulation time 5964788586 ps
CPU time 14.15 seconds
Started Mar 21 01:52:36 PM PDT 24
Finished Mar 21 01:52:50 PM PDT 24
Peak memory 199592 kb
Host smart-256a65c4-ef1d-4b64-b42e-46549faa9302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1007703178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1007703178
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.901140005
Short name T715
Test name
Test status
Simulation time 50241604725 ps
CPU time 77.66 seconds
Started Mar 21 01:52:35 PM PDT 24
Finished Mar 21 01:53:52 PM PDT 24
Peak memory 200376 kb
Host smart-d4c4b340-8af3-4e79-a49e-1c36c031e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901140005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.901140005
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4192074794
Short name T297
Test name
Test status
Simulation time 4722683698 ps
CPU time 7.5 seconds
Started Mar 21 01:52:35 PM PDT 24
Finished Mar 21 01:52:42 PM PDT 24
Peak memory 196776 kb
Host smart-1854b667-c608-4829-827b-5df16db9e77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192074794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4192074794
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2340507566
Short name T102
Test name
Test status
Simulation time 142787567 ps
CPU time 0.8 seconds
Started Mar 21 01:52:37 PM PDT 24
Finished Mar 21 01:52:38 PM PDT 24
Peak memory 218408 kb
Host smart-7aca90ed-ddc2-465f-af54-5fa02e8660d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340507566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2340507566
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1977714726
Short name T337
Test name
Test status
Simulation time 771408940 ps
CPU time 1.32 seconds
Started Mar 21 01:52:35 PM PDT 24
Finished Mar 21 01:52:37 PM PDT 24
Peak memory 199720 kb
Host smart-d307f393-7b8d-4ce5-a46f-66571e5232b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977714726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1977714726
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3209393919
Short name T285
Test name
Test status
Simulation time 436559105118 ps
CPU time 158.21 seconds
Started Mar 21 01:52:37 PM PDT 24
Finished Mar 21 01:55:16 PM PDT 24
Peak memory 200448 kb
Host smart-00abb311-6333-4332-ba61-7655c8808fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209393919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3209393919
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2377905666
Short name T1058
Test name
Test status
Simulation time 12881650113 ps
CPU time 38.84 seconds
Started Mar 21 01:52:37 PM PDT 24
Finished Mar 21 01:53:16 PM PDT 24
Peak memory 200096 kb
Host smart-479d97e7-afb7-4141-bcd2-88338e48df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377905666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2377905666
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1816995454
Short name T865
Test name
Test status
Simulation time 125239871440 ps
CPU time 99.23 seconds
Started Mar 21 01:52:36 PM PDT 24
Finished Mar 21 01:54:15 PM PDT 24
Peak memory 200360 kb
Host smart-120ae250-1e17-47aa-bd0d-4bd5c02e54aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816995454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1816995454
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2449366696
Short name T404
Test name
Test status
Simulation time 13116686 ps
CPU time 0.56 seconds
Started Mar 21 01:52:47 PM PDT 24
Finished Mar 21 01:52:47 PM PDT 24
Peak memory 195276 kb
Host smart-faa7b476-c4e6-4dd7-be0c-61400459222d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449366696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2449366696
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.97089870
Short name T124
Test name
Test status
Simulation time 82543486409 ps
CPU time 27.36 seconds
Started Mar 21 01:52:38 PM PDT 24
Finished Mar 21 01:53:05 PM PDT 24
Peak memory 200404 kb
Host smart-6eb6bb7f-03a1-4b05-a85d-4434ef833277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97089870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.97089870
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.15746664
Short name T584
Test name
Test status
Simulation time 15790221296 ps
CPU time 12.84 seconds
Started Mar 21 01:52:48 PM PDT 24
Finished Mar 21 01:53:02 PM PDT 24
Peak memory 200408 kb
Host smart-dc4e2aab-cf6b-483f-882b-bbdeda89ea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15746664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.15746664
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.400598317
Short name T1099
Test name
Test status
Simulation time 28169004033 ps
CPU time 45.25 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:53:36 PM PDT 24
Peak memory 200348 kb
Host smart-642ca1f4-b1b3-4451-8f6f-f8911b037a10
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400598317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.400598317
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.731052735
Short name T1102
Test name
Test status
Simulation time 64496955742 ps
CPU time 214.95 seconds
Started Mar 21 01:52:47 PM PDT 24
Finished Mar 21 01:56:22 PM PDT 24
Peak memory 200444 kb
Host smart-ab49f137-cb94-425d-97a7-d6f503441447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731052735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.731052735
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2805812965
Short name T1089
Test name
Test status
Simulation time 3964977265 ps
CPU time 4.64 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:52:53 PM PDT 24
Peak memory 199732 kb
Host smart-e313e465-8ff0-4969-8c6f-19e8c0c1f5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805812965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2805812965
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.197487911
Short name T403
Test name
Test status
Simulation time 341249355466 ps
CPU time 55.85 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:53:48 PM PDT 24
Peak memory 200776 kb
Host smart-d823af30-a438-40ba-a6ca-eed932bdb3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197487911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.197487911
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3645057389
Short name T1038
Test name
Test status
Simulation time 14204853945 ps
CPU time 722.87 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 02:04:52 PM PDT 24
Peak memory 200372 kb
Host smart-70189126-e6ad-4b6a-aa24-ed90149ffdeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645057389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3645057389
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2839304944
Short name T804
Test name
Test status
Simulation time 4424832863 ps
CPU time 9.44 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:52:59 PM PDT 24
Peak memory 199076 kb
Host smart-aafadeb1-fcdc-4208-83db-1075df1ea6f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839304944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2839304944
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2323332716
Short name T909
Test name
Test status
Simulation time 101417649194 ps
CPU time 38.6 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:53:29 PM PDT 24
Peak memory 200380 kb
Host smart-b7419d90-4e51-4954-8a1a-df48eddf4bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323332716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2323332716
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1630330009
Short name T717
Test name
Test status
Simulation time 2071175850 ps
CPU time 1.53 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:52 PM PDT 24
Peak memory 195980 kb
Host smart-cf396c0b-642d-457b-a2a0-9a870021f0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630330009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1630330009
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1445809884
Short name T34
Test name
Test status
Simulation time 212972048 ps
CPU time 0.77 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:51 PM PDT 24
Peak memory 218516 kb
Host smart-a5174909-75ec-4b40-9bb8-c1ba7986c78c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445809884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1445809884
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_stress_all.3557066250
Short name T611
Test name
Test status
Simulation time 154717908209 ps
CPU time 190.92 seconds
Started Mar 21 01:52:54 PM PDT 24
Finished Mar 21 01:56:05 PM PDT 24
Peak memory 216744 kb
Host smart-5afb2e2e-d436-41ed-8c76-60646c13c1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557066250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3557066250
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2625518379
Short name T265
Test name
Test status
Simulation time 1028936643 ps
CPU time 3.61 seconds
Started Mar 21 01:52:48 PM PDT 24
Finished Mar 21 01:52:51 PM PDT 24
Peak memory 200128 kb
Host smart-67057c5b-a1e8-43f7-9c9e-a25cd7520e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625518379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2625518379
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1730138498
Short name T322
Test name
Test status
Simulation time 120899902546 ps
CPU time 66.91 seconds
Started Mar 21 01:52:37 PM PDT 24
Finished Mar 21 01:53:44 PM PDT 24
Peak memory 200452 kb
Host smart-382d0e29-654b-4bee-9610-c4bc6dd9ccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730138498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1730138498
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.927903852
Short name T568
Test name
Test status
Simulation time 40268533 ps
CPU time 0.58 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 195900 kb
Host smart-404897c8-2d40-4f12-8d28-787a8454109d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927903852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.927903852
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2110724153
Short name T148
Test name
Test status
Simulation time 230754302584 ps
CPU time 253.75 seconds
Started Mar 21 01:53:48 PM PDT 24
Finished Mar 21 01:58:02 PM PDT 24
Peak memory 200432 kb
Host smart-562322ad-d04e-49ea-8b9b-f83754ad5cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110724153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2110724153
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2093707472
Short name T756
Test name
Test status
Simulation time 52765422891 ps
CPU time 57.88 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:54:42 PM PDT 24
Peak memory 200384 kb
Host smart-887c4b49-e030-493c-997d-10435f2d7d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093707472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2093707472
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3638445835
Short name T875
Test name
Test status
Simulation time 74907060245 ps
CPU time 26.88 seconds
Started Mar 21 01:53:47 PM PDT 24
Finished Mar 21 01:54:15 PM PDT 24
Peak memory 200096 kb
Host smart-cc9a364c-08d8-4a3b-b935-25de488366ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638445835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3638445835
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.840027817
Short name T132
Test name
Test status
Simulation time 393055238138 ps
CPU time 716.39 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 02:05:58 PM PDT 24
Peak memory 200392 kb
Host smart-bf0adf42-119c-49a0-bd60-7f6f716d9cac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840027817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.840027817
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1433670265
Short name T542
Test name
Test status
Simulation time 102493859921 ps
CPU time 486.58 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 200368 kb
Host smart-727e0102-d994-446d-8cc0-396e36cd7f31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433670265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1433670265
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1802878113
Short name T484
Test name
Test status
Simulation time 6026339233 ps
CPU time 11.4 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:14 PM PDT 24
Peak memory 200288 kb
Host smart-ab19b6cb-45a0-4ab0-a1cd-daffc67621f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802878113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1802878113
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1612289446
Short name T994
Test name
Test status
Simulation time 139759912824 ps
CPU time 82.01 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 01:55:22 PM PDT 24
Peak memory 199144 kb
Host smart-320f159b-51f3-46c2-8a04-fcfcf8b485e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612289446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1612289446
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2514392100
Short name T290
Test name
Test status
Simulation time 21258150553 ps
CPU time 1211.22 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 02:14:12 PM PDT 24
Peak memory 200356 kb
Host smart-1a2124c0-afce-4776-b91f-ef3bb26d00f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514392100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2514392100
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.154047870
Short name T621
Test name
Test status
Simulation time 6427938651 ps
CPU time 5.75 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:54:11 PM PDT 24
Peak memory 199104 kb
Host smart-8ec12ff0-99e0-43e7-b758-36a5df61cb3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154047870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.154047870
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1699757681
Short name T517
Test name
Test status
Simulation time 96285066307 ps
CPU time 190.66 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:57:12 PM PDT 24
Peak memory 200360 kb
Host smart-442c9ece-910f-4eeb-bef9-e6ce7073fd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699757681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1699757681
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2729558187
Short name T382
Test name
Test status
Simulation time 29727960321 ps
CPU time 11.48 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 01:54:11 PM PDT 24
Peak memory 196508 kb
Host smart-754618ba-cfe2-432a-b557-1fddbe4fd91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729558187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2729558187
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4105124705
Short name T5
Test name
Test status
Simulation time 697970063 ps
CPU time 1.2 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:53:47 PM PDT 24
Peak memory 198920 kb
Host smart-7ebc3167-3681-4884-9584-358732f33714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105124705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4105124705
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2298987914
Short name T785
Test name
Test status
Simulation time 24324204772 ps
CPU time 252.46 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:58:15 PM PDT 24
Peak memory 200340 kb
Host smart-1cd1f66d-ddbb-41d4-a565-57b2cbea4855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298987914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2298987914
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1909741820
Short name T703
Test name
Test status
Simulation time 133363631790 ps
CPU time 1408.09 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 02:17:32 PM PDT 24
Peak memory 231472 kb
Host smart-75b6ff2b-cfdb-4956-98a5-feec67e55f7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909741820 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1909741820
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1153720710
Short name T268
Test name
Test status
Simulation time 7189258748 ps
CPU time 14.95 seconds
Started Mar 21 01:53:59 PM PDT 24
Finished Mar 21 01:54:14 PM PDT 24
Peak memory 199612 kb
Host smart-23cb060b-9476-4d0b-a389-4dd9942d7298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153720710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1153720710
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.826157265
Short name T518
Test name
Test status
Simulation time 358217620743 ps
CPU time 36.07 seconds
Started Mar 21 01:53:48 PM PDT 24
Finished Mar 21 01:54:24 PM PDT 24
Peak memory 200304 kb
Host smart-1702050e-dbed-4513-9522-de929009fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826157265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.826157265
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3296811337
Short name T1087
Test name
Test status
Simulation time 16383202773 ps
CPU time 16.48 seconds
Started Mar 21 01:57:56 PM PDT 24
Finished Mar 21 01:58:13 PM PDT 24
Peak memory 200460 kb
Host smart-a8d90e87-7629-445f-9ef1-28052cf3c054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296811337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3296811337
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.372651933
Short name T721
Test name
Test status
Simulation time 264460536685 ps
CPU time 34.49 seconds
Started Mar 21 01:57:59 PM PDT 24
Finished Mar 21 01:58:35 PM PDT 24
Peak memory 200324 kb
Host smart-671234e6-c063-49d4-8b89-07f0ccb468ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372651933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.372651933
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2087475880
Short name T600
Test name
Test status
Simulation time 15030723389 ps
CPU time 27.31 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:58:27 PM PDT 24
Peak memory 200424 kb
Host smart-73c15077-9f64-4f94-b01a-616a6187fc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087475880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2087475880
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.319839297
Short name T3
Test name
Test status
Simulation time 14001965596 ps
CPU time 27.42 seconds
Started Mar 21 01:58:01 PM PDT 24
Finished Mar 21 01:58:29 PM PDT 24
Peak memory 200120 kb
Host smart-8459811b-889e-4a8d-af17-d8cc88c73ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319839297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.319839297
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3559060625
Short name T1055
Test name
Test status
Simulation time 151561679098 ps
CPU time 251.16 seconds
Started Mar 21 01:57:59 PM PDT 24
Finished Mar 21 02:02:12 PM PDT 24
Peak memory 200412 kb
Host smart-81dde7bf-3d15-486c-819f-277fd2fa2bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559060625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3559060625
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2650409848
Short name T501
Test name
Test status
Simulation time 77420641732 ps
CPU time 94.5 seconds
Started Mar 21 01:57:59 PM PDT 24
Finished Mar 21 01:59:34 PM PDT 24
Peak memory 200236 kb
Host smart-eac2334f-4286-46f0-8e1a-b1db34d0068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650409848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2650409848
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2685473627
Short name T479
Test name
Test status
Simulation time 14896435 ps
CPU time 0.58 seconds
Started Mar 21 01:54:07 PM PDT 24
Finished Mar 21 01:54:08 PM PDT 24
Peak memory 195852 kb
Host smart-96197bdf-9af5-4b9b-9c7b-c0fd671a33c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685473627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2685473627
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1593801557
Short name T664
Test name
Test status
Simulation time 91450375657 ps
CPU time 28.13 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:54:33 PM PDT 24
Peak memory 199852 kb
Host smart-893088e3-85b8-4af4-bd11-0ded77424394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593801557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1593801557
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.330929962
Short name T590
Test name
Test status
Simulation time 104397787665 ps
CPU time 169.82 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 01:56:50 PM PDT 24
Peak memory 200468 kb
Host smart-83f92893-b67a-4fb6-b8e0-1e65fa97c130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330929962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.330929962
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.441600680
Short name T440
Test name
Test status
Simulation time 234008770691 ps
CPU time 399.7 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 02:00:40 PM PDT 24
Peak memory 200300 kb
Host smart-72c53013-bab4-4341-958f-2d53be1b2b54
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441600680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.441600680
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2088526239
Short name T1078
Test name
Test status
Simulation time 87426986001 ps
CPU time 692.19 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 02:05:32 PM PDT 24
Peak memory 200348 kb
Host smart-39845d80-0563-4e34-90f8-7538b0f6dbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088526239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2088526239
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1809632091
Short name T461
Test name
Test status
Simulation time 7298619979 ps
CPU time 8.27 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:11 PM PDT 24
Peak memory 199980 kb
Host smart-6f760c40-1805-4d3a-be91-8b1f25ef8057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809632091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1809632091
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2287568104
Short name T308
Test name
Test status
Simulation time 53959791879 ps
CPU time 46.45 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:49 PM PDT 24
Peak memory 200124 kb
Host smart-a3c16575-87ac-4a35-9db2-22c6ada60a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287568104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2287568104
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3407329161
Short name T456
Test name
Test status
Simulation time 22298530666 ps
CPU time 1177.34 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 02:13:39 PM PDT 24
Peak memory 200536 kb
Host smart-10216d7c-af63-42cf-93ec-f8e1b6d0fd4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407329161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3407329161
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1567211143
Short name T15
Test name
Test status
Simulation time 4350044823 ps
CPU time 6.76 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:08 PM PDT 24
Peak memory 199756 kb
Host smart-8d7e5cf0-bb3f-4bef-9110-9713b3856581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567211143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1567211143
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.11579616
Short name T1049
Test name
Test status
Simulation time 113965462595 ps
CPU time 56.77 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:55:00 PM PDT 24
Peak memory 200292 kb
Host smart-846e69ad-6a05-4a0b-9098-66726fa690f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11579616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.11579616
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3628573317
Short name T840
Test name
Test status
Simulation time 1915788741 ps
CPU time 3.86 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:07 PM PDT 24
Peak memory 195936 kb
Host smart-513c453b-d2eb-4b46-bfad-f337a0c5c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628573317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3628573317
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1807916301
Short name T613
Test name
Test status
Simulation time 444826241 ps
CPU time 2.43 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 199196 kb
Host smart-0d2fb241-863d-4826-a9ca-d0ee32c69a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807916301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1807916301
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2589320102
Short name T598
Test name
Test status
Simulation time 375398896178 ps
CPU time 253.27 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:58:15 PM PDT 24
Peak memory 200356 kb
Host smart-79195a65-100f-4462-8c1b-0d404e30ced6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589320102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2589320102
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1469659805
Short name T915
Test name
Test status
Simulation time 1038943708 ps
CPU time 1.44 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 198576 kb
Host smart-83deaa36-663b-4950-9e69-7181c06b7aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469659805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1469659805
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4079944597
Short name T609
Test name
Test status
Simulation time 156392157909 ps
CPU time 94.05 seconds
Started Mar 21 01:54:00 PM PDT 24
Finished Mar 21 01:55:34 PM PDT 24
Peak memory 200416 kb
Host smart-a7283cb4-1027-4ee8-b01c-ae71e5a31312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079944597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4079944597
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1488582859
Short name T616
Test name
Test status
Simulation time 84778568067 ps
CPU time 33 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:58:32 PM PDT 24
Peak memory 200420 kb
Host smart-46ae0aa5-6ea3-4c62-accb-273f943cff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488582859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1488582859
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1322015602
Short name T890
Test name
Test status
Simulation time 72688497084 ps
CPU time 32.41 seconds
Started Mar 21 01:58:00 PM PDT 24
Finished Mar 21 01:58:34 PM PDT 24
Peak memory 200440 kb
Host smart-ea25b170-b703-47b2-a982-4f771873eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322015602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1322015602
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2226990641
Short name T200
Test name
Test status
Simulation time 64318773594 ps
CPU time 67.4 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:59:07 PM PDT 24
Peak memory 200440 kb
Host smart-ed6e484a-b222-4933-9b45-8e66a5df02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226990641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2226990641
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1240529776
Short name T522
Test name
Test status
Simulation time 11535094759 ps
CPU time 35.65 seconds
Started Mar 21 01:57:56 PM PDT 24
Finished Mar 21 01:58:32 PM PDT 24
Peak memory 200408 kb
Host smart-b59edd2d-100c-4198-8eff-e4cadb6ee215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240529776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1240529776
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2089282519
Short name T1004
Test name
Test status
Simulation time 123031283927 ps
CPU time 197.28 seconds
Started Mar 21 01:57:57 PM PDT 24
Finished Mar 21 02:01:16 PM PDT 24
Peak memory 200376 kb
Host smart-d1e1042a-faea-4dd2-ab50-119f84ca7dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089282519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2089282519
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2595034560
Short name T526
Test name
Test status
Simulation time 20830927559 ps
CPU time 41.71 seconds
Started Mar 21 01:58:05 PM PDT 24
Finished Mar 21 01:58:46 PM PDT 24
Peak memory 200372 kb
Host smart-a221f9e4-c15c-432a-9c15-f1eaae286c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595034560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2595034560
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3251794735
Short name T693
Test name
Test status
Simulation time 120255265528 ps
CPU time 100.37 seconds
Started Mar 21 01:57:59 PM PDT 24
Finished Mar 21 01:59:42 PM PDT 24
Peak memory 200368 kb
Host smart-b9784108-f717-4ff3-9689-7d528752471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251794735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3251794735
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4243830138
Short name T1066
Test name
Test status
Simulation time 94081465514 ps
CPU time 56.58 seconds
Started Mar 21 01:57:57 PM PDT 24
Finished Mar 21 01:58:55 PM PDT 24
Peak memory 200304 kb
Host smart-cb01d4f8-dfbf-4f06-a3df-d76cd1c707cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243830138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4243830138
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.4217318777
Short name T1112
Test name
Test status
Simulation time 159655122708 ps
CPU time 31.11 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:58:31 PM PDT 24
Peak memory 200428 kb
Host smart-a40df9cd-7f47-4821-9eef-94e5d6efd4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217318777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4217318777
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2235016118
Short name T622
Test name
Test status
Simulation time 45685752 ps
CPU time 0.57 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:05 PM PDT 24
Peak memory 195872 kb
Host smart-68199a10-4485-4675-8604-2004315fb236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235016118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2235016118
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2771387116
Short name T153
Test name
Test status
Simulation time 39034660050 ps
CPU time 26.66 seconds
Started Mar 21 01:54:01 PM PDT 24
Finished Mar 21 01:54:28 PM PDT 24
Peak memory 200320 kb
Host smart-98964c54-2ed0-4dfd-8964-a57e8f274296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771387116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2771387116
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1170868094
Short name T928
Test name
Test status
Simulation time 138063174513 ps
CPU time 115.21 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:55:59 PM PDT 24
Peak memory 200460 kb
Host smart-559283c1-38b8-46bd-a744-c87d7b614516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170868094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1170868094
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.305119848
Short name T133
Test name
Test status
Simulation time 41516708002 ps
CPU time 71.36 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:55:15 PM PDT 24
Peak memory 199884 kb
Host smart-bc88f353-6b2b-4142-8538-61844fbcebeb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305119848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.305119848
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.837134424
Short name T962
Test name
Test status
Simulation time 93802078672 ps
CPU time 336.97 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:59:40 PM PDT 24
Peak memory 200372 kb
Host smart-a75f5d34-d548-4304-b6bd-c2698ac37ca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837134424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.837134424
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1123576986
Short name T120
Test name
Test status
Simulation time 8018098909 ps
CPU time 14.25 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:54:20 PM PDT 24
Peak memory 197952 kb
Host smart-b06e8c78-bde2-44bf-b1b3-e3e5537504e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123576986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1123576986
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2160503306
Short name T246
Test name
Test status
Simulation time 167258778037 ps
CPU time 94.79 seconds
Started Mar 21 01:54:07 PM PDT 24
Finished Mar 21 01:55:42 PM PDT 24
Peak memory 216388 kb
Host smart-7cebaafe-5110-4be3-9392-7a8c2a1533c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160503306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2160503306
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1900566977
Short name T1023
Test name
Test status
Simulation time 15850623192 ps
CPU time 362.81 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 02:00:06 PM PDT 24
Peak memory 200424 kb
Host smart-5c87d053-2a86-4807-b301-12fb3b742c05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900566977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1900566977
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3778898540
Short name T833
Test name
Test status
Simulation time 1695791767 ps
CPU time 8.75 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:11 PM PDT 24
Peak memory 197220 kb
Host smart-59f509c3-8b44-4274-9754-8d6605086803
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778898540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3778898540
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3726572648
Short name T835
Test name
Test status
Simulation time 84935336259 ps
CPU time 124.4 seconds
Started Mar 21 01:54:07 PM PDT 24
Finished Mar 21 01:56:12 PM PDT 24
Peak memory 200344 kb
Host smart-5b92cb59-f187-4823-82d0-b6652694a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726572648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3726572648
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.545153744
Short name T955
Test name
Test status
Simulation time 43362486837 ps
CPU time 11.23 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:16 PM PDT 24
Peak memory 196224 kb
Host smart-bf421627-ad3f-41a0-907f-aa37337c02fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545153744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.545153744
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3992015120
Short name T741
Test name
Test status
Simulation time 478241791 ps
CPU time 1.19 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:54:04 PM PDT 24
Peak memory 199108 kb
Host smart-cfe6862e-8842-4332-ba69-e7057f8a32dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992015120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3992015120
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2446040031
Short name T823
Test name
Test status
Simulation time 407543472262 ps
CPU time 195.37 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:57:20 PM PDT 24
Peak memory 200076 kb
Host smart-e4fc135e-f46e-4d39-b920-6a61103d0290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446040031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2446040031
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.4177405944
Short name T340
Test name
Test status
Simulation time 2154275165 ps
CPU time 2.33 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:05 PM PDT 24
Peak memory 198764 kb
Host smart-8c623399-7e18-42d6-80c2-7ffb6f8f2dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177405944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4177405944
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.73978325
Short name T938
Test name
Test status
Simulation time 71966983221 ps
CPU time 30.82 seconds
Started Mar 21 01:54:02 PM PDT 24
Finished Mar 21 01:54:33 PM PDT 24
Peak memory 200424 kb
Host smart-73bd2bad-aa54-42a7-ad0d-c448d14d4215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73978325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.73978325
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3990655885
Short name T151
Test name
Test status
Simulation time 28244388442 ps
CPU time 19.01 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:58:18 PM PDT 24
Peak memory 200432 kb
Host smart-b7deb787-5d22-4298-8dbb-80cadc658d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990655885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3990655885
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3392715559
Short name T606
Test name
Test status
Simulation time 64583633790 ps
CPU time 30.78 seconds
Started Mar 21 01:57:59 PM PDT 24
Finished Mar 21 01:58:30 PM PDT 24
Peak memory 200324 kb
Host smart-a483eb08-a3bc-4041-b741-d6cb7a380de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392715559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3392715559
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.360295280
Short name T778
Test name
Test status
Simulation time 214542822125 ps
CPU time 40.66 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:58:40 PM PDT 24
Peak memory 200348 kb
Host smart-a6e939e2-2b3e-4ecf-9df8-7dee37696776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360295280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.360295280
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2112111008
Short name T161
Test name
Test status
Simulation time 81834391167 ps
CPU time 131.8 seconds
Started Mar 21 01:58:01 PM PDT 24
Finished Mar 21 02:00:14 PM PDT 24
Peak memory 200452 kb
Host smart-dfcd1890-6672-4951-9ba4-a00f9326b940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112111008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2112111008
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2725543045
Short name T706
Test name
Test status
Simulation time 10375432885 ps
CPU time 15.86 seconds
Started Mar 21 01:58:00 PM PDT 24
Finished Mar 21 01:58:17 PM PDT 24
Peak memory 200276 kb
Host smart-a7323b97-556c-4714-ab85-6d28948acde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725543045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2725543045
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.4233395005
Short name T800
Test name
Test status
Simulation time 34240819452 ps
CPU time 16.11 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:58:16 PM PDT 24
Peak memory 200336 kb
Host smart-421266b7-2a60-4ab4-9b11-1352f50b3c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233395005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4233395005
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3676177775
Short name T220
Test name
Test status
Simulation time 36479578726 ps
CPU time 16.75 seconds
Started Mar 21 01:58:04 PM PDT 24
Finished Mar 21 01:58:21 PM PDT 24
Peak memory 200352 kb
Host smart-3b2da685-23ed-483c-8cb9-31ada6e0b0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676177775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3676177775
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.579300414
Short name T281
Test name
Test status
Simulation time 13240070036 ps
CPU time 6.92 seconds
Started Mar 21 01:58:01 PM PDT 24
Finished Mar 21 01:58:09 PM PDT 24
Peak memory 200320 kb
Host smart-414b7feb-7dc5-4275-a063-6a3e259bdae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579300414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.579300414
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2386483790
Short name T1012
Test name
Test status
Simulation time 105702622419 ps
CPU time 281.56 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 02:02:41 PM PDT 24
Peak memory 200456 kb
Host smart-879ded04-0e97-472e-b555-f2920a8a0849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386483790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2386483790
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3744322984
Short name T894
Test name
Test status
Simulation time 37783700220 ps
CPU time 23.72 seconds
Started Mar 21 01:58:00 PM PDT 24
Finished Mar 21 01:58:25 PM PDT 24
Peak memory 200452 kb
Host smart-ea39393a-3253-48f5-bca6-a0e21fe426d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744322984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3744322984
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1930230097
Short name T1003
Test name
Test status
Simulation time 35323921 ps
CPU time 0.55 seconds
Started Mar 21 01:54:21 PM PDT 24
Finished Mar 21 01:54:21 PM PDT 24
Peak memory 195284 kb
Host smart-59f74354-c313-45c3-a7aa-fb94ee4aea60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930230097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1930230097
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.779502510
Short name T79
Test name
Test status
Simulation time 122646461911 ps
CPU time 348.86 seconds
Started Mar 21 01:54:03 PM PDT 24
Finished Mar 21 01:59:52 PM PDT 24
Peak memory 200452 kb
Host smart-5170afc5-88a7-45f1-a7e7-df4752b4b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779502510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.779502510
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.491236946
Short name T448
Test name
Test status
Simulation time 24559163679 ps
CPU time 36.82 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:41 PM PDT 24
Peak memory 200436 kb
Host smart-c522991c-ce26-4a1d-b0b1-725a85b2d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491236946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.491236946
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.37220665
Short name T198
Test name
Test status
Simulation time 114402084973 ps
CPU time 228.71 seconds
Started Mar 21 01:54:15 PM PDT 24
Finished Mar 21 01:58:04 PM PDT 24
Peak memory 200348 kb
Host smart-f1d08b81-8e2d-4f64-8f77-576eede978e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37220665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.37220665
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.4099024498
Short name T491
Test name
Test status
Simulation time 7329872401 ps
CPU time 1.64 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:54:22 PM PDT 24
Peak memory 197380 kb
Host smart-a86dbfae-24f1-45dd-bb83-c98b47346061
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099024498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4099024498
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2818918324
Short name T709
Test name
Test status
Simulation time 106511229957 ps
CPU time 882.98 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 02:09:01 PM PDT 24
Peak memory 200348 kb
Host smart-f13c919f-bafe-412e-b2fd-50568ffa62d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818918324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2818918324
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.676100906
Short name T577
Test name
Test status
Simulation time 7860672507 ps
CPU time 5.17 seconds
Started Mar 21 01:54:16 PM PDT 24
Finished Mar 21 01:54:21 PM PDT 24
Peak memory 200384 kb
Host smart-634ef254-9538-4857-813f-59363cb50a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676100906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.676100906
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1957887973
Short name T695
Test name
Test status
Simulation time 58456012383 ps
CPU time 42.76 seconds
Started Mar 21 01:54:23 PM PDT 24
Finished Mar 21 01:55:06 PM PDT 24
Peak memory 199652 kb
Host smart-64ef4e30-3504-4a9c-af42-259d91ebdb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957887973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1957887973
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2204842847
Short name T953
Test name
Test status
Simulation time 14462443971 ps
CPU time 209.22 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:57:47 PM PDT 24
Peak memory 200396 kb
Host smart-cecb2255-09a1-49bb-bb8f-710d954d288f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204842847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2204842847
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2602045520
Short name T720
Test name
Test status
Simulation time 6632794436 ps
CPU time 64.37 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:55:31 PM PDT 24
Peak memory 199216 kb
Host smart-2d5b5a0f-7b61-4f76-ac77-1973ea33a021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602045520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2602045520
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3188514981
Short name T1026
Test name
Test status
Simulation time 46252935763 ps
CPU time 22.1 seconds
Started Mar 21 01:54:16 PM PDT 24
Finished Mar 21 01:54:38 PM PDT 24
Peak memory 200384 kb
Host smart-773d86a6-a4e9-47c3-813a-a2c6faa91960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188514981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3188514981
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2348745372
Short name T752
Test name
Test status
Simulation time 74367961499 ps
CPU time 108.45 seconds
Started Mar 21 01:54:12 PM PDT 24
Finished Mar 21 01:56:01 PM PDT 24
Peak memory 196484 kb
Host smart-0765da81-345a-4964-ac09-3c33ed272f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348745372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2348745372
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1304468981
Short name T1016
Test name
Test status
Simulation time 698733798 ps
CPU time 1.37 seconds
Started Mar 21 01:54:04 PM PDT 24
Finished Mar 21 01:54:06 PM PDT 24
Peak memory 199136 kb
Host smart-fe6c3bdf-17f3-4689-8444-19ccd5a494cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304468981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1304468981
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.595240373
Short name T934
Test name
Test status
Simulation time 268895635929 ps
CPU time 142.52 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:56:42 PM PDT 24
Peak memory 208784 kb
Host smart-8198f2f2-2a0f-4623-b78f-087b332752c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595240373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.595240373
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.4025447626
Short name T406
Test name
Test status
Simulation time 2225296060 ps
CPU time 2.8 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:54:30 PM PDT 24
Peak memory 199180 kb
Host smart-2312f47c-895a-4be9-b2d3-f56a05759a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025447626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4025447626
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1624088841
Short name T781
Test name
Test status
Simulation time 90074617806 ps
CPU time 198.77 seconds
Started Mar 21 01:54:05 PM PDT 24
Finished Mar 21 01:57:24 PM PDT 24
Peak memory 200312 kb
Host smart-18cfd473-113b-49c8-90aa-baefcb2dbbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624088841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1624088841
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3608766501
Short name T532
Test name
Test status
Simulation time 133276578452 ps
CPU time 48.92 seconds
Started Mar 21 01:57:59 PM PDT 24
Finished Mar 21 01:58:50 PM PDT 24
Peak memory 200344 kb
Host smart-49368765-e06c-4626-b9c4-64a1dfd674d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608766501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3608766501
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.97494342
Short name T593
Test name
Test status
Simulation time 53983039434 ps
CPU time 93.19 seconds
Started Mar 21 01:58:05 PM PDT 24
Finished Mar 21 01:59:39 PM PDT 24
Peak memory 200392 kb
Host smart-6f94d434-cd3a-4223-94dc-9dd8af8300cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97494342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.97494342
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3041890387
Short name T799
Test name
Test status
Simulation time 232609484493 ps
CPU time 57.56 seconds
Started Mar 21 01:58:00 PM PDT 24
Finished Mar 21 01:59:00 PM PDT 24
Peak memory 200452 kb
Host smart-d023678e-ef83-4dda-a05b-be0ecf816efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041890387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3041890387
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2464037899
Short name T301
Test name
Test status
Simulation time 138078945933 ps
CPU time 264.05 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 02:02:23 PM PDT 24
Peak memory 200400 kb
Host smart-964303a0-8c19-47a6-8e4a-38b315269bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464037899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2464037899
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2105991675
Short name T698
Test name
Test status
Simulation time 126551374134 ps
CPU time 131.38 seconds
Started Mar 21 01:58:00 PM PDT 24
Finished Mar 21 02:00:13 PM PDT 24
Peak memory 200452 kb
Host smart-bb3fd727-2371-4f98-8591-9063cd2658de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105991675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2105991675
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2745312490
Short name T780
Test name
Test status
Simulation time 10697995552 ps
CPU time 13.72 seconds
Started Mar 21 01:57:58 PM PDT 24
Finished Mar 21 01:58:13 PM PDT 24
Peak memory 200444 kb
Host smart-37e2fab0-340c-4fee-a2ed-fde346f7101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745312490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2745312490
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.4203955358
Short name T187
Test name
Test status
Simulation time 28513624885 ps
CPU time 46.34 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 01:58:57 PM PDT 24
Peak memory 200416 kb
Host smart-58a6ca55-39e5-4fd9-a326-70c480d3f615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203955358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.4203955358
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4082222156
Short name T985
Test name
Test status
Simulation time 135709703453 ps
CPU time 233.35 seconds
Started Mar 21 01:58:12 PM PDT 24
Finished Mar 21 02:02:05 PM PDT 24
Peak memory 200380 kb
Host smart-a5c963ec-5f05-4c12-a4bc-2e27f4e1ea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082222156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4082222156
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3762576006
Short name T61
Test name
Test status
Simulation time 15067779 ps
CPU time 0.54 seconds
Started Mar 21 01:54:16 PM PDT 24
Finished Mar 21 01:54:17 PM PDT 24
Peak memory 195812 kb
Host smart-11e8bb29-76ce-42fe-b988-b34a93fe3e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762576006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3762576006
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.384069517
Short name T36
Test name
Test status
Simulation time 25847481722 ps
CPU time 42.39 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:55:01 PM PDT 24
Peak memory 200292 kb
Host smart-118fdd15-788f-49df-a142-b70b6477c7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384069517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.384069517
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2565167216
Short name T597
Test name
Test status
Simulation time 36340400878 ps
CPU time 60.38 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:55:19 PM PDT 24
Peak memory 200344 kb
Host smart-4d566a21-df7a-4179-ba77-70399e24311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565167216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2565167216
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2233946246
Short name T228
Test name
Test status
Simulation time 45199035586 ps
CPU time 34.68 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 01:54:52 PM PDT 24
Peak memory 200428 kb
Host smart-ad81c31e-cb25-4d7b-b913-32c44b939ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233946246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2233946246
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.4039620060
Short name T719
Test name
Test status
Simulation time 27687922554 ps
CPU time 3.99 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 01:54:21 PM PDT 24
Peak memory 199380 kb
Host smart-c8c7105f-db01-423f-b3b8-dccaffcfca74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039620060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4039620060
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1268674256
Short name T1067
Test name
Test status
Simulation time 99651234505 ps
CPU time 329.61 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 01:59:47 PM PDT 24
Peak memory 200352 kb
Host smart-3dcf6b5f-882e-4c37-8708-26199443b613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268674256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1268674256
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2578678536
Short name T394
Test name
Test status
Simulation time 8027123175 ps
CPU time 7.18 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:54:34 PM PDT 24
Peak memory 199412 kb
Host smart-46308dda-fe3c-46ea-8842-0674d3b86f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578678536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2578678536
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1340192544
Short name T653
Test name
Test status
Simulation time 67483223535 ps
CPU time 113.67 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:56:12 PM PDT 24
Peak memory 199972 kb
Host smart-cf26ea85-48d4-4aad-b062-1097d6590e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340192544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1340192544
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3202843357
Short name T670
Test name
Test status
Simulation time 8870507985 ps
CPU time 222.99 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:58:02 PM PDT 24
Peak memory 200424 kb
Host smart-bfa06961-75f5-4dd2-8631-43d575f2daee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202843357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3202843357
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.481348125
Short name T723
Test name
Test status
Simulation time 7125000184 ps
CPU time 65.06 seconds
Started Mar 21 01:54:16 PM PDT 24
Finished Mar 21 01:55:21 PM PDT 24
Peak memory 199020 kb
Host smart-28554d21-2258-4277-8f4c-ff0092d0c816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481348125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.481348125
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4238472441
Short name T884
Test name
Test status
Simulation time 2782014971 ps
CPU time 5.09 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:54:24 PM PDT 24
Peak memory 196176 kb
Host smart-e7824304-4a46-4df9-b19a-2898a23e1dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238472441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4238472441
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1484329286
Short name T46
Test name
Test status
Simulation time 896233199 ps
CPU time 1.81 seconds
Started Mar 21 01:54:12 PM PDT 24
Finished Mar 21 01:54:13 PM PDT 24
Peak memory 199088 kb
Host smart-7664bc65-dfef-4691-8123-c479669314c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484329286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1484329286
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.60892717
Short name T1014
Test name
Test status
Simulation time 145837451025 ps
CPU time 73.65 seconds
Started Mar 21 01:54:16 PM PDT 24
Finished Mar 21 01:55:30 PM PDT 24
Peak memory 200440 kb
Host smart-7ee4bb5f-16d8-48d9-8214-a5aca011ea0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60892717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.60892717
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.93939737
Short name T64
Test name
Test status
Simulation time 194119044058 ps
CPU time 300.13 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:59:20 PM PDT 24
Peak memory 217084 kb
Host smart-a045eb06-7c45-4622-9ee7-e49bd36a7327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93939737 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.93939737
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4048665538
Short name T1035
Test name
Test status
Simulation time 1426047919 ps
CPU time 3.88 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:54:22 PM PDT 24
Peak memory 199168 kb
Host smart-f590c54b-72c8-4d6b-a3c6-8b58aea47fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048665538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4048665538
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.992261750
Short name T963
Test name
Test status
Simulation time 8663707173 ps
CPU time 17.51 seconds
Started Mar 21 01:54:16 PM PDT 24
Finished Mar 21 01:54:34 PM PDT 24
Peak memory 200436 kb
Host smart-6f8877f1-624e-4460-990e-1a3b8596f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992261750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.992261750
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.4083557397
Short name T442
Test name
Test status
Simulation time 139744836860 ps
CPU time 218.56 seconds
Started Mar 21 01:58:10 PM PDT 24
Finished Mar 21 02:01:49 PM PDT 24
Peak memory 200420 kb
Host smart-d6d08e8c-ff2b-41b0-a626-6156313303c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083557397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.4083557397
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.890048601
Short name T78
Test name
Test status
Simulation time 64459395255 ps
CPU time 107.65 seconds
Started Mar 21 01:58:26 PM PDT 24
Finished Mar 21 02:00:14 PM PDT 24
Peak memory 200360 kb
Host smart-1b447fdd-33ce-4d3c-9e8e-2ee21fa496e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890048601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.890048601
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1372567457
Short name T942
Test name
Test status
Simulation time 96321391049 ps
CPU time 41.21 seconds
Started Mar 21 01:58:19 PM PDT 24
Finished Mar 21 01:59:00 PM PDT 24
Peak memory 200392 kb
Host smart-98ad2694-56db-496f-9ad5-65a4c24c2d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372567457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1372567457
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.385235114
Short name T329
Test name
Test status
Simulation time 50602118372 ps
CPU time 41.59 seconds
Started Mar 21 01:58:15 PM PDT 24
Finished Mar 21 01:58:58 PM PDT 24
Peak memory 200632 kb
Host smart-526ae7bd-0b53-4509-a692-5b141d7577be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385235114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.385235114
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2248288424
Short name T326
Test name
Test status
Simulation time 62037728831 ps
CPU time 28.16 seconds
Started Mar 21 01:58:15 PM PDT 24
Finished Mar 21 01:58:43 PM PDT 24
Peak memory 200584 kb
Host smart-86bc1581-3766-4848-8374-de3c023b0b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248288424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2248288424
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2034119505
Short name T1050
Test name
Test status
Simulation time 79808657286 ps
CPU time 138.07 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 02:00:30 PM PDT 24
Peak memory 200388 kb
Host smart-0a09ee7f-f283-4a48-919c-e9de8aa46b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034119505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2034119505
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1532743348
Short name T13
Test name
Test status
Simulation time 35139063727 ps
CPU time 61.36 seconds
Started Mar 21 01:58:26 PM PDT 24
Finished Mar 21 01:59:28 PM PDT 24
Peak memory 200076 kb
Host smart-41352440-49d2-449c-be66-6d38b2453210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532743348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1532743348
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3582537971
Short name T1057
Test name
Test status
Simulation time 109717359380 ps
CPU time 201.54 seconds
Started Mar 21 01:58:10 PM PDT 24
Finished Mar 21 02:01:32 PM PDT 24
Peak memory 200436 kb
Host smart-05ff74da-c15b-4e4f-af2c-13cb8e1f5507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582537971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3582537971
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2011319450
Short name T688
Test name
Test status
Simulation time 157373444256 ps
CPU time 63.25 seconds
Started Mar 21 01:58:13 PM PDT 24
Finished Mar 21 01:59:16 PM PDT 24
Peak memory 200312 kb
Host smart-60971e22-ec3e-4907-871d-2af571e1e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011319450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2011319450
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1374526595
Short name T490
Test name
Test status
Simulation time 39206616596 ps
CPU time 17.25 seconds
Started Mar 21 01:58:12 PM PDT 24
Finished Mar 21 01:58:30 PM PDT 24
Peak memory 200468 kb
Host smart-16b5348e-46c6-4302-b78c-0681a896a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374526595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1374526595
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.111306009
Short name T1021
Test name
Test status
Simulation time 111341339549 ps
CPU time 193.66 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:57:33 PM PDT 24
Peak memory 200360 kb
Host smart-adb8078e-4a64-4fff-9fc0-aef13c74cdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111306009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.111306009
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1755692107
Short name T105
Test name
Test status
Simulation time 108686798380 ps
CPU time 46.17 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:55:06 PM PDT 24
Peak memory 200376 kb
Host smart-e9dc3707-165c-4f58-9e48-28865a3101cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755692107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1755692107
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.646892974
Short name T1001
Test name
Test status
Simulation time 20586760076 ps
CPU time 36.35 seconds
Started Mar 21 01:54:12 PM PDT 24
Finished Mar 21 01:54:48 PM PDT 24
Peak memory 200324 kb
Host smart-bd10e9b9-360f-496b-98ec-b6873a8526de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646892974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.646892974
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.577682497
Short name T993
Test name
Test status
Simulation time 52797325780 ps
CPU time 22.63 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:54:43 PM PDT 24
Peak memory 200344 kb
Host smart-51810b1f-b4f3-48fb-badb-6879c76223a0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577682497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.577682497
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.318926421
Short name T364
Test name
Test status
Simulation time 40113547915 ps
CPU time 284.42 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:59:05 PM PDT 24
Peak memory 200364 kb
Host smart-3abe5594-8e4c-42c5-8369-5ddeeb53b79e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318926421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.318926421
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3561531261
Short name T545
Test name
Test status
Simulation time 10788442843 ps
CPU time 13.51 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 01:54:31 PM PDT 24
Peak memory 199476 kb
Host smart-9aaafe6f-c0d6-45bf-91ca-e49dbce3d95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561531261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3561531261
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2716630546
Short name T467
Test name
Test status
Simulation time 66250297596 ps
CPU time 172.24 seconds
Started Mar 21 01:54:16 PM PDT 24
Finished Mar 21 01:57:09 PM PDT 24
Peak memory 199928 kb
Host smart-ca5332ad-f679-4ce1-b463-28cebba761c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716630546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2716630546
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2555980444
Short name T389
Test name
Test status
Simulation time 15091967126 ps
CPU time 812.35 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 02:07:50 PM PDT 24
Peak memory 200328 kb
Host smart-db480415-8782-4a7e-b704-c04786130415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555980444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2555980444
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2900831797
Short name T392
Test name
Test status
Simulation time 6278851061 ps
CPU time 61.79 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:55:21 PM PDT 24
Peak memory 199236 kb
Host smart-873e298f-2502-41e6-987a-95f4d2d4f910
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900831797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2900831797
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1803078500
Short name T1042
Test name
Test status
Simulation time 3051095892 ps
CPU time 5.3 seconds
Started Mar 21 01:54:12 PM PDT 24
Finished Mar 21 01:54:18 PM PDT 24
Peak memory 196500 kb
Host smart-1b76b99f-d758-4642-a0b1-7e85f0220dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803078500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1803078500
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.859233316
Short name T882
Test name
Test status
Simulation time 5814589075 ps
CPU time 8.96 seconds
Started Mar 21 01:54:15 PM PDT 24
Finished Mar 21 01:54:24 PM PDT 24
Peak memory 199636 kb
Host smart-66817620-147b-4b0d-8e5f-b3c6b7b849ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859233316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.859233316
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3494635513
Short name T319
Test name
Test status
Simulation time 352992511292 ps
CPU time 176.24 seconds
Started Mar 21 01:54:13 PM PDT 24
Finished Mar 21 01:57:09 PM PDT 24
Peak memory 216984 kb
Host smart-b70385d1-1307-4cf7-90c9-d23ba5862ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494635513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3494635513
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.902297586
Short name T373
Test name
Test status
Simulation time 8427331526 ps
CPU time 9.95 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:54:30 PM PDT 24
Peak memory 200340 kb
Host smart-65adf56c-5dcf-403b-8761-fb5fef110a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902297586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.902297586
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3216378341
Short name T556
Test name
Test status
Simulation time 15712994602 ps
CPU time 24.9 seconds
Started Mar 21 01:54:14 PM PDT 24
Finished Mar 21 01:54:39 PM PDT 24
Peak memory 200312 kb
Host smart-05b57d2a-922d-4f44-bf55-296795316162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216378341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3216378341
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.806862530
Short name T1051
Test name
Test status
Simulation time 66465415451 ps
CPU time 16.55 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 01:58:27 PM PDT 24
Peak memory 200388 kb
Host smart-380ea92a-c5e4-4011-b23e-4acf2e89afbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806862530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.806862530
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2591137982
Short name T420
Test name
Test status
Simulation time 185634703928 ps
CPU time 267.54 seconds
Started Mar 21 01:58:26 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 200436 kb
Host smart-0b2c420b-9d5b-48cb-97c9-f8d363cb02f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591137982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2591137982
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.520568437
Short name T433
Test name
Test status
Simulation time 33244139152 ps
CPU time 56.83 seconds
Started Mar 21 01:58:26 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 200096 kb
Host smart-d51f4c90-cf2e-4334-a5fd-8a9058a04963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520568437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.520568437
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3284519826
Short name T911
Test name
Test status
Simulation time 185062258920 ps
CPU time 374.89 seconds
Started Mar 21 01:58:26 PM PDT 24
Finished Mar 21 02:04:41 PM PDT 24
Peak memory 200236 kb
Host smart-eb43ea2e-f094-48c3-9a37-f30bf7aecdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284519826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3284519826
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2293411486
Short name T1059
Test name
Test status
Simulation time 14343263361 ps
CPU time 20.94 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 01:58:33 PM PDT 24
Peak memory 200344 kb
Host smart-a359f4ba-a0d0-49c3-9601-f99840cbcaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293411486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2293411486
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.794471588
Short name T1047
Test name
Test status
Simulation time 143510047748 ps
CPU time 98.03 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 01:59:49 PM PDT 24
Peak memory 200420 kb
Host smart-bab764b1-9297-455f-9648-80cae565f5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794471588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.794471588
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.931267016
Short name T905
Test name
Test status
Simulation time 166342095864 ps
CPU time 67.3 seconds
Started Mar 21 01:58:18 PM PDT 24
Finished Mar 21 01:59:26 PM PDT 24
Peak memory 200456 kb
Host smart-e367229d-a528-4114-9c46-5d9dfec065a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931267016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.931267016
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.826354205
Short name T330
Test name
Test status
Simulation time 20731726476 ps
CPU time 32.43 seconds
Started Mar 21 01:58:10 PM PDT 24
Finished Mar 21 01:58:43 PM PDT 24
Peak memory 200372 kb
Host smart-fc719fc9-18df-4a6e-a3c2-e926547d818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826354205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.826354205
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1522947011
Short name T193
Test name
Test status
Simulation time 45556090235 ps
CPU time 34.88 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 01:58:47 PM PDT 24
Peak memory 200344 kb
Host smart-a374a8db-30a0-4518-82cf-fc62944d95c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522947011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1522947011
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2879054900
Short name T142
Test name
Test status
Simulation time 33445226309 ps
CPU time 49.91 seconds
Started Mar 21 01:58:15 PM PDT 24
Finished Mar 21 01:59:06 PM PDT 24
Peak memory 200680 kb
Host smart-f4e30bba-ad5a-4ebf-a29a-2fe9ae222cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879054900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2879054900
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.988944283
Short name T973
Test name
Test status
Simulation time 14281986 ps
CPU time 0.59 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 01:54:18 PM PDT 24
Peak memory 195884 kb
Host smart-3faff594-642e-4354-a3d5-0736556138fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988944283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.988944283
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1307196138
Short name T240
Test name
Test status
Simulation time 79156666835 ps
CPU time 59.18 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:55:18 PM PDT 24
Peak memory 200400 kb
Host smart-70ccf021-cf76-44cf-b428-b0e023ba33ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307196138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1307196138
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3790620540
Short name T51
Test name
Test status
Simulation time 154382936222 ps
CPU time 123.45 seconds
Started Mar 21 01:54:12 PM PDT 24
Finished Mar 21 01:56:16 PM PDT 24
Peak memory 200416 kb
Host smart-067ad5fb-5a45-4857-8cec-2db1b5e99bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790620540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3790620540
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2476614399
Short name T885
Test name
Test status
Simulation time 109678293755 ps
CPU time 163.26 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:57:02 PM PDT 24
Peak memory 200344 kb
Host smart-c6e48440-491a-4ae8-acdd-675c1e47decb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476614399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2476614399
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1346469370
Short name T734
Test name
Test status
Simulation time 194878997894 ps
CPU time 62.31 seconds
Started Mar 21 01:54:18 PM PDT 24
Finished Mar 21 01:55:20 PM PDT 24
Peak memory 199876 kb
Host smart-fe6fbe54-9d8c-4798-be11-4865dd68f992
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346469370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1346469370
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1798816281
Short name T995
Test name
Test status
Simulation time 217314518557 ps
CPU time 611.29 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 02:04:30 PM PDT 24
Peak memory 200364 kb
Host smart-56233e87-8cec-428a-a0cd-71f567b15de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798816281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1798816281
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1246071915
Short name T396
Test name
Test status
Simulation time 10084758708 ps
CPU time 6.34 seconds
Started Mar 21 01:54:13 PM PDT 24
Finished Mar 21 01:54:19 PM PDT 24
Peak memory 199100 kb
Host smart-29b07cf5-b02e-42bb-b07d-7a8f02b44a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246071915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1246071915
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3817121805
Short name T696
Test name
Test status
Simulation time 35613505451 ps
CPU time 19.59 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:54:47 PM PDT 24
Peak memory 198964 kb
Host smart-df9a3d36-fdc0-4a85-b6ed-38256c8a360d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817121805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3817121805
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1180058904
Short name T970
Test name
Test status
Simulation time 19661568693 ps
CPU time 234.86 seconds
Started Mar 21 01:54:12 PM PDT 24
Finished Mar 21 01:58:07 PM PDT 24
Peak memory 200392 kb
Host smart-aaede57a-a57b-4cfb-924c-56b4a1439813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180058904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1180058904
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3292308773
Short name T307
Test name
Test status
Simulation time 3200715574 ps
CPU time 11.89 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:54:31 PM PDT 24
Peak memory 198392 kb
Host smart-03f2a506-a6b9-47bd-a632-f7b01b6578fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292308773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3292308773
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.349855192
Short name T820
Test name
Test status
Simulation time 39849458763 ps
CPU time 14.15 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:54:34 PM PDT 24
Peak memory 200436 kb
Host smart-2fa99eac-aed3-4707-9678-2a458a909f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349855192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.349855192
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.344484482
Short name T952
Test name
Test status
Simulation time 2401225791 ps
CPU time 4.75 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:54:25 PM PDT 24
Peak memory 195860 kb
Host smart-addc038b-4109-4f75-911d-47038a7c6e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344484482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.344484482
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.69423609
Short name T572
Test name
Test status
Simulation time 295034026 ps
CPU time 1.29 seconds
Started Mar 21 01:54:19 PM PDT 24
Finished Mar 21 01:54:21 PM PDT 24
Peak memory 199472 kb
Host smart-24ecd086-871d-4b9c-9369-672c1d3ed943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69423609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.69423609
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.329800846
Short name T26
Test name
Test status
Simulation time 204326306774 ps
CPU time 452.21 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 02:01:49 PM PDT 24
Peak memory 217016 kb
Host smart-51d87ff6-037e-4bf6-aac3-d4453cec947b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329800846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.329800846
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2496018225
Short name T109
Test name
Test status
Simulation time 1171877769 ps
CPU time 4.16 seconds
Started Mar 21 01:54:20 PM PDT 24
Finished Mar 21 01:54:24 PM PDT 24
Peak memory 198816 kb
Host smart-b383d0ac-8e92-4cb9-bd2b-5cf998bb6e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496018225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2496018225
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1567230748
Short name T60
Test name
Test status
Simulation time 123172722600 ps
CPU time 116.59 seconds
Started Mar 21 01:54:17 PM PDT 24
Finished Mar 21 01:56:14 PM PDT 24
Peak memory 200288 kb
Host smart-c91a4ee8-8032-4174-9d34-b1947a5d8a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567230748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1567230748
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1209710339
Short name T901
Test name
Test status
Simulation time 13357725361 ps
CPU time 5.87 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 01:58:18 PM PDT 24
Peak memory 200440 kb
Host smart-126479ff-1d7e-4578-80dc-d1f94130936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209710339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1209710339
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.91988419
Short name T195
Test name
Test status
Simulation time 20312684914 ps
CPU time 38.1 seconds
Started Mar 21 01:58:12 PM PDT 24
Finished Mar 21 01:58:51 PM PDT 24
Peak memory 200412 kb
Host smart-cafa8500-d565-44b8-8ee1-36fb89054da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91988419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.91988419
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.394555526
Short name T521
Test name
Test status
Simulation time 14297997308 ps
CPU time 28.31 seconds
Started Mar 21 01:58:10 PM PDT 24
Finished Mar 21 01:58:38 PM PDT 24
Peak memory 200408 kb
Host smart-09be15a0-dbea-4649-ac84-7736ca71e6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394555526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.394555526
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2933128162
Short name T822
Test name
Test status
Simulation time 98149781173 ps
CPU time 54.13 seconds
Started Mar 21 01:58:15 PM PDT 24
Finished Mar 21 01:59:09 PM PDT 24
Peak memory 200516 kb
Host smart-460d9f11-c51c-402a-9a1f-c376bd90f462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933128162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2933128162
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.4012897289
Short name T183
Test name
Test status
Simulation time 37260778670 ps
CPU time 60.65 seconds
Started Mar 21 01:58:13 PM PDT 24
Finished Mar 21 01:59:14 PM PDT 24
Peak memory 200388 kb
Host smart-645d57c5-84d3-4c76-9d02-9638b174a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012897289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4012897289
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.666965233
Short name T262
Test name
Test status
Simulation time 57699588239 ps
CPU time 93.83 seconds
Started Mar 21 01:58:13 PM PDT 24
Finished Mar 21 01:59:47 PM PDT 24
Peak memory 200392 kb
Host smart-ccb8b5d2-97bd-441c-9829-27bb175c27ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666965233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.666965233
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3059516919
Short name T157
Test name
Test status
Simulation time 10403261417 ps
CPU time 16.43 seconds
Started Mar 21 01:58:12 PM PDT 24
Finished Mar 21 01:58:29 PM PDT 24
Peak memory 200448 kb
Host smart-61cee2b7-6aa5-4794-adaf-2dc87cecb860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059516919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3059516919
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2709029087
Short name T745
Test name
Test status
Simulation time 127920933749 ps
CPU time 42.06 seconds
Started Mar 21 01:58:13 PM PDT 24
Finished Mar 21 01:58:55 PM PDT 24
Peak memory 200364 kb
Host smart-a63b8344-6a98-4769-a1ce-38930892ebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709029087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2709029087
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.605683960
Short name T476
Test name
Test status
Simulation time 29197200925 ps
CPU time 48.44 seconds
Started Mar 21 01:58:12 PM PDT 24
Finished Mar 21 01:59:01 PM PDT 24
Peak memory 200460 kb
Host smart-6cef8a5a-605f-40d0-a825-0cb0b13c4d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605683960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.605683960
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1792726328
Short name T201
Test name
Test status
Simulation time 28368368620 ps
CPU time 109.12 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 02:00:00 PM PDT 24
Peak memory 200384 kb
Host smart-d96c9ed9-8c26-48bc-8f1c-d31cf357d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792726328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1792726328
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3211549883
Short name T926
Test name
Test status
Simulation time 80146881 ps
CPU time 0.57 seconds
Started Mar 21 01:54:23 PM PDT 24
Finished Mar 21 01:54:24 PM PDT 24
Peak memory 195976 kb
Host smart-ba493860-9112-4e85-bae1-77d3a1261888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211549883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3211549883
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1374789782
Short name T263
Test name
Test status
Simulation time 125620179998 ps
CPU time 102.47 seconds
Started Mar 21 01:54:27 PM PDT 24
Finished Mar 21 01:56:10 PM PDT 24
Peak memory 200312 kb
Host smart-68e16740-6a98-4789-bf0d-b35eda51ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374789782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1374789782
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3918971671
Short name T505
Test name
Test status
Simulation time 95857806923 ps
CPU time 12.87 seconds
Started Mar 21 01:54:24 PM PDT 24
Finished Mar 21 01:54:37 PM PDT 24
Peak memory 200328 kb
Host smart-c7cdf312-d579-465c-a40f-d58ec211d7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918971671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3918971671
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1956454146
Short name T383
Test name
Test status
Simulation time 32677467424 ps
CPU time 31.19 seconds
Started Mar 21 01:54:25 PM PDT 24
Finished Mar 21 01:54:57 PM PDT 24
Peak memory 200292 kb
Host smart-0b47ecd5-570f-42bd-a32f-ecac1cfa33af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956454146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1956454146
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3974379507
Short name T1009
Test name
Test status
Simulation time 27163873327 ps
CPU time 14.05 seconds
Started Mar 21 01:54:25 PM PDT 24
Finished Mar 21 01:54:39 PM PDT 24
Peak memory 200340 kb
Host smart-3bf61cfb-713b-4e9d-8275-679753213e24
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974379507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3974379507
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.533077954
Short name T729
Test name
Test status
Simulation time 64740235708 ps
CPU time 202.63 seconds
Started Mar 21 01:54:24 PM PDT 24
Finished Mar 21 01:57:47 PM PDT 24
Peak memory 200352 kb
Host smart-0fe2533a-2483-45db-bced-47056044deb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533077954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.533077954
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2184795883
Short name T711
Test name
Test status
Simulation time 1049751660 ps
CPU time 2.44 seconds
Started Mar 21 01:54:24 PM PDT 24
Finished Mar 21 01:54:26 PM PDT 24
Peak memory 196600 kb
Host smart-41773254-5ec0-4f6e-8847-a786f20398d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184795883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2184795883
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1192733835
Short name T464
Test name
Test status
Simulation time 22891874061 ps
CPU time 34.77 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:55:02 PM PDT 24
Peak memory 200576 kb
Host smart-b50229d2-36ca-400d-9fd5-36ae643f065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192733835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1192733835
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.692291163
Short name T1077
Test name
Test status
Simulation time 25396119202 ps
CPU time 386.82 seconds
Started Mar 21 01:54:29 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 200372 kb
Host smart-d391a530-e6bf-42ab-8f23-458a19d2bc20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692291163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.692291163
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2890531261
Short name T19
Test name
Test status
Simulation time 1917770865 ps
CPU time 2.83 seconds
Started Mar 21 01:54:23 PM PDT 24
Finished Mar 21 01:54:26 PM PDT 24
Peak memory 198496 kb
Host smart-22eeb530-6df4-42e1-86e0-6187fdd2457b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890531261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2890531261
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3038143641
Short name T818
Test name
Test status
Simulation time 29487948301 ps
CPU time 56.18 seconds
Started Mar 21 01:54:25 PM PDT 24
Finished Mar 21 01:55:23 PM PDT 24
Peak memory 200356 kb
Host smart-d0717fc7-cb55-4d85-a822-a933950440de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038143641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3038143641
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1896928863
Short name T267
Test name
Test status
Simulation time 4181774266 ps
CPU time 7.46 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:54:34 PM PDT 24
Peak memory 196448 kb
Host smart-574ee579-2122-4e23-a7c9-70b85cabb2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896928863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1896928863
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.106807136
Short name T276
Test name
Test status
Simulation time 840329067 ps
CPU time 5.15 seconds
Started Mar 21 01:54:24 PM PDT 24
Finished Mar 21 01:54:29 PM PDT 24
Peak memory 199712 kb
Host smart-8b687711-4866-42ab-8472-da59cb43672e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106807136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.106807136
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.397048475
Short name T819
Test name
Test status
Simulation time 1931700576 ps
CPU time 2.46 seconds
Started Mar 21 01:54:29 PM PDT 24
Finished Mar 21 01:54:31 PM PDT 24
Peak memory 198740 kb
Host smart-9abf6c51-be93-4800-aa62-94c7913e55da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397048475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.397048475
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.651032443
Short name T284
Test name
Test status
Simulation time 66039577189 ps
CPU time 26.57 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:55:06 PM PDT 24
Peak memory 200428 kb
Host smart-205c5f7a-9fcc-4f97-8d8e-115b140e2173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651032443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.651032443
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2669567554
Short name T989
Test name
Test status
Simulation time 22527575168 ps
CPU time 38.5 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 01:58:50 PM PDT 24
Peak memory 200392 kb
Host smart-b0862755-dc18-4059-b7e6-873e07cc10b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669567554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2669567554
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3889898084
Short name T987
Test name
Test status
Simulation time 79714709215 ps
CPU time 429 seconds
Started Mar 21 01:58:13 PM PDT 24
Finished Mar 21 02:05:23 PM PDT 24
Peak memory 199984 kb
Host smart-1a077da7-ed27-4ce0-801b-c40d2f752211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889898084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3889898084
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1776223822
Short name T222
Test name
Test status
Simulation time 19689480629 ps
CPU time 31.84 seconds
Started Mar 21 01:58:18 PM PDT 24
Finished Mar 21 01:58:50 PM PDT 24
Peak memory 200128 kb
Host smart-8f8e25ec-2a91-4336-9e77-057d5625b220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776223822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1776223822
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.476974820
Short name T652
Test name
Test status
Simulation time 89929966649 ps
CPU time 141.39 seconds
Started Mar 21 01:58:13 PM PDT 24
Finished Mar 21 02:00:35 PM PDT 24
Peak memory 200312 kb
Host smart-27cff087-e8ca-48fd-9a6b-427d52ce2b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476974820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.476974820
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.813878593
Short name T388
Test name
Test status
Simulation time 211992430893 ps
CPU time 360.9 seconds
Started Mar 21 01:58:26 PM PDT 24
Finished Mar 21 02:04:28 PM PDT 24
Peak memory 200204 kb
Host smart-a7684bb1-98c7-4f37-aa08-e01ca27cb1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813878593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.813878593
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3015323888
Short name T801
Test name
Test status
Simulation time 18415735436 ps
CPU time 13.97 seconds
Started Mar 21 01:58:13 PM PDT 24
Finished Mar 21 01:58:28 PM PDT 24
Peak memory 198512 kb
Host smart-6aa26878-7a2c-4f2f-88d5-6c679915efad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015323888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3015323888
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2464821296
Short name T417
Test name
Test status
Simulation time 8493226045 ps
CPU time 15.98 seconds
Started Mar 21 01:58:13 PM PDT 24
Finished Mar 21 01:58:29 PM PDT 24
Peak memory 200384 kb
Host smart-19224b13-2e0d-4937-8de1-a7ee43c924e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464821296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2464821296
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1665599829
Short name T197
Test name
Test status
Simulation time 13105825857 ps
CPU time 6.83 seconds
Started Mar 21 01:58:18 PM PDT 24
Finished Mar 21 01:58:25 PM PDT 24
Peak memory 200272 kb
Host smart-ef13f479-746c-4e92-a8a2-21383509de46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665599829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1665599829
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.341712519
Short name T226
Test name
Test status
Simulation time 38296954414 ps
CPU time 21.13 seconds
Started Mar 21 01:58:11 PM PDT 24
Finished Mar 21 01:58:32 PM PDT 24
Peak memory 200440 kb
Host smart-e99d77cf-b85c-42af-9f20-65f7b35482de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341712519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.341712519
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3595494953
Short name T441
Test name
Test status
Simulation time 13170835 ps
CPU time 0.56 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:54:40 PM PDT 24
Peak memory 195264 kb
Host smart-78025852-96eb-46cc-a0bb-6a2b21c08ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595494953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3595494953
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2027946806
Short name T925
Test name
Test status
Simulation time 58653088136 ps
CPU time 48.21 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:55:15 PM PDT 24
Peak memory 200440 kb
Host smart-58a9f0ad-d092-427e-b92a-df29bf5835d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027946806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2027946806
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2784797328
Short name T11
Test name
Test status
Simulation time 86106529138 ps
CPU time 27.52 seconds
Started Mar 21 01:54:24 PM PDT 24
Finished Mar 21 01:54:52 PM PDT 24
Peak memory 200412 kb
Host smart-562707f3-f8e6-41ca-b717-3d76cf68b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784797328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2784797328
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.280688003
Short name T1091
Test name
Test status
Simulation time 93116274973 ps
CPU time 210.83 seconds
Started Mar 21 01:54:23 PM PDT 24
Finished Mar 21 01:57:54 PM PDT 24
Peak memory 200348 kb
Host smart-3978f95b-3462-462c-baa8-70ce8ef197f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280688003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.280688003
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3722030742
Short name T482
Test name
Test status
Simulation time 27705231084 ps
CPU time 8.29 seconds
Started Mar 21 01:54:43 PM PDT 24
Finished Mar 21 01:54:52 PM PDT 24
Peak memory 200424 kb
Host smart-5170b82d-c762-4f2c-ac62-397ae57bca96
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722030742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3722030742
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.564893736
Short name T900
Test name
Test status
Simulation time 55978484220 ps
CPU time 143.91 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:57:03 PM PDT 24
Peak memory 200408 kb
Host smart-d898a4b3-cb61-4503-927f-0fb8c0250e3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564893736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.564893736
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3260160312
Short name T943
Test name
Test status
Simulation time 4346895740 ps
CPU time 2.87 seconds
Started Mar 21 01:54:41 PM PDT 24
Finished Mar 21 01:54:44 PM PDT 24
Peak memory 199276 kb
Host smart-6fcac1c9-52e0-4024-86b8-c2f9430e97a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260160312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3260160312
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3651163997
Short name T941
Test name
Test status
Simulation time 55226012644 ps
CPU time 112.77 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:56:31 PM PDT 24
Peak memory 198660 kb
Host smart-bef1077b-8eba-4896-b9cc-25468caa77d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651163997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3651163997
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.4030862643
Short name T409
Test name
Test status
Simulation time 26057235899 ps
CPU time 1194.74 seconds
Started Mar 21 01:54:37 PM PDT 24
Finished Mar 21 02:14:33 PM PDT 24
Peak memory 200396 kb
Host smart-834bc8d9-c3bb-472c-9673-56b0dc0d9bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030862643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4030862643
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2733964304
Short name T472
Test name
Test status
Simulation time 1914549626 ps
CPU time 12.77 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:54:40 PM PDT 24
Peak memory 198524 kb
Host smart-e2bf30e4-3dd5-476a-905c-5d3a8284427b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733964304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2733964304
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1839733282
Short name T504
Test name
Test status
Simulation time 49363218490 ps
CPU time 37.01 seconds
Started Mar 21 01:54:42 PM PDT 24
Finished Mar 21 01:55:20 PM PDT 24
Peak memory 200460 kb
Host smart-a43311c8-18d2-4f34-a859-0242d31b4701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839733282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1839733282
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.4216748979
Short name T731
Test name
Test status
Simulation time 5030140072 ps
CPU time 8.07 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:54:46 PM PDT 24
Peak memory 196776 kb
Host smart-e5eafd29-6e41-4803-a03d-a0e2de6a4ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216748979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4216748979
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1797948824
Short name T961
Test name
Test status
Simulation time 292626810 ps
CPU time 1.09 seconds
Started Mar 21 01:54:26 PM PDT 24
Finished Mar 21 01:54:28 PM PDT 24
Peak memory 198656 kb
Host smart-1814e7cc-3366-4fa2-9802-d6ab0b1df8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797948824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1797948824
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1616241248
Short name T115
Test name
Test status
Simulation time 350630553870 ps
CPU time 98.36 seconds
Started Mar 21 01:54:43 PM PDT 24
Finished Mar 21 01:56:22 PM PDT 24
Peak memory 200200 kb
Host smart-2160d0f8-9f21-4ef2-9a94-f1ca10b4171a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616241248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1616241248
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.661802720
Short name T112
Test name
Test status
Simulation time 230468084105 ps
CPU time 621.63 seconds
Started Mar 21 01:54:37 PM PDT 24
Finished Mar 21 02:04:59 PM PDT 24
Peak memory 208628 kb
Host smart-f1ea586d-aa2c-460c-ae9c-eb178716cd71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661802720 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.661802720
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1264588382
Short name T309
Test name
Test status
Simulation time 1186463897 ps
CPU time 3.14 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:54:43 PM PDT 24
Peak memory 199736 kb
Host smart-aa3ff872-4857-4727-88da-185f556cfcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264588382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1264588382
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.622511396
Short name T789
Test name
Test status
Simulation time 23908850113 ps
CPU time 37.4 seconds
Started Mar 21 01:54:25 PM PDT 24
Finished Mar 21 01:55:04 PM PDT 24
Peak memory 200344 kb
Host smart-a1835308-ada7-4c8c-befd-56ab68f5ffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622511396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.622511396
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2849233164
Short name T188
Test name
Test status
Simulation time 128083424276 ps
CPU time 208.27 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 200456 kb
Host smart-ae8643ab-0e6c-47d7-8a56-b3aadb34d223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849233164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2849233164
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.162631359
Short name T155
Test name
Test status
Simulation time 122384820299 ps
CPU time 48.12 seconds
Started Mar 21 01:58:23 PM PDT 24
Finished Mar 21 01:59:11 PM PDT 24
Peak memory 200428 kb
Host smart-6e1f7819-0474-4210-a715-47c44232694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162631359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.162631359
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1357193636
Short name T1018
Test name
Test status
Simulation time 55582653878 ps
CPU time 22.85 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 01:58:47 PM PDT 24
Peak memory 200200 kb
Host smart-1231fb23-3a94-45fb-9da5-c28ea8fb3686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357193636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1357193636
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3209506475
Short name T1034
Test name
Test status
Simulation time 42726178418 ps
CPU time 32.09 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 01:58:56 PM PDT 24
Peak memory 199484 kb
Host smart-b8d08c39-b969-4ee3-9d7c-ed02758e0299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209506475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3209506475
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.132757241
Short name T369
Test name
Test status
Simulation time 92991580956 ps
CPU time 70.9 seconds
Started Mar 21 01:58:25 PM PDT 24
Finished Mar 21 01:59:36 PM PDT 24
Peak memory 200416 kb
Host smart-843adb6b-1dfc-4d70-9321-3e0cedf10967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132757241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.132757241
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2826700527
Short name T733
Test name
Test status
Simulation time 109916997999 ps
CPU time 126.22 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 02:00:30 PM PDT 24
Peak memory 200432 kb
Host smart-2380bbae-5a58-4f1e-afdf-dcdc454ffd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826700527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2826700527
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.416370236
Short name T802
Test name
Test status
Simulation time 13336915822 ps
CPU time 11.53 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 01:58:35 PM PDT 24
Peak memory 200404 kb
Host smart-73b6b8b3-02c3-41b1-ae39-9edba1c41f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416370236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.416370236
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.199206684
Short name T384
Test name
Test status
Simulation time 113988502734 ps
CPU time 17.38 seconds
Started Mar 21 01:58:26 PM PDT 24
Finished Mar 21 01:58:43 PM PDT 24
Peak memory 200392 kb
Host smart-681feae8-b23d-4901-9dc3-88d906ffc0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199206684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.199206684
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2082639828
Short name T578
Test name
Test status
Simulation time 38236049 ps
CPU time 0.55 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:54:39 PM PDT 24
Peak memory 194880 kb
Host smart-28d80a4f-22b5-4067-88cf-1f2688bf32ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082639828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2082639828
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4229870859
Short name T742
Test name
Test status
Simulation time 31689437187 ps
CPU time 52.51 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:55:42 PM PDT 24
Peak memory 200388 kb
Host smart-b0e762d1-5286-4e3b-8c07-e48c6fee2190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229870859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4229870859
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.583706924
Short name T244
Test name
Test status
Simulation time 154105302009 ps
CPU time 132.32 seconds
Started Mar 21 01:54:42 PM PDT 24
Finished Mar 21 01:56:54 PM PDT 24
Peak memory 200360 kb
Host smart-36b6057a-fd88-4a5f-a89a-ee6d2099578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583706924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.583706924
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3580223750
Short name T1010
Test name
Test status
Simulation time 7031448332 ps
CPU time 15.16 seconds
Started Mar 21 01:54:37 PM PDT 24
Finished Mar 21 01:54:52 PM PDT 24
Peak memory 200444 kb
Host smart-a9205aa6-ace5-4bc2-90a1-fae2f8154cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580223750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3580223750
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.764297191
Short name T581
Test name
Test status
Simulation time 57608675809 ps
CPU time 44.17 seconds
Started Mar 21 01:54:37 PM PDT 24
Finished Mar 21 01:55:21 PM PDT 24
Peak memory 198236 kb
Host smart-44f3e50d-3e1b-4a70-b94c-afba87903f4e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764297191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.764297191
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.116462101
Short name T881
Test name
Test status
Simulation time 63793138727 ps
CPU time 113.81 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:56:33 PM PDT 24
Peak memory 200316 kb
Host smart-67739e3b-a91b-4570-aea8-98002cd76b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116462101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.116462101
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1685392243
Short name T632
Test name
Test status
Simulation time 3379857025 ps
CPU time 5.43 seconds
Started Mar 21 01:54:37 PM PDT 24
Finished Mar 21 01:54:43 PM PDT 24
Peak memory 198860 kb
Host smart-6df0412a-9421-49e0-8815-fb11b805fa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685392243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1685392243
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2867269473
Short name T328
Test name
Test status
Simulation time 118054926010 ps
CPU time 198.92 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:57:57 PM PDT 24
Peak memory 200632 kb
Host smart-c84a4416-a5a6-42d9-a210-e1dd0960d850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867269473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2867269473
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1552082314
Short name T553
Test name
Test status
Simulation time 18218044242 ps
CPU time 1000.71 seconds
Started Mar 21 01:54:40 PM PDT 24
Finished Mar 21 02:11:21 PM PDT 24
Peak memory 200400 kb
Host smart-e67e154c-68d4-4cc7-a7b8-fd07adbb04e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552082314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1552082314
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3175560277
Short name T828
Test name
Test status
Simulation time 3259601408 ps
CPU time 28.14 seconds
Started Mar 21 01:54:41 PM PDT 24
Finished Mar 21 01:55:10 PM PDT 24
Peak memory 198756 kb
Host smart-b9f9d5ae-9064-46aa-b19f-8c0eb3ef5a34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175560277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3175560277
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3413262666
Short name T94
Test name
Test status
Simulation time 94884401733 ps
CPU time 84.97 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:56:04 PM PDT 24
Peak memory 200412 kb
Host smart-a6f8c224-0991-43ba-b3ab-835074b40cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413262666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3413262666
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.4126375917
Short name T573
Test name
Test status
Simulation time 4345444415 ps
CPU time 6.85 seconds
Started Mar 21 01:54:43 PM PDT 24
Finished Mar 21 01:54:50 PM PDT 24
Peak memory 196396 kb
Host smart-652ac9bf-9de5-4285-a04f-b6afc8a0380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126375917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4126375917
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1981229176
Short name T242
Test name
Test status
Simulation time 300861309 ps
CPU time 1.09 seconds
Started Mar 21 01:54:37 PM PDT 24
Finished Mar 21 01:54:39 PM PDT 24
Peak memory 199392 kb
Host smart-ed792d83-674c-4362-9768-1a85d6bd6905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981229176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1981229176
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2741855976
Short name T805
Test name
Test status
Simulation time 321290009310 ps
CPU time 1326.6 seconds
Started Mar 21 01:54:41 PM PDT 24
Finished Mar 21 02:16:48 PM PDT 24
Peak memory 200388 kb
Host smart-48788b8c-2df8-457c-915f-b5ed7e829b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741855976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2741855976
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.760447984
Short name T544
Test name
Test status
Simulation time 2095846329 ps
CPU time 2.01 seconds
Started Mar 21 01:54:40 PM PDT 24
Finished Mar 21 01:54:42 PM PDT 24
Peak memory 199380 kb
Host smart-23dfb64c-8240-4e9a-9201-a4dbc290db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760447984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.760447984
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3555037207
Short name T1110
Test name
Test status
Simulation time 106611305748 ps
CPU time 56.31 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:55:36 PM PDT 24
Peak memory 200348 kb
Host smart-d1769d28-6dff-45c5-949b-bcbd24e5c20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555037207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3555037207
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2655951330
Short name T223
Test name
Test status
Simulation time 98142905859 ps
CPU time 366.54 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 02:04:31 PM PDT 24
Peak memory 200388 kb
Host smart-884b4f2c-8576-42a4-a850-3d4b46ae8ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655951330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2655951330
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.4110099708
Short name T1053
Test name
Test status
Simulation time 261010629295 ps
CPU time 46.97 seconds
Started Mar 21 01:58:23 PM PDT 24
Finished Mar 21 01:59:10 PM PDT 24
Peak memory 200360 kb
Host smart-b0ba9fd2-213e-4aef-943c-791ccf30b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110099708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4110099708
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2336154329
Short name T980
Test name
Test status
Simulation time 28159263395 ps
CPU time 13.01 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 01:58:38 PM PDT 24
Peak memory 200300 kb
Host smart-b7022948-5d46-46ee-accc-be72d945daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336154329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2336154329
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2264006516
Short name T817
Test name
Test status
Simulation time 182606759770 ps
CPU time 127.01 seconds
Started Mar 21 01:58:24 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 200444 kb
Host smart-2c9aa072-a11b-401c-a868-0bd42efc9545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264006516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2264006516
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1643580429
Short name T1063
Test name
Test status
Simulation time 95899443733 ps
CPU time 104.82 seconds
Started Mar 21 01:58:23 PM PDT 24
Finished Mar 21 02:00:08 PM PDT 24
Peak memory 200404 kb
Host smart-c4e29385-5452-4658-ba15-915061172ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643580429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1643580429
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2178107555
Short name T194
Test name
Test status
Simulation time 244945721340 ps
CPU time 35.48 seconds
Started Mar 21 01:58:41 PM PDT 24
Finished Mar 21 01:59:16 PM PDT 24
Peak memory 200336 kb
Host smart-a1d04734-ff35-4c84-b137-ecaf529c5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178107555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2178107555
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3711904141
Short name T485
Test name
Test status
Simulation time 113931176524 ps
CPU time 110.51 seconds
Started Mar 21 01:58:41 PM PDT 24
Finished Mar 21 02:00:32 PM PDT 24
Peak memory 200412 kb
Host smart-8dac0c56-50ab-4c9f-ad1f-073894c1362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711904141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3711904141
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3112129760
Short name T320
Test name
Test status
Simulation time 12096299015 ps
CPU time 19.45 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:59:03 PM PDT 24
Peak memory 200448 kb
Host smart-47282648-902d-41f2-8adf-564af272b98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112129760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3112129760
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3861635588
Short name T108
Test name
Test status
Simulation time 12558699 ps
CPU time 0.55 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:52:53 PM PDT 24
Peak memory 194860 kb
Host smart-08e12edb-ae0c-481f-ad79-fcfa89e51092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861635588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3861635588
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2671057895
Short name T372
Test name
Test status
Simulation time 41324009685 ps
CPU time 68.48 seconds
Started Mar 21 01:52:48 PM PDT 24
Finished Mar 21 01:53:57 PM PDT 24
Peak memory 200428 kb
Host smart-c264c108-3549-4c9d-adaa-fba2f3e8c9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671057895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2671057895
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1794977412
Short name T410
Test name
Test status
Simulation time 166336491158 ps
CPU time 58.66 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:53:49 PM PDT 24
Peak memory 200424 kb
Host smart-392e55ce-d9d5-4dab-a8d7-e2620685d55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794977412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1794977412
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1695242303
Short name T850
Test name
Test status
Simulation time 18566474019 ps
CPU time 27.57 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:53:17 PM PDT 24
Peak memory 200328 kb
Host smart-fc5b4252-9b1e-4d39-b479-54c75abc1e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695242303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1695242303
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.820172862
Short name T93
Test name
Test status
Simulation time 269800122989 ps
CPU time 117.17 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:54:47 PM PDT 24
Peak memory 200384 kb
Host smart-3fa6934a-86ac-49fe-b7cb-470755464ea6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820172862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.820172862
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4075010774
Short name T314
Test name
Test status
Simulation time 58630487768 ps
CPU time 382.18 seconds
Started Mar 21 01:52:53 PM PDT 24
Finished Mar 21 01:59:15 PM PDT 24
Peak memory 200384 kb
Host smart-e1d151c6-1208-4ccb-ad02-d7a10edbbd5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075010774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4075010774
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1101663881
Short name T753
Test name
Test status
Simulation time 139170235 ps
CPU time 0.74 seconds
Started Mar 21 01:52:51 PM PDT 24
Finished Mar 21 01:52:51 PM PDT 24
Peak memory 196576 kb
Host smart-bfac743b-3325-4fde-ae52-a3eba957e116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101663881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1101663881
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.4059335440
Short name T250
Test name
Test status
Simulation time 280664655951 ps
CPU time 49.3 seconds
Started Mar 21 01:52:46 PM PDT 24
Finished Mar 21 01:53:35 PM PDT 24
Peak memory 216460 kb
Host smart-42af836c-f502-453b-b555-c459a7bd3e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059335440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.4059335440
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1927372460
Short name T253
Test name
Test status
Simulation time 13971788809 ps
CPU time 38.48 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:53:29 PM PDT 24
Peak memory 200268 kb
Host smart-05a511f6-bceb-4269-a8e7-a95373bd7a68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927372460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1927372460
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1669914077
Short name T984
Test name
Test status
Simulation time 3577791933 ps
CPU time 30.45 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:53:22 PM PDT 24
Peak memory 198480 kb
Host smart-a89c0b38-9d9b-449a-b41b-99d70a177223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669914077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1669914077
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2242867286
Short name T628
Test name
Test status
Simulation time 37885805636 ps
CPU time 32.42 seconds
Started Mar 21 01:52:48 PM PDT 24
Finished Mar 21 01:53:21 PM PDT 24
Peak memory 200492 kb
Host smart-a26c4895-5a25-4c35-a409-918e4e5b4fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242867286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2242867286
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.197688015
Short name T546
Test name
Test status
Simulation time 33543269307 ps
CPU time 47.51 seconds
Started Mar 21 01:52:51 PM PDT 24
Finished Mar 21 01:53:39 PM PDT 24
Peak memory 196488 kb
Host smart-c0b7e12b-a390-429a-860f-f8a94d804efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197688015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.197688015
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.4003006425
Short name T33
Test name
Test status
Simulation time 71573864 ps
CPU time 0.83 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:51 PM PDT 24
Peak memory 218392 kb
Host smart-a6ca3635-f166-4d96-bfbb-67432c5bef9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003006425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4003006425
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2615729924
Short name T524
Test name
Test status
Simulation time 716039539 ps
CPU time 1.65 seconds
Started Mar 21 01:52:54 PM PDT 24
Finished Mar 21 01:52:55 PM PDT 24
Peak memory 199256 kb
Host smart-acf592a4-12d8-42f9-9c41-8bf3b45038b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615729924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2615729924
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2594273306
Short name T949
Test name
Test status
Simulation time 345197634832 ps
CPU time 1005.88 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 02:09:36 PM PDT 24
Peak memory 200376 kb
Host smart-47a04625-621b-4935-a95b-095e3695bfc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594273306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2594273306
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.175183468
Short name T831
Test name
Test status
Simulation time 2970260378 ps
CPU time 1.51 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:51 PM PDT 24
Peak memory 199212 kb
Host smart-e2f77342-dcd5-4d08-b912-4c2088a9bc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175183468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.175183468
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.691192508
Short name T790
Test name
Test status
Simulation time 80132412200 ps
CPU time 144.9 seconds
Started Mar 21 01:52:46 PM PDT 24
Finished Mar 21 01:55:11 PM PDT 24
Peak memory 200368 kb
Host smart-ef12255b-555c-4262-834f-7047ae1bd6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691192508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.691192508
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2873937410
Short name T368
Test name
Test status
Simulation time 23565993 ps
CPU time 0.58 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:54:40 PM PDT 24
Peak memory 195892 kb
Host smart-53f7d1f4-e892-4850-aa04-bc39e1e190fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873937410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2873937410
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.4283737241
Short name T880
Test name
Test status
Simulation time 48402779443 ps
CPU time 48.01 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:55:26 PM PDT 24
Peak memory 200420 kb
Host smart-7828a6bc-9a2a-4772-a100-06d2240f7616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283737241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4283737241
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3691534004
Short name T779
Test name
Test status
Simulation time 72896771210 ps
CPU time 62.64 seconds
Started Mar 21 01:54:40 PM PDT 24
Finished Mar 21 01:55:43 PM PDT 24
Peak memory 200376 kb
Host smart-80039f4b-bf04-4657-bead-ed37acd8ed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691534004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3691534004
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3120362903
Short name T192
Test name
Test status
Simulation time 187561994237 ps
CPU time 21.96 seconds
Started Mar 21 01:54:42 PM PDT 24
Finished Mar 21 01:55:04 PM PDT 24
Peak memory 200444 kb
Host smart-b76901c2-592e-4b03-a42f-130fbd9c653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120362903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3120362903
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2583777636
Short name T427
Test name
Test status
Simulation time 20257129665 ps
CPU time 17.97 seconds
Started Mar 21 01:54:43 PM PDT 24
Finished Mar 21 01:55:01 PM PDT 24
Peak memory 198492 kb
Host smart-3480b72f-515d-4099-914f-8553fda297fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583777636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2583777636
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3637927380
Short name T344
Test name
Test status
Simulation time 76269974208 ps
CPU time 307.23 seconds
Started Mar 21 01:54:42 PM PDT 24
Finished Mar 21 01:59:50 PM PDT 24
Peak memory 200344 kb
Host smart-60f080e0-df2e-4b50-9cad-f578f2dd38e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3637927380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3637927380
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2621790339
Short name T399
Test name
Test status
Simulation time 2349927056 ps
CPU time 2.89 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:54:41 PM PDT 24
Peak memory 197848 kb
Host smart-d9a6a263-0ef2-4ef1-b88e-24d405fb7597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621790339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2621790339
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.222789517
Short name T405
Test name
Test status
Simulation time 144506730075 ps
CPU time 35.5 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:55:14 PM PDT 24
Peak memory 199028 kb
Host smart-c1517263-7505-4439-8bcf-9e2cb3955fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222789517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.222789517
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2401683531
Short name T957
Test name
Test status
Simulation time 11092967635 ps
CPU time 226.14 seconds
Started Mar 21 01:54:41 PM PDT 24
Finished Mar 21 01:58:27 PM PDT 24
Peak memory 200376 kb
Host smart-e4cc0fa3-2766-4104-b830-46d8691848d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401683531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2401683531
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3398496203
Short name T452
Test name
Test status
Simulation time 1716410224 ps
CPU time 1.99 seconds
Started Mar 21 01:54:40 PM PDT 24
Finished Mar 21 01:54:42 PM PDT 24
Peak memory 198304 kb
Host smart-124b743b-4e7e-4fad-9dda-cf8c0562574d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398496203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3398496203
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3397981006
Short name T649
Test name
Test status
Simulation time 45869557391 ps
CPU time 38.54 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:55:18 PM PDT 24
Peak memory 200412 kb
Host smart-63f2b0a6-2d39-49f9-bed1-4c0974de281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397981006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3397981006
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3293576408
Short name T947
Test name
Test status
Simulation time 3124399670 ps
CPU time 3.01 seconds
Started Mar 21 01:54:41 PM PDT 24
Finished Mar 21 01:54:44 PM PDT 24
Peak memory 196504 kb
Host smart-73071742-2de5-448a-a131-7e4d490fcebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293576408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3293576408
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2338336730
Short name T390
Test name
Test status
Simulation time 5361505411 ps
CPU time 8.16 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:54:46 PM PDT 24
Peak memory 200192 kb
Host smart-4941d582-713d-4143-926d-d6d722a4bd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338336730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2338336730
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2281482246
Short name T630
Test name
Test status
Simulation time 58968642576 ps
CPU time 120.92 seconds
Started Mar 21 01:54:40 PM PDT 24
Finished Mar 21 01:56:41 PM PDT 24
Peak memory 200424 kb
Host smart-545d1bcb-c1ca-4c9d-ac3a-ed94b547d057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281482246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2281482246
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2098825384
Short name T1
Test name
Test status
Simulation time 2060468990 ps
CPU time 1.91 seconds
Started Mar 21 01:54:39 PM PDT 24
Finished Mar 21 01:54:41 PM PDT 24
Peak memory 199080 kb
Host smart-9a2ced32-1a20-4c5e-982c-c2ea18824fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098825384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2098825384
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.621215546
Short name T1088
Test name
Test status
Simulation time 30332794686 ps
CPU time 54.01 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:55:32 PM PDT 24
Peak memory 200408 kb
Host smart-d81f8b07-4525-4ed8-b37d-1b7a7afe278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621215546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.621215546
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4038017232
Short name T166
Test name
Test status
Simulation time 65843101763 ps
CPU time 26.03 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 01:59:08 PM PDT 24
Peak memory 200448 kb
Host smart-69e14723-d863-421e-acfd-8a5bca8c1ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038017232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4038017232
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3302699420
Short name T182
Test name
Test status
Simulation time 85495751946 ps
CPU time 44.22 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:59:27 PM PDT 24
Peak memory 200428 kb
Host smart-c145d36a-0b99-4ab0-a733-7c0c0bb51d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302699420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3302699420
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.755359001
Short name T519
Test name
Test status
Simulation time 16651563252 ps
CPU time 15.51 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:58:59 PM PDT 24
Peak memory 200412 kb
Host smart-fe412d28-f4db-4acf-a69b-ee9f5763b6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755359001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.755359001
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3628875819
Short name T921
Test name
Test status
Simulation time 36409006840 ps
CPU time 44.16 seconds
Started Mar 21 01:58:45 PM PDT 24
Finished Mar 21 01:59:29 PM PDT 24
Peak memory 200352 kb
Host smart-cf9c9046-23aa-4564-83e5-fa0e8f887496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628875819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3628875819
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2335923184
Short name T299
Test name
Test status
Simulation time 151321037626 ps
CPU time 251.44 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 200388 kb
Host smart-b77d93c1-6d5a-42da-9c99-12cecc2d5cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335923184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2335923184
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2951235994
Short name T677
Test name
Test status
Simulation time 105514705113 ps
CPU time 36 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 01:59:18 PM PDT 24
Peak memory 200404 kb
Host smart-ddd02a9d-2781-4ec0-8b95-d7fbd1f8bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951235994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2951235994
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1902805773
Short name T150
Test name
Test status
Simulation time 69335278713 ps
CPU time 18.98 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 01:59:01 PM PDT 24
Peak memory 200420 kb
Host smart-886cc40f-b152-48b9-b7f1-1a6809d3f993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902805773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1902805773
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1183186467
Short name T1115
Test name
Test status
Simulation time 56127515375 ps
CPU time 314.67 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 02:03:58 PM PDT 24
Peak memory 200440 kb
Host smart-a2c8a49e-c502-4b96-b65c-260462b7b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183186467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1183186467
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1803645470
Short name T1061
Test name
Test status
Simulation time 74404402269 ps
CPU time 28.24 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 01:59:11 PM PDT 24
Peak memory 200480 kb
Host smart-bc62edbf-5e98-47af-992b-8acf013d8b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803645470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1803645470
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1304626582
Short name T982
Test name
Test status
Simulation time 88570148535 ps
CPU time 11.21 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 01:58:53 PM PDT 24
Peak memory 199776 kb
Host smart-74be0280-7c10-425b-be8c-86412d4fc937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304626582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1304626582
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2099060631
Short name T755
Test name
Test status
Simulation time 12550477 ps
CPU time 0.54 seconds
Started Mar 21 01:54:53 PM PDT 24
Finished Mar 21 01:54:53 PM PDT 24
Peak memory 194860 kb
Host smart-fb0abd50-456c-49ae-8298-d2082e4f476f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099060631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2099060631
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1927179689
Short name T887
Test name
Test status
Simulation time 189401139603 ps
CPU time 86.33 seconds
Started Mar 21 01:54:41 PM PDT 24
Finished Mar 21 01:56:07 PM PDT 24
Peak memory 200440 kb
Host smart-761bb4a6-0bbc-4849-9704-f45905d59f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927179689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1927179689
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1080787097
Short name T335
Test name
Test status
Simulation time 30542457161 ps
CPU time 15.96 seconds
Started Mar 21 01:54:38 PM PDT 24
Finished Mar 21 01:54:54 PM PDT 24
Peak memory 198416 kb
Host smart-bf253ec0-00a2-43b3-86e9-a027e79df0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080787097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1080787097
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2389593927
Short name T1108
Test name
Test status
Simulation time 96667610675 ps
CPU time 88.89 seconds
Started Mar 21 01:54:36 PM PDT 24
Finished Mar 21 01:56:05 PM PDT 24
Peak memory 200352 kb
Host smart-01470236-d797-4e4e-91fa-b3e846583172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389593927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2389593927
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.561332741
Short name T375
Test name
Test status
Simulation time 17393374161 ps
CPU time 10.25 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:55:02 PM PDT 24
Peak memory 199740 kb
Host smart-c3e71f8f-c9a8-4914-8540-ff1aad0812a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561332741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.561332741
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1772703964
Short name T816
Test name
Test status
Simulation time 50174817246 ps
CPU time 200.24 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:58:10 PM PDT 24
Peak memory 200352 kb
Host smart-cabec9a1-95cd-4833-a50d-7c4230f51250
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772703964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1772703964
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3128310509
Short name T315
Test name
Test status
Simulation time 1160173656 ps
CPU time 1.62 seconds
Started Mar 21 01:54:48 PM PDT 24
Finished Mar 21 01:54:50 PM PDT 24
Peak memory 196512 kb
Host smart-500bd0b0-456a-4eca-b821-5ba7ad12eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128310509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3128310509
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1363349292
Short name T651
Test name
Test status
Simulation time 43513045761 ps
CPU time 17.06 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:55:07 PM PDT 24
Peak memory 198536 kb
Host smart-e0437e97-3251-4b65-851a-ef5f79a5d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363349292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1363349292
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3258161168
Short name T844
Test name
Test status
Simulation time 9001411060 ps
CPU time 161.31 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:57:33 PM PDT 24
Peak memory 200464 kb
Host smart-79cf679a-c79c-4f39-8197-2d29748c47f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258161168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3258161168
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.4197956861
Short name T1037
Test name
Test status
Simulation time 3241976597 ps
CPU time 12.77 seconds
Started Mar 21 01:54:42 PM PDT 24
Finished Mar 21 01:54:55 PM PDT 24
Peak memory 198568 kb
Host smart-7435ee1f-eb15-4236-b450-0e0a823abbd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197956861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.4197956861
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1020167299
Short name T1022
Test name
Test status
Simulation time 11765294224 ps
CPU time 26.14 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:55:16 PM PDT 24
Peak memory 200460 kb
Host smart-9cac7bc6-fd2d-4c56-8b55-1111a1bf1593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020167299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1020167299
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2964212172
Short name T924
Test name
Test status
Simulation time 40464557260 ps
CPU time 61.08 seconds
Started Mar 21 01:54:54 PM PDT 24
Finished Mar 21 01:55:55 PM PDT 24
Peak memory 196480 kb
Host smart-04b26f3f-8b66-4d48-b754-f8a4974fcf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964212172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2964212172
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1771227248
Short name T261
Test name
Test status
Simulation time 11581121165 ps
CPU time 18.67 seconds
Started Mar 21 01:54:42 PM PDT 24
Finished Mar 21 01:55:00 PM PDT 24
Peak memory 200288 kb
Host smart-e8b78a19-baec-4e69-ac0d-0365621471a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771227248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1771227248
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1072588405
Short name T960
Test name
Test status
Simulation time 321452232389 ps
CPU time 186.74 seconds
Started Mar 21 01:54:48 PM PDT 24
Finished Mar 21 01:57:56 PM PDT 24
Peak memory 200448 kb
Host smart-12ba7f39-eb14-4048-99fb-ec89f50e38f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072588405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1072588405
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1331043303
Short name T275
Test name
Test status
Simulation time 7161598278 ps
CPU time 61.09 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:55:50 PM PDT 24
Peak memory 200300 kb
Host smart-fcc88a8c-368d-4897-ad83-1e4278fadb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331043303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1331043303
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2602485689
Short name T1029
Test name
Test status
Simulation time 70269661842 ps
CPU time 29.2 seconds
Started Mar 21 01:54:37 PM PDT 24
Finished Mar 21 01:55:07 PM PDT 24
Peak memory 200304 kb
Host smart-6b40fdbb-a6bc-4760-897f-a8ea90b045b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602485689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2602485689
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2964486828
Short name T302
Test name
Test status
Simulation time 150347997163 ps
CPU time 36.85 seconds
Started Mar 21 01:58:41 PM PDT 24
Finished Mar 21 01:59:18 PM PDT 24
Peak memory 200232 kb
Host smart-44314166-cd46-4215-8b2d-51a9db2a1656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964486828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2964486828
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.606703270
Short name T1017
Test name
Test status
Simulation time 15118309426 ps
CPU time 26.93 seconds
Started Mar 21 01:58:45 PM PDT 24
Finished Mar 21 01:59:12 PM PDT 24
Peak memory 200464 kb
Host smart-233d5cf3-fc52-4964-8787-8ed74488159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606703270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.606703270
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3389846464
Short name T164
Test name
Test status
Simulation time 73267706310 ps
CPU time 156.6 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 02:01:20 PM PDT 24
Peak memory 200156 kb
Host smart-d9de31bc-2137-477a-abfa-4196d7dc2c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389846464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3389846464
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1316186862
Short name T465
Test name
Test status
Simulation time 52055466767 ps
CPU time 28.97 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 01:59:11 PM PDT 24
Peak memory 200320 kb
Host smart-0b97a8a8-aca0-4b6e-88ff-afd9b9b95be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316186862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1316186862
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.505437011
Short name T927
Test name
Test status
Simulation time 23896770009 ps
CPU time 39.68 seconds
Started Mar 21 01:58:45 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 200444 kb
Host smart-68ba7491-07c6-4feb-a38b-b91966ee0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505437011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.505437011
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2214237550
Short name T128
Test name
Test status
Simulation time 90424397528 ps
CPU time 232.55 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 200388 kb
Host smart-522b73c5-0c78-437d-b3cd-3233cdd2f606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214237550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2214237550
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2118092114
Short name T184
Test name
Test status
Simulation time 31602113798 ps
CPU time 22.36 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:59:05 PM PDT 24
Peak memory 199384 kb
Host smart-d60a46e0-62ad-455e-9dae-4cf703957bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118092114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2118092114
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.982847770
Short name T730
Test name
Test status
Simulation time 23466418179 ps
CPU time 35.3 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 01:59:17 PM PDT 24
Peak memory 200396 kb
Host smart-31b471ef-5bbc-4853-bb81-a3148b74ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982847770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.982847770
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3369229295
Short name T726
Test name
Test status
Simulation time 100780212317 ps
CPU time 183.61 seconds
Started Mar 21 01:58:44 PM PDT 24
Finished Mar 21 02:01:48 PM PDT 24
Peak memory 200404 kb
Host smart-797e89e4-c348-4cce-b313-874f3b7cd60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369229295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3369229295
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2355269232
Short name T580
Test name
Test status
Simulation time 28945170575 ps
CPU time 46.16 seconds
Started Mar 21 01:58:41 PM PDT 24
Finished Mar 21 01:59:28 PM PDT 24
Peak memory 200412 kb
Host smart-32c56701-ab8d-456e-97b6-b912728022d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355269232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2355269232
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1771014522
Short name T345
Test name
Test status
Simulation time 63142043 ps
CPU time 0.54 seconds
Started Mar 21 01:54:54 PM PDT 24
Finished Mar 21 01:54:55 PM PDT 24
Peak memory 195852 kb
Host smart-3b0e0f50-e584-41bd-b128-f2b11ac77ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771014522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1771014522
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2909530676
Short name T788
Test name
Test status
Simulation time 79302692778 ps
CPU time 62.8 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:55:54 PM PDT 24
Peak memory 200356 kb
Host smart-76178700-4882-4cda-a8d2-504242974c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909530676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2909530676
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3718624016
Short name T50
Test name
Test status
Simulation time 123799475362 ps
CPU time 45.28 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:55:37 PM PDT 24
Peak memory 200376 kb
Host smart-188a9a6b-1dd5-4a45-bd4e-f848277b90ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718624016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3718624016
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2666182153
Short name T764
Test name
Test status
Simulation time 29720472405 ps
CPU time 14.61 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:55:06 PM PDT 24
Peak memory 199868 kb
Host smart-52bf2493-2e3a-43bc-8b27-edf5e6bd1bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666182153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2666182153
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1462740167
Short name T774
Test name
Test status
Simulation time 40227121045 ps
CPU time 26.77 seconds
Started Mar 21 01:54:48 PM PDT 24
Finished Mar 21 01:55:16 PM PDT 24
Peak memory 200392 kb
Host smart-ce5c659c-984c-4e0f-a17b-19ede484e892
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462740167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1462740167
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1736982799
Short name T342
Test name
Test status
Simulation time 171590852918 ps
CPU time 223.47 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:58:33 PM PDT 24
Peak memory 200400 kb
Host smart-721eefd8-46e9-4313-aae3-014cb2bd8a85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736982799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1736982799
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1340831302
Short name T499
Test name
Test status
Simulation time 6356978375 ps
CPU time 7.87 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:54:57 PM PDT 24
Peak memory 199392 kb
Host smart-73bcbd0a-ca12-42b7-9849-3c20b6772294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340831302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1340831302
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2820606005
Short name T350
Test name
Test status
Simulation time 22281285362 ps
CPU time 36.99 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:55:29 PM PDT 24
Peak memory 199244 kb
Host smart-55f10260-c5f3-4cc1-b48c-75a046012a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820606005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2820606005
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2865153590
Short name T972
Test name
Test status
Simulation time 11037519459 ps
CPU time 637.8 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 02:05:28 PM PDT 24
Peak memory 200352 kb
Host smart-2f1bbe55-7aab-4309-aa02-847a2ffc4185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865153590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2865153590
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.4176502798
Short name T480
Test name
Test status
Simulation time 4193402874 ps
CPU time 3.67 seconds
Started Mar 21 01:54:54 PM PDT 24
Finished Mar 21 01:54:58 PM PDT 24
Peak memory 198580 kb
Host smart-3cf0ffd2-b1b6-4d16-af7b-c7456b01efa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176502798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4176502798
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2907754399
Short name T56
Test name
Test status
Simulation time 135322731004 ps
CPU time 369.05 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 200388 kb
Host smart-2be63ec6-dc53-4197-be02-d78fa19e6322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907754399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2907754399
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.998380284
Short name T857
Test name
Test status
Simulation time 3249850113 ps
CPU time 5.81 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:54:56 PM PDT 24
Peak memory 196488 kb
Host smart-f2238ffd-53d5-4cb0-a212-ecc771cf3e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998380284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.998380284
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3574982702
Short name T701
Test name
Test status
Simulation time 448430332 ps
CPU time 1.77 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:54:52 PM PDT 24
Peak memory 199064 kb
Host smart-d1e33e60-28d4-44f3-a7d3-a30dc9420ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574982702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3574982702
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4206414498
Short name T849
Test name
Test status
Simulation time 55608032071 ps
CPU time 832.28 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 02:08:42 PM PDT 24
Peak memory 200440 kb
Host smart-6f44181e-ce9e-4b55-a49e-0c8fac6c647b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206414498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4206414498
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4114293505
Short name T751
Test name
Test status
Simulation time 1748733186 ps
CPU time 2.17 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:54:53 PM PDT 24
Peak memory 199204 kb
Host smart-a8952ad2-b0d8-4767-9c1d-872cc09d6b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114293505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4114293505
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1812388646
Short name T1013
Test name
Test status
Simulation time 172493639005 ps
CPU time 67.46 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:55:58 PM PDT 24
Peak memory 200196 kb
Host smart-fc5649c7-48e3-4201-8ffe-c7eade5d46b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812388646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1812388646
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1194575618
Short name T209
Test name
Test status
Simulation time 8298107539 ps
CPU time 14.41 seconds
Started Mar 21 01:58:44 PM PDT 24
Finished Mar 21 01:58:58 PM PDT 24
Peak memory 200392 kb
Host smart-1dcafab8-3371-4f83-91db-56df8712d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194575618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1194575618
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1340727391
Short name T646
Test name
Test status
Simulation time 76154958292 ps
CPU time 15.18 seconds
Started Mar 21 01:58:44 PM PDT 24
Finished Mar 21 01:58:59 PM PDT 24
Peak memory 200356 kb
Host smart-e856bf68-855d-46cc-83fd-b3c655a11e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340727391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1340727391
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1545373804
Short name T595
Test name
Test status
Simulation time 51563598591 ps
CPU time 17.18 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:59:00 PM PDT 24
Peak memory 200428 kb
Host smart-79e4f801-afb4-4236-8bb1-cae53a2de90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545373804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1545373804
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.818537329
Short name T45
Test name
Test status
Simulation time 18946433324 ps
CPU time 31.92 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:59:15 PM PDT 24
Peak memory 199904 kb
Host smart-ff096a19-65d0-4c9f-910c-85733d35bdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818537329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.818537329
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.369766311
Short name T714
Test name
Test status
Simulation time 20718684727 ps
CPU time 35.44 seconds
Started Mar 21 01:58:41 PM PDT 24
Finished Mar 21 01:59:17 PM PDT 24
Peak memory 200336 kb
Host smart-879842aa-637a-49f3-afd2-1a8d7c6849e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369766311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.369766311
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1160434309
Short name T824
Test name
Test status
Simulation time 118001952468 ps
CPU time 175.64 seconds
Started Mar 21 01:58:44 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 200436 kb
Host smart-480971f0-5118-4807-abd7-a2dbd3772e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160434309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1160434309
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1427729741
Short name T1095
Test name
Test status
Simulation time 106545908346 ps
CPU time 15.47 seconds
Started Mar 21 01:58:44 PM PDT 24
Finished Mar 21 01:58:59 PM PDT 24
Peak memory 200400 kb
Host smart-8332705f-9177-4160-8ebb-97c69ff8cbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427729741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1427729741
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3021409845
Short name T583
Test name
Test status
Simulation time 161433317684 ps
CPU time 70.92 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 199932 kb
Host smart-0ff067d8-5a44-4aaa-84a6-a0fe9c0d3eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021409845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3021409845
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.694687984
Short name T180
Test name
Test status
Simulation time 158125747505 ps
CPU time 280.57 seconds
Started Mar 21 01:58:42 PM PDT 24
Finished Mar 21 02:03:23 PM PDT 24
Peak memory 200296 kb
Host smart-0ab3b706-f748-4b18-b3e3-7911ea1ac947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694687984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.694687984
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2472060148
Short name T339
Test name
Test status
Simulation time 26690852 ps
CPU time 0.55 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:54:52 PM PDT 24
Peak memory 195900 kb
Host smart-171786c3-cc78-4e99-85ce-3dd1939834b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472060148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2472060148
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3028124286
Short name T561
Test name
Test status
Simulation time 62129851162 ps
CPU time 70.5 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:56:02 PM PDT 24
Peak memory 200328 kb
Host smart-704b673c-ad68-4957-b00f-fa03351db6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028124286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3028124286
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.825984068
Short name T173
Test name
Test status
Simulation time 73765581690 ps
CPU time 29.67 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:55:19 PM PDT 24
Peak memory 200344 kb
Host smart-0ebab1cc-32d3-40dd-a4a4-4339d25eb814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825984068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.825984068
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2680557065
Short name T640
Test name
Test status
Simulation time 65030168905 ps
CPU time 149.07 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:57:19 PM PDT 24
Peak memory 200316 kb
Host smart-cc934a53-16c7-4fa8-9eb2-5889ed0ab83e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680557065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2680557065
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2294868838
Short name T853
Test name
Test status
Simulation time 102885088693 ps
CPU time 371.39 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 02:01:02 PM PDT 24
Peak memory 200432 kb
Host smart-1534dc86-c886-4ad5-8376-7ce6a822eb25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294868838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2294868838
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1167127825
Short name T1090
Test name
Test status
Simulation time 10668726474 ps
CPU time 4.43 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:54:54 PM PDT 24
Peak memory 199060 kb
Host smart-b35c03f5-23a1-4b22-a1d4-232e62121d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167127825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1167127825
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3245653804
Short name T292
Test name
Test status
Simulation time 64457582600 ps
CPU time 48.4 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:55:38 PM PDT 24
Peak memory 200704 kb
Host smart-0a641eb6-a795-41a4-9a82-29a2c5fa71ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245653804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3245653804
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2583686476
Short name T601
Test name
Test status
Simulation time 12111421149 ps
CPU time 190.48 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:58:01 PM PDT 24
Peak memory 200388 kb
Host smart-ac736ef2-7bb1-46cb-87bc-6553b64d8aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583686476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2583686476
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1188037419
Short name T758
Test name
Test status
Simulation time 1932359903 ps
CPU time 3.2 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:54:53 PM PDT 24
Peak memory 198700 kb
Host smart-1b941dad-de2e-4360-9a6e-9554490bbb12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188037419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1188037419
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.4237992289
Short name T362
Test name
Test status
Simulation time 31342609300 ps
CPU time 62.81 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:55:53 PM PDT 24
Peak memory 200408 kb
Host smart-411340a3-5411-40cb-8655-a140ad4726f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237992289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.4237992289
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2480050921
Short name T978
Test name
Test status
Simulation time 4475788195 ps
CPU time 2.49 seconds
Started Mar 21 01:54:54 PM PDT 24
Finished Mar 21 01:54:57 PM PDT 24
Peak memory 196504 kb
Host smart-14c93f0a-37d0-47a9-b41d-54f060ce50e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480050921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2480050921
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3637839849
Short name T659
Test name
Test status
Simulation time 6113167164 ps
CPU time 6.25 seconds
Started Mar 21 01:54:53 PM PDT 24
Finished Mar 21 01:54:59 PM PDT 24
Peak memory 199900 kb
Host smart-811c003e-1166-4f42-b261-7d74f28c9ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637839849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3637839849
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1654786614
Short name T117
Test name
Test status
Simulation time 390744664184 ps
CPU time 182.31 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:57:52 PM PDT 24
Peak memory 208960 kb
Host smart-d34c9dd3-e713-4580-bb93-cccf83f8d979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654786614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1654786614
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2947258856
Short name T502
Test name
Test status
Simulation time 5958484391 ps
CPU time 35.97 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:55:28 PM PDT 24
Peak memory 200296 kb
Host smart-24b0f737-59c1-4f02-b2e7-40488fdfea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947258856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2947258856
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.367027441
Short name T923
Test name
Test status
Simulation time 36310921329 ps
CPU time 152.2 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:57:22 PM PDT 24
Peak memory 200352 kb
Host smart-ee455db7-2efc-44fd-945e-765a1bc9454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367027441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.367027441
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.203461534
Short name T566
Test name
Test status
Simulation time 273439399771 ps
CPU time 118.33 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 02:00:41 PM PDT 24
Peak memory 200396 kb
Host smart-8c2a026f-f4ce-44b1-8774-12dc3951c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203461534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.203461534
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3460472745
Short name T199
Test name
Test status
Simulation time 32639367396 ps
CPU time 42.7 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:59:26 PM PDT 24
Peak memory 200380 kb
Host smart-52a4066c-a88f-4909-bbec-ab9ec3673e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460472745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3460472745
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3737366224
Short name T216
Test name
Test status
Simulation time 19929433868 ps
CPU time 9.28 seconds
Started Mar 21 01:58:45 PM PDT 24
Finished Mar 21 01:58:55 PM PDT 24
Peak memory 200440 kb
Host smart-021d86a1-59a4-4ab9-abec-cb6d483f0523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737366224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3737366224
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2402673704
Short name T658
Test name
Test status
Simulation time 87996433258 ps
CPU time 35.9 seconds
Started Mar 21 01:58:43 PM PDT 24
Finished Mar 21 01:59:19 PM PDT 24
Peak memory 200388 kb
Host smart-e13188da-605c-418f-b0f5-0eba42b28a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402673704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2402673704
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.191571000
Short name T122
Test name
Test status
Simulation time 63408571109 ps
CPU time 8.38 seconds
Started Mar 21 01:58:55 PM PDT 24
Finished Mar 21 01:59:03 PM PDT 24
Peak memory 200384 kb
Host smart-b93e4195-aaf0-4821-907e-e141d75a54c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191571000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.191571000
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3754647602
Short name T158
Test name
Test status
Simulation time 73681732348 ps
CPU time 43.66 seconds
Started Mar 21 01:58:55 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 200508 kb
Host smart-3284ca6d-3bd9-407f-a9a4-d6d5bdc23df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754647602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3754647602
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3789932506
Short name T967
Test name
Test status
Simulation time 77663697254 ps
CPU time 105.86 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 02:00:42 PM PDT 24
Peak memory 200428 kb
Host smart-de07f0df-33a5-4f8c-9e73-0056c2ed4243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789932506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3789932506
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4147067456
Short name T668
Test name
Test status
Simulation time 11537877 ps
CPU time 0.59 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:54:51 PM PDT 24
Peak memory 195876 kb
Host smart-0c8ee990-f9c8-458e-a371-3cab139cc1b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147067456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4147067456
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2345334600
Short name T177
Test name
Test status
Simulation time 315059967576 ps
CPU time 35.25 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:55:27 PM PDT 24
Peak memory 200396 kb
Host smart-cd3acbb4-14d7-4f3e-98ce-eb18b654cc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345334600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2345334600
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3487589658
Short name T641
Test name
Test status
Simulation time 25026677041 ps
CPU time 41.42 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:55:33 PM PDT 24
Peak memory 200368 kb
Host smart-61152c01-21b7-43a9-81ab-5be979d20224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487589658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3487589658
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1229229207
Short name T208
Test name
Test status
Simulation time 6510743559 ps
CPU time 14.52 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:55:07 PM PDT 24
Peak memory 200384 kb
Host smart-7314c3fb-5298-4c9f-9cc2-001ec253ac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229229207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1229229207
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3257918530
Short name T951
Test name
Test status
Simulation time 39868232778 ps
CPU time 29.15 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:55:21 PM PDT 24
Peak memory 200392 kb
Host smart-86d9509d-4330-4bcf-ac4b-ec8c39423b28
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257918530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3257918530
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4230462568
Short name T361
Test name
Test status
Simulation time 171817587661 ps
CPU time 642.23 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 02:05:33 PM PDT 24
Peak memory 200432 kb
Host smart-f0581c8d-a6be-479a-a743-fcd6e86d4014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4230462568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4230462568
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3111017260
Short name T385
Test name
Test status
Simulation time 3317260220 ps
CPU time 2.34 seconds
Started Mar 21 01:54:56 PM PDT 24
Finished Mar 21 01:54:58 PM PDT 24
Peak memory 198912 kb
Host smart-c63b6c71-66dc-41b1-a9f7-b6c37a15790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111017260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3111017260
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2642591870
Short name T511
Test name
Test status
Simulation time 201211146936 ps
CPU time 110.64 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:56:42 PM PDT 24
Peak memory 199484 kb
Host smart-1cd6b664-5f16-456d-9abd-60dfddc05b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642591870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2642591870
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.278026965
Short name T998
Test name
Test status
Simulation time 7154055135 ps
CPU time 100.26 seconds
Started Mar 21 01:54:55 PM PDT 24
Finished Mar 21 01:56:35 PM PDT 24
Peak memory 200400 kb
Host smart-6ad7ac9a-e2b8-4330-bad1-dbfdf1bafd15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278026965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.278026965
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.198662454
Short name T432
Test name
Test status
Simulation time 2535033012 ps
CPU time 4.62 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:54:55 PM PDT 24
Peak memory 199488 kb
Host smart-544c807e-89ce-4be8-8629-2dc6784ee20a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198662454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.198662454
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2079445455
Short name T348
Test name
Test status
Simulation time 106052711522 ps
CPU time 58.53 seconds
Started Mar 21 01:54:53 PM PDT 24
Finished Mar 21 01:55:51 PM PDT 24
Peak memory 200372 kb
Host smart-e37fcdb7-e9fa-487e-bfcd-17b7241fbb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079445455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2079445455
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1573724913
Short name T81
Test name
Test status
Simulation time 5566422691 ps
CPU time 2.43 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:54:53 PM PDT 24
Peak memory 196500 kb
Host smart-2ccd9d65-6efa-4dd2-b674-eaf62ed7f76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573724913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1573724913
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.458914843
Short name T574
Test name
Test status
Simulation time 972974097 ps
CPU time 1.52 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:54:54 PM PDT 24
Peak memory 198708 kb
Host smart-7d9c0885-0d30-4117-98b4-fb56e3a6c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458914843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.458914843
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3930239106
Short name T990
Test name
Test status
Simulation time 187531421042 ps
CPU time 227.39 seconds
Started Mar 21 01:54:54 PM PDT 24
Finished Mar 21 01:58:42 PM PDT 24
Peak memory 200396 kb
Host smart-575bc385-582d-40e4-b757-fce6064abd86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930239106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3930239106
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2911365240
Short name T1080
Test name
Test status
Simulation time 974221195 ps
CPU time 1.39 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 01:54:53 PM PDT 24
Peak memory 200164 kb
Host smart-80bebc1a-efe8-462f-b1d9-efa20c5c97c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911365240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2911365240
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1664434878
Short name T1025
Test name
Test status
Simulation time 78187449893 ps
CPU time 95.16 seconds
Started Mar 21 01:54:49 PM PDT 24
Finished Mar 21 01:56:25 PM PDT 24
Peak memory 200372 kb
Host smart-bfa4fa0e-b30f-4d4c-a016-af68312cfdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664434878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1664434878
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.802311513
Short name T238
Test name
Test status
Simulation time 80418075936 ps
CPU time 25.02 seconds
Started Mar 21 01:59:01 PM PDT 24
Finished Mar 21 01:59:26 PM PDT 24
Peak memory 200408 kb
Host smart-be0c30ef-05f2-4cc7-b099-d47f9505e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802311513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.802311513
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.4289666062
Short name T836
Test name
Test status
Simulation time 25816078780 ps
CPU time 41.87 seconds
Started Mar 21 01:58:57 PM PDT 24
Finished Mar 21 01:59:39 PM PDT 24
Peak memory 200332 kb
Host smart-90e28fa1-7d35-48e3-9950-088c75e5129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289666062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4289666062
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1180511455
Short name T864
Test name
Test status
Simulation time 96737857478 ps
CPU time 43.24 seconds
Started Mar 21 01:58:54 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 200440 kb
Host smart-651d4d74-726f-488b-ac07-0310acae44a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180511455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1180511455
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2122797185
Short name T727
Test name
Test status
Simulation time 23287663848 ps
CPU time 32.66 seconds
Started Mar 21 01:58:58 PM PDT 24
Finished Mar 21 01:59:31 PM PDT 24
Peak memory 200432 kb
Host smart-696c9f60-4f9b-4bfb-86c3-16003dd5077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122797185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2122797185
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1917731842
Short name T454
Test name
Test status
Simulation time 56634602579 ps
CPU time 99.92 seconds
Started Mar 21 01:58:55 PM PDT 24
Finished Mar 21 02:00:35 PM PDT 24
Peak memory 200448 kb
Host smart-1694ecb0-bbb6-4a3b-8b06-26be1393b31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917731842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1917731842
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1607330973
Short name T662
Test name
Test status
Simulation time 48300227922 ps
CPU time 24.93 seconds
Started Mar 21 01:59:01 PM PDT 24
Finished Mar 21 01:59:26 PM PDT 24
Peak memory 200348 kb
Host smart-90892f22-bd6b-43c6-b768-bfc243c0fd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607330973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1607330973
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1086200678
Short name T140
Test name
Test status
Simulation time 36868424133 ps
CPU time 41.75 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 200460 kb
Host smart-8e923304-ad9c-4c4a-9591-d255bbedbec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086200678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1086200678
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2463039983
Short name T1065
Test name
Test status
Simulation time 38399777141 ps
CPU time 57.66 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 01:59:53 PM PDT 24
Peak memory 200472 kb
Host smart-4c1b712c-45ef-4e25-96cf-05f344008d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463039983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2463039983
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1074046088
Short name T624
Test name
Test status
Simulation time 67215519953 ps
CPU time 27.39 seconds
Started Mar 21 01:58:57 PM PDT 24
Finished Mar 21 01:59:25 PM PDT 24
Peak memory 200372 kb
Host smart-ee237312-1cdb-4533-bdc2-a9ba38b721c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074046088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1074046088
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.995032510
Short name T913
Test name
Test status
Simulation time 15929503 ps
CPU time 0.59 seconds
Started Mar 21 01:55:04 PM PDT 24
Finished Mar 21 01:55:05 PM PDT 24
Peak memory 195892 kb
Host smart-827a821e-36d5-43df-9527-285320b23642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995032510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.995032510
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1011492476
Short name T608
Test name
Test status
Simulation time 195211069997 ps
CPU time 145.93 seconds
Started Mar 21 01:54:52 PM PDT 24
Finished Mar 21 01:57:18 PM PDT 24
Peak memory 200332 kb
Host smart-00608d25-0b7a-46c3-aaaf-c3a5be304e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011492476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1011492476
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1833250428
Short name T481
Test name
Test status
Simulation time 229430695992 ps
CPU time 404.32 seconds
Started Mar 21 01:54:51 PM PDT 24
Finished Mar 21 02:01:36 PM PDT 24
Peak memory 200396 kb
Host smart-9594cb9d-a416-44ad-9a9c-6b3855ff0d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833250428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1833250428
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2398359461
Short name T676
Test name
Test status
Simulation time 143149239856 ps
CPU time 261.97 seconds
Started Mar 21 01:55:01 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 200380 kb
Host smart-719a0f8f-9f82-467f-b78d-f56606497427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398359461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2398359461
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2372471532
Short name T430
Test name
Test status
Simulation time 15940345583 ps
CPU time 9.99 seconds
Started Mar 21 01:55:04 PM PDT 24
Finished Mar 21 01:55:15 PM PDT 24
Peak memory 198672 kb
Host smart-a7e9579a-4456-4e06-95f2-30c39cc779aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372471532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2372471532
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.4007296387
Short name T940
Test name
Test status
Simulation time 90277969680 ps
CPU time 78.43 seconds
Started Mar 21 01:54:59 PM PDT 24
Finished Mar 21 01:56:19 PM PDT 24
Peak memory 200396 kb
Host smart-e4df7b3f-2e3d-4e2a-abe2-54752c7c66c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4007296387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4007296387
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3928330345
Short name T551
Test name
Test status
Simulation time 2869954419 ps
CPU time 6.85 seconds
Started Mar 21 01:54:58 PM PDT 24
Finished Mar 21 01:55:06 PM PDT 24
Peak memory 198932 kb
Host smart-be774228-a27f-4c92-953f-d2e0b93fc62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928330345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3928330345
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1230187695
Short name T902
Test name
Test status
Simulation time 57334045117 ps
CPU time 38.11 seconds
Started Mar 21 01:55:00 PM PDT 24
Finished Mar 21 01:55:39 PM PDT 24
Peak memory 208824 kb
Host smart-0b0283c5-882e-4d7a-afc1-02671a537b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230187695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1230187695
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1970241726
Short name T773
Test name
Test status
Simulation time 19301497918 ps
CPU time 1165.64 seconds
Started Mar 21 01:55:03 PM PDT 24
Finished Mar 21 02:14:30 PM PDT 24
Peak memory 200376 kb
Host smart-75e761d8-32b5-4601-bf46-22608e27f7c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970241726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1970241726
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.381274184
Short name T466
Test name
Test status
Simulation time 2943842701 ps
CPU time 22.76 seconds
Started Mar 21 01:55:00 PM PDT 24
Finished Mar 21 01:55:23 PM PDT 24
Peak memory 199320 kb
Host smart-37e285fc-aed5-4992-a58e-2b86e1ed5274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381274184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.381274184
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1790667350
Short name T851
Test name
Test status
Simulation time 97855516394 ps
CPU time 78.84 seconds
Started Mar 21 01:55:02 PM PDT 24
Finished Mar 21 01:56:22 PM PDT 24
Peak memory 200420 kb
Host smart-836ec30b-932c-4c10-a139-5ec9fd53111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790667350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1790667350
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1001628435
Short name T259
Test name
Test status
Simulation time 3347579379 ps
CPU time 1.65 seconds
Started Mar 21 01:55:01 PM PDT 24
Finished Mar 21 01:55:03 PM PDT 24
Peak memory 196716 kb
Host smart-14a5af3f-cbd1-4e6d-9d1a-bad63f98d6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001628435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1001628435
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1201013269
Short name T23
Test name
Test status
Simulation time 873542696 ps
CPU time 1.66 seconds
Started Mar 21 01:54:55 PM PDT 24
Finished Mar 21 01:54:57 PM PDT 24
Peak memory 198764 kb
Host smart-a293f48d-619d-4921-aa23-d288ccb4ec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201013269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1201013269
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1482471164
Short name T1106
Test name
Test status
Simulation time 222318617094 ps
CPU time 150.99 seconds
Started Mar 21 01:54:59 PM PDT 24
Finished Mar 21 01:57:30 PM PDT 24
Peak memory 208772 kb
Host smart-e787235e-2018-42ae-b25d-5e21692d3f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482471164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1482471164
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2878351841
Short name T948
Test name
Test status
Simulation time 864864227 ps
CPU time 3.12 seconds
Started Mar 21 01:55:01 PM PDT 24
Finished Mar 21 01:55:05 PM PDT 24
Peak memory 199100 kb
Host smart-25561a79-3da2-4f12-93a6-cebac2df9101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878351841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2878351841
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3901135887
Short name T866
Test name
Test status
Simulation time 97336005101 ps
CPU time 110.34 seconds
Started Mar 21 01:54:50 PM PDT 24
Finished Mar 21 01:56:41 PM PDT 24
Peak memory 200444 kb
Host smart-9c1b8e1f-970a-4c65-9a49-9b1a0e1e7943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901135887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3901135887
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3795105289
Short name T1046
Test name
Test status
Simulation time 87338442804 ps
CPU time 28.11 seconds
Started Mar 21 01:58:57 PM PDT 24
Finished Mar 21 01:59:25 PM PDT 24
Peak memory 200184 kb
Host smart-99060bd4-b833-406e-a55a-699b41fde797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795105289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3795105289
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2255471878
Short name T645
Test name
Test status
Simulation time 96418358100 ps
CPU time 56.09 seconds
Started Mar 21 01:59:01 PM PDT 24
Finished Mar 21 01:59:57 PM PDT 24
Peak memory 200404 kb
Host smart-40be5a97-1e2a-4e2b-931f-ea8dffcfc5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255471878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2255471878
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1436911962
Short name T234
Test name
Test status
Simulation time 60295217278 ps
CPU time 112.99 seconds
Started Mar 21 01:58:58 PM PDT 24
Finished Mar 21 02:00:51 PM PDT 24
Peak memory 200372 kb
Host smart-8e1218ab-a41d-4e32-86e5-7c922d69c5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436911962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1436911962
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1798428876
Short name T1062
Test name
Test status
Simulation time 206375138083 ps
CPU time 79.92 seconds
Started Mar 21 01:58:55 PM PDT 24
Finished Mar 21 02:00:15 PM PDT 24
Peak memory 200448 kb
Host smart-c05f486d-7cfb-45ce-b0ce-4d7ea6d4a16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798428876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1798428876
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.4225935645
Short name T997
Test name
Test status
Simulation time 30099210359 ps
CPU time 17.38 seconds
Started Mar 21 01:58:53 PM PDT 24
Finished Mar 21 01:59:11 PM PDT 24
Peak memory 200420 kb
Host smart-ef435acb-fab1-4550-9568-7c7c56428189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225935645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.4225935645
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2744503214
Short name T888
Test name
Test status
Simulation time 40880961923 ps
CPU time 17.17 seconds
Started Mar 21 01:58:58 PM PDT 24
Finished Mar 21 01:59:15 PM PDT 24
Peak memory 200392 kb
Host smart-08814853-cc29-47fe-a93d-5588a9fa019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744503214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2744503214
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3890364626
Short name T230
Test name
Test status
Simulation time 17503012005 ps
CPU time 32.53 seconds
Started Mar 21 01:58:55 PM PDT 24
Finished Mar 21 01:59:28 PM PDT 24
Peak memory 200460 kb
Host smart-f877a862-22a5-4de4-bc5e-5aa974a0703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890364626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3890364626
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2591830409
Short name T1019
Test name
Test status
Simulation time 14833531600 ps
CPU time 24.51 seconds
Started Mar 21 01:58:57 PM PDT 24
Finished Mar 21 01:59:22 PM PDT 24
Peak memory 200296 kb
Host smart-b9d0d805-b976-4884-9524-04edb1a1dc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591830409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2591830409
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2606048710
Short name T357
Test name
Test status
Simulation time 44167575 ps
CPU time 0.56 seconds
Started Mar 21 01:55:04 PM PDT 24
Finished Mar 21 01:55:05 PM PDT 24
Peak memory 195892 kb
Host smart-2b4e06f5-f70a-41c7-9d5b-87f6c71e88ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606048710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2606048710
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3063494193
Short name T623
Test name
Test status
Simulation time 30692992103 ps
CPU time 27.12 seconds
Started Mar 21 01:55:00 PM PDT 24
Finished Mar 21 01:55:28 PM PDT 24
Peak memory 200376 kb
Host smart-6a62613f-9cf5-47f2-a421-fe495eac7a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063494193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3063494193
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2750507826
Short name T1030
Test name
Test status
Simulation time 34670966345 ps
CPU time 45.06 seconds
Started Mar 21 01:55:04 PM PDT 24
Finished Mar 21 01:55:50 PM PDT 24
Peak memory 200392 kb
Host smart-55fb6236-8ca8-4f7f-87cf-353a0b34bb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750507826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2750507826
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3595069778
Short name T231
Test name
Test status
Simulation time 35523051061 ps
CPU time 31.58 seconds
Started Mar 21 01:55:02 PM PDT 24
Finished Mar 21 01:55:35 PM PDT 24
Peak memory 200436 kb
Host smart-9e7f2f79-7ae5-45fd-a20c-3e1d460330a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595069778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3595069778
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2819061923
Short name T24
Test name
Test status
Simulation time 206481282186 ps
CPU time 306.23 seconds
Started Mar 21 01:55:03 PM PDT 24
Finished Mar 21 02:00:10 PM PDT 24
Peak memory 197568 kb
Host smart-ed3aefc7-6b5c-4803-be41-f3c2e160b621
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819061923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2819061923
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1602628374
Short name T353
Test name
Test status
Simulation time 80828281939 ps
CPU time 279.82 seconds
Started Mar 21 01:55:02 PM PDT 24
Finished Mar 21 01:59:43 PM PDT 24
Peak memory 200364 kb
Host smart-c7330fef-6333-452d-98ce-27d4cd9f2ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1602628374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1602628374
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.220193324
Short name T443
Test name
Test status
Simulation time 1714777051 ps
CPU time 3.64 seconds
Started Mar 21 01:55:01 PM PDT 24
Finished Mar 21 01:55:06 PM PDT 24
Peak memory 196584 kb
Host smart-dc25d935-af84-473a-aa8c-0d2406193b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220193324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.220193324
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1541970019
Short name T660
Test name
Test status
Simulation time 90881440201 ps
CPU time 277.75 seconds
Started Mar 21 01:55:00 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 208596 kb
Host smart-32358630-4c9b-49b9-bb2f-3c32e116ebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541970019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1541970019
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1872749290
Short name T929
Test name
Test status
Simulation time 9587708761 ps
CPU time 115.91 seconds
Started Mar 21 01:55:02 PM PDT 24
Finished Mar 21 01:56:59 PM PDT 24
Peak memory 200340 kb
Host smart-ac1b625a-0ac5-4f1f-b209-ec63015801f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872749290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1872749290
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2732424261
Short name T7
Test name
Test status
Simulation time 4474998830 ps
CPU time 31.12 seconds
Started Mar 21 01:54:59 PM PDT 24
Finished Mar 21 01:55:32 PM PDT 24
Peak memory 198552 kb
Host smart-140dc733-9e9b-4dea-a475-da1182513083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2732424261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2732424261
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1933253315
Short name T958
Test name
Test status
Simulation time 156141762692 ps
CPU time 47.25 seconds
Started Mar 21 01:55:02 PM PDT 24
Finished Mar 21 01:55:51 PM PDT 24
Peak memory 200468 kb
Host smart-c70f0396-d24c-454b-ad4b-b79da14d573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933253315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1933253315
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2557012034
Short name T839
Test name
Test status
Simulation time 4862738461 ps
CPU time 2.79 seconds
Started Mar 21 01:54:59 PM PDT 24
Finished Mar 21 01:55:02 PM PDT 24
Peak memory 196532 kb
Host smart-e31a5bce-14b6-4665-9fd2-91f552588046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557012034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2557012034
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1708487003
Short name T918
Test name
Test status
Simulation time 5975357620 ps
CPU time 15.28 seconds
Started Mar 21 01:55:02 PM PDT 24
Finished Mar 21 01:55:19 PM PDT 24
Peak memory 200272 kb
Host smart-f85034b4-9f6f-4c08-ad4a-f91fce828975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708487003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1708487003
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.4282411318
Short name T111
Test name
Test status
Simulation time 91238091890 ps
CPU time 964.75 seconds
Started Mar 21 01:55:02 PM PDT 24
Finished Mar 21 02:11:08 PM PDT 24
Peak memory 225288 kb
Host smart-d4553024-dda7-4623-875b-b7ae79bae530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282411318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.4282411318
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2079558586
Short name T672
Test name
Test status
Simulation time 1737392309 ps
CPU time 1.81 seconds
Started Mar 21 01:55:00 PM PDT 24
Finished Mar 21 01:55:03 PM PDT 24
Peak memory 199484 kb
Host smart-2dfc286d-c2c7-4ad0-bbab-bf251aed10e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079558586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2079558586
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.4135313266
Short name T893
Test name
Test status
Simulation time 32520076606 ps
CPU time 60.66 seconds
Started Mar 21 01:54:59 PM PDT 24
Finished Mar 21 01:56:01 PM PDT 24
Peak memory 200364 kb
Host smart-839e61aa-8098-4f2a-a5d4-204e83a0a0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135313266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.4135313266
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2657596704
Short name T196
Test name
Test status
Simulation time 82488370036 ps
CPU time 29.14 seconds
Started Mar 21 01:58:58 PM PDT 24
Finished Mar 21 01:59:27 PM PDT 24
Peak memory 200332 kb
Host smart-23af0890-ab1c-400e-ba81-f6b7c8d9c26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657596704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2657596704
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1739605116
Short name T1114
Test name
Test status
Simulation time 20790328725 ps
CPU time 17.78 seconds
Started Mar 21 01:58:57 PM PDT 24
Finished Mar 21 01:59:14 PM PDT 24
Peak memory 200436 kb
Host smart-552aadba-0b0f-4a57-bb32-80e7d00cb766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739605116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1739605116
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3934085263
Short name T699
Test name
Test status
Simulation time 37504563167 ps
CPU time 22.69 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 01:59:19 PM PDT 24
Peak memory 200464 kb
Host smart-f93d3277-fa11-4888-a7a6-db92f93041d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934085263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3934085263
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.396020103
Short name T690
Test name
Test status
Simulation time 98211424581 ps
CPU time 133.64 seconds
Started Mar 21 01:58:55 PM PDT 24
Finished Mar 21 02:01:09 PM PDT 24
Peak memory 200436 kb
Host smart-050d065f-c2b5-4365-b8ca-f81248669d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396020103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.396020103
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.774437672
Short name T146
Test name
Test status
Simulation time 133358006927 ps
CPU time 103.74 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 02:00:40 PM PDT 24
Peak memory 200420 kb
Host smart-58ef7f06-e7e8-4fd2-a633-254d87b8abb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774437672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.774437672
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.487269502
Short name T439
Test name
Test status
Simulation time 129415004651 ps
CPU time 349.67 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 02:04:45 PM PDT 24
Peak memory 200320 kb
Host smart-f76825cc-86c6-43da-a92b-7650ec974c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487269502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.487269502
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3011462199
Short name T225
Test name
Test status
Simulation time 18367835954 ps
CPU time 9.99 seconds
Started Mar 21 01:58:54 PM PDT 24
Finished Mar 21 01:59:04 PM PDT 24
Peak memory 200448 kb
Host smart-8b3e7d0c-4dc2-4ac1-8e03-b99fa511ff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011462199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3011462199
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.382479636
Short name T1031
Test name
Test status
Simulation time 15841142746 ps
CPU time 18.41 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 01:59:14 PM PDT 24
Peak memory 200408 kb
Host smart-30776c36-71ac-4a1f-884f-cce8f4be067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382479636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.382479636
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.230787151
Short name T365
Test name
Test status
Simulation time 41023355 ps
CPU time 0.55 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:55:15 PM PDT 24
Peak memory 195884 kb
Host smart-77099e3f-a04f-4f1b-bec2-957044f81c67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230787151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.230787151
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3834761696
Short name T59
Test name
Test status
Simulation time 46993716000 ps
CPU time 43.61 seconds
Started Mar 21 01:55:00 PM PDT 24
Finished Mar 21 01:55:44 PM PDT 24
Peak memory 200400 kb
Host smart-30050464-49b3-4583-8c83-8d7e4893ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834761696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3834761696
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.109174163
Short name T451
Test name
Test status
Simulation time 83136189024 ps
CPU time 36.33 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:55:50 PM PDT 24
Peak memory 200416 kb
Host smart-b5cf75b4-4266-42d1-bc5b-705c8eddea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109174163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.109174163
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.3340690932
Short name T1045
Test name
Test status
Simulation time 423063182666 ps
CPU time 344.39 seconds
Started Mar 21 01:55:17 PM PDT 24
Finished Mar 21 02:01:02 PM PDT 24
Peak memory 198468 kb
Host smart-6ee27ff8-315e-4bfa-8554-76bdc259cdc4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340690932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3340690932
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3672451904
Short name T487
Test name
Test status
Simulation time 161031923975 ps
CPU time 663.68 seconds
Started Mar 21 01:55:13 PM PDT 24
Finished Mar 21 02:06:17 PM PDT 24
Peak memory 200380 kb
Host smart-18f23923-477a-4c65-adc6-9d09b0ba99a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672451904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3672451904
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.801058696
Short name T815
Test name
Test status
Simulation time 6104626275 ps
CPU time 5.01 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:55:19 PM PDT 24
Peak memory 199736 kb
Host smart-c16df428-6c60-458d-b374-a30ff6f0e082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801058696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.801058696
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2070149107
Short name T418
Test name
Test status
Simulation time 42963716674 ps
CPU time 74.41 seconds
Started Mar 21 01:55:16 PM PDT 24
Finished Mar 21 01:56:31 PM PDT 24
Peak memory 200272 kb
Host smart-28263922-5f48-4ed9-a38c-d48219080e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070149107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2070149107
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3031307229
Short name T766
Test name
Test status
Simulation time 21358543070 ps
CPU time 323.15 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 02:00:48 PM PDT 24
Peak memory 200360 kb
Host smart-c2f2b312-2d7d-4949-8569-c2345dea5ecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031307229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3031307229
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1331359032
Short name T527
Test name
Test status
Simulation time 7474101517 ps
CPU time 32.55 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 01:55:57 PM PDT 24
Peak memory 199348 kb
Host smart-8467c617-becc-421f-91ac-390876186d46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331359032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1331359032
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2628312952
Short name T575
Test name
Test status
Simulation time 15486015505 ps
CPU time 15.19 seconds
Started Mar 21 01:55:13 PM PDT 24
Finished Mar 21 01:55:29 PM PDT 24
Peak memory 200380 kb
Host smart-453ae31b-e60d-455c-9eb1-f3234784043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628312952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2628312952
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2933725782
Short name T685
Test name
Test status
Simulation time 3260923179 ps
CPU time 5.5 seconds
Started Mar 21 01:55:13 PM PDT 24
Finished Mar 21 01:55:19 PM PDT 24
Peak memory 196512 kb
Host smart-93db9a37-cbde-4b2c-94e9-1c282345ae5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933725782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2933725782
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3517924925
Short name T694
Test name
Test status
Simulation time 5380011626 ps
CPU time 22.67 seconds
Started Mar 21 01:55:04 PM PDT 24
Finished Mar 21 01:55:27 PM PDT 24
Peak memory 199520 kb
Host smart-ea70bd0e-5bdd-4f79-b07c-bb9b93c1a45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517924925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3517924925
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3919210109
Short name T596
Test name
Test status
Simulation time 233179764030 ps
CPU time 526.29 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 02:04:00 PM PDT 24
Peak memory 200436 kb
Host smart-a1f35c02-c4d6-41bf-b5e1-16c4eff08c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919210109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3919210109
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2372819939
Short name T899
Test name
Test status
Simulation time 6756489178 ps
CPU time 10.04 seconds
Started Mar 21 01:55:15 PM PDT 24
Finished Mar 21 01:55:25 PM PDT 24
Peak memory 200208 kb
Host smart-c50efd6e-8194-4636-896a-8da376a66c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372819939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2372819939
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3547907447
Short name T555
Test name
Test status
Simulation time 249622505842 ps
CPU time 26.65 seconds
Started Mar 21 01:55:02 PM PDT 24
Finished Mar 21 01:55:30 PM PDT 24
Peak memory 197384 kb
Host smart-9f9451d1-6f5f-4f34-a4be-8eb2386812dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547907447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3547907447
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1213322682
Short name T814
Test name
Test status
Simulation time 121767715443 ps
CPU time 182.78 seconds
Started Mar 21 01:58:59 PM PDT 24
Finished Mar 21 02:02:02 PM PDT 24
Peak memory 200452 kb
Host smart-a68c79d5-e3a9-4e1b-b57a-3cb30ff1d9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213322682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1213322682
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.879481628
Short name T610
Test name
Test status
Simulation time 34519049643 ps
CPU time 10.47 seconds
Started Mar 21 01:58:57 PM PDT 24
Finished Mar 21 01:59:07 PM PDT 24
Peak memory 200328 kb
Host smart-35180555-c0dc-40e3-97f4-f41b7303f906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879481628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.879481628
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.396460072
Short name T215
Test name
Test status
Simulation time 23552565906 ps
CPU time 43.9 seconds
Started Mar 21 01:58:53 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 200432 kb
Host smart-6db56c0a-2bd6-4207-b99a-569de9244203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396460072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.396460072
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2435826552
Short name T412
Test name
Test status
Simulation time 61941904475 ps
CPU time 10.45 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 01:59:06 PM PDT 24
Peak memory 200312 kb
Host smart-632d6151-47fb-4068-8be1-5ecfc0dacd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435826552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2435826552
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1748288814
Short name T130
Test name
Test status
Simulation time 126904180652 ps
CPU time 49.75 seconds
Started Mar 21 01:58:56 PM PDT 24
Finished Mar 21 01:59:46 PM PDT 24
Peak memory 200384 kb
Host smart-242365f7-ec47-469b-9424-52a8bd2d84c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748288814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1748288814
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2086702786
Short name T206
Test name
Test status
Simulation time 103685725666 ps
CPU time 28.46 seconds
Started Mar 21 01:59:08 PM PDT 24
Finished Mar 21 01:59:36 PM PDT 24
Peak memory 200480 kb
Host smart-d0bf6095-aecc-4e59-a4e0-00cdba9c3757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086702786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2086702786
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2224587581
Short name T1070
Test name
Test status
Simulation time 30482469333 ps
CPU time 24.88 seconds
Started Mar 21 01:59:10 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 200364 kb
Host smart-3138a920-1fdc-41a3-812e-c2a0250ef8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224587581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2224587581
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2791086683
Short name T212
Test name
Test status
Simulation time 143265030853 ps
CPU time 75.78 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 02:00:27 PM PDT 24
Peak memory 200388 kb
Host smart-dad9d2b8-22d8-48c9-99c4-9644659f13a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791086683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2791086683
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3021377943
Short name T44
Test name
Test status
Simulation time 22624662793 ps
CPU time 18.84 seconds
Started Mar 21 01:59:08 PM PDT 24
Finished Mar 21 01:59:27 PM PDT 24
Peak memory 200416 kb
Host smart-3e410229-2a62-4acc-a534-65e8bd2aa80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021377943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3021377943
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3059367168
Short name T826
Test name
Test status
Simulation time 89561961 ps
CPU time 0.56 seconds
Started Mar 21 01:55:24 PM PDT 24
Finished Mar 21 01:55:25 PM PDT 24
Peak memory 195880 kb
Host smart-757d1cb0-def2-42ff-b249-aeb446292da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059367168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3059367168
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.432842331
Short name T988
Test name
Test status
Simulation time 182276457561 ps
CPU time 149.17 seconds
Started Mar 21 01:55:13 PM PDT 24
Finished Mar 21 01:57:43 PM PDT 24
Peak memory 200476 kb
Host smart-5110b3d9-2672-440c-ab44-38933461e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432842331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.432842331
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.178628757
Short name T321
Test name
Test status
Simulation time 108394565201 ps
CPU time 51.49 seconds
Started Mar 21 01:55:16 PM PDT 24
Finished Mar 21 01:56:08 PM PDT 24
Peak memory 200392 kb
Host smart-9c20b4b8-ceb0-4141-acd0-ac18d8197b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178628757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.178628757
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3080424021
Short name T325
Test name
Test status
Simulation time 17397142607 ps
CPU time 8.8 seconds
Started Mar 21 01:55:15 PM PDT 24
Finished Mar 21 01:55:24 PM PDT 24
Peak memory 200412 kb
Host smart-3e93d182-fad3-4415-9892-f39cf96d27ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080424021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3080424021
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.4028651918
Short name T58
Test name
Test status
Simulation time 253163082210 ps
CPU time 1952.01 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 02:27:46 PM PDT 24
Peak memory 200392 kb
Host smart-7eff906f-e345-4229-a734-ff82e0d1b659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028651918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.4028651918
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2786651157
Short name T457
Test name
Test status
Simulation time 8457546502 ps
CPU time 8.77 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 01:55:34 PM PDT 24
Peak memory 200248 kb
Host smart-23adb034-baa5-47f5-9a6d-1104a39a3760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786651157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2786651157
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3353036364
Short name T296
Test name
Test status
Simulation time 64506969217 ps
CPU time 57.94 seconds
Started Mar 21 01:55:15 PM PDT 24
Finished Mar 21 01:56:13 PM PDT 24
Peak memory 199692 kb
Host smart-d61d25e4-c7b8-4a20-a857-64e7940385e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353036364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3353036364
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1864968215
Short name T992
Test name
Test status
Simulation time 7724203690 ps
CPU time 432.24 seconds
Started Mar 21 01:55:13 PM PDT 24
Finished Mar 21 02:02:26 PM PDT 24
Peak memory 200344 kb
Host smart-f1d500a9-3dca-40ef-b050-e321bfd50589
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864968215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1864968215
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.325036378
Short name T14
Test name
Test status
Simulation time 5913586716 ps
CPU time 54.67 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:56:09 PM PDT 24
Peak memory 199036 kb
Host smart-49b73b9c-cd50-425a-8893-4b85a565c99c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325036378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.325036378
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4158776203
Short name T174
Test name
Test status
Simulation time 46846218817 ps
CPU time 22.27 seconds
Started Mar 21 01:55:16 PM PDT 24
Finished Mar 21 01:55:39 PM PDT 24
Peak memory 200372 kb
Host smart-233ab386-4c98-4225-9eaa-a43840bb939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158776203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4158776203
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.715210182
Short name T386
Test name
Test status
Simulation time 431143378 ps
CPU time 0.79 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:55:15 PM PDT 24
Peak memory 195916 kb
Host smart-835d65c9-ec4e-4c2b-b8eb-1f6447836398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715210182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.715210182
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2099354455
Short name T917
Test name
Test status
Simulation time 279941889 ps
CPU time 1.38 seconds
Started Mar 21 01:55:15 PM PDT 24
Finished Mar 21 01:55:16 PM PDT 24
Peak memory 199108 kb
Host smart-4f8bd181-44b1-42df-9b9f-6b07202b896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099354455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2099354455
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1507044415
Short name T371
Test name
Test status
Simulation time 498201917 ps
CPU time 1.77 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:55:16 PM PDT 24
Peak memory 198680 kb
Host smart-097d8433-199d-4abc-ba84-8d9fa141c95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507044415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1507044415
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3395137207
Short name T784
Test name
Test status
Simulation time 187187670163 ps
CPU time 45.82 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:56:00 PM PDT 24
Peak memory 200436 kb
Host smart-4576a7bc-e011-4100-be5f-2b893e35a7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395137207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3395137207
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3399011749
Short name T49
Test name
Test status
Simulation time 32210009542 ps
CPU time 46.35 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 01:59:58 PM PDT 24
Peak memory 200316 kb
Host smart-d1ebcad9-46d4-469c-ba1c-52ba18d3324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399011749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3399011749
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1331216530
Short name T154
Test name
Test status
Simulation time 62740349432 ps
CPU time 110.73 seconds
Started Mar 21 01:59:10 PM PDT 24
Finished Mar 21 02:01:03 PM PDT 24
Peak memory 200432 kb
Host smart-f85802b0-3d5c-4d61-8a14-c9c052105b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331216530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1331216530
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.422071338
Short name T239
Test name
Test status
Simulation time 38368220996 ps
CPU time 215.22 seconds
Started Mar 21 01:59:08 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 200368 kb
Host smart-2435208f-4f20-47f5-8d9a-782f6fbd265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422071338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.422071338
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3129877786
Short name T872
Test name
Test status
Simulation time 71525613650 ps
CPU time 26.38 seconds
Started Mar 21 01:59:07 PM PDT 24
Finished Mar 21 01:59:34 PM PDT 24
Peak memory 200400 kb
Host smart-e4aee9d4-6bea-48ad-8d3c-7e9c80bedb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129877786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3129877786
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2575109998
Short name T681
Test name
Test status
Simulation time 220768554790 ps
CPU time 379.42 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 02:05:31 PM PDT 24
Peak memory 200384 kb
Host smart-f8bdc739-0c6c-4dd5-a10a-2184fb55603e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575109998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2575109998
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.366807997
Short name T567
Test name
Test status
Simulation time 132340123505 ps
CPU time 192.07 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 02:02:24 PM PDT 24
Peak memory 200356 kb
Host smart-9d13215d-8888-4a1f-97ba-d8ddc4310c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366807997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.366807997
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.4126112956
Short name T1109
Test name
Test status
Simulation time 22205467663 ps
CPU time 51.75 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 200448 kb
Host smart-3b29b8b1-4715-4f3c-b0d0-10ea9f6ea1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126112956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.4126112956
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1937201243
Short name T186
Test name
Test status
Simulation time 31707849425 ps
CPU time 15.01 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 01:59:27 PM PDT 24
Peak memory 200344 kb
Host smart-f4d6ac25-0aec-4b45-8da8-f1bb3471f7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937201243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1937201243
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2971290768
Short name T737
Test name
Test status
Simulation time 27423013 ps
CPU time 0.57 seconds
Started Mar 21 01:55:28 PM PDT 24
Finished Mar 21 01:55:28 PM PDT 24
Peak memory 195152 kb
Host smart-e98049ee-6f87-4761-8f7c-aaf706c9edde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971290768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2971290768
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3961228031
Short name T152
Test name
Test status
Simulation time 20189624034 ps
CPU time 31.15 seconds
Started Mar 21 01:55:17 PM PDT 24
Finished Mar 21 01:55:48 PM PDT 24
Peak memory 200436 kb
Host smart-d67f8e91-b732-485f-884f-9d60ebd21d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961228031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3961228031
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.491228258
Short name T830
Test name
Test status
Simulation time 126888378786 ps
CPU time 55.35 seconds
Started Mar 21 01:55:16 PM PDT 24
Finished Mar 21 01:56:11 PM PDT 24
Peak memory 200456 kb
Host smart-d75b004f-2d29-4804-9d9a-a434f6a4e5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491228258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.491228258
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1298239847
Short name T754
Test name
Test status
Simulation time 24121602410 ps
CPU time 18.79 seconds
Started Mar 21 01:55:15 PM PDT 24
Finished Mar 21 01:55:33 PM PDT 24
Peak memory 200380 kb
Host smart-5cc514ec-29cf-4e3c-9c4c-53283388d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298239847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1298239847
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2846227376
Short name T687
Test name
Test status
Simulation time 23423366889 ps
CPU time 13.55 seconds
Started Mar 21 01:55:12 PM PDT 24
Finished Mar 21 01:55:27 PM PDT 24
Peak memory 200364 kb
Host smart-5fec0876-21a1-476d-b8e7-2ed41e70a099
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846227376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2846227376
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3091611081
Short name T592
Test name
Test status
Simulation time 159595372107 ps
CPU time 213.01 seconds
Started Mar 21 01:55:28 PM PDT 24
Finished Mar 21 01:59:01 PM PDT 24
Peak memory 200400 kb
Host smart-3b42cde7-e075-4f82-8b7a-37cee65800db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091611081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3091611081
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.51646493
Short name T991
Test name
Test status
Simulation time 7716482421 ps
CPU time 19.54 seconds
Started Mar 21 01:55:33 PM PDT 24
Finished Mar 21 01:55:52 PM PDT 24
Peak memory 199432 kb
Host smart-9e6a5749-73f0-445c-a775-e4fdf429c112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51646493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.51646493
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.4173669609
Short name T903
Test name
Test status
Simulation time 23243983946 ps
CPU time 16.41 seconds
Started Mar 21 01:55:16 PM PDT 24
Finished Mar 21 01:55:32 PM PDT 24
Peak memory 199232 kb
Host smart-3d80cf6f-50f6-4dc5-9d7a-e915980b955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173669609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4173669609
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3361140985
Short name T743
Test name
Test status
Simulation time 7514221663 ps
CPU time 214.18 seconds
Started Mar 21 01:55:24 PM PDT 24
Finished Mar 21 01:58:58 PM PDT 24
Peak memory 200396 kb
Host smart-a4955cb7-43cb-4101-8f30-730944813790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3361140985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3361140985
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1568262015
Short name T387
Test name
Test status
Simulation time 6339727120 ps
CPU time 13.9 seconds
Started Mar 21 01:55:16 PM PDT 24
Finished Mar 21 01:55:30 PM PDT 24
Peak memory 199596 kb
Host smart-6599a5ea-444a-4b01-9d89-7c0c9c962c4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568262015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1568262015
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1934102643
Short name T381
Test name
Test status
Simulation time 93536207356 ps
CPU time 375.9 seconds
Started Mar 21 01:55:29 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 200408 kb
Host smart-453ec701-2171-442b-8c20-291a1397fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934102643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1934102643
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3394686402
Short name T617
Test name
Test status
Simulation time 5513398908 ps
CPU time 2.05 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:55:16 PM PDT 24
Peak memory 196752 kb
Host smart-cd2ea4ef-27af-47f7-b782-8c45b275b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394686402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3394686402
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.932728584
Short name T591
Test name
Test status
Simulation time 248162609 ps
CPU time 1.55 seconds
Started Mar 21 01:55:14 PM PDT 24
Finished Mar 21 01:55:16 PM PDT 24
Peak memory 198812 kb
Host smart-9a7e7011-d5b2-4c40-a299-27fdddd5d2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932728584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.932728584
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1759013041
Short name T855
Test name
Test status
Simulation time 1309800223 ps
CPU time 1.53 seconds
Started Mar 21 01:55:26 PM PDT 24
Finished Mar 21 01:55:27 PM PDT 24
Peak memory 198656 kb
Host smart-5531177b-c683-42fd-8136-1e1eab6c0343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759013041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1759013041
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3123388611
Short name T530
Test name
Test status
Simulation time 9852145070 ps
CPU time 9.03 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 01:55:34 PM PDT 24
Peak memory 200408 kb
Host smart-c1ce8fe8-fad5-49ac-9206-ee1ba733fb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123388611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3123388611
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.63509313
Short name T402
Test name
Test status
Simulation time 201963492654 ps
CPU time 82.94 seconds
Started Mar 21 01:59:16 PM PDT 24
Finished Mar 21 02:00:39 PM PDT 24
Peak memory 200320 kb
Host smart-04bad6f2-67d3-4dbf-9c8f-271e14c4c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63509313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.63509313
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1475668846
Short name T639
Test name
Test status
Simulation time 63537210082 ps
CPU time 14.12 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 200436 kb
Host smart-346daad5-5788-4a77-bcc8-b00a6ef0c669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475668846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1475668846
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.374105713
Short name T247
Test name
Test status
Simulation time 21102259753 ps
CPU time 11.02 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 200412 kb
Host smart-26464ff1-ef60-44bb-b016-e2318136e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374105713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.374105713
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1571096539
Short name T707
Test name
Test status
Simulation time 111343391172 ps
CPU time 122.44 seconds
Started Mar 21 01:59:17 PM PDT 24
Finished Mar 21 02:01:21 PM PDT 24
Peak memory 200400 kb
Host smart-6d00513a-9fb1-4999-bccb-1a09210e4506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571096539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1571096539
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.338639478
Short name T886
Test name
Test status
Simulation time 17399491045 ps
CPU time 13.87 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 01:59:26 PM PDT 24
Peak memory 200388 kb
Host smart-2239ec66-294a-49ab-997f-95ce19b93280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338639478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.338639478
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1195728682
Short name T1033
Test name
Test status
Simulation time 22442968498 ps
CPU time 30.45 seconds
Started Mar 21 01:59:07 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 200052 kb
Host smart-67693ba7-68c6-4107-aefc-8c313a2150f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195728682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1195728682
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3013191709
Short name T513
Test name
Test status
Simulation time 46436293909 ps
CPU time 76.88 seconds
Started Mar 21 01:59:07 PM PDT 24
Finished Mar 21 02:00:24 PM PDT 24
Peak memory 200372 kb
Host smart-8530b11d-2378-4dda-a519-260d8edb1d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013191709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3013191709
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.4240577970
Short name T190
Test name
Test status
Simulation time 32271753707 ps
CPU time 74.18 seconds
Started Mar 21 01:59:08 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 200380 kb
Host smart-55f5476a-663a-4752-a7bc-b9c2405a3d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240577970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4240577970
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.610827889
Short name T571
Test name
Test status
Simulation time 74204082239 ps
CPU time 57.85 seconds
Started Mar 21 01:59:07 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 200420 kb
Host smart-4b9863d7-8796-4c35-a717-d6872ed5749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610827889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.610827889
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2065992310
Short name T700
Test name
Test status
Simulation time 34872858 ps
CPU time 0.63 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:04 PM PDT 24
Peak memory 195920 kb
Host smart-45005d83-94ba-42fb-803f-36bb3d2b1bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065992310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2065992310
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2985208939
Short name T956
Test name
Test status
Simulation time 16901697897 ps
CPU time 26.49 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:53:18 PM PDT 24
Peak memory 200348 kb
Host smart-d2b215b1-ab13-4b8f-a59a-104ada977441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985208939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2985208939
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1219551486
Short name T436
Test name
Test status
Simulation time 73555230679 ps
CPU time 126.14 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:54:56 PM PDT 24
Peak memory 199844 kb
Host smart-5f086876-2e74-4b33-9858-cfc8d935be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219551486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1219551486
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3219449865
Short name T812
Test name
Test status
Simulation time 31898372378 ps
CPU time 61.24 seconds
Started Mar 21 01:52:52 PM PDT 24
Finished Mar 21 01:53:54 PM PDT 24
Peak memory 200436 kb
Host smart-44b20346-5753-4a8c-8600-1e75c51a90b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219449865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3219449865
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.289915143
Short name T317
Test name
Test status
Simulation time 318251819691 ps
CPU time 541.29 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 02:01:51 PM PDT 24
Peak memory 200228 kb
Host smart-c122be96-755e-4e33-bae9-581470a122b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289915143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.289915143
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1555803605
Short name T243
Test name
Test status
Simulation time 135491080443 ps
CPU time 429.38 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:59:58 PM PDT 24
Peak memory 200320 kb
Host smart-9bd227bc-d98f-4b22-a7cb-3fcc41bf80ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555803605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1555803605
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3118258095
Short name T349
Test name
Test status
Simulation time 10776781945 ps
CPU time 21.68 seconds
Started Mar 21 01:52:51 PM PDT 24
Finished Mar 21 01:53:13 PM PDT 24
Peak memory 200400 kb
Host smart-27ef8cee-3d0a-45bd-8b07-59189734c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118258095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3118258095
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.549485609
Short name T1052
Test name
Test status
Simulation time 13001415882 ps
CPU time 21.12 seconds
Started Mar 21 01:52:57 PM PDT 24
Finished Mar 21 01:53:18 PM PDT 24
Peak memory 198672 kb
Host smart-6c8733e6-9264-4b3c-a066-6d738a3d5480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549485609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.549485609
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1488907361
Short name T854
Test name
Test status
Simulation time 27411982298 ps
CPU time 1571.1 seconds
Started Mar 21 01:52:51 PM PDT 24
Finished Mar 21 02:19:03 PM PDT 24
Peak memory 200384 kb
Host smart-9e8f5266-1ca9-48d9-a86c-c9c59f83b458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488907361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1488907361
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3052785480
Short name T356
Test name
Test status
Simulation time 5978606393 ps
CPU time 48.82 seconds
Started Mar 21 01:52:47 PM PDT 24
Finished Mar 21 01:53:36 PM PDT 24
Peak memory 199488 kb
Host smart-864ac894-f48f-4922-b208-11aa425c89c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052785480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3052785480
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3049289701
Short name T977
Test name
Test status
Simulation time 21739842139 ps
CPU time 35.02 seconds
Started Mar 21 01:52:56 PM PDT 24
Finished Mar 21 01:53:31 PM PDT 24
Peak memory 200364 kb
Host smart-633f5880-415e-446e-aa8d-04c3f915a826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049289701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3049289701
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.755469018
Short name T732
Test name
Test status
Simulation time 2776809525 ps
CPU time 5.06 seconds
Started Mar 21 01:52:49 PM PDT 24
Finished Mar 21 01:52:54 PM PDT 24
Peak memory 196152 kb
Host smart-924ec71f-7432-4f1e-a8d9-6393f03acff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755469018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.755469018
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1277887463
Short name T103
Test name
Test status
Simulation time 448493651 ps
CPU time 0.83 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:04 PM PDT 24
Peak memory 218776 kb
Host smart-def0c136-9dda-4478-ac96-b6d7aa8deec4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277887463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1277887463
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.864603051
Short name T271
Test name
Test status
Simulation time 511723028 ps
CPU time 1.38 seconds
Started Mar 21 01:52:48 PM PDT 24
Finished Mar 21 01:52:50 PM PDT 24
Peak memory 199096 kb
Host smart-5d025670-7989-48f2-86ca-04a3ac09f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864603051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.864603051
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.88487460
Short name T937
Test name
Test status
Simulation time 1512133318 ps
CPU time 2.2 seconds
Started Mar 21 01:52:50 PM PDT 24
Finished Mar 21 01:52:52 PM PDT 24
Peak memory 198332 kb
Host smart-e7f69c32-7f90-46f8-8a0b-3e40a86640cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88487460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.88487460
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.924363237
Short name T245
Test name
Test status
Simulation time 123549743328 ps
CPU time 66.68 seconds
Started Mar 21 01:52:53 PM PDT 24
Finished Mar 21 01:54:00 PM PDT 24
Peak memory 200424 kb
Host smart-cc8847a2-fa73-4e6b-8325-3111a1d10ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924363237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.924363237
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4140835153
Short name T30
Test name
Test status
Simulation time 12742542 ps
CPU time 0.54 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 01:55:26 PM PDT 24
Peak memory 195240 kb
Host smart-e5c7406c-44e5-487f-a31e-fc906cdcce42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140835153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4140835153
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.4218692876
Short name T643
Test name
Test status
Simulation time 23956924768 ps
CPU time 4.78 seconds
Started Mar 21 01:55:27 PM PDT 24
Finished Mar 21 01:55:32 PM PDT 24
Peak memory 199292 kb
Host smart-b055207c-fce0-464a-b1bd-78315714e1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218692876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4218692876
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1572057494
Short name T976
Test name
Test status
Simulation time 28715468693 ps
CPU time 48.61 seconds
Started Mar 21 01:55:27 PM PDT 24
Finished Mar 21 01:56:16 PM PDT 24
Peak memory 200392 kb
Host smart-07f5980c-5912-4beb-b44f-4c3689452d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572057494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1572057494
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3505908862
Short name T878
Test name
Test status
Simulation time 20859616878 ps
CPU time 32.91 seconds
Started Mar 21 01:55:24 PM PDT 24
Finished Mar 21 01:55:57 PM PDT 24
Peak memory 200420 kb
Host smart-78d66bd5-fa87-41bd-8f81-0e7d8d3516ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505908862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3505908862
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2991005563
Short name T858
Test name
Test status
Simulation time 31144151365 ps
CPU time 33.86 seconds
Started Mar 21 01:55:28 PM PDT 24
Finished Mar 21 01:56:02 PM PDT 24
Peak memory 200052 kb
Host smart-896d5f3b-8b40-4022-a523-26e9bac4ccdf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991005563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2991005563
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.4068374038
Short name T702
Test name
Test status
Simulation time 84701315078 ps
CPU time 328.85 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 02:00:54 PM PDT 24
Peak memory 200380 kb
Host smart-37d37d02-0728-40ed-a234-29c280240b71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068374038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.4068374038
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.303568562
Short name T744
Test name
Test status
Simulation time 7582746806 ps
CPU time 16.96 seconds
Started Mar 21 01:55:26 PM PDT 24
Finished Mar 21 01:55:43 PM PDT 24
Peak memory 200260 kb
Host smart-982d4320-dda6-4135-bcf0-a1cdb4f4a996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303568562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.303568562
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2317140793
Short name T1068
Test name
Test status
Simulation time 27287722948 ps
CPU time 42.11 seconds
Started Mar 21 01:55:24 PM PDT 24
Finished Mar 21 01:56:07 PM PDT 24
Peak memory 200516 kb
Host smart-493bfa66-9164-4713-bed9-252b0567b7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317140793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2317140793
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.204837467
Short name T859
Test name
Test status
Simulation time 12576309373 ps
CPU time 148.02 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 01:57:53 PM PDT 24
Peak memory 200440 kb
Host smart-4b34dc59-8e58-4ea9-9b7f-054741e4c2bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204837467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.204837467
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2656758304
Short name T999
Test name
Test status
Simulation time 6293138284 ps
CPU time 5.03 seconds
Started Mar 21 01:55:27 PM PDT 24
Finished Mar 21 01:55:32 PM PDT 24
Peak memory 198544 kb
Host smart-c7a682f4-ee8b-4291-b538-a54ec267df7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656758304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2656758304
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.718229013
Short name T500
Test name
Test status
Simulation time 24412006226 ps
CPU time 7.89 seconds
Started Mar 21 01:55:23 PM PDT 24
Finished Mar 21 01:55:31 PM PDT 24
Peak memory 200644 kb
Host smart-14cbe260-3ae0-4a50-8c91-4f9428badf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718229013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.718229013
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1036696918
Short name T735
Test name
Test status
Simulation time 542961112 ps
CPU time 1.08 seconds
Started Mar 21 01:55:27 PM PDT 24
Finished Mar 21 01:55:28 PM PDT 24
Peak memory 196112 kb
Host smart-7608ae16-befd-4303-a4ae-0ba34001c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036696918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1036696918
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2746439129
Short name T1094
Test name
Test status
Simulation time 287632681 ps
CPU time 1.07 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 01:55:26 PM PDT 24
Peak memory 198988 kb
Host smart-3cbdbf79-e03c-47ff-8815-5ccc900d2b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746439129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2746439129
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3565233012
Short name T936
Test name
Test status
Simulation time 414561720265 ps
CPU time 340.29 seconds
Started Mar 21 01:55:33 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 200388 kb
Host smart-b09a0e9b-d7e8-4fba-a97e-e8f89b862de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565233012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3565233012
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1014171373
Short name T1079
Test name
Test status
Simulation time 1088906666 ps
CPU time 4.45 seconds
Started Mar 21 01:55:25 PM PDT 24
Finished Mar 21 01:55:29 PM PDT 24
Peak memory 199836 kb
Host smart-c96a1231-1278-4888-a4a5-374c00349ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014171373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1014171373
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2989664721
Short name T981
Test name
Test status
Simulation time 98368306549 ps
CPU time 69.98 seconds
Started Mar 21 01:55:27 PM PDT 24
Finished Mar 21 01:56:37 PM PDT 24
Peak memory 200380 kb
Host smart-a03ce70e-2cce-4ec5-aeb7-051b7f46fa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989664721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2989664721
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3740161206
Short name T1069
Test name
Test status
Simulation time 11608655 ps
CPU time 0.55 seconds
Started Mar 21 01:55:41 PM PDT 24
Finished Mar 21 01:55:42 PM PDT 24
Peak memory 195892 kb
Host smart-718dfbd4-8c26-4629-a17a-876498baf018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740161206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3740161206
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.4186670109
Short name T1041
Test name
Test status
Simulation time 221706190831 ps
CPU time 117.72 seconds
Started Mar 21 01:55:26 PM PDT 24
Finished Mar 21 01:57:24 PM PDT 24
Peak memory 200372 kb
Host smart-bf378d45-d06e-4099-8949-c3508c493de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186670109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.4186670109
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3416745709
Short name T562
Test name
Test status
Simulation time 101734305421 ps
CPU time 88.35 seconds
Started Mar 21 01:55:33 PM PDT 24
Finished Mar 21 01:57:01 PM PDT 24
Peak memory 200356 kb
Host smart-a0140fe3-3055-4821-91e8-49c75faa0957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416745709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3416745709
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3334040453
Short name T895
Test name
Test status
Simulation time 22584440974 ps
CPU time 11.46 seconds
Started Mar 21 01:55:28 PM PDT 24
Finished Mar 21 01:55:39 PM PDT 24
Peak memory 200212 kb
Host smart-e7cf3560-2691-4892-b211-692b63bc3f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334040453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3334040453
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.409257791
Short name T1082
Test name
Test status
Simulation time 62697438940 ps
CPU time 38.56 seconds
Started Mar 21 01:55:24 PM PDT 24
Finished Mar 21 01:56:03 PM PDT 24
Peak memory 200408 kb
Host smart-c3932442-2cfe-44e6-88bb-213c7bdd51e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409257791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.409257791
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.481972171
Short name T496
Test name
Test status
Simulation time 107225091713 ps
CPU time 1026.54 seconds
Started Mar 21 01:55:28 PM PDT 24
Finished Mar 21 02:12:35 PM PDT 24
Peak memory 200380 kb
Host smart-c61eeee6-bc20-4ae7-82f3-4178753acf33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481972171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.481972171
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.510398035
Short name T1000
Test name
Test status
Simulation time 3936718151 ps
CPU time 2.44 seconds
Started Mar 21 01:55:28 PM PDT 24
Finished Mar 21 01:55:30 PM PDT 24
Peak memory 199068 kb
Host smart-0ba54498-aa0e-4a74-a1ba-a9b3e3149c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510398035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.510398035
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2143127756
Short name T843
Test name
Test status
Simulation time 103506498087 ps
CPU time 312.61 seconds
Started Mar 21 01:55:29 PM PDT 24
Finished Mar 21 02:00:42 PM PDT 24
Peak memory 200444 kb
Host smart-c43418fe-3064-4917-be9a-34587d5587ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143127756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2143127756
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.535503942
Short name T897
Test name
Test status
Simulation time 9938982195 ps
CPU time 148.08 seconds
Started Mar 21 01:55:26 PM PDT 24
Finished Mar 21 01:57:54 PM PDT 24
Peak memory 200332 kb
Host smart-91df40b1-d975-47d0-8221-f9b21f5548fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535503942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.535503942
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.980416780
Short name T1083
Test name
Test status
Simulation time 3688137173 ps
CPU time 16.56 seconds
Started Mar 21 01:55:32 PM PDT 24
Finished Mar 21 01:55:49 PM PDT 24
Peak memory 199472 kb
Host smart-20e8229b-cdb7-4898-aa0c-52840dd1b4a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980416780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.980416780
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1045767795
Short name T170
Test name
Test status
Simulation time 145158734350 ps
CPU time 63.93 seconds
Started Mar 21 01:55:28 PM PDT 24
Finished Mar 21 01:56:32 PM PDT 24
Peak memory 200416 kb
Host smart-9b0cb9da-0654-4130-b265-6cf7a5183381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045767795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1045767795
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1591516953
Short name T428
Test name
Test status
Simulation time 4796835199 ps
CPU time 1.13 seconds
Started Mar 21 01:55:24 PM PDT 24
Finished Mar 21 01:55:26 PM PDT 24
Peak memory 196488 kb
Host smart-e2d1095c-7f74-4ff9-ba62-de8be906e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591516953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1591516953
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1986554104
Short name T507
Test name
Test status
Simulation time 887554278 ps
CPU time 2.47 seconds
Started Mar 21 01:55:27 PM PDT 24
Finished Mar 21 01:55:30 PM PDT 24
Peak memory 198576 kb
Host smart-fa2e99b7-dc22-491c-b18e-93a67091df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986554104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1986554104
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1946089049
Short name T116
Test name
Test status
Simulation time 118063861202 ps
CPU time 207.68 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 01:59:12 PM PDT 24
Peak memory 200312 kb
Host smart-fd406be4-42b0-4507-8ce3-a9756987d0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946089049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1946089049
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3686611234
Short name T305
Test name
Test status
Simulation time 38338567853 ps
CPU time 456.38 seconds
Started Mar 21 01:55:26 PM PDT 24
Finished Mar 21 02:03:02 PM PDT 24
Peak memory 216356 kb
Host smart-2481a7ff-9bb6-4ba2-9d28-e711ab4c828d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686611234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3686611234
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3052657531
Short name T821
Test name
Test status
Simulation time 938410875 ps
CPU time 3.32 seconds
Started Mar 21 01:55:33 PM PDT 24
Finished Mar 21 01:55:37 PM PDT 24
Peak memory 199116 kb
Host smart-99165fae-b374-4c3e-b3ba-45445f98f2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052657531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3052657531
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.4224521827
Short name T675
Test name
Test status
Simulation time 16652456193 ps
CPU time 14.93 seconds
Started Mar 21 01:55:26 PM PDT 24
Finished Mar 21 01:55:41 PM PDT 24
Peak memory 198728 kb
Host smart-81f31ff0-f361-4424-948a-1ce878ef8809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224521827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4224521827
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.542362867
Short name T407
Test name
Test status
Simulation time 12428782 ps
CPU time 0.55 seconds
Started Mar 21 01:55:45 PM PDT 24
Finished Mar 21 01:55:46 PM PDT 24
Peak memory 195880 kb
Host smart-ba93a5bf-af14-42c0-9f24-35daecaf4835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542362867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.542362867
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2144283698
Short name T776
Test name
Test status
Simulation time 190869739242 ps
CPU time 290.47 seconds
Started Mar 21 01:55:45 PM PDT 24
Finished Mar 21 02:00:36 PM PDT 24
Peak memory 200436 kb
Host smart-08a5ac7a-fd60-44a4-9a32-010013959c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144283698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2144283698
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.233478995
Short name T354
Test name
Test status
Simulation time 20675809427 ps
CPU time 34.7 seconds
Started Mar 21 01:55:41 PM PDT 24
Finished Mar 21 01:56:16 PM PDT 24
Peak memory 200364 kb
Host smart-a51e7d12-df93-4362-b580-bf21fa9788a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233478995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.233478995
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1548405506
Short name T807
Test name
Test status
Simulation time 5122180812 ps
CPU time 5.6 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 01:55:48 PM PDT 24
Peak memory 200420 kb
Host smart-07e1bf1a-30ab-43b6-9303-7eb199c6ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548405506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1548405506
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.4273220190
Short name T1032
Test name
Test status
Simulation time 19897431849 ps
CPU time 3.54 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 01:55:45 PM PDT 24
Peak memory 197444 kb
Host smart-41a15e6f-d52f-42b4-b1f3-444732339f52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273220190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4273220190
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.263106000
Short name T358
Test name
Test status
Simulation time 59450720699 ps
CPU time 361.37 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 200440 kb
Host smart-5419b2a5-9d71-469d-b967-3313ac0b4371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=263106000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.263106000
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1301225329
Short name T570
Test name
Test status
Simulation time 9641103948 ps
CPU time 15.78 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 01:56:00 PM PDT 24
Peak memory 200200 kb
Host smart-1c9d3275-8030-4d1c-936b-7363c7fc8eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301225329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1301225329
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.104584944
Short name T1056
Test name
Test status
Simulation time 23499923630 ps
CPU time 38.71 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 01:56:21 PM PDT 24
Peak memory 198944 kb
Host smart-f7841ad7-fbe3-45ad-a8c1-590f4c6d3e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104584944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.104584944
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1327672863
Short name T294
Test name
Test status
Simulation time 8431160213 ps
CPU time 114.74 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 01:57:39 PM PDT 24
Peak memory 200416 kb
Host smart-4252cbdf-5957-4ce2-8545-d8cb7d4b7e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327672863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1327672863
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.207175739
Short name T346
Test name
Test status
Simulation time 2468831644 ps
CPU time 3.07 seconds
Started Mar 21 01:55:41 PM PDT 24
Finished Mar 21 01:55:45 PM PDT 24
Peak memory 199624 kb
Host smart-e5c8caa6-d790-4a54-9738-2d7610528a65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=207175739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.207175739
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1412669186
Short name T679
Test name
Test status
Simulation time 77632543577 ps
CPU time 144.06 seconds
Started Mar 21 01:55:45 PM PDT 24
Finished Mar 21 01:58:09 PM PDT 24
Peak memory 200392 kb
Host smart-d4d37cb7-4901-4921-95fc-f4b622c13445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412669186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1412669186
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1275397814
Short name T594
Test name
Test status
Simulation time 5314809286 ps
CPU time 2.78 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 01:55:45 PM PDT 24
Peak memory 196568 kb
Host smart-853e17bc-8100-4622-b9d8-bae3c17cc945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275397814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1275397814
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.292194149
Short name T910
Test name
Test status
Simulation time 458039639 ps
CPU time 1.5 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 01:55:44 PM PDT 24
Peak memory 198876 kb
Host smart-1b36e078-1650-4ef9-857c-19addc5151f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292194149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.292194149
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.208578904
Short name T291
Test name
Test status
Simulation time 2601397823 ps
CPU time 1.87 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 01:55:44 PM PDT 24
Peak memory 199200 kb
Host smart-08e12c5b-140d-4445-8bb8-b95ee8ef25ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208578904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.208578904
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1543980521
Short name T534
Test name
Test status
Simulation time 87719496412 ps
CPU time 80.12 seconds
Started Mar 21 01:55:45 PM PDT 24
Finished Mar 21 01:57:05 PM PDT 24
Peak memory 200432 kb
Host smart-acb03ea9-ed9a-4327-bd70-a30988d29a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543980521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1543980521
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.37205420
Short name T31
Test name
Test status
Simulation time 14315249 ps
CPU time 0.57 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 01:55:44 PM PDT 24
Peak memory 195876 kb
Host smart-415a91a1-b5f8-4d98-aa0c-3e254ad389a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37205420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.37205420
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2028977469
Short name T614
Test name
Test status
Simulation time 149430541484 ps
CPU time 277.49 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 200440 kb
Host smart-91e356dd-6dcf-489b-800c-8f9f54aa6448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028977469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2028977469
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.797187294
Short name T57
Test name
Test status
Simulation time 17927411343 ps
CPU time 30.74 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:56:14 PM PDT 24
Peak memory 200428 kb
Host smart-4c3cff3e-28dc-4115-a5f1-2626f426b182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797187294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.797187294
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3912143221
Short name T879
Test name
Test status
Simulation time 22881217542 ps
CPU time 38.94 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:56:22 PM PDT 24
Peak memory 200372 kb
Host smart-87da232e-09b5-4942-bcdd-71ec4d9effb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912143221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3912143221
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2355972106
Short name T538
Test name
Test status
Simulation time 24402533442 ps
CPU time 10.09 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 01:55:52 PM PDT 24
Peak memory 200344 kb
Host smart-c48c3713-5fac-453f-a1d9-50acc552776d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355972106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2355972106
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3486898015
Short name T425
Test name
Test status
Simulation time 172929917921 ps
CPU time 351.03 seconds
Started Mar 21 01:55:45 PM PDT 24
Finished Mar 21 02:01:36 PM PDT 24
Peak memory 200360 kb
Host smart-a69885f3-8a7f-424e-82ca-0c971fb55a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486898015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3486898015
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2219029038
Short name T629
Test name
Test status
Simulation time 2342634235 ps
CPU time 2.54 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:55:46 PM PDT 24
Peak memory 200212 kb
Host smart-6e39b09a-5b4e-4172-9a69-c46847c7df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219029038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2219029038
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2713470949
Short name T846
Test name
Test status
Simulation time 17516285724 ps
CPU time 15.19 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:55:58 PM PDT 24
Peak memory 197268 kb
Host smart-4dae95e2-1134-4e73-9961-b5d1828a186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713470949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2713470949
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.953627697
Short name T540
Test name
Test status
Simulation time 11507704041 ps
CPU time 300.42 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 02:00:42 PM PDT 24
Peak memory 200348 kb
Host smart-5d04471d-fa76-4a25-9410-1142115cfc8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953627697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.953627697
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1103654743
Short name T351
Test name
Test status
Simulation time 4541399904 ps
CPU time 40.9 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:56:24 PM PDT 24
Peak memory 198668 kb
Host smart-0373a6b0-e8a8-4a0f-9f10-7bdf9f9abc99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103654743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1103654743
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.293061523
Short name T680
Test name
Test status
Simulation time 66225913986 ps
CPU time 52.44 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 01:56:37 PM PDT 24
Peak memory 199948 kb
Host smart-107b3c36-bafa-4468-877c-532f2c95915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293061523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.293061523
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1449239955
Short name T463
Test name
Test status
Simulation time 40080907276 ps
CPU time 8.66 seconds
Started Mar 21 01:55:42 PM PDT 24
Finished Mar 21 01:55:51 PM PDT 24
Peak memory 196748 kb
Host smart-af47d98a-09bf-4050-a2b0-5cbc730b6845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449239955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1449239955
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3994139639
Short name T557
Test name
Test status
Simulation time 761348146 ps
CPU time 1.11 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:55:44 PM PDT 24
Peak memory 198892 kb
Host smart-b61c5ef5-920e-4bae-ba68-85dfa4c41db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994139639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3994139639
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2145173796
Short name T907
Test name
Test status
Simulation time 125707826949 ps
CPU time 435.34 seconds
Started Mar 21 01:55:41 PM PDT 24
Finished Mar 21 02:02:56 PM PDT 24
Peak memory 200384 kb
Host smart-281a9c67-9082-4885-b503-49680aa099b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145173796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2145173796
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.4294827312
Short name T605
Test name
Test status
Simulation time 7447623386 ps
CPU time 19.2 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:56:03 PM PDT 24
Peak memory 200076 kb
Host smart-2904d813-f06e-4c2f-a023-a7eef19a4ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294827312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.4294827312
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.4186931193
Short name T615
Test name
Test status
Simulation time 116425662765 ps
CPU time 56.41 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 01:56:41 PM PDT 24
Peak memory 200356 kb
Host smart-9dccd236-675c-44fe-8ad6-f1003def8f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186931193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.4186931193
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3376482644
Short name T514
Test name
Test status
Simulation time 14359974 ps
CPU time 0.55 seconds
Started Mar 21 01:55:58 PM PDT 24
Finished Mar 21 01:55:59 PM PDT 24
Peak memory 195880 kb
Host smart-d5275c91-7089-4bdd-b470-8a4eccfee85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376482644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3376482644
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.4054316218
Short name T795
Test name
Test status
Simulation time 101417264818 ps
CPU time 251.38 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:59:55 PM PDT 24
Peak memory 200472 kb
Host smart-c68e6fd9-af55-4827-812c-8e62ca9fb488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054316218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4054316218
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.308425430
Short name T129
Test name
Test status
Simulation time 23279903014 ps
CPU time 11.55 seconds
Started Mar 21 01:55:55 PM PDT 24
Finished Mar 21 01:56:06 PM PDT 24
Peak memory 200412 kb
Host smart-dce12d0b-caf4-4cf5-a703-d64cc44b778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308425430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.308425430
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2770059351
Short name T76
Test name
Test status
Simulation time 70740921681 ps
CPU time 21.24 seconds
Started Mar 21 01:55:56 PM PDT 24
Finished Mar 21 01:56:18 PM PDT 24
Peak memory 200376 kb
Host smart-404887d9-7063-4176-9ac1-b811c355d3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770059351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2770059351
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1460618782
Short name T529
Test name
Test status
Simulation time 96328049754 ps
CPU time 161.33 seconds
Started Mar 21 01:55:56 PM PDT 24
Finished Mar 21 01:58:37 PM PDT 24
Peak memory 199812 kb
Host smart-954a0b2a-949e-431b-84de-dfb47f12161c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460618782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1460618782
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3448457348
Short name T398
Test name
Test status
Simulation time 111479601334 ps
CPU time 953.44 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 02:11:51 PM PDT 24
Peak memory 200416 kb
Host smart-28545cc3-c1f8-4c95-991b-ebed81381499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448457348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3448457348
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2228845422
Short name T333
Test name
Test status
Simulation time 13198268089 ps
CPU time 9.32 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:56:07 PM PDT 24
Peak memory 200236 kb
Host smart-36b02f9e-7dee-4710-a310-582886753b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228845422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2228845422
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3717961508
Short name T825
Test name
Test status
Simulation time 51566169344 ps
CPU time 11.38 seconds
Started Mar 21 01:55:55 PM PDT 24
Finished Mar 21 01:56:06 PM PDT 24
Peak memory 200440 kb
Host smart-2309a654-0abd-4f5c-9eee-987ad234464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717961508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3717961508
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1197965749
Short name T312
Test name
Test status
Simulation time 16692545701 ps
CPU time 386.19 seconds
Started Mar 21 01:56:01 PM PDT 24
Finished Mar 21 02:02:27 PM PDT 24
Peak memory 200296 kb
Host smart-2d258e82-8629-4c62-be7d-c1e1a6fe5508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197965749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1197965749
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1526014289
Short name T841
Test name
Test status
Simulation time 3153343101 ps
CPU time 19.87 seconds
Started Mar 21 01:56:00 PM PDT 24
Finished Mar 21 01:56:20 PM PDT 24
Peak memory 199428 kb
Host smart-d1f594f9-43c4-44f1-9aec-479d82beccac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526014289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1526014289
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.153252356
Short name T832
Test name
Test status
Simulation time 21665222966 ps
CPU time 34.52 seconds
Started Mar 21 01:55:54 PM PDT 24
Finished Mar 21 01:56:29 PM PDT 24
Peak memory 199116 kb
Host smart-6e42f5e1-af76-4bef-88b8-9e117f4f97ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153252356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.153252356
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.4246391100
Short name T313
Test name
Test status
Simulation time 1302649014 ps
CPU time 1.53 seconds
Started Mar 21 01:56:00 PM PDT 24
Finished Mar 21 01:56:02 PM PDT 24
Peak memory 196096 kb
Host smart-1b67eaca-ab0c-46f2-afe4-8ae4ad5ccd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246391100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4246391100
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2510009311
Short name T416
Test name
Test status
Simulation time 649735001 ps
CPU time 2.62 seconds
Started Mar 21 01:55:44 PM PDT 24
Finished Mar 21 01:55:47 PM PDT 24
Peak memory 198628 kb
Host smart-8544d1f2-5979-49de-aa95-2c5551a507fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510009311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2510009311
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1852692376
Short name T413
Test name
Test status
Simulation time 24110938568 ps
CPU time 551.17 seconds
Started Mar 21 01:55:54 PM PDT 24
Finished Mar 21 02:05:05 PM PDT 24
Peak memory 200364 kb
Host smart-cb0f3bc8-7ce8-40fb-82b1-a9aaa8555767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852692376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1852692376
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.467544861
Short name T602
Test name
Test status
Simulation time 779995966 ps
CPU time 2.62 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:56:00 PM PDT 24
Peak memory 198408 kb
Host smart-13038a7e-1dcb-44c8-8a64-b1e9e8916981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467544861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.467544861
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1043734767
Short name T979
Test name
Test status
Simulation time 46356227533 ps
CPU time 79.01 seconds
Started Mar 21 01:55:43 PM PDT 24
Finished Mar 21 01:57:02 PM PDT 24
Peak memory 200412 kb
Host smart-09906a1e-fc36-417f-a471-37271821b6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043734767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1043734767
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1745224002
Short name T415
Test name
Test status
Simulation time 10627169 ps
CPU time 0.55 seconds
Started Mar 21 01:55:55 PM PDT 24
Finished Mar 21 01:55:55 PM PDT 24
Peak memory 194884 kb
Host smart-d02d4b08-bbe9-4d1e-bd28-16d0471af0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745224002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1745224002
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.4008472810
Short name T126
Test name
Test status
Simulation time 88088504006 ps
CPU time 60.09 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:56:57 PM PDT 24
Peak memory 200376 kb
Host smart-456c87df-0611-40e5-9e11-6410dc4c6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008472810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.4008472810
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2101108869
Short name T541
Test name
Test status
Simulation time 38446270482 ps
CPU time 32.61 seconds
Started Mar 21 01:55:56 PM PDT 24
Finished Mar 21 01:56:29 PM PDT 24
Peak memory 200356 kb
Host smart-7470d969-7d7f-4e21-9765-b583db6d9296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101108869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2101108869
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1747166727
Short name T975
Test name
Test status
Simulation time 114721207932 ps
CPU time 28.24 seconds
Started Mar 21 01:55:55 PM PDT 24
Finished Mar 21 01:56:23 PM PDT 24
Peak memory 200172 kb
Host smart-7a88b67f-be90-4999-839b-a14ad60065ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747166727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1747166727
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.484180251
Short name T627
Test name
Test status
Simulation time 39965615549 ps
CPU time 32.1 seconds
Started Mar 21 01:55:54 PM PDT 24
Finished Mar 21 01:56:26 PM PDT 24
Peak memory 200004 kb
Host smart-3c7b85c8-d197-437b-871e-9cf8b93c3e5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484180251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.484180251
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1682294770
Short name T270
Test name
Test status
Simulation time 81342030622 ps
CPU time 753.78 seconds
Started Mar 21 01:55:56 PM PDT 24
Finished Mar 21 02:08:30 PM PDT 24
Peak memory 200384 kb
Host smart-6015ad1c-22c7-4b33-92bd-2bb4b124ba34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1682294770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1682294770
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.378111157
Short name T560
Test name
Test status
Simulation time 3761338183 ps
CPU time 2.02 seconds
Started Mar 21 01:55:56 PM PDT 24
Finished Mar 21 01:55:58 PM PDT 24
Peak memory 197944 kb
Host smart-562e6db5-0991-4455-8901-5e9977370ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378111157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.378111157
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1534166023
Short name T520
Test name
Test status
Simulation time 161674640074 ps
CPU time 176.2 seconds
Started Mar 21 01:56:00 PM PDT 24
Finished Mar 21 01:58:57 PM PDT 24
Peak memory 200608 kb
Host smart-4366fe0b-9776-4b02-bd9c-f76029af81d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534166023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1534166023
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2288077991
Short name T697
Test name
Test status
Simulation time 18774297363 ps
CPU time 979.64 seconds
Started Mar 21 01:56:01 PM PDT 24
Finished Mar 21 02:12:20 PM PDT 24
Peak memory 200296 kb
Host smart-d95afb3a-eaec-4bb8-91ce-75d0ccacf323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288077991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2288077991
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1023613122
Short name T477
Test name
Test status
Simulation time 2210366351 ps
CPU time 12.6 seconds
Started Mar 21 01:55:54 PM PDT 24
Finished Mar 21 01:56:07 PM PDT 24
Peak memory 199568 kb
Host smart-7566a9e1-dec6-43b5-b508-9076f2b669aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023613122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1023613122
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2378225622
Short name T678
Test name
Test status
Simulation time 69679100612 ps
CPU time 30.67 seconds
Started Mar 21 01:55:55 PM PDT 24
Finished Mar 21 01:56:25 PM PDT 24
Peak memory 200276 kb
Host smart-dd200b8d-79d2-4b23-9e84-2b6bacffc2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378225622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2378225622
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1205711645
Short name T468
Test name
Test status
Simulation time 34301349925 ps
CPU time 52.02 seconds
Started Mar 21 01:56:00 PM PDT 24
Finished Mar 21 01:56:53 PM PDT 24
Peak memory 196504 kb
Host smart-cdaca15d-c3cf-471b-bf5f-45ffd7586b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205711645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1205711645
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.676521577
Short name T1074
Test name
Test status
Simulation time 5636412970 ps
CPU time 9.68 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:56:06 PM PDT 24
Peak memory 200108 kb
Host smart-28205b56-1621-407d-a192-408e00f9d717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676521577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.676521577
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2506815961
Short name T969
Test name
Test status
Simulation time 260455312424 ps
CPU time 577.87 seconds
Started Mar 21 01:55:55 PM PDT 24
Finished Mar 21 02:05:33 PM PDT 24
Peak memory 200380 kb
Host smart-e479a987-ad1c-4c7f-95fc-8dc0a9f528a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506815961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2506815961
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1311469814
Short name T40
Test name
Test status
Simulation time 44731264293 ps
CPU time 369.71 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 216904 kb
Host smart-9f2970bd-05cd-4a12-9f8b-5d7ad8610d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311469814 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1311469814
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3625592770
Short name T787
Test name
Test status
Simulation time 938726588 ps
CPU time 3.1 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:56:00 PM PDT 24
Peak memory 199004 kb
Host smart-e56609d7-d794-4dab-8c3a-f117f676f4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625592770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3625592770
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3331236093
Short name T274
Test name
Test status
Simulation time 56676040189 ps
CPU time 22.31 seconds
Started Mar 21 01:55:56 PM PDT 24
Finished Mar 21 01:56:18 PM PDT 24
Peak memory 200416 kb
Host smart-77f7f281-fd68-43f1-a0f6-8b7f56397861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331236093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3331236093
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3590077610
Short name T604
Test name
Test status
Simulation time 13056222 ps
CPU time 0.56 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:56:12 PM PDT 24
Peak memory 195860 kb
Host smart-dc4160bc-9dc9-4603-ae64-fffcd0aab2dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590077610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3590077610
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2186800864
Short name T80
Test name
Test status
Simulation time 161335857666 ps
CPU time 247.92 seconds
Started Mar 21 01:55:56 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 200340 kb
Host smart-ef81f0b5-2ef7-4235-93e0-23dcdcbb1fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186800864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2186800864
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2762285812
Short name T770
Test name
Test status
Simulation time 27064603695 ps
CPU time 28.12 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:56:26 PM PDT 24
Peak memory 200400 kb
Host smart-e1c43d3a-1ce8-4ec5-943c-2efbed779cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762285812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2762285812
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4177810154
Short name T125
Test name
Test status
Simulation time 101499232718 ps
CPU time 157.74 seconds
Started Mar 21 01:56:01 PM PDT 24
Finished Mar 21 01:58:38 PM PDT 24
Peak memory 200384 kb
Host smart-92ddf4c8-8323-4b2e-8099-aefee03fef10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177810154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4177810154
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2620332914
Short name T760
Test name
Test status
Simulation time 25111686176 ps
CPU time 10.88 seconds
Started Mar 21 01:55:56 PM PDT 24
Finished Mar 21 01:56:07 PM PDT 24
Peak memory 200348 kb
Host smart-0357e65e-0b65-4683-b729-e9b3fb78aa24
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620332914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2620332914
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.247307755
Short name T370
Test name
Test status
Simulation time 80809907066 ps
CPU time 193.83 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 200356 kb
Host smart-24c1f923-3e26-4a54-8efa-d018da5c8a9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247307755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.247307755
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3129573369
Short name T665
Test name
Test status
Simulation time 9791400023 ps
CPU time 13.15 seconds
Started Mar 21 01:56:09 PM PDT 24
Finished Mar 21 01:56:22 PM PDT 24
Peak memory 200028 kb
Host smart-259a1d20-f791-4bff-877b-5a4c02c109cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129573369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3129573369
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.4163499132
Short name T63
Test name
Test status
Simulation time 161669139440 ps
CPU time 82.41 seconds
Started Mar 21 01:55:55 PM PDT 24
Finished Mar 21 01:57:18 PM PDT 24
Peak memory 200616 kb
Host smart-23970f1e-1833-4174-894b-b2ff17b98d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163499132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.4163499132
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3292036506
Short name T896
Test name
Test status
Simulation time 26526761227 ps
CPU time 1252.67 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 02:17:03 PM PDT 24
Peak memory 200356 kb
Host smart-71c733b3-0c6b-45ae-b297-1cfe47f6cd4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292036506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3292036506
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.693599331
Short name T656
Test name
Test status
Simulation time 3465776147 ps
CPU time 23.38 seconds
Started Mar 21 01:56:01 PM PDT 24
Finished Mar 21 01:56:24 PM PDT 24
Peak memory 199460 kb
Host smart-c531646b-f071-4639-9466-e4cf16927cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693599331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.693599331
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.338441183
Short name T808
Test name
Test status
Simulation time 198007247552 ps
CPU time 149.15 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:58:27 PM PDT 24
Peak memory 200352 kb
Host smart-e66bca98-e9e0-4768-ba93-82e848201ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338441183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.338441183
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.982500153
Short name T469
Test name
Test status
Simulation time 1916899475 ps
CPU time 1.49 seconds
Started Mar 21 01:55:54 PM PDT 24
Finished Mar 21 01:55:56 PM PDT 24
Peak memory 196208 kb
Host smart-a3b287fb-1277-4e61-aa92-0441d7f16e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982500153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.982500153
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.138637700
Short name T712
Test name
Test status
Simulation time 5916734385 ps
CPU time 7.37 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:56:05 PM PDT 24
Peak memory 200332 kb
Host smart-e11fbd43-127d-4d0e-bb65-cbcb7b6c9ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138637700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.138637700
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2781608144
Short name T503
Test name
Test status
Simulation time 34758537928 ps
CPU time 1083.22 seconds
Started Mar 21 01:56:09 PM PDT 24
Finished Mar 21 02:14:13 PM PDT 24
Peak memory 200432 kb
Host smart-c00cee42-a196-4ed8-b7ad-67cc5348925c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781608144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2781608144
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1731261579
Short name T686
Test name
Test status
Simulation time 7185272543 ps
CPU time 15.46 seconds
Started Mar 21 01:55:57 PM PDT 24
Finished Mar 21 01:56:12 PM PDT 24
Peak memory 200136 kb
Host smart-0e9555c6-b7dc-4928-b009-47336ee8c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731261579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1731261579
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.861855464
Short name T775
Test name
Test status
Simulation time 7193529692 ps
CPU time 12.63 seconds
Started Mar 21 01:56:00 PM PDT 24
Finished Mar 21 01:56:12 PM PDT 24
Peak memory 198200 kb
Host smart-23d5de35-0f8e-4134-965e-9d720b2ac02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861855464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.861855464
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2935019032
Short name T768
Test name
Test status
Simulation time 29379359 ps
CPU time 0.55 seconds
Started Mar 21 01:56:13 PM PDT 24
Finished Mar 21 01:56:14 PM PDT 24
Peak memory 194856 kb
Host smart-1543d870-ae2c-4e3d-8a13-aec8a4535dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935019032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2935019032
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2625076516
Short name T459
Test name
Test status
Simulation time 424378671659 ps
CPU time 52.6 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:57:04 PM PDT 24
Peak memory 200308 kb
Host smart-31263220-3bec-4a63-a4bc-087a6a94680b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625076516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2625076516
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1622024470
Short name T793
Test name
Test status
Simulation time 128575720339 ps
CPU time 93.24 seconds
Started Mar 21 01:56:09 PM PDT 24
Finished Mar 21 01:57:42 PM PDT 24
Peak memory 200372 kb
Host smart-ca5b7645-4d05-4217-a3fd-04c66df14b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622024470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1622024470
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.173634605
Short name T919
Test name
Test status
Simulation time 93178677374 ps
CPU time 36.62 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:56:48 PM PDT 24
Peak memory 200412 kb
Host smart-f65de875-c343-491e-81db-502ca48b3dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173634605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.173634605
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3096880707
Short name T674
Test name
Test status
Simulation time 51301147788 ps
CPU time 30.48 seconds
Started Mar 21 01:56:09 PM PDT 24
Finished Mar 21 01:56:40 PM PDT 24
Peak memory 200348 kb
Host smart-9c479bcd-66fc-4264-9a87-c813f6dae8af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096880707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3096880707
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4072974044
Short name T906
Test name
Test status
Simulation time 133800769123 ps
CPU time 831.89 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 02:10:02 PM PDT 24
Peak memory 200412 kb
Host smart-b0505178-efe6-40ab-b50e-3daa50dbb922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072974044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4072974044
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3004827367
Short name T914
Test name
Test status
Simulation time 2254059028 ps
CPU time 4.94 seconds
Started Mar 21 01:56:15 PM PDT 24
Finished Mar 21 01:56:20 PM PDT 24
Peak memory 199196 kb
Host smart-c22ec020-eb41-42bd-8cac-ee727ba04298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004827367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3004827367
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3813433520
Short name T738
Test name
Test status
Simulation time 15395149353 ps
CPU time 2.19 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 01:56:12 PM PDT 24
Peak memory 195376 kb
Host smart-eb9e1fa6-246b-4b64-8b90-d79b430892ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813433520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3813433520
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4262018716
Short name T252
Test name
Test status
Simulation time 3173311296 ps
CPU time 60.3 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:57:12 PM PDT 24
Peak memory 200336 kb
Host smart-7c6e3138-0480-4be1-8296-e3c2605e741b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262018716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4262018716
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.24135271
Short name T426
Test name
Test status
Simulation time 5898125607 ps
CPU time 8.29 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:56:20 PM PDT 24
Peak memory 199628 kb
Host smart-91061e02-956c-4682-8a3e-011d114bd92a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24135271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.24135271
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1352693434
Short name T692
Test name
Test status
Simulation time 104598106314 ps
CPU time 189.41 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:59:21 PM PDT 24
Peak memory 200396 kb
Host smart-e30294fb-39ef-437e-9f1c-e6b5bcf5c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352693434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1352693434
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.4041612374
Short name T77
Test name
Test status
Simulation time 4123223669 ps
CPU time 7.53 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:56:19 PM PDT 24
Peak memory 196732 kb
Host smart-24bacef3-f77d-4098-b4ee-08de60ebe606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041612374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4041612374
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.770555821
Short name T1007
Test name
Test status
Simulation time 6104119931 ps
CPU time 16.43 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 01:56:27 PM PDT 24
Peak memory 199688 kb
Host smart-5f6cff7c-7fdb-4309-b2f1-63cb6e9ea23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770555821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.770555821
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.422080426
Short name T669
Test name
Test status
Simulation time 148911608777 ps
CPU time 294.25 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 02:01:07 PM PDT 24
Peak memory 200432 kb
Host smart-b974f5d9-3d72-4e7b-ae1e-cbf79073272b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422080426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.422080426
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1858786647
Short name T636
Test name
Test status
Simulation time 812738274 ps
CPU time 3.19 seconds
Started Mar 21 01:56:15 PM PDT 24
Finished Mar 21 01:56:18 PM PDT 24
Peak memory 200276 kb
Host smart-5cbbb27b-f8bf-473a-80d8-6d6ea1d6a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858786647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1858786647
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.791427179
Short name T783
Test name
Test status
Simulation time 56520204233 ps
CPU time 24.27 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:56:36 PM PDT 24
Peak memory 200348 kb
Host smart-fb7bafe9-c967-483a-ac58-727d29c21575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791427179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.791427179
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1003456259
Short name T626
Test name
Test status
Simulation time 18911942 ps
CPU time 0.56 seconds
Started Mar 21 01:56:07 PM PDT 24
Finished Mar 21 01:56:08 PM PDT 24
Peak memory 195884 kb
Host smart-6c476571-8b78-4684-a147-3e420543ad98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003456259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1003456259
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1048058993
Short name T547
Test name
Test status
Simulation time 116986695825 ps
CPU time 193.53 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:59:25 PM PDT 24
Peak memory 200476 kb
Host smart-f83415e1-d108-4fff-8e17-9befd86d2b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048058993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1048058993
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4135215324
Short name T434
Test name
Test status
Simulation time 50041468091 ps
CPU time 21.21 seconds
Started Mar 21 01:56:13 PM PDT 24
Finished Mar 21 01:56:34 PM PDT 24
Peak memory 200456 kb
Host smart-8ab882c9-e761-45b4-b7a9-0413f4e89c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135215324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4135215324
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.170976103
Short name T772
Test name
Test status
Simulation time 35107804391 ps
CPU time 27.28 seconds
Started Mar 21 01:56:14 PM PDT 24
Finished Mar 21 01:56:42 PM PDT 24
Peak memory 200436 kb
Host smart-20823bd5-ba57-4963-857f-06faca9d7c78
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170976103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.170976103
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.824929222
Short name T475
Test name
Test status
Simulation time 73254418732 ps
CPU time 641.23 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 02:06:53 PM PDT 24
Peak memory 200440 kb
Host smart-27e9d961-083f-421c-8c2a-79b7ed2f95dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824929222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.824929222
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2267883138
Short name T401
Test name
Test status
Simulation time 2342124774 ps
CPU time 3.16 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 01:56:14 PM PDT 24
Peak memory 198612 kb
Host smart-70e201fc-7401-44b2-8c9b-58f4ef28b318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267883138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2267883138
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3768272155
Short name T916
Test name
Test status
Simulation time 95761609016 ps
CPU time 93.73 seconds
Started Mar 21 01:56:13 PM PDT 24
Finished Mar 21 01:57:46 PM PDT 24
Peak memory 200264 kb
Host smart-596dd2ff-3b87-4489-92c1-b4fe0d012f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768272155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3768272155
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.634042274
Short name T834
Test name
Test status
Simulation time 8467218234 ps
CPU time 474.58 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 02:04:07 PM PDT 24
Peak memory 200396 kb
Host smart-f00542f0-f733-488c-84c9-9748e05f4c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634042274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.634042274
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2570714525
Short name T550
Test name
Test status
Simulation time 4085627361 ps
CPU time 2.82 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 01:56:13 PM PDT 24
Peak memory 198604 kb
Host smart-fd045ae1-074c-4626-94f2-05c7c18c30ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570714525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2570714525
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2161938050
Short name T20
Test name
Test status
Simulation time 289133115509 ps
CPU time 190.66 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 200356 kb
Host smart-03568ad6-bfea-402b-b3fb-c30171d4fe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161938050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2161938050
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.432866402
Short name T283
Test name
Test status
Simulation time 30806773842 ps
CPU time 43.3 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:56:55 PM PDT 24
Peak memory 196504 kb
Host smart-87e8dd07-7cbb-4e2f-ba0a-6cfd1e83d0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432866402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.432866402
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4048144774
Short name T435
Test name
Test status
Simulation time 5496596998 ps
CPU time 30.01 seconds
Started Mar 21 01:56:09 PM PDT 24
Finished Mar 21 01:56:39 PM PDT 24
Peak memory 199544 kb
Host smart-4f90af58-0fc9-4a76-9548-5cc61885c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048144774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4048144774
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3020523744
Short name T204
Test name
Test status
Simulation time 394139921458 ps
CPU time 158.08 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:58:50 PM PDT 24
Peak memory 208828 kb
Host smart-99591c99-1e85-4215-ae4b-34299493f2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020523744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3020523744
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.249590785
Short name T359
Test name
Test status
Simulation time 16719664074 ps
CPU time 8.69 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:56:19 PM PDT 24
Peak memory 200264 kb
Host smart-04229d53-bc6d-4365-9348-aaa7d467f351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249590785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.249590785
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2632244703
Short name T438
Test name
Test status
Simulation time 26154359555 ps
CPU time 44.78 seconds
Started Mar 21 01:56:11 PM PDT 24
Finished Mar 21 01:56:56 PM PDT 24
Peak memory 200344 kb
Host smart-235ed0d5-3fa3-4ed0-9c04-121fcae6e243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632244703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2632244703
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2658145692
Short name T1101
Test name
Test status
Simulation time 44744851 ps
CPU time 0.55 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:56:24 PM PDT 24
Peak memory 195260 kb
Host smart-a4f5c75c-d1b3-422b-ba17-5e7a5a27c359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658145692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2658145692
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3636447693
Short name T366
Test name
Test status
Simulation time 14072187416 ps
CPU time 24.53 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 01:56:35 PM PDT 24
Peak memory 200348 kb
Host smart-ae430857-1237-43cd-a08b-77e10e51c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636447693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3636447693
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3027643731
Short name T411
Test name
Test status
Simulation time 16437467061 ps
CPU time 25.96 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:56:39 PM PDT 24
Peak memory 198860 kb
Host smart-f9a3d47d-3a7e-4b7a-a537-71fa5979c284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027643731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3027643731
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.511417110
Short name T762
Test name
Test status
Simulation time 89341303186 ps
CPU time 17.33 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:56:30 PM PDT 24
Peak memory 200444 kb
Host smart-5cd4be20-9632-442f-925d-9487ae624fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511417110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.511417110
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3685775982
Short name T837
Test name
Test status
Simulation time 10821272461 ps
CPU time 4.2 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 01:56:14 PM PDT 24
Peak memory 196556 kb
Host smart-42ff233b-cd4b-4825-8e45-85809e0cdbdb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685775982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3685775982
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1330187491
Short name T421
Test name
Test status
Simulation time 130911444009 ps
CPU time 332.29 seconds
Started Mar 21 01:56:23 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 200308 kb
Host smart-d642a12e-7a2e-4743-bf7c-10de5922c136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330187491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1330187491
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4194447128
Short name T1097
Test name
Test status
Simulation time 3340655273 ps
CPU time 3.79 seconds
Started Mar 21 01:56:23 PM PDT 24
Finished Mar 21 01:56:26 PM PDT 24
Peak memory 200392 kb
Host smart-b2d4553d-30ad-4007-bcaa-99f3017d68f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194447128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4194447128
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3218086431
Short name T868
Test name
Test status
Simulation time 70324513391 ps
CPU time 118.29 seconds
Started Mar 21 01:56:14 PM PDT 24
Finished Mar 21 01:58:12 PM PDT 24
Peak memory 200620 kb
Host smart-cde8a11d-0502-426b-bd8b-276a3848d08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218086431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3218086431
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.497655835
Short name T431
Test name
Test status
Simulation time 14979271368 ps
CPU time 457.67 seconds
Started Mar 21 01:56:31 PM PDT 24
Finished Mar 21 02:04:09 PM PDT 24
Peak memory 200308 kb
Host smart-c9af9200-0a3f-42df-b62c-2356413073fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497655835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.497655835
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.216284878
Short name T341
Test name
Test status
Simulation time 4269646666 ps
CPU time 3.16 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:56:15 PM PDT 24
Peak memory 199280 kb
Host smart-0f64c55e-7830-4275-9a1d-4f477b1f33d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216284878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.216284878
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4196309697
Short name T445
Test name
Test status
Simulation time 196136932508 ps
CPU time 83.93 seconds
Started Mar 21 01:56:29 PM PDT 24
Finished Mar 21 01:57:53 PM PDT 24
Peak memory 200436 kb
Host smart-53838a0a-b669-4c87-ab77-4134c9386490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196309697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4196309697
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1665578014
Short name T289
Test name
Test status
Simulation time 35886815416 ps
CPU time 57.24 seconds
Started Mar 21 01:56:30 PM PDT 24
Finished Mar 21 01:57:28 PM PDT 24
Peak memory 196108 kb
Host smart-63e7b1de-dcd7-4f76-8045-97cd20d2464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665578014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1665578014
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.859484747
Short name T444
Test name
Test status
Simulation time 5554201197 ps
CPU time 5.73 seconds
Started Mar 21 01:56:12 PM PDT 24
Finished Mar 21 01:56:18 PM PDT 24
Peak memory 200332 kb
Host smart-df6ca443-4442-49b5-b9d9-e154064ef9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859484747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.859484747
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2896880859
Short name T1113
Test name
Test status
Simulation time 200694304787 ps
CPU time 150.24 seconds
Started Mar 21 01:56:32 PM PDT 24
Finished Mar 21 01:59:02 PM PDT 24
Peak memory 200380 kb
Host smart-aca2caa9-53ee-4242-9737-f942cf4f8d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896880859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2896880859
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.439462219
Short name T298
Test name
Test status
Simulation time 1874174660 ps
CPU time 2.07 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:56:26 PM PDT 24
Peak memory 200128 kb
Host smart-b13b5b86-b3ba-4353-8f8f-a4170901fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439462219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.439462219
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2975680016
Short name T1092
Test name
Test status
Simulation time 54473416047 ps
CPU time 46.74 seconds
Started Mar 21 01:56:10 PM PDT 24
Finished Mar 21 01:56:57 PM PDT 24
Peak memory 200420 kb
Host smart-514722b1-a491-4b4b-9b2d-5dba3410d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975680016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2975680016
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1819750719
Short name T803
Test name
Test status
Simulation time 17459856 ps
CPU time 0.56 seconds
Started Mar 21 01:53:00 PM PDT 24
Finished Mar 21 01:53:01 PM PDT 24
Peak memory 195900 kb
Host smart-d56510ce-b085-4ca8-823f-b24a03cd559c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819750719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1819750719
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3256496939
Short name T1107
Test name
Test status
Simulation time 205014656428 ps
CPU time 433.59 seconds
Started Mar 21 01:52:59 PM PDT 24
Finished Mar 21 02:00:12 PM PDT 24
Peak memory 200432 kb
Host smart-2ce7986e-85fb-4b98-a9f4-a852cd20e508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256496939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3256496939
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1771604369
Short name T739
Test name
Test status
Simulation time 25249169879 ps
CPU time 45.07 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 200424 kb
Host smart-fe39ab53-4deb-4f2c-8893-84f0168ff079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771604369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1771604369
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3243574278
Short name T966
Test name
Test status
Simulation time 23744968930 ps
CPU time 12.93 seconds
Started Mar 21 01:53:04 PM PDT 24
Finished Mar 21 01:53:18 PM PDT 24
Peak memory 200184 kb
Host smart-97e4ef37-7eab-4d47-9e60-3219b09470e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243574278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3243574278
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3102512777
Short name T17
Test name
Test status
Simulation time 19075475114 ps
CPU time 8.8 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:53:12 PM PDT 24
Peak memory 198232 kb
Host smart-d4ef189b-cd5f-42fa-b444-a71edc7f4633
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102512777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3102512777
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3088832382
Short name T1015
Test name
Test status
Simulation time 154469288412 ps
CPU time 212 seconds
Started Mar 21 01:52:59 PM PDT 24
Finished Mar 21 01:56:31 PM PDT 24
Peak memory 200396 kb
Host smart-b3be18cf-d774-4d50-afca-f5e53992cdfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088832382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3088832382
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2676316540
Short name T360
Test name
Test status
Simulation time 4918202743 ps
CPU time 9.75 seconds
Started Mar 21 01:53:00 PM PDT 24
Finished Mar 21 01:53:10 PM PDT 24
Peak memory 199660 kb
Host smart-a9af9a0b-6326-4a41-9e95-0fbe80fb4391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676316540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2676316540
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2265841720
Short name T478
Test name
Test status
Simulation time 69045029688 ps
CPU time 51.71 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:54 PM PDT 24
Peak memory 208424 kb
Host smart-7b2013b2-db83-4550-ab0d-5a317ad473ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265841720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2265841720
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.24944270
Short name T286
Test name
Test status
Simulation time 25419937293 ps
CPU time 353.38 seconds
Started Mar 21 01:53:05 PM PDT 24
Finished Mar 21 01:58:58 PM PDT 24
Peak memory 200384 kb
Host smart-9adec7d6-4ea4-4915-ab47-37e52748f720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24944270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.24944270
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1633421399
Short name T450
Test name
Test status
Simulation time 3872654070 ps
CPU time 18.31 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:20 PM PDT 24
Peak memory 199872 kb
Host smart-65c23fd6-9a07-4cb5-81bb-89aa9d76774f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1633421399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1633421399
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4038738625
Short name T144
Test name
Test status
Simulation time 124688222160 ps
CPU time 50.02 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:52 PM PDT 24
Peak memory 200436 kb
Host smart-1d61afdf-d5a2-4e70-b326-ca9f71c17b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038738625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4038738625
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.491883412
Short name T654
Test name
Test status
Simulation time 43890332127 ps
CPU time 70.07 seconds
Started Mar 21 01:53:04 PM PDT 24
Finished Mar 21 01:54:14 PM PDT 24
Peak memory 196204 kb
Host smart-f5d34f6e-573e-4461-992d-9058ec0635f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491883412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.491883412
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_smoke.3553753222
Short name T619
Test name
Test status
Simulation time 486599263 ps
CPU time 1.5 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:03 PM PDT 24
Peak memory 199132 kb
Host smart-ad87eefb-fd1c-4a04-b114-296b2a4740bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553753222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3553753222
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2329550123
Short name T891
Test name
Test status
Simulation time 171346963891 ps
CPU time 300.45 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:58:03 PM PDT 24
Peak memory 216560 kb
Host smart-8cc9e107-6fef-4446-ab29-afec90e780ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329550123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2329550123
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.90742773
Short name T974
Test name
Test status
Simulation time 6936309961 ps
CPU time 17.02 seconds
Started Mar 21 01:53:05 PM PDT 24
Finished Mar 21 01:53:22 PM PDT 24
Peak memory 200304 kb
Host smart-ff5ad45f-8ea4-4243-ae67-0b9f91689bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90742773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.90742773
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.4013481844
Short name T791
Test name
Test status
Simulation time 28481491714 ps
CPU time 40.61 seconds
Started Mar 21 01:53:00 PM PDT 24
Finished Mar 21 01:53:41 PM PDT 24
Peak memory 200468 kb
Host smart-e8c74001-9a9a-4104-80a4-1795a8d9b4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013481844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.4013481844
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.4169078654
Short name T400
Test name
Test status
Simulation time 18245113 ps
CPU time 0.55 seconds
Started Mar 21 01:56:28 PM PDT 24
Finished Mar 21 01:56:29 PM PDT 24
Peak memory 194804 kb
Host smart-9ef2d267-396e-4bec-adee-c7615ef7e589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169078654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.4169078654
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1893149819
Short name T873
Test name
Test status
Simulation time 167510776783 ps
CPU time 230.56 seconds
Started Mar 21 01:56:32 PM PDT 24
Finished Mar 21 02:00:23 PM PDT 24
Peak memory 200360 kb
Host smart-fa5b2498-1aea-4c66-bcce-cedd9e8b10a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893149819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1893149819
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1961400732
Short name T946
Test name
Test status
Simulation time 43628673024 ps
CPU time 36.53 seconds
Started Mar 21 01:56:25 PM PDT 24
Finished Mar 21 01:57:02 PM PDT 24
Peak memory 200356 kb
Host smart-c07d7c24-7db3-40f5-a8ad-ffa9a163df57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961400732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1961400732
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1252833334
Short name T408
Test name
Test status
Simulation time 49884930400 ps
CPU time 79.55 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:57:43 PM PDT 24
Peak memory 200284 kb
Host smart-5efaeef1-63c8-4841-b577-39237ab517a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252833334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1252833334
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.4187893173
Short name T288
Test name
Test status
Simulation time 91555175189 ps
CPU time 33.01 seconds
Started Mar 21 01:56:32 PM PDT 24
Finished Mar 21 01:57:05 PM PDT 24
Peak memory 200408 kb
Host smart-c8f2efaf-cb7c-4f80-b204-8f8361f402bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187893173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.4187893173
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.180694835
Short name T683
Test name
Test status
Simulation time 51516172581 ps
CPU time 360.53 seconds
Started Mar 21 01:56:23 PM PDT 24
Finished Mar 21 02:02:24 PM PDT 24
Peak memory 200236 kb
Host smart-c5a6a18a-423a-4469-bdfe-47be1c381314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=180694835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.180694835
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.4140159782
Short name T876
Test name
Test status
Simulation time 5445943576 ps
CPU time 15.85 seconds
Started Mar 21 01:56:25 PM PDT 24
Finished Mar 21 01:56:41 PM PDT 24
Peak memory 199680 kb
Host smart-a375965d-5d45-4458-931b-6fa5ed438f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140159782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4140159782
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.442532749
Short name T631
Test name
Test status
Simulation time 81708817112 ps
CPU time 134.81 seconds
Started Mar 21 01:56:27 PM PDT 24
Finished Mar 21 01:58:42 PM PDT 24
Peak memory 200488 kb
Host smart-96ac56e8-c6ff-4c8a-a4da-2f659cb05332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442532749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.442532749
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.139739759
Short name T1024
Test name
Test status
Simulation time 9205589612 ps
CPU time 466.44 seconds
Started Mar 21 01:56:25 PM PDT 24
Finished Mar 21 02:04:12 PM PDT 24
Peak memory 200532 kb
Host smart-10354e7f-a458-46f8-8692-886d04ea54d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139739759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.139739759
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1226970404
Short name T725
Test name
Test status
Simulation time 2733788420 ps
CPU time 12.93 seconds
Started Mar 21 01:56:31 PM PDT 24
Finished Mar 21 01:56:44 PM PDT 24
Peak memory 199504 kb
Host smart-c3105d08-9053-4876-b22d-4a95c51d26e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226970404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1226970404
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.203221791
Short name T1105
Test name
Test status
Simulation time 10173756257 ps
CPU time 6.83 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:56:31 PM PDT 24
Peak memory 200420 kb
Host smart-b6b27db2-b3da-4410-85fa-a2827281bcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203221791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.203221791
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3991790994
Short name T423
Test name
Test status
Simulation time 45780003873 ps
CPU time 20.51 seconds
Started Mar 21 01:56:23 PM PDT 24
Finished Mar 21 01:56:44 PM PDT 24
Peak memory 196492 kb
Host smart-07657b19-7461-42ef-9859-511bee421b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991790994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3991790994
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1363259494
Short name T708
Test name
Test status
Simulation time 247025340 ps
CPU time 1.33 seconds
Started Mar 21 01:56:22 PM PDT 24
Finished Mar 21 01:56:24 PM PDT 24
Peak memory 198864 kb
Host smart-d5647d7e-c101-4847-9896-cc341881bbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363259494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1363259494
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1213961184
Short name T642
Test name
Test status
Simulation time 186201544801 ps
CPU time 298.31 seconds
Started Mar 21 01:56:23 PM PDT 24
Finished Mar 21 02:01:22 PM PDT 24
Peak memory 200248 kb
Host smart-01dbe99f-19e0-4fee-be77-96f362bda830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213961184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1213961184
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.358452105
Short name T1040
Test name
Test status
Simulation time 3161165718 ps
CPU time 2.19 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:56:27 PM PDT 24
Peak memory 200392 kb
Host smart-f957c742-857b-4ab4-8303-395ed59d648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358452105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.358452105
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.423136475
Short name T588
Test name
Test status
Simulation time 35515905915 ps
CPU time 29.57 seconds
Started Mar 21 01:56:27 PM PDT 24
Finished Mar 21 01:56:57 PM PDT 24
Peak memory 200368 kb
Host smart-d7ea3d4c-e91c-4fcc-8ed6-78526ca6da27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423136475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.423136475
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.87854431
Short name T378
Test name
Test status
Simulation time 13983474 ps
CPU time 0.55 seconds
Started Mar 21 01:56:25 PM PDT 24
Finished Mar 21 01:56:26 PM PDT 24
Peak memory 195160 kb
Host smart-d8a38b01-378f-4a2f-9502-6f585f76e0bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87854431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.87854431
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2527060498
Short name T722
Test name
Test status
Simulation time 124372449363 ps
CPU time 36.39 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:57:00 PM PDT 24
Peak memory 200472 kb
Host smart-eadeb734-e9cd-40ea-b20b-9069274242b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527060498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2527060498
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3988361583
Short name T1043
Test name
Test status
Simulation time 72074887325 ps
CPU time 59.95 seconds
Started Mar 21 01:56:23 PM PDT 24
Finished Mar 21 01:57:23 PM PDT 24
Peak memory 200328 kb
Host smart-ba91f83d-c2c8-4977-9cb2-36102f1538c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988361583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3988361583
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.1399675764
Short name T494
Test name
Test status
Simulation time 18062860893 ps
CPU time 26.48 seconds
Started Mar 21 01:56:25 PM PDT 24
Finished Mar 21 01:56:52 PM PDT 24
Peak memory 198260 kb
Host smart-eb2a48a7-b668-4f3b-9b13-3c8e734f5daf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399675764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1399675764
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3094252664
Short name T82
Test name
Test status
Simulation time 67280705842 ps
CPU time 111.5 seconds
Started Mar 21 01:56:25 PM PDT 24
Finished Mar 21 01:58:17 PM PDT 24
Peak memory 200416 kb
Host smart-0b03277d-c779-434b-9127-b37e9ccfef9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094252664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3094252664
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1648505620
Short name T543
Test name
Test status
Simulation time 6880614924 ps
CPU time 2.37 seconds
Started Mar 21 01:56:32 PM PDT 24
Finished Mar 21 01:56:35 PM PDT 24
Peak memory 200432 kb
Host smart-4b55a692-5e79-4de6-abf7-782fe21d04be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648505620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1648505620
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2186319396
Short name T264
Test name
Test status
Simulation time 127941013184 ps
CPU time 214.73 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:59:59 PM PDT 24
Peak memory 199300 kb
Host smart-04d6d698-f14a-4dd8-97e3-e12dac673259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186319396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2186319396
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1400852035
Short name T765
Test name
Test status
Simulation time 25073613011 ps
CPU time 335.85 seconds
Started Mar 21 01:56:31 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 200228 kb
Host smart-b79577b1-d0e7-44a9-b94f-4bbc6c53cdad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400852035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1400852035
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3703220481
Short name T306
Test name
Test status
Simulation time 6113241561 ps
CPU time 26.27 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:56:51 PM PDT 24
Peak memory 199060 kb
Host smart-f8d1c2ab-1305-4385-af02-db6525183093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703220481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3703220481
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3791503665
Short name T862
Test name
Test status
Simulation time 70382815901 ps
CPU time 58.94 seconds
Started Mar 21 01:56:23 PM PDT 24
Finished Mar 21 01:57:22 PM PDT 24
Peak memory 200384 kb
Host smart-71cf1503-3c1f-439d-b7db-8b268c8af267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791503665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3791503665
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2648396388
Short name T950
Test name
Test status
Simulation time 34989408303 ps
CPU time 49.85 seconds
Started Mar 21 01:56:27 PM PDT 24
Finished Mar 21 01:57:17 PM PDT 24
Peak memory 196512 kb
Host smart-333a281e-5de0-4160-b104-c7ec72626eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648396388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2648396388
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2543402182
Short name T713
Test name
Test status
Simulation time 472694112 ps
CPU time 2.28 seconds
Started Mar 21 01:56:27 PM PDT 24
Finished Mar 21 01:56:30 PM PDT 24
Peak memory 200100 kb
Host smart-b10f030c-8f25-483e-a601-331c99610622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543402182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2543402182
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.546132700
Short name T750
Test name
Test status
Simulation time 199146789875 ps
CPU time 516.93 seconds
Started Mar 21 01:56:23 PM PDT 24
Finished Mar 21 02:05:00 PM PDT 24
Peak memory 200408 kb
Host smart-551e07b8-921c-4953-8f87-4aa4c66d9f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546132700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.546132700
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.88075388
Short name T460
Test name
Test status
Simulation time 8986581798 ps
CPU time 12.77 seconds
Started Mar 21 01:56:31 PM PDT 24
Finished Mar 21 01:56:45 PM PDT 24
Peak memory 200444 kb
Host smart-19fe8049-3031-4f94-987a-4af8c3929732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88075388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.88075388
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.208199563
Short name T280
Test name
Test status
Simulation time 74060073360 ps
CPU time 100.54 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:58:05 PM PDT 24
Peak memory 200404 kb
Host smart-90b4a734-f2f8-4c91-a67e-bad1bfd222d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208199563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.208199563
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3076405702
Short name T338
Test name
Test status
Simulation time 12623472 ps
CPU time 0.55 seconds
Started Mar 21 01:56:37 PM PDT 24
Finished Mar 21 01:56:39 PM PDT 24
Peak memory 195884 kb
Host smart-f05dc5f9-170c-48d0-82e1-51ef8d65e0f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076405702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3076405702
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2260420539
Short name T939
Test name
Test status
Simulation time 50969213269 ps
CPU time 77.52 seconds
Started Mar 21 01:56:28 PM PDT 24
Finished Mar 21 01:57:46 PM PDT 24
Peak memory 200416 kb
Host smart-c77e3f18-bfad-4c65-ab3f-92c26d92e306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260420539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2260420539
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1329654832
Short name T671
Test name
Test status
Simulation time 84713001449 ps
CPU time 80.33 seconds
Started Mar 21 01:56:27 PM PDT 24
Finished Mar 21 01:57:48 PM PDT 24
Peak memory 200364 kb
Host smart-6b8ae58c-e540-4d1b-b72d-68fc69d4009b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329654832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1329654832
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.4217066704
Short name T232
Test name
Test status
Simulation time 22803519824 ps
CPU time 41.42 seconds
Started Mar 21 01:56:32 PM PDT 24
Finished Mar 21 01:57:13 PM PDT 24
Peak memory 200272 kb
Host smart-a49ef6c4-6685-42c7-8f15-38cd2ca0124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217066704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.4217066704
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3329259440
Short name T318
Test name
Test status
Simulation time 10187108908 ps
CPU time 21.21 seconds
Started Mar 21 01:56:35 PM PDT 24
Finished Mar 21 01:56:59 PM PDT 24
Peak memory 200376 kb
Host smart-ea60c8bc-2eb5-4164-be3a-289961556ff2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329259440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3329259440
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_loopback.3859861997
Short name T782
Test name
Test status
Simulation time 4945976635 ps
CPU time 19.16 seconds
Started Mar 21 01:56:38 PM PDT 24
Finished Mar 21 01:56:59 PM PDT 24
Peak memory 200324 kb
Host smart-ee717cd8-6a61-4f9f-80a3-a65352d1a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859861997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3859861997
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2089932027
Short name T1111
Test name
Test status
Simulation time 90340419738 ps
CPU time 187.52 seconds
Started Mar 21 01:56:36 PM PDT 24
Finished Mar 21 01:59:45 PM PDT 24
Peak memory 200340 kb
Host smart-dda37393-99f0-4274-90b9-544b55748c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089932027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2089932027
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3258195373
Short name T792
Test name
Test status
Simulation time 25637116731 ps
CPU time 1347.86 seconds
Started Mar 21 01:56:38 PM PDT 24
Finished Mar 21 02:19:08 PM PDT 24
Peak memory 200288 kb
Host smart-82691c60-c520-4d4b-913c-0e4d2ad3c342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258195373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3258195373
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2201762458
Short name T367
Test name
Test status
Simulation time 2006493304 ps
CPU time 9.35 seconds
Started Mar 21 01:56:30 PM PDT 24
Finished Mar 21 01:56:40 PM PDT 24
Peak memory 198440 kb
Host smart-f3e29f1f-a90f-4d5f-bb01-2edd1bae6e4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201762458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2201762458
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3274619075
Short name T273
Test name
Test status
Simulation time 59492035937 ps
CPU time 105.09 seconds
Started Mar 21 01:56:35 PM PDT 24
Finished Mar 21 01:58:23 PM PDT 24
Peak memory 200404 kb
Host smart-784adce3-f74b-4238-9536-8efa4774d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274619075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3274619075
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1755396252
Short name T563
Test name
Test status
Simulation time 624955047 ps
CPU time 1.44 seconds
Started Mar 21 01:56:43 PM PDT 24
Finished Mar 21 01:56:45 PM PDT 24
Peak memory 195816 kb
Host smart-be3f4f94-1bd8-4356-a7dd-ece351b825f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755396252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1755396252
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3617117593
Short name T257
Test name
Test status
Simulation time 453533894 ps
CPU time 2.48 seconds
Started Mar 21 01:56:24 PM PDT 24
Finished Mar 21 01:56:27 PM PDT 24
Peak memory 199204 kb
Host smart-aa85b187-aae7-4ecd-9b06-4cba73bc43ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617117593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3617117593
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.933197264
Short name T1020
Test name
Test status
Simulation time 2332820698 ps
CPU time 1.62 seconds
Started Mar 21 01:56:39 PM PDT 24
Finished Mar 21 01:56:42 PM PDT 24
Peak memory 199432 kb
Host smart-aa442c7e-4923-4996-9bf7-60b018f52129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933197264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.933197264
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3819003217
Short name T767
Test name
Test status
Simulation time 16398032879 ps
CPU time 14.38 seconds
Started Mar 21 01:56:25 PM PDT 24
Finished Mar 21 01:56:40 PM PDT 24
Peak memory 200308 kb
Host smart-95434464-d2a4-49ec-868d-2f4c57ce3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819003217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3819003217
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1913547987
Short name T343
Test name
Test status
Simulation time 44724660 ps
CPU time 0.56 seconds
Started Mar 21 01:56:37 PM PDT 24
Finished Mar 21 01:56:39 PM PDT 24
Peak memory 195844 kb
Host smart-35f8b74c-4822-4dd0-86b3-63dfc3035794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913547987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1913547987
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1084318643
Short name T470
Test name
Test status
Simulation time 135155071082 ps
CPU time 321.35 seconds
Started Mar 21 01:56:38 PM PDT 24
Finished Mar 21 02:02:01 PM PDT 24
Peak memory 200428 kb
Host smart-ec909303-6e2c-4d2f-bdf4-a9ba35f72dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084318643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1084318643
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.834846087
Short name T179
Test name
Test status
Simulation time 48450003137 ps
CPU time 37.61 seconds
Started Mar 21 01:56:43 PM PDT 24
Finished Mar 21 01:57:21 PM PDT 24
Peak memory 200248 kb
Host smart-ff27dcfe-c4bd-423b-a697-2a4401f6c893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834846087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.834846087
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1550666572
Short name T954
Test name
Test status
Simulation time 47538717235 ps
CPU time 21.85 seconds
Started Mar 21 01:56:35 PM PDT 24
Finished Mar 21 01:56:59 PM PDT 24
Peak memory 200384 kb
Host smart-b9f8d5f2-ce3c-4597-9cde-537835f6162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550666572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1550666572
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3280544544
Short name T1002
Test name
Test status
Simulation time 8712725744 ps
CPU time 21.8 seconds
Started Mar 21 01:56:39 PM PDT 24
Finished Mar 21 01:57:02 PM PDT 24
Peak memory 200368 kb
Host smart-bfa3830d-f904-48d3-a0d4-590903a7d93b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280544544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3280544544
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1958719074
Short name T446
Test name
Test status
Simulation time 207347555842 ps
CPU time 108.82 seconds
Started Mar 21 01:56:36 PM PDT 24
Finished Mar 21 01:58:26 PM PDT 24
Peak memory 200372 kb
Host smart-a9934d88-2fbc-4d96-9c93-b820679cc919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958719074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1958719074
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3892237919
Short name T1073
Test name
Test status
Simulation time 2706891234 ps
CPU time 2.85 seconds
Started Mar 21 01:56:36 PM PDT 24
Finished Mar 21 01:56:40 PM PDT 24
Peak memory 197772 kb
Host smart-87041fda-4421-4bf7-826f-9deae90c2d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892237919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3892237919
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2445188884
Short name T258
Test name
Test status
Simulation time 76113949874 ps
CPU time 153.9 seconds
Started Mar 21 01:56:37 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 199748 kb
Host smart-b4f4d630-ab49-4cf5-b177-a2bd6d83333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445188884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2445188884
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1978067123
Short name T515
Test name
Test status
Simulation time 18089565110 ps
CPU time 531.22 seconds
Started Mar 21 01:56:38 PM PDT 24
Finished Mar 21 02:05:31 PM PDT 24
Peak memory 200412 kb
Host smart-c3e31ff0-e8a7-4399-b0a2-a353c33609e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978067123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1978067123
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.578627255
Short name T377
Test name
Test status
Simulation time 1834442870 ps
CPU time 1.85 seconds
Started Mar 21 01:56:37 PM PDT 24
Finished Mar 21 01:56:41 PM PDT 24
Peak memory 198420 kb
Host smart-da735cec-53b2-44b8-8139-0755e5a30eb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578627255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.578627255
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1390320059
Short name T510
Test name
Test status
Simulation time 70720350518 ps
CPU time 25.73 seconds
Started Mar 21 01:56:42 PM PDT 24
Finished Mar 21 01:57:09 PM PDT 24
Peak memory 200436 kb
Host smart-73bb6677-b1cc-4c7d-b270-fae6c68aca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390320059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1390320059
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1788038712
Short name T1084
Test name
Test status
Simulation time 3956078316 ps
CPU time 7.22 seconds
Started Mar 21 01:56:36 PM PDT 24
Finished Mar 21 01:56:44 PM PDT 24
Peak memory 196480 kb
Host smart-df079b0b-8632-49a9-8ff4-37d177b74897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788038712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1788038712
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.510309805
Short name T968
Test name
Test status
Simulation time 694904182 ps
CPU time 2.46 seconds
Started Mar 21 01:56:44 PM PDT 24
Finished Mar 21 01:56:47 PM PDT 24
Peak memory 199712 kb
Host smart-56d2b4f3-ad9c-4907-8cba-e02cb3f64354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510309805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.510309805
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3722951474
Short name T620
Test name
Test status
Simulation time 2028620787 ps
CPU time 2.24 seconds
Started Mar 21 01:56:39 PM PDT 24
Finished Mar 21 01:56:43 PM PDT 24
Peak memory 198600 kb
Host smart-d5bc8d67-4905-4d54-8f6c-f70a01949fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722951474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3722951474
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.716591559
Short name T749
Test name
Test status
Simulation time 113518268734 ps
CPU time 70.9 seconds
Started Mar 21 01:56:37 PM PDT 24
Finished Mar 21 01:57:50 PM PDT 24
Peak memory 200396 kb
Host smart-8f425730-2b78-4c49-9dac-2fec3c109866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716591559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.716591559
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2647235052
Short name T363
Test name
Test status
Simulation time 12943934 ps
CPU time 0.54 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:56:49 PM PDT 24
Peak memory 195164 kb
Host smart-5da3f230-a620-4f6d-8c9b-128f91fbf621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647235052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2647235052
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4105350770
Short name T1064
Test name
Test status
Simulation time 92383738023 ps
CPU time 145.44 seconds
Started Mar 21 01:56:36 PM PDT 24
Finished Mar 21 01:59:04 PM PDT 24
Peak memory 200384 kb
Host smart-772d58dc-d297-4b72-a506-3e4e51e722bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105350770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4105350770
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2005906394
Short name T311
Test name
Test status
Simulation time 30091076368 ps
CPU time 25.3 seconds
Started Mar 21 01:56:37 PM PDT 24
Finished Mar 21 01:57:04 PM PDT 24
Peak memory 200096 kb
Host smart-a2a5146e-1762-4683-8cd3-a46ecaa542a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005906394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2005906394
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3679113582
Short name T935
Test name
Test status
Simulation time 165448397163 ps
CPU time 96.73 seconds
Started Mar 21 01:56:38 PM PDT 24
Finished Mar 21 01:58:16 PM PDT 24
Peak memory 200324 kb
Host smart-a0d8ec93-65a8-47e0-b59a-4cb2fe45e622
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679113582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3679113582
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.197246346
Short name T277
Test name
Test status
Simulation time 281164995519 ps
CPU time 147.49 seconds
Started Mar 21 01:56:47 PM PDT 24
Finished Mar 21 01:59:15 PM PDT 24
Peak memory 200368 kb
Host smart-4aa9b046-b977-4ade-92a4-0bcbd1055d2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=197246346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.197246346
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1054464296
Short name T492
Test name
Test status
Simulation time 8493171063 ps
CPU time 6.4 seconds
Started Mar 21 01:56:36 PM PDT 24
Finished Mar 21 01:56:43 PM PDT 24
Peak memory 200144 kb
Host smart-f4db2590-4be7-4a98-bc96-64a6edd61146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054464296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1054464296
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2412792668
Short name T861
Test name
Test status
Simulation time 56572243844 ps
CPU time 50.46 seconds
Started Mar 21 01:56:36 PM PDT 24
Finished Mar 21 01:57:29 PM PDT 24
Peak memory 200572 kb
Host smart-22e70e0e-62c7-4027-a549-92d8fd8dedeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412792668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2412792668
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1893766365
Short name T1093
Test name
Test status
Simulation time 16288813982 ps
CPU time 766.41 seconds
Started Mar 21 01:56:37 PM PDT 24
Finished Mar 21 02:09:25 PM PDT 24
Peak memory 200432 kb
Host smart-ea2821da-8149-4c24-9cfa-985a7a2df89f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893766365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1893766365
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2998975675
Short name T704
Test name
Test status
Simulation time 4121790750 ps
CPU time 37.96 seconds
Started Mar 21 01:56:39 PM PDT 24
Finished Mar 21 01:57:19 PM PDT 24
Peak memory 199628 kb
Host smart-dc20542d-3e5a-4f50-bf3c-93f1f95728db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998975675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2998975675
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.890175477
Short name T376
Test name
Test status
Simulation time 22083042281 ps
CPU time 30.14 seconds
Started Mar 21 01:56:42 PM PDT 24
Finished Mar 21 01:57:13 PM PDT 24
Peak memory 200136 kb
Host smart-48916b0a-4d93-4edb-9822-5319854a292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890175477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.890175477
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1563166353
Short name T586
Test name
Test status
Simulation time 26958485439 ps
CPU time 39.72 seconds
Started Mar 21 01:56:38 PM PDT 24
Finished Mar 21 01:57:19 PM PDT 24
Peak memory 196560 kb
Host smart-711866a0-67dd-4471-903c-8dcb5c287034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563166353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1563166353
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2260965589
Short name T1005
Test name
Test status
Simulation time 484611955 ps
CPU time 1.74 seconds
Started Mar 21 01:56:37 PM PDT 24
Finished Mar 21 01:56:40 PM PDT 24
Peak memory 199208 kb
Host smart-8447b605-1994-4560-8192-72a9a193d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260965589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2260965589
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2182211452
Short name T1104
Test name
Test status
Simulation time 576644012403 ps
CPU time 1578.49 seconds
Started Mar 21 01:56:51 PM PDT 24
Finished Mar 21 02:23:10 PM PDT 24
Peak memory 200404 kb
Host smart-74fce733-fbc4-410b-99cb-c9798595e721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182211452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2182211452
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.204872334
Short name T1039
Test name
Test status
Simulation time 467950246 ps
CPU time 1.89 seconds
Started Mar 21 01:56:41 PM PDT 24
Finished Mar 21 01:56:44 PM PDT 24
Peak memory 198904 kb
Host smart-2764eaf2-e9a6-4269-80d8-fe43b83d7cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204872334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.204872334
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_alert_test.3948133408
Short name T419
Test name
Test status
Simulation time 43275458 ps
CPU time 0.58 seconds
Started Mar 21 01:56:50 PM PDT 24
Finished Mar 21 01:56:51 PM PDT 24
Peak memory 195356 kb
Host smart-c94bb3a2-cca7-40ce-aa19-887b104dad5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948133408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3948133408
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3923178428
Short name T920
Test name
Test status
Simulation time 32245650253 ps
CPU time 38.03 seconds
Started Mar 21 01:56:48 PM PDT 24
Finished Mar 21 01:57:27 PM PDT 24
Peak memory 200412 kb
Host smart-604fb5e0-95aa-4aef-a249-633b6b4067d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923178428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3923178428
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.577208295
Short name T282
Test name
Test status
Simulation time 82655318555 ps
CPU time 34.41 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:57:24 PM PDT 24
Peak memory 200260 kb
Host smart-dcf1bc2e-13d2-4504-acfc-b60b82b8c959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577208295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.577208295
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4154320993
Short name T845
Test name
Test status
Simulation time 222997137577 ps
CPU time 165.17 seconds
Started Mar 21 01:56:53 PM PDT 24
Finished Mar 21 01:59:39 PM PDT 24
Peak memory 200448 kb
Host smart-f778d75b-64ff-48f3-8e1c-feb1963c412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154320993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4154320993
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3531862826
Short name T498
Test name
Test status
Simulation time 54785211500 ps
CPU time 73.55 seconds
Started Mar 21 01:56:51 PM PDT 24
Finished Mar 21 01:58:05 PM PDT 24
Peak memory 200364 kb
Host smart-8e4e6489-5ed8-4cd3-9080-deb1ad2c3c48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531862826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3531862826
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.4066814987
Short name T54
Test name
Test status
Simulation time 56524998596 ps
CPU time 397.09 seconds
Started Mar 21 01:56:51 PM PDT 24
Finished Mar 21 02:03:28 PM PDT 24
Peak memory 200360 kb
Host smart-23c62939-7467-4535-8aa3-48922a16729a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066814987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4066814987
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.620154245
Short name T379
Test name
Test status
Simulation time 6306055928 ps
CPU time 9.73 seconds
Started Mar 21 01:56:47 PM PDT 24
Finished Mar 21 01:56:57 PM PDT 24
Peak memory 199280 kb
Host smart-5e08baf6-1e05-4217-9319-84d2ea1bb2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620154245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.620154245
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.4116739994
Short name T748
Test name
Test status
Simulation time 156921305170 ps
CPU time 607.54 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 02:06:56 PM PDT 24
Peak memory 200620 kb
Host smart-734f0be1-970c-4913-9a3f-c397b5c3602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116739994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4116739994
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3752764722
Short name T1054
Test name
Test status
Simulation time 46201452997 ps
CPU time 606.84 seconds
Started Mar 21 01:56:51 PM PDT 24
Finished Mar 21 02:06:58 PM PDT 24
Peak memory 200412 kb
Host smart-b5524c7f-aee1-4064-ba8b-43ec8307b0a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752764722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3752764722
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.339063356
Short name T1096
Test name
Test status
Simulation time 2082759946 ps
CPU time 1.56 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:56:50 PM PDT 24
Peak memory 199588 kb
Host smart-b48a1a9e-837a-4a8c-b7b3-5fe5e7f958dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339063356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.339063356
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2496917564
Short name T852
Test name
Test status
Simulation time 49513519245 ps
CPU time 42.1 seconds
Started Mar 21 01:56:54 PM PDT 24
Finished Mar 21 01:57:36 PM PDT 24
Peak memory 200056 kb
Host smart-9d812f05-ff87-41c6-a9f3-3923ad8a3425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496917564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2496917564
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1252114500
Short name T380
Test name
Test status
Simulation time 1404161948 ps
CPU time 2.89 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:56:52 PM PDT 24
Peak memory 195936 kb
Host smart-97bfc916-6f5d-421b-8274-e57341b6c2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252114500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1252114500
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3334996580
Short name T945
Test name
Test status
Simulation time 6013640265 ps
CPU time 11.99 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:57:01 PM PDT 24
Peak memory 200244 kb
Host smart-06ad310f-78f8-4295-972f-debc73b83e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334996580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3334996580
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.819404859
Short name T163
Test name
Test status
Simulation time 120801001565 ps
CPU time 221.35 seconds
Started Mar 21 01:56:53 PM PDT 24
Finished Mar 21 02:00:34 PM PDT 24
Peak memory 200324 kb
Host smart-4f7a8a73-eede-4ec7-8b17-d1d0df72d13b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819404859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.819404859
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1424614242
Short name T506
Test name
Test status
Simulation time 7016359918 ps
CPU time 21.2 seconds
Started Mar 21 01:56:52 PM PDT 24
Finished Mar 21 01:57:13 PM PDT 24
Peak memory 200244 kb
Host smart-be5d888e-b74d-42d7-b028-642d3b9d3a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424614242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1424614242
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.269650816
Short name T104
Test name
Test status
Simulation time 13566484154 ps
CPU time 24.41 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:57:14 PM PDT 24
Peak memory 200404 kb
Host smart-0c13753a-c1fa-442a-92e6-552659860df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269650816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.269650816
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.849260480
Short name T638
Test name
Test status
Simulation time 22920792 ps
CPU time 0.57 seconds
Started Mar 21 01:56:50 PM PDT 24
Finished Mar 21 01:56:51 PM PDT 24
Peak memory 195188 kb
Host smart-0bc408fb-d999-4109-8e47-f26c21e64c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849260480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.849260480
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.450131921
Short name T548
Test name
Test status
Simulation time 37730426615 ps
CPU time 70.72 seconds
Started Mar 21 01:56:48 PM PDT 24
Finished Mar 21 01:57:59 PM PDT 24
Peak memory 200324 kb
Host smart-6480c424-8e52-4623-9348-19ba360c99e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450131921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.450131921
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.152688180
Short name T933
Test name
Test status
Simulation time 19194526639 ps
CPU time 14.99 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:57:04 PM PDT 24
Peak memory 199852 kb
Host smart-9f8e6049-78da-4ba1-b8e9-691601df12dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152688180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.152688180
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3734269200
Short name T207
Test name
Test status
Simulation time 27345545571 ps
CPU time 21.13 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:57:10 PM PDT 24
Peak memory 200312 kb
Host smart-47fc48c8-c99f-4394-a009-281bfac404ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734269200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3734269200
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2107494157
Short name T827
Test name
Test status
Simulation time 28850164335 ps
CPU time 17.76 seconds
Started Mar 21 01:56:53 PM PDT 24
Finished Mar 21 01:57:11 PM PDT 24
Peak memory 200044 kb
Host smart-f69fd636-7b59-4af7-a2f7-1b3797b26d6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107494157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2107494157
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1086957330
Short name T453
Test name
Test status
Simulation time 113172784711 ps
CPU time 617.81 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 02:07:07 PM PDT 24
Peak memory 200368 kb
Host smart-4e33e9a4-2515-4abc-904e-c8109e9ce3e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086957330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1086957330
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2170338057
Short name T870
Test name
Test status
Simulation time 4314936508 ps
CPU time 10.89 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:57:00 PM PDT 24
Peak memory 200048 kb
Host smart-ce537e17-32a8-4b75-99ba-002e8790da0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170338057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2170338057
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4269369562
Short name T796
Test name
Test status
Simulation time 122319720870 ps
CPU time 109.21 seconds
Started Mar 21 01:56:50 PM PDT 24
Finished Mar 21 01:58:39 PM PDT 24
Peak memory 200288 kb
Host smart-0ddf916c-e1ca-4ba6-9410-a88ecfb36f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269369562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4269369562
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2750875788
Short name T874
Test name
Test status
Simulation time 21573659021 ps
CPU time 543.32 seconds
Started Mar 21 01:56:53 PM PDT 24
Finished Mar 21 02:05:57 PM PDT 24
Peak memory 200372 kb
Host smart-02d384aa-f02b-48e6-b7c6-a468122044b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750875788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2750875788
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.171366958
Short name T374
Test name
Test status
Simulation time 6097171273 ps
CPU time 54.55 seconds
Started Mar 21 01:56:48 PM PDT 24
Finished Mar 21 01:57:43 PM PDT 24
Peak memory 198696 kb
Host smart-efed5873-8350-4452-a618-9b7ac426c8cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171366958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.171366958
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3888773073
Short name T508
Test name
Test status
Simulation time 35434905956 ps
CPU time 20.14 seconds
Started Mar 21 01:56:51 PM PDT 24
Finished Mar 21 01:57:12 PM PDT 24
Peak memory 200292 kb
Host smart-7df68f34-758a-4fec-8bf9-bc39b2ff4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888773073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3888773073
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2058389909
Short name T55
Test name
Test status
Simulation time 4498626641 ps
CPU time 7.1 seconds
Started Mar 21 01:56:52 PM PDT 24
Finished Mar 21 01:57:00 PM PDT 24
Peak memory 196792 kb
Host smart-c2f910f1-cacd-4a2c-8448-b93d86b4baf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058389909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2058389909
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3681572354
Short name T552
Test name
Test status
Simulation time 430963854 ps
CPU time 1.85 seconds
Started Mar 21 01:56:48 PM PDT 24
Finished Mar 21 01:56:50 PM PDT 24
Peak memory 199136 kb
Host smart-e0a454b0-1d95-4a95-8470-eee7d2e28913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681572354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3681572354
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.937421739
Short name T618
Test name
Test status
Simulation time 119271382498 ps
CPU time 170.36 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:59:40 PM PDT 24
Peak memory 200368 kb
Host smart-d1a1c30e-6ce3-42cf-9eb7-49139aa81ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937421739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.937421739
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.449702037
Short name T22
Test name
Test status
Simulation time 468543639 ps
CPU time 2.07 seconds
Started Mar 21 01:56:50 PM PDT 24
Finished Mar 21 01:56:52 PM PDT 24
Peak memory 200052 kb
Host smart-0afa9b71-94e3-40a6-89f7-f2a9c7370ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449702037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.449702037
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1950775015
Short name T4
Test name
Test status
Simulation time 49027682190 ps
CPU time 85.52 seconds
Started Mar 21 01:56:49 PM PDT 24
Finished Mar 21 01:58:15 PM PDT 24
Peak memory 200348 kb
Host smart-2d195bb6-5de6-4765-90b7-3592df757dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950775015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1950775015
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3617197692
Short name T10
Test name
Test status
Simulation time 27279816 ps
CPU time 0.56 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:03 PM PDT 24
Peak memory 195836 kb
Host smart-07260d76-bf2a-4617-b1a6-e0bc5acfb35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617197692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3617197692
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1421579652
Short name T648
Test name
Test status
Simulation time 148632197240 ps
CPU time 311.6 seconds
Started Mar 21 01:57:04 PM PDT 24
Finished Mar 21 02:02:15 PM PDT 24
Peak memory 200396 kb
Host smart-5b15e66a-44a7-49f0-af2f-c95bfdad3821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421579652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1421579652
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3623639060
Short name T883
Test name
Test status
Simulation time 80761112841 ps
CPU time 254.44 seconds
Started Mar 21 01:57:04 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 200440 kb
Host smart-83d517e0-49e0-4cd1-a06f-3ffa8b040946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623639060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3623639060
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.854366094
Short name T323
Test name
Test status
Simulation time 5521343802 ps
CPU time 9.3 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:11 PM PDT 24
Peak memory 200380 kb
Host smart-f59fa3cb-21d9-46ad-8134-d63a3addbe7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854366094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.854366094
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1226955124
Short name T647
Test name
Test status
Simulation time 84593050031 ps
CPU time 393.65 seconds
Started Mar 21 01:57:04 PM PDT 24
Finished Mar 21 02:03:38 PM PDT 24
Peak memory 200364 kb
Host smart-77d8911e-41b5-41b0-9a88-1b8aa12583ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226955124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1226955124
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2647219933
Short name T912
Test name
Test status
Simulation time 3122032482 ps
CPU time 5.73 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:08 PM PDT 24
Peak memory 196308 kb
Host smart-2141c0ce-4e57-4fd4-ace6-bf782ebea853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647219933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2647219933
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.549049472
Short name T663
Test name
Test status
Simulation time 2197640135 ps
CPU time 4.18 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:06 PM PDT 24
Peak memory 195124 kb
Host smart-93cb1e9a-5e75-411a-aa3c-c0afba8aa31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549049472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.549049472
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4209986187
Short name T512
Test name
Test status
Simulation time 27803495157 ps
CPU time 1604.79 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 02:23:47 PM PDT 24
Peak memory 200400 kb
Host smart-fbacae4b-9786-4db6-b137-55d67f9e2dbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209986187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4209986187
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2475525114
Short name T684
Test name
Test status
Simulation time 2233565067 ps
CPU time 8.42 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:11 PM PDT 24
Peak memory 198388 kb
Host smart-dedb7003-cffd-4929-a397-c601599b3dc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475525114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2475525114
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.4084781996
Short name T798
Test name
Test status
Simulation time 79276176795 ps
CPU time 74.64 seconds
Started Mar 21 01:57:03 PM PDT 24
Finished Mar 21 01:58:18 PM PDT 24
Peak memory 200488 kb
Host smart-d56af7e4-701a-463b-87b2-a95fac1ee226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084781996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4084781996
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3313327127
Short name T1027
Test name
Test status
Simulation time 51560758818 ps
CPU time 68.97 seconds
Started Mar 21 01:57:04 PM PDT 24
Finished Mar 21 01:58:13 PM PDT 24
Peak memory 196440 kb
Host smart-4bbe7571-949c-459e-a2bc-6d3bc7fc0dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313327127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3313327127
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2452119522
Short name T931
Test name
Test status
Simulation time 5720773915 ps
CPU time 7.53 seconds
Started Mar 21 01:56:48 PM PDT 24
Finished Mar 21 01:56:56 PM PDT 24
Peak memory 200128 kb
Host smart-97548709-fb53-469f-9f07-7af7c384b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452119522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2452119522
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.462831035
Short name T1075
Test name
Test status
Simulation time 393134410366 ps
CPU time 746.79 seconds
Started Mar 21 01:57:04 PM PDT 24
Finished Mar 21 02:09:31 PM PDT 24
Peak memory 216260 kb
Host smart-cc3021ab-ad47-49ab-a78b-a37561ed4cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462831035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.462831035
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1197455464
Short name T397
Test name
Test status
Simulation time 224087479 ps
CPU time 1.15 seconds
Started Mar 21 01:57:01 PM PDT 24
Finished Mar 21 01:57:02 PM PDT 24
Peak memory 197356 kb
Host smart-11f35724-3c35-42bb-8aa2-67a6195901f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197455464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1197455464
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3223979614
Short name T254
Test name
Test status
Simulation time 21518260568 ps
CPU time 40.42 seconds
Started Mar 21 01:57:03 PM PDT 24
Finished Mar 21 01:57:44 PM PDT 24
Peak memory 200380 kb
Host smart-951d81bd-dc03-4bac-85b3-8e2a8fce4a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223979614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3223979614
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3505267908
Short name T395
Test name
Test status
Simulation time 20607342 ps
CPU time 0.55 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:03 PM PDT 24
Peak memory 195836 kb
Host smart-f822af8a-1760-4a0b-b581-d95c4c7fea5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505267908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3505267908
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.632802821
Short name T867
Test name
Test status
Simulation time 201139716267 ps
CPU time 356.68 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 02:02:59 PM PDT 24
Peak memory 200348 kb
Host smart-1a2425af-118f-4540-934d-944f2598821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632802821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.632802821
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1473104088
Short name T810
Test name
Test status
Simulation time 87585492331 ps
CPU time 41.2 seconds
Started Mar 21 01:57:12 PM PDT 24
Finished Mar 21 01:57:53 PM PDT 24
Peak memory 200396 kb
Host smart-4ec05153-3f60-427c-a58a-db00021037b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473104088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1473104088
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2542283030
Short name T35
Test name
Test status
Simulation time 17493462718 ps
CPU time 13.41 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:15 PM PDT 24
Peak memory 200420 kb
Host smart-dcfedaa3-d72a-458c-86ae-1a630b875731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542283030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2542283030
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3032033233
Short name T848
Test name
Test status
Simulation time 111301166721 ps
CPU time 97.41 seconds
Started Mar 21 01:57:04 PM PDT 24
Finished Mar 21 01:58:42 PM PDT 24
Peak memory 200288 kb
Host smart-e79c64f2-c217-4cd0-b4d9-7bd8c88185eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032033233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3032033233
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.718486759
Short name T705
Test name
Test status
Simulation time 37912907174 ps
CPU time 180.31 seconds
Started Mar 21 01:57:03 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 200396 kb
Host smart-2fcbc75c-24c1-4e91-abde-1592307169b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=718486759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.718486759
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.980292311
Short name T497
Test name
Test status
Simulation time 5371934096 ps
CPU time 9.8 seconds
Started Mar 21 01:57:01 PM PDT 24
Finished Mar 21 01:57:11 PM PDT 24
Peak memory 198768 kb
Host smart-786f9b4b-9fc1-424c-b295-3a1860bb4155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980292311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.980292311
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.58908847
Short name T718
Test name
Test status
Simulation time 268931198653 ps
CPU time 225.71 seconds
Started Mar 21 01:57:01 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 200568 kb
Host smart-3ed91da0-48a9-4aa7-9c40-81cce53bd077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58908847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.58908847
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3213294964
Short name T716
Test name
Test status
Simulation time 10665831156 ps
CPU time 64.36 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:58:06 PM PDT 24
Peak memory 200368 kb
Host smart-6da115f5-5cea-4506-8d9a-c0dff02626a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213294964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3213294964
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3588494360
Short name T682
Test name
Test status
Simulation time 1525593678 ps
CPU time 1.48 seconds
Started Mar 21 01:57:03 PM PDT 24
Finished Mar 21 01:57:05 PM PDT 24
Peak memory 198600 kb
Host smart-41bfd218-f60f-446b-8514-1c163661ad96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588494360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3588494360
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1949668910
Short name T495
Test name
Test status
Simulation time 152836730863 ps
CPU time 54.22 seconds
Started Mar 21 01:57:04 PM PDT 24
Finished Mar 21 01:57:58 PM PDT 24
Peak memory 200424 kb
Host smart-2e7b14a8-e6c5-4968-ba1f-366160842fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949668910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1949668910
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1268774794
Short name T847
Test name
Test status
Simulation time 33796934567 ps
CPU time 55.18 seconds
Started Mar 21 01:57:01 PM PDT 24
Finished Mar 21 01:57:57 PM PDT 24
Peak memory 196504 kb
Host smart-2da884f0-29e3-4eaf-8c2f-ae88083bb857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268774794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1268774794
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.235830285
Short name T336
Test name
Test status
Simulation time 986553970 ps
CPU time 3.32 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:05 PM PDT 24
Peak memory 198640 kb
Host smart-574b44a1-7cd4-4efc-8c94-3e1d68fba81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235830285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.235830285
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2592790050
Short name T585
Test name
Test status
Simulation time 67942428884 ps
CPU time 270.87 seconds
Started Mar 21 01:57:08 PM PDT 24
Finished Mar 21 02:01:39 PM PDT 24
Peak memory 200408 kb
Host smart-df45bb72-dd93-4785-be62-d618b53a90bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592790050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2592790050
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.453285652
Short name T842
Test name
Test status
Simulation time 6684475987 ps
CPU time 11.74 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:14 PM PDT 24
Peak memory 200124 kb
Host smart-ee89f274-f90f-42c8-81e5-0f684f40048d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453285652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.453285652
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.512640520
Short name T809
Test name
Test status
Simulation time 48764620924 ps
CPU time 79.64 seconds
Started Mar 21 01:57:07 PM PDT 24
Finished Mar 21 01:58:27 PM PDT 24
Peak memory 200328 kb
Host smart-fae6fc0d-8c3a-4e7e-bab2-0682a5c74a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512640520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.512640520
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2297582709
Short name T892
Test name
Test status
Simulation time 44503903 ps
CPU time 0.55 seconds
Started Mar 21 01:57:15 PM PDT 24
Finished Mar 21 01:57:16 PM PDT 24
Peak memory 195324 kb
Host smart-7b4e54b5-8725-4684-b935-0eb9e4d87253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297582709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2297582709
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1868833402
Short name T447
Test name
Test status
Simulation time 63028596865 ps
CPU time 33.96 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:36 PM PDT 24
Peak memory 200396 kb
Host smart-f6eb1e44-78b0-47cf-a783-2ae6e92f41e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868833402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1868833402
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3385351826
Short name T272
Test name
Test status
Simulation time 30476326992 ps
CPU time 27.93 seconds
Started Mar 21 01:56:59 PM PDT 24
Finished Mar 21 01:57:27 PM PDT 24
Peak memory 200384 kb
Host smart-fd1f2755-6f6c-42dd-8376-c4eaf9c05dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385351826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3385351826
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.2677269557
Short name T509
Test name
Test status
Simulation time 42326355597 ps
CPU time 33.42 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:36 PM PDT 24
Peak memory 200324 kb
Host smart-dc67c14f-68ac-4dd7-b1d4-508247aa7039
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677269557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2677269557
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_loopback.2672844453
Short name T533
Test name
Test status
Simulation time 3848263100 ps
CPU time 2.62 seconds
Started Mar 21 01:57:15 PM PDT 24
Finished Mar 21 01:57:18 PM PDT 24
Peak memory 197148 kb
Host smart-cf6f179b-facf-4551-a344-b407612a0736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672844453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2672844453
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2498251067
Short name T549
Test name
Test status
Simulation time 199906386228 ps
CPU time 39.93 seconds
Started Mar 21 01:57:02 PM PDT 24
Finished Mar 21 01:57:42 PM PDT 24
Peak memory 200564 kb
Host smart-616cb9db-65ce-42c1-bba3-53180997bf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498251067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2498251067
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2412668219
Short name T473
Test name
Test status
Simulation time 19390282812 ps
CPU time 257.39 seconds
Started Mar 21 01:57:13 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 200416 kb
Host smart-3ce90aff-1d92-4ec3-be77-ba927e1502d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412668219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2412668219
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3112459592
Short name T813
Test name
Test status
Simulation time 6472888707 ps
CPU time 51.4 seconds
Started Mar 21 01:57:08 PM PDT 24
Finished Mar 21 01:57:59 PM PDT 24
Peak memory 199556 kb
Host smart-7d5d689f-0c18-453e-b20a-c1227fe73d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112459592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3112459592
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.835846197
Short name T869
Test name
Test status
Simulation time 118174935416 ps
CPU time 48.24 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 01:58:04 PM PDT 24
Peak memory 200360 kb
Host smart-b687b729-cfe3-4111-825e-8fd52f446396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835846197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.835846197
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.892868755
Short name T424
Test name
Test status
Simulation time 1813645246 ps
CPU time 1.42 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 01:57:17 PM PDT 24
Peak memory 195920 kb
Host smart-f883e97d-662f-45d8-81f1-f56e320b7da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892868755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.892868755
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2449933967
Short name T391
Test name
Test status
Simulation time 310029861 ps
CPU time 1.14 seconds
Started Mar 21 01:57:01 PM PDT 24
Finished Mar 21 01:57:02 PM PDT 24
Peak memory 198640 kb
Host smart-db9069b1-5da7-411c-afe7-c42a303cc556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449933967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2449933967
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.236261727
Short name T922
Test name
Test status
Simulation time 180935546660 ps
CPU time 182.28 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 200392 kb
Host smart-5155beb4-7683-4d55-9273-a9dbe44f9d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236261727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.236261727
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2755412267
Short name T1036
Test name
Test status
Simulation time 6119148158 ps
CPU time 18.21 seconds
Started Mar 21 01:57:15 PM PDT 24
Finished Mar 21 01:57:33 PM PDT 24
Peak memory 200172 kb
Host smart-ccc7ad23-b329-4916-9265-9ce889e95d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755412267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2755412267
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3628828993
Short name T528
Test name
Test status
Simulation time 107732209888 ps
CPU time 117.77 seconds
Started Mar 21 01:57:20 PM PDT 24
Finished Mar 21 01:59:18 PM PDT 24
Peak memory 200416 kb
Host smart-7aba24b1-2bff-44c9-9004-585ad80b8edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628828993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3628828993
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3100269779
Short name T393
Test name
Test status
Simulation time 156704118 ps
CPU time 0.52 seconds
Started Mar 21 01:53:25 PM PDT 24
Finished Mar 21 01:53:26 PM PDT 24
Peak memory 194872 kb
Host smart-5555bae4-0ca5-49b8-9a2c-c7bbe10912c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100269779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3100269779
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.422666132
Short name T811
Test name
Test status
Simulation time 223348065242 ps
CPU time 58.93 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:54:02 PM PDT 24
Peak memory 200420 kb
Host smart-714da4c0-ffff-4456-86b7-529bdf1c33b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422666132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.422666132
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4116428518
Short name T1048
Test name
Test status
Simulation time 167172807847 ps
CPU time 61.53 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:54:05 PM PDT 24
Peak memory 200372 kb
Host smart-08139500-d690-4e61-baed-c3952caf1a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116428518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4116428518
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1940065805
Short name T48
Test name
Test status
Simulation time 33758523331 ps
CPU time 10.68 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:53:14 PM PDT 24
Peak memory 200284 kb
Host smart-b90a6192-666a-467b-8de4-ffc7f40fe0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940065805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1940065805
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1976969593
Short name T449
Test name
Test status
Simulation time 9192981409 ps
CPU time 14.06 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:15 PM PDT 24
Peak memory 197196 kb
Host smart-2db8405f-0d1e-497e-8e6e-4727cb9bb732
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976969593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1976969593
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1656824522
Short name T355
Test name
Test status
Simulation time 67784655088 ps
CPU time 690 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 02:04:42 PM PDT 24
Peak memory 200336 kb
Host smart-d4435b18-04ec-4f1c-abe1-b4ecd8dfc2ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656824522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1656824522
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3874999877
Short name T474
Test name
Test status
Simulation time 1796448990 ps
CPU time 2.48 seconds
Started Mar 21 01:53:12 PM PDT 24
Finished Mar 21 01:53:15 PM PDT 24
Peak memory 199056 kb
Host smart-f072c7f3-5bde-4239-92a6-9d960aa900b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874999877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3874999877
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1986683967
Short name T667
Test name
Test status
Simulation time 157726921431 ps
CPU time 43.11 seconds
Started Mar 21 01:53:02 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 200584 kb
Host smart-326c917a-b91a-4d74-a5c7-7214b3dde13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986683967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1986683967
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.4242940256
Short name T1100
Test name
Test status
Simulation time 8491222512 ps
CPU time 387.19 seconds
Started Mar 21 01:53:09 PM PDT 24
Finished Mar 21 01:59:36 PM PDT 24
Peak memory 200344 kb
Host smart-773af290-8dee-4493-bd8a-bd8c93b75368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242940256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4242940256
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1004122601
Short name T908
Test name
Test status
Simulation time 3410559790 ps
CPU time 7.98 seconds
Started Mar 21 01:53:04 PM PDT 24
Finished Mar 21 01:53:12 PM PDT 24
Peak memory 199332 kb
Host smart-f92f9adb-25f0-41f9-b7a1-a926c2f81ea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004122601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1004122601
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3413556605
Short name T1085
Test name
Test status
Simulation time 304754806107 ps
CPU time 165.56 seconds
Started Mar 21 01:53:08 PM PDT 24
Finished Mar 21 01:55:54 PM PDT 24
Peak memory 200420 kb
Host smart-1dab5bf0-5a80-4133-aeba-8a19d916fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413556605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3413556605
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.606014411
Short name T746
Test name
Test status
Simulation time 81183808645 ps
CPU time 140.9 seconds
Started Mar 21 01:53:14 PM PDT 24
Finished Mar 21 01:55:36 PM PDT 24
Peak memory 196204 kb
Host smart-0831eb97-4010-4abe-a0ce-e34732272a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606014411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.606014411
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3581847739
Short name T650
Test name
Test status
Simulation time 291327813 ps
CPU time 1.39 seconds
Started Mar 21 01:53:01 PM PDT 24
Finished Mar 21 01:53:03 PM PDT 24
Peak memory 198740 kb
Host smart-dea0374c-d679-4af0-812e-dfddd1829c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581847739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3581847739
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1554216362
Short name T172
Test name
Test status
Simulation time 396299359015 ps
CPU time 1111.89 seconds
Started Mar 21 01:53:10 PM PDT 24
Finished Mar 21 02:11:43 PM PDT 24
Peak memory 200360 kb
Host smart-2d50e0a7-38b4-4cea-9b47-45f83c168975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554216362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1554216362
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.489809546
Short name T589
Test name
Test status
Simulation time 159328500106 ps
CPU time 227.54 seconds
Started Mar 21 01:53:12 PM PDT 24
Finished Mar 21 01:57:01 PM PDT 24
Peak memory 208716 kb
Host smart-5306b12e-85e2-40d3-8e00-8143f763bdd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489809546 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.489809546
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2943011121
Short name T930
Test name
Test status
Simulation time 1659062916 ps
CPU time 1.93 seconds
Started Mar 21 01:53:19 PM PDT 24
Finished Mar 21 01:53:21 PM PDT 24
Peak memory 198924 kb
Host smart-2875f488-29c3-48c1-a446-ee7f8f80375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943011121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2943011121
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1260652969
Short name T856
Test name
Test status
Simulation time 228608980055 ps
CPU time 160.24 seconds
Started Mar 21 01:53:03 PM PDT 24
Finished Mar 21 01:55:44 PM PDT 24
Peak memory 200388 kb
Host smart-633af336-4118-4210-b131-cbd5ac38243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260652969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1260652969
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2058874825
Short name T118
Test name
Test status
Simulation time 39089526316 ps
CPU time 64.25 seconds
Started Mar 21 01:57:17 PM PDT 24
Finished Mar 21 01:58:21 PM PDT 24
Peak memory 200424 kb
Host smart-eb6ed6cc-3ba6-4ec8-8a1c-e72d5c695de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058874825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2058874825
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2448854809
Short name T559
Test name
Test status
Simulation time 55126580100 ps
CPU time 43.41 seconds
Started Mar 21 01:57:15 PM PDT 24
Finished Mar 21 01:57:58 PM PDT 24
Peak memory 200344 kb
Host smart-ccc2d99b-ca2b-4239-b457-e5481fa184d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448854809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2448854809
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.318618133
Short name T806
Test name
Test status
Simulation time 46151463670 ps
CPU time 104.09 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 01:59:00 PM PDT 24
Peak memory 200324 kb
Host smart-5e417110-d9eb-4868-85e4-20585056d5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318618133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.318618133
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1947855638
Short name T965
Test name
Test status
Simulation time 5439835700 ps
CPU time 8.81 seconds
Started Mar 21 01:57:17 PM PDT 24
Finished Mar 21 01:57:26 PM PDT 24
Peak memory 200156 kb
Host smart-a231c2b7-1ed9-485f-bc94-0fd5957e04c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947855638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1947855638
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3695315429
Short name T141
Test name
Test status
Simulation time 95077027092 ps
CPU time 51.38 seconds
Started Mar 21 01:57:15 PM PDT 24
Finished Mar 21 01:58:07 PM PDT 24
Peak memory 200368 kb
Host smart-602d5d7a-d68c-4689-90ed-981490ff98a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695315429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3695315429
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3375471371
Short name T728
Test name
Test status
Simulation time 237612235682 ps
CPU time 925.67 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 02:12:42 PM PDT 24
Peak memory 225156 kb
Host smart-5039df04-e94d-4ea8-bf49-9ed97b178e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375471371 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3375471371
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.609982923
Short name T904
Test name
Test status
Simulation time 134792281324 ps
CPU time 45 seconds
Started Mar 21 01:57:14 PM PDT 24
Finished Mar 21 01:57:59 PM PDT 24
Peak memory 200164 kb
Host smart-ee983a9c-ebd3-41c1-b4a0-1a0edd64ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609982923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.609982923
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.4287995330
Short name T740
Test name
Test status
Simulation time 168125817364 ps
CPU time 179.25 seconds
Started Mar 21 01:57:17 PM PDT 24
Finished Mar 21 02:00:16 PM PDT 24
Peak memory 200376 kb
Host smart-02fe77cf-facd-498a-92e6-4460819eb5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287995330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.4287995330
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1911341018
Short name T205
Test name
Test status
Simulation time 77560320039 ps
CPU time 34.55 seconds
Started Mar 21 01:57:17 PM PDT 24
Finished Mar 21 01:57:51 PM PDT 24
Peak memory 200380 kb
Host smart-f9d23ffa-50a7-42c3-afc5-0ba9c36d69b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911341018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1911341018
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1568293905
Short name T1103
Test name
Test status
Simulation time 67237651391 ps
CPU time 61.41 seconds
Started Mar 21 01:57:19 PM PDT 24
Finished Mar 21 01:58:21 PM PDT 24
Peak memory 200440 kb
Host smart-48a3eca8-200e-4a98-ad74-00a0859590cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568293905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1568293905
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.4281095645
Short name T971
Test name
Test status
Simulation time 56805257667 ps
CPU time 649.05 seconds
Started Mar 21 01:57:16 PM PDT 24
Finished Mar 21 02:08:05 PM PDT 24
Peak memory 217072 kb
Host smart-8ee69a45-c37d-4839-993b-4a80c4e4fdb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281095645 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.4281095645
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1037985353
Short name T747
Test name
Test status
Simulation time 17117657 ps
CPU time 0.56 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 01:53:12 PM PDT 24
Peak memory 195292 kb
Host smart-55e86b77-ca11-4c9c-b11c-cb13218a7527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037985353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1037985353
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2959931215
Short name T689
Test name
Test status
Simulation time 20985115306 ps
CPU time 16.3 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 01:53:27 PM PDT 24
Peak memory 200260 kb
Host smart-7b86404f-1bb6-4421-9e3e-bd4e5c6db6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959931215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2959931215
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1059904507
Short name T516
Test name
Test status
Simulation time 19571737544 ps
CPU time 32.11 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:45 PM PDT 24
Peak memory 200256 kb
Host smart-c6fba1fa-d9d1-4569-82ba-a0cbf24d3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059904507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1059904507
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4539392
Short name T219
Test name
Test status
Simulation time 119784962492 ps
CPU time 46.6 seconds
Started Mar 21 01:53:12 PM PDT 24
Finished Mar 21 01:54:00 PM PDT 24
Peak memory 200372 kb
Host smart-35445117-5b14-4479-ace2-b68853380ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4539392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4539392
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.340273902
Short name T635
Test name
Test status
Simulation time 9654016605 ps
CPU time 5.39 seconds
Started Mar 21 01:53:25 PM PDT 24
Finished Mar 21 01:53:31 PM PDT 24
Peak memory 197880 kb
Host smart-aac12c92-4200-4e5e-8f6f-511adeed0763
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340273902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.340273902
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.193053307
Short name T769
Test name
Test status
Simulation time 111388658725 ps
CPU time 492.9 seconds
Started Mar 21 01:53:10 PM PDT 24
Finished Mar 21 02:01:24 PM PDT 24
Peak memory 200396 kb
Host smart-4ada08ae-03c9-4bce-9b9e-22e0e92475e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193053307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.193053307
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.308026265
Short name T786
Test name
Test status
Simulation time 7245386073 ps
CPU time 4.17 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:53:17 PM PDT 24
Peak memory 199292 kb
Host smart-1d3d6f19-1145-43a5-a050-2c0df1d0be25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308026265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.308026265
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.340523010
Short name T871
Test name
Test status
Simulation time 80283510661 ps
CPU time 130.12 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 01:55:22 PM PDT 24
Peak memory 208816 kb
Host smart-797954c5-efd0-486b-a10c-bee7cead84a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340523010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.340523010
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3168739729
Short name T462
Test name
Test status
Simulation time 11993949954 ps
CPU time 337.88 seconds
Started Mar 21 01:53:10 PM PDT 24
Finished Mar 21 01:58:48 PM PDT 24
Peak memory 200316 kb
Host smart-5b07fcec-f6e6-405a-aa00-e30f19892eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168739729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3168739729
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1452602398
Short name T121
Test name
Test status
Simulation time 2021286975 ps
CPU time 4.09 seconds
Started Mar 21 01:53:25 PM PDT 24
Finished Mar 21 01:53:29 PM PDT 24
Peak memory 198348 kb
Host smart-bd974208-6bb2-467c-bdb2-06f177133bea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452602398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1452602398
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2464735169
Short name T255
Test name
Test status
Simulation time 80046263384 ps
CPU time 165.86 seconds
Started Mar 21 01:53:25 PM PDT 24
Finished Mar 21 01:56:11 PM PDT 24
Peak memory 200416 kb
Host smart-49fb8f9c-9a2c-4260-a3d6-b4d5ba55b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464735169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2464735169
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3022571504
Short name T666
Test name
Test status
Simulation time 39599627425 ps
CPU time 3.89 seconds
Started Mar 21 01:53:10 PM PDT 24
Finished Mar 21 01:53:14 PM PDT 24
Peak memory 196560 kb
Host smart-abb5b044-793b-49f6-882f-8f8f9eb90f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022571504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3022571504
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2052414543
Short name T1076
Test name
Test status
Simulation time 428005641 ps
CPU time 1.77 seconds
Started Mar 21 01:53:20 PM PDT 24
Finished Mar 21 01:53:22 PM PDT 24
Peak memory 198704 kb
Host smart-054ce99b-7d02-455b-acff-70dadd47d1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052414543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2052414543
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2385510447
Short name T29
Test name
Test status
Simulation time 61782131379 ps
CPU time 876.76 seconds
Started Mar 21 01:53:10 PM PDT 24
Finished Mar 21 02:07:47 PM PDT 24
Peak memory 228836 kb
Host smart-f0093088-c7b8-4b49-b291-6af6a3df43f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385510447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2385510447
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2672819649
Short name T483
Test name
Test status
Simulation time 1369983405 ps
CPU time 2.18 seconds
Started Mar 21 01:53:14 PM PDT 24
Finished Mar 21 01:53:17 PM PDT 24
Peak memory 199400 kb
Host smart-d8a214a9-6990-4d80-af0f-35bdbe3793cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672819649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2672819649
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4249626037
Short name T414
Test name
Test status
Simulation time 72226594448 ps
CPU time 131.8 seconds
Started Mar 21 01:53:13 PM PDT 24
Finished Mar 21 01:55:25 PM PDT 24
Peak memory 200436 kb
Host smart-8c8ea457-346c-4195-a6a0-2464ca848bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249626037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4249626037
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1223394278
Short name T1011
Test name
Test status
Simulation time 61081905265 ps
CPU time 241.4 seconds
Started Mar 21 01:57:17 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 200512 kb
Host smart-01f13de5-4afc-4f08-9f53-203cca2c21c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223394278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1223394278
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3443162968
Short name T147
Test name
Test status
Simulation time 23335518232 ps
CPU time 38.67 seconds
Started Mar 21 01:57:17 PM PDT 24
Finished Mar 21 01:57:56 PM PDT 24
Peak memory 200412 kb
Host smart-4114cc1b-457f-4a23-a96f-58148685fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443162968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3443162968
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1756247970
Short name T41
Test name
Test status
Simulation time 20463357611 ps
CPU time 179.24 seconds
Started Mar 21 01:57:15 PM PDT 24
Finished Mar 21 02:00:14 PM PDT 24
Peak memory 217112 kb
Host smart-f143cb41-861a-4db0-a7de-a8a5338a163e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756247970 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1756247970
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.52290823
Short name T324
Test name
Test status
Simulation time 54790474167 ps
CPU time 23.49 seconds
Started Mar 21 01:57:19 PM PDT 24
Finished Mar 21 01:57:42 PM PDT 24
Peak memory 200440 kb
Host smart-a9b3e87d-bc6d-4696-9d0f-afc37b8640e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52290823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.52290823
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.766782679
Short name T422
Test name
Test status
Simulation time 58265507868 ps
CPU time 53.07 seconds
Started Mar 21 01:57:29 PM PDT 24
Finished Mar 21 01:58:23 PM PDT 24
Peak memory 200392 kb
Host smart-d2e4571a-1d9d-4549-8c26-97ee2f9111af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766782679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.766782679
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3892343168
Short name T143
Test name
Test status
Simulation time 21816068172 ps
CPU time 36.84 seconds
Started Mar 21 01:57:28 PM PDT 24
Finished Mar 21 01:58:06 PM PDT 24
Peak memory 200288 kb
Host smart-ac8e9cae-a019-4a88-bf5c-d8506e1fcc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892343168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3892343168
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3403122693
Short name T1008
Test name
Test status
Simulation time 100512138515 ps
CPU time 301.97 seconds
Started Mar 21 01:57:29 PM PDT 24
Finished Mar 21 02:02:31 PM PDT 24
Peak memory 217080 kb
Host smart-2691426d-d497-4b32-9713-a667a46389ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403122693 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3403122693
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.940229769
Short name T763
Test name
Test status
Simulation time 170933361505 ps
CPU time 66.17 seconds
Started Mar 21 01:57:28 PM PDT 24
Finished Mar 21 01:58:34 PM PDT 24
Peak memory 200428 kb
Host smart-92747afe-3e63-4b4f-865c-e7fb665493d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940229769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.940229769
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3875393944
Short name T691
Test name
Test status
Simulation time 60268769290 ps
CPU time 44.05 seconds
Started Mar 21 01:57:28 PM PDT 24
Finished Mar 21 01:58:13 PM PDT 24
Peak memory 200432 kb
Host smart-9aac1fbb-7617-4520-a8c7-eeacf83f840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875393944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3875393944
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.681216579
Short name T113
Test name
Test status
Simulation time 90796648183 ps
CPU time 199 seconds
Started Mar 21 01:57:27 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 216536 kb
Host smart-0110ac6e-ef98-48ad-b5c6-adb3899c26c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681216579 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.681216579
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2883051130
Short name T771
Test name
Test status
Simulation time 79439692180 ps
CPU time 63.1 seconds
Started Mar 21 01:57:27 PM PDT 24
Finished Mar 21 01:58:31 PM PDT 24
Peak memory 200424 kb
Host smart-52f37a0b-4140-4dbd-a2fa-51f6d43e87a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883051130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2883051130
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.267431317
Short name T352
Test name
Test status
Simulation time 42378434965 ps
CPU time 17.22 seconds
Started Mar 21 01:57:31 PM PDT 24
Finished Mar 21 01:57:48 PM PDT 24
Peak memory 199616 kb
Host smart-f9728f81-819a-43a6-a342-c79efdb935bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267431317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.267431317
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.275969523
Short name T1081
Test name
Test status
Simulation time 11404911 ps
CPU time 0.57 seconds
Started Mar 21 01:53:20 PM PDT 24
Finished Mar 21 01:53:20 PM PDT 24
Peak memory 195876 kb
Host smart-56297e65-dd91-4e0b-bfa6-44b43bd55f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275969523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.275969523
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.411243101
Short name T1044
Test name
Test status
Simulation time 67132853589 ps
CPU time 65.69 seconds
Started Mar 21 01:53:11 PM PDT 24
Finished Mar 21 01:54:17 PM PDT 24
Peak memory 200364 kb
Host smart-fdc2e6d5-36e6-4354-b5bb-c174a1ebe6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411243101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.411243101
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.4044377969
Short name T860
Test name
Test status
Simulation time 19226906167 ps
CPU time 30.58 seconds
Started Mar 21 01:53:15 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 200120 kb
Host smart-014527db-59eb-4e7c-a4d9-0d37da6be71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044377969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.4044377969
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.752879948
Short name T944
Test name
Test status
Simulation time 79074325696 ps
CPU time 21.6 seconds
Started Mar 21 01:53:27 PM PDT 24
Finished Mar 21 01:53:49 PM PDT 24
Peak memory 200420 kb
Host smart-80db62ef-8474-4eab-a13a-0af9422331fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752879948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.752879948
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.4292734793
Short name T316
Test name
Test status
Simulation time 36666610630 ps
CPU time 30.99 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:53:53 PM PDT 24
Peak memory 200256 kb
Host smart-2a96c328-ba8f-4f66-bae6-800d0cd2d3b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292734793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.4292734793
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3013329856
Short name T347
Test name
Test status
Simulation time 75729092565 ps
CPU time 184.12 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:56:26 PM PDT 24
Peak memory 200372 kb
Host smart-139832c2-2788-439e-9c9b-361aa526862e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013329856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3013329856
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1819402184
Short name T673
Test name
Test status
Simulation time 6100901144 ps
CPU time 2.07 seconds
Started Mar 21 01:53:24 PM PDT 24
Finished Mar 21 01:53:26 PM PDT 24
Peak memory 199252 kb
Host smart-8b443e7d-991c-45f3-a09a-f8d3bdfb28a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819402184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1819402184
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4024997578
Short name T53
Test name
Test status
Simulation time 32218054078 ps
CPU time 56.03 seconds
Started Mar 21 01:53:30 PM PDT 24
Finished Mar 21 01:54:26 PM PDT 24
Peak memory 199188 kb
Host smart-fd370a0a-a557-4a67-9e77-ffd89afd07ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024997578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4024997578
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.629762049
Short name T637
Test name
Test status
Simulation time 20681471765 ps
CPU time 298.05 seconds
Started Mar 21 01:53:22 PM PDT 24
Finished Mar 21 01:58:20 PM PDT 24
Peak memory 200400 kb
Host smart-e3d7fdea-cddc-408a-9143-6b7dce0b7e3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=629762049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.629762049
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1330011449
Short name T437
Test name
Test status
Simulation time 6741786204 ps
CPU time 15.9 seconds
Started Mar 21 01:53:23 PM PDT 24
Finished Mar 21 01:53:40 PM PDT 24
Peak memory 199472 kb
Host smart-f1fc016f-dc58-4bad-b2eb-f57bc5aa6046
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330011449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1330011449
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3227360685
Short name T964
Test name
Test status
Simulation time 78837209918 ps
CPU time 72.59 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:54:34 PM PDT 24
Peak memory 200472 kb
Host smart-df02a62c-71b4-4c05-8ee5-0a4b1b82de5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227360685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3227360685
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3735468902
Short name T471
Test name
Test status
Simulation time 41185810319 ps
CPU time 31.93 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:53:53 PM PDT 24
Peak memory 196504 kb
Host smart-46d64c2d-2b11-4791-9725-a4e492df2a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735468902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3735468902
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3876602619
Short name T1060
Test name
Test status
Simulation time 848981871 ps
CPU time 2.1 seconds
Started Mar 21 01:53:18 PM PDT 24
Finished Mar 21 01:53:20 PM PDT 24
Peak memory 200212 kb
Host smart-78e718a4-a254-4bdb-8feb-dc2ebdd2f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876602619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3876602619
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.593000942
Short name T536
Test name
Test status
Simulation time 71551310511 ps
CPU time 106.17 seconds
Started Mar 21 01:53:22 PM PDT 24
Finished Mar 21 01:55:08 PM PDT 24
Peak memory 200584 kb
Host smart-9b0c75b7-1957-4424-8ce2-f8381a174048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593000942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.593000942
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3745474148
Short name T564
Test name
Test status
Simulation time 320843026 ps
CPU time 1.37 seconds
Started Mar 21 01:53:22 PM PDT 24
Finished Mar 21 01:53:24 PM PDT 24
Peak memory 197400 kb
Host smart-7f703866-2e7a-4c35-99d5-e3fb52694b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745474148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3745474148
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.4227313191
Short name T983
Test name
Test status
Simulation time 65151048909 ps
CPU time 113.46 seconds
Started Mar 21 01:53:19 PM PDT 24
Finished Mar 21 01:55:13 PM PDT 24
Peak memory 200392 kb
Host smart-65a0589f-be44-4d25-83fc-b409c75152c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227313191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.4227313191
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2996173036
Short name T523
Test name
Test status
Simulation time 66773655717 ps
CPU time 30.45 seconds
Started Mar 21 01:57:26 PM PDT 24
Finished Mar 21 01:57:57 PM PDT 24
Peak memory 200396 kb
Host smart-609f048a-82fb-409d-90e1-9d388e79aad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996173036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2996173036
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1894254538
Short name T612
Test name
Test status
Simulation time 105338260613 ps
CPU time 82.73 seconds
Started Mar 21 01:57:31 PM PDT 24
Finished Mar 21 01:58:54 PM PDT 24
Peak memory 200368 kb
Host smart-5a85e836-26f7-4c1d-bb44-b8836c18a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894254538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1894254538
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.670298259
Short name T633
Test name
Test status
Simulation time 22381667856 ps
CPU time 16.31 seconds
Started Mar 21 01:57:29 PM PDT 24
Finished Mar 21 01:57:46 PM PDT 24
Peak memory 200208 kb
Host smart-c662544c-4e10-4ab7-8170-c067b149cb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670298259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.670298259
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2229716366
Short name T12
Test name
Test status
Simulation time 40049275528 ps
CPU time 16.35 seconds
Started Mar 21 01:57:31 PM PDT 24
Finished Mar 21 01:57:47 PM PDT 24
Peak memory 200408 kb
Host smart-80e877bb-9132-49d0-9382-5ed913781258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229716366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2229716366
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2083835235
Short name T644
Test name
Test status
Simulation time 9409631477 ps
CPU time 16.24 seconds
Started Mar 21 01:57:32 PM PDT 24
Finished Mar 21 01:57:49 PM PDT 24
Peak memory 200260 kb
Host smart-567a0132-b788-4186-85f8-22b06aa45391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083835235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2083835235
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3032623
Short name T303
Test name
Test status
Simulation time 158539843301 ps
CPU time 1086.27 seconds
Started Mar 21 01:57:27 PM PDT 24
Finished Mar 21 02:15:34 PM PDT 24
Peak memory 225280 kb
Host smart-0aff219d-2b98-4362-b564-1106ef337153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032623 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3032623
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3163152627
Short name T569
Test name
Test status
Simulation time 37919913230 ps
CPU time 16.9 seconds
Started Mar 21 01:57:28 PM PDT 24
Finished Mar 21 01:57:46 PM PDT 24
Peak memory 200300 kb
Host smart-ca799ccb-db99-4351-87ee-752907c04f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163152627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3163152627
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2597565840
Short name T1072
Test name
Test status
Simulation time 77152911317 ps
CPU time 18.35 seconds
Started Mar 21 01:57:28 PM PDT 24
Finished Mar 21 01:57:47 PM PDT 24
Peak memory 200388 kb
Host smart-eb7158ab-1aed-40ba-ab8d-cac29d1d9dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597565840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2597565840
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1525432368
Short name T724
Test name
Test status
Simulation time 30198087622 ps
CPU time 28.88 seconds
Started Mar 21 01:57:29 PM PDT 24
Finished Mar 21 01:57:58 PM PDT 24
Peak memory 200440 kb
Host smart-ba1bfc12-9f65-4bf0-a55b-ea700a2481a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525432368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1525432368
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3967949471
Short name T759
Test name
Test status
Simulation time 70128923718 ps
CPU time 23.99 seconds
Started Mar 21 01:57:28 PM PDT 24
Finished Mar 21 01:57:53 PM PDT 24
Peak memory 200252 kb
Host smart-6bb90f9f-b1fe-47d3-9041-7ec70a9c2c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967949471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3967949471
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1436481035
Short name T1086
Test name
Test status
Simulation time 26510979335 ps
CPU time 46.34 seconds
Started Mar 21 01:57:27 PM PDT 24
Finished Mar 21 01:58:13 PM PDT 24
Peak memory 200420 kb
Host smart-9877dd7a-f350-4d91-bcfa-278f08eacbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436481035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1436481035
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3161107130
Short name T797
Test name
Test status
Simulation time 24379939 ps
CPU time 0.55 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:53:44 PM PDT 24
Peak memory 195276 kb
Host smart-1d051a35-81ab-4ba4-81a1-eb63b23c50e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161107130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3161107130
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1900854559
Short name T293
Test name
Test status
Simulation time 51552122747 ps
CPU time 90.51 seconds
Started Mar 21 01:53:20 PM PDT 24
Finished Mar 21 01:54:51 PM PDT 24
Peak memory 200356 kb
Host smart-f1d558b6-9643-4fe9-9714-6060e1418920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900854559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1900854559
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1036991294
Short name T761
Test name
Test status
Simulation time 155210078652 ps
CPU time 66.08 seconds
Started Mar 21 01:53:23 PM PDT 24
Finished Mar 21 01:54:30 PM PDT 24
Peak memory 200256 kb
Host smart-b2bdacf8-f062-4f1e-bdd2-d9cd0470ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036991294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1036991294
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.709642880
Short name T537
Test name
Test status
Simulation time 48370362358 ps
CPU time 43.11 seconds
Started Mar 21 01:53:23 PM PDT 24
Finished Mar 21 01:54:07 PM PDT 24
Peak memory 200320 kb
Host smart-09077f95-2180-4d61-8655-0d81407103a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709642880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.709642880
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2328488544
Short name T986
Test name
Test status
Simulation time 190361229466 ps
CPU time 155.63 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:55:57 PM PDT 24
Peak memory 200400 kb
Host smart-e9f360a3-df60-4d05-8fe7-4827c1bd0083
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328488544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2328488544
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.154985254
Short name T1006
Test name
Test status
Simulation time 138877555923 ps
CPU time 362.15 seconds
Started Mar 21 01:53:49 PM PDT 24
Finished Mar 21 01:59:51 PM PDT 24
Peak memory 200356 kb
Host smart-8dbbe4fc-e9dc-4912-95b2-15d2a4c8aa6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154985254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.154985254
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2930818456
Short name T332
Test name
Test status
Simulation time 7092297815 ps
CPU time 9.01 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:53:53 PM PDT 24
Peak memory 199752 kb
Host smart-9c7286ac-844d-405a-86e7-ff47e66195b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930818456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2930818456
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3284213695
Short name T710
Test name
Test status
Simulation time 102400057963 ps
CPU time 92.31 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:55:19 PM PDT 24
Peak memory 208784 kb
Host smart-225c87d1-fc42-4eea-9ee8-40fe10c55a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284213695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3284213695
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2290269441
Short name T576
Test name
Test status
Simulation time 23858356254 ps
CPU time 338.23 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 200420 kb
Host smart-2d53b86c-5ae0-46de-8340-58b43f3c0aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290269441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2290269441
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3352733213
Short name T898
Test name
Test status
Simulation time 2835107711 ps
CPU time 19.91 seconds
Started Mar 21 01:53:21 PM PDT 24
Finished Mar 21 01:53:41 PM PDT 24
Peak memory 198908 kb
Host smart-bbbbf498-b40d-4845-8ce2-22024831e52b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352733213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3352733213
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4028156727
Short name T587
Test name
Test status
Simulation time 17880766754 ps
CPU time 7.15 seconds
Started Mar 21 01:53:48 PM PDT 24
Finished Mar 21 01:53:56 PM PDT 24
Peak memory 198752 kb
Host smart-f083e901-265b-46d7-813a-2ddeb2d61b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028156727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4028156727
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2703986235
Short name T565
Test name
Test status
Simulation time 38953586778 ps
CPU time 13.07 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:53:59 PM PDT 24
Peak memory 196800 kb
Host smart-49a24b16-e27a-4f60-8b99-6c1cf61998c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703986235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2703986235
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.80715844
Short name T634
Test name
Test status
Simulation time 555591427 ps
CPU time 2.51 seconds
Started Mar 21 01:53:23 PM PDT 24
Finished Mar 21 01:53:26 PM PDT 24
Peak memory 199192 kb
Host smart-f1775a07-1d28-4cf2-ad74-149c847fdb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80715844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.80715844
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3363317125
Short name T278
Test name
Test status
Simulation time 768192277834 ps
CPU time 206.33 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:57:10 PM PDT 24
Peak memory 200456 kb
Host smart-d6de8c74-9148-4d40-b08f-005cedda61c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363317125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3363317125
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.4069683664
Short name T757
Test name
Test status
Simulation time 1779070657 ps
CPU time 1.74 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 198892 kb
Host smart-555f8d5d-1845-4a80-8fd5-42db23356a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069683664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.4069683664
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2985820236
Short name T327
Test name
Test status
Simulation time 25110350482 ps
CPU time 44.98 seconds
Started Mar 21 01:57:29 PM PDT 24
Finished Mar 21 01:58:14 PM PDT 24
Peak memory 200368 kb
Host smart-38b4db77-9f92-455f-a7d8-6eb289818b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985820236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2985820236
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1843549142
Short name T889
Test name
Test status
Simulation time 27899167553 ps
CPU time 45.56 seconds
Started Mar 21 01:57:30 PM PDT 24
Finished Mar 21 01:58:16 PM PDT 24
Peak memory 200340 kb
Host smart-28abed65-2af3-4eef-a2c9-716de1b37e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843549142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1843549142
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1359246061
Short name T525
Test name
Test status
Simulation time 20932390192 ps
CPU time 251.56 seconds
Started Mar 21 01:57:29 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 208724 kb
Host smart-208d95f4-74b2-4595-adab-b04a9dd03da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359246061 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1359246061
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1657246829
Short name T171
Test name
Test status
Simulation time 35646950831 ps
CPU time 14.44 seconds
Started Mar 21 01:57:31 PM PDT 24
Finished Mar 21 01:57:46 PM PDT 24
Peak memory 200448 kb
Host smart-a8c92ac3-9b01-4cea-8b6b-a949460e16cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657246829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1657246829
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1273709221
Short name T279
Test name
Test status
Simulation time 331560017412 ps
CPU time 40.91 seconds
Started Mar 21 01:57:38 PM PDT 24
Finished Mar 21 01:58:19 PM PDT 24
Peak memory 200468 kb
Host smart-7c37b97b-da08-4b7c-9a7a-f528a0a13aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273709221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1273709221
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3098241788
Short name T558
Test name
Test status
Simulation time 239270522204 ps
CPU time 186.8 seconds
Started Mar 21 01:57:39 PM PDT 24
Finished Mar 21 02:00:46 PM PDT 24
Peak memory 217104 kb
Host smart-e250d578-d33f-4541-abc8-e3c8dc2c66c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098241788 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3098241788
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2500678475
Short name T210
Test name
Test status
Simulation time 49475931103 ps
CPU time 45.7 seconds
Started Mar 21 01:57:42 PM PDT 24
Finished Mar 21 01:58:28 PM PDT 24
Peak memory 200380 kb
Host smart-1dac0085-d522-41e3-a25b-f97875a2c446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500678475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2500678475
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3444939832
Short name T241
Test name
Test status
Simulation time 162679967429 ps
CPU time 357.96 seconds
Started Mar 21 01:57:38 PM PDT 24
Finished Mar 21 02:03:36 PM PDT 24
Peak memory 200296 kb
Host smart-4d11d55d-3421-4f26-bd1c-8f7e57972661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444939832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3444939832
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2084100066
Short name T489
Test name
Test status
Simulation time 109026525810 ps
CPU time 282.67 seconds
Started Mar 21 01:57:38 PM PDT 24
Finished Mar 21 02:02:21 PM PDT 24
Peak memory 200416 kb
Host smart-b4135d80-48aa-4570-b5e8-a5600297024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084100066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2084100066
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1725505937
Short name T249
Test name
Test status
Simulation time 160712926362 ps
CPU time 43.93 seconds
Started Mar 21 01:57:41 PM PDT 24
Finished Mar 21 01:58:25 PM PDT 24
Peak memory 200420 kb
Host smart-9ac04f1b-0f53-4450-8f05-e7e5ff03f487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725505937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1725505937
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3121008068
Short name T213
Test name
Test status
Simulation time 88155483243 ps
CPU time 38.88 seconds
Started Mar 21 01:57:40 PM PDT 24
Finished Mar 21 01:58:20 PM PDT 24
Peak memory 200444 kb
Host smart-7077da4f-79f0-4c21-b925-887bae510792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121008068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3121008068
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1850026244
Short name T1028
Test name
Test status
Simulation time 427181548168 ps
CPU time 786.85 seconds
Started Mar 21 01:57:38 PM PDT 24
Finished Mar 21 02:10:45 PM PDT 24
Peak memory 217112 kb
Host smart-a6b4a74b-e26a-41ec-a98a-b1d6ce1870fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850026244 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1850026244
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3438128212
Short name T607
Test name
Test status
Simulation time 24530961 ps
CPU time 0.58 seconds
Started Mar 21 01:53:43 PM PDT 24
Finished Mar 21 01:53:44 PM PDT 24
Peak memory 195900 kb
Host smart-b813ad9a-d0fa-426d-8119-5a87bf8cae50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438128212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3438128212
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.541276363
Short name T657
Test name
Test status
Simulation time 140237096437 ps
CPU time 60.84 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:54:47 PM PDT 24
Peak memory 200432 kb
Host smart-55822a5f-2e82-440f-b5b6-b1930625da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541276363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.541276363
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1070248578
Short name T1098
Test name
Test status
Simulation time 21286848685 ps
CPU time 31.92 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:54:17 PM PDT 24
Peak memory 200408 kb
Host smart-db4e66e5-193e-4270-b0a7-9837d6797ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070248578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1070248578
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3600802882
Short name T217
Test name
Test status
Simulation time 4415214683 ps
CPU time 7.67 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:53:53 PM PDT 24
Peak memory 200264 kb
Host smart-c26b7405-e965-4b23-98df-5357081023c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600802882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3600802882
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2388753454
Short name T539
Test name
Test status
Simulation time 132728808916 ps
CPU time 201.61 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:57:07 PM PDT 24
Peak memory 197492 kb
Host smart-6996c640-bf33-413d-9a2f-9abc1715779b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388753454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2388753454
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4195684945
Short name T794
Test name
Test status
Simulation time 186006906517 ps
CPU time 149.38 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:56:16 PM PDT 24
Peak memory 200392 kb
Host smart-a75bcde0-6645-4fe3-b487-9a421d9fe443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195684945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4195684945
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3579944801
Short name T661
Test name
Test status
Simulation time 11910787548 ps
CPU time 5.53 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:53:51 PM PDT 24
Peak memory 200280 kb
Host smart-04ede0f2-c18a-470c-ab61-2125ce4e5670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579944801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3579944801
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1752014754
Short name T829
Test name
Test status
Simulation time 33863911329 ps
CPU time 59.62 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:54:44 PM PDT 24
Peak memory 199376 kb
Host smart-30919ab3-073a-456c-9435-f5b2ad8abaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752014754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1752014754
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1501676554
Short name T1071
Test name
Test status
Simulation time 4039671540 ps
CPU time 242.7 seconds
Started Mar 21 01:53:43 PM PDT 24
Finished Mar 21 01:57:46 PM PDT 24
Peak memory 200420 kb
Host smart-d96f8e93-6576-4e3e-88d9-16abc2410510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501676554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1501676554
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2245660626
Short name T625
Test name
Test status
Simulation time 3715876022 ps
CPU time 29.7 seconds
Started Mar 21 01:53:46 PM PDT 24
Finished Mar 21 01:54:17 PM PDT 24
Peak memory 200336 kb
Host smart-6ecaebf9-72e1-4179-8a3e-93f7d0f2e389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245660626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2245660626
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.4286381840
Short name T554
Test name
Test status
Simulation time 69118859630 ps
CPU time 107.98 seconds
Started Mar 21 01:53:43 PM PDT 24
Finished Mar 21 01:55:31 PM PDT 24
Peak memory 200416 kb
Host smart-fe499119-e8e9-4bfa-b563-7ad3e17fe62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286381840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4286381840
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.899217075
Short name T458
Test name
Test status
Simulation time 7192841953 ps
CPU time 3.45 seconds
Started Mar 21 01:53:47 PM PDT 24
Finished Mar 21 01:53:51 PM PDT 24
Peak memory 196476 kb
Host smart-a59e834e-a780-475f-9d2e-779064db3a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899217075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.899217075
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3075080478
Short name T959
Test name
Test status
Simulation time 668089010 ps
CPU time 1.77 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:53:46 PM PDT 24
Peak memory 199104 kb
Host smart-5ccc0a89-f872-4e07-9bcd-be2a28030766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075080478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3075080478
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.723965379
Short name T535
Test name
Test status
Simulation time 483509186 ps
CPU time 1.91 seconds
Started Mar 21 01:53:45 PM PDT 24
Finished Mar 21 01:53:47 PM PDT 24
Peak memory 198876 kb
Host smart-442c2885-763f-45f0-8fb2-cdfc7f190357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723965379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.723965379
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3510140158
Short name T655
Test name
Test status
Simulation time 427143771215 ps
CPU time 45.99 seconds
Started Mar 21 01:53:44 PM PDT 24
Finished Mar 21 01:54:30 PM PDT 24
Peak memory 200436 kb
Host smart-9001ddaf-6afc-48ab-9de1-4fb0b9626982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510140158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3510140158
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3437981098
Short name T777
Test name
Test status
Simulation time 154636783663 ps
CPU time 71.49 seconds
Started Mar 21 01:57:40 PM PDT 24
Finished Mar 21 01:58:51 PM PDT 24
Peak memory 200388 kb
Host smart-92b8f33a-8d51-4f06-9b11-d5f92dbae324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437981098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3437981098
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2180016947
Short name T236
Test name
Test status
Simulation time 21327946363 ps
CPU time 10.8 seconds
Started Mar 21 01:57:39 PM PDT 24
Finished Mar 21 01:57:50 PM PDT 24
Peak memory 200408 kb
Host smart-e943ed3c-a567-4c34-9371-94c99a5b8201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180016947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2180016947
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3305664416
Short name T139
Test name
Test status
Simulation time 14947907421 ps
CPU time 27.3 seconds
Started Mar 21 01:57:42 PM PDT 24
Finished Mar 21 01:58:10 PM PDT 24
Peak memory 200412 kb
Host smart-4fe8e45a-1bc9-4253-8127-8bcca7d513ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305664416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3305664416
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.873375565
Short name T996
Test name
Test status
Simulation time 17664360198 ps
CPU time 25.43 seconds
Started Mar 21 01:57:40 PM PDT 24
Finished Mar 21 01:58:06 PM PDT 24
Peak memory 200356 kb
Host smart-3b6705f7-fd8e-42b1-a386-f7dba12edfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873375565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.873375565
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2540950037
Short name T251
Test name
Test status
Simulation time 86964188677 ps
CPU time 1421.25 seconds
Started Mar 21 01:57:39 PM PDT 24
Finished Mar 21 02:21:20 PM PDT 24
Peak memory 215988 kb
Host smart-1d61bc12-0aed-46ae-b661-b45cd856eed4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540950037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2540950037
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3905298001
Short name T877
Test name
Test status
Simulation time 183409753130 ps
CPU time 257.14 seconds
Started Mar 21 01:57:40 PM PDT 24
Finished Mar 21 02:01:57 PM PDT 24
Peak memory 200296 kb
Host smart-0b26102f-c7f8-48c8-9e2b-d5451d6bd199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905298001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3905298001
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2327818683
Short name T287
Test name
Test status
Simulation time 49007085580 ps
CPU time 115.06 seconds
Started Mar 21 01:57:39 PM PDT 24
Finished Mar 21 01:59:34 PM PDT 24
Peak memory 200384 kb
Host smart-c61a9e6c-d540-4a65-b46b-7eacc096ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327818683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2327818683
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2208552474
Short name T579
Test name
Test status
Simulation time 86395155051 ps
CPU time 41.08 seconds
Started Mar 21 01:57:40 PM PDT 24
Finished Mar 21 01:58:21 PM PDT 24
Peak memory 200164 kb
Host smart-ad35584e-0052-46c3-8c6d-163229bcbde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208552474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2208552474
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.4200579246
Short name T39
Test name
Test status
Simulation time 21146073245 ps
CPU time 161.04 seconds
Started Mar 21 01:57:41 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 216272 kb
Host smart-34d97c0e-3a21-4745-b396-067d3f085c16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200579246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.4200579246
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2745956473
Short name T75
Test name
Test status
Simulation time 71320065755 ps
CPU time 27.18 seconds
Started Mar 21 01:57:43 PM PDT 24
Finished Mar 21 01:58:11 PM PDT 24
Peak memory 200356 kb
Host smart-178b76fd-80da-4050-943f-16d9fec29232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745956473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2745956473
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3110052202
Short name T191
Test name
Test status
Simulation time 8063760898 ps
CPU time 14.06 seconds
Started Mar 21 01:57:39 PM PDT 24
Finished Mar 21 01:57:54 PM PDT 24
Peak memory 199940 kb
Host smart-83d2a1f8-e2f9-4775-843a-1d538dff1c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110052202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3110052202
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1404417580
Short name T175
Test name
Test status
Simulation time 71060855278 ps
CPU time 355.47 seconds
Started Mar 21 01:57:40 PM PDT 24
Finished Mar 21 02:03:36 PM PDT 24
Peak memory 216864 kb
Host smart-6c812afd-8700-4ff2-a5a7-8386e1f8ccb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404417580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1404417580
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.85825336
Short name T214
Test name
Test status
Simulation time 25426900271 ps
CPU time 25.12 seconds
Started Mar 21 01:57:37 PM PDT 24
Finished Mar 21 01:58:03 PM PDT 24
Peak memory 200304 kb
Host smart-911476dc-04f9-4f3e-b105-4a2a8d5746b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85825336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.85825336
Directory /workspace/99.uart_fifo_reset/latest
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