Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	86860	1			T1	11		T2	2		T3	13
all_values[1]	86860	1			T1	11		T2	2		T3	13
all_values[2]	86860	1			T1	11		T2	2		T3	13
all_values[3]	86860	1			T1	11		T2	2		T3	13
all_values[4]	86860	1			T1	11		T2	2		T3	13
all_values[5]	86860	1			T1	11		T2	2		T3	13
all_values[6]	86860	1			T1	11		T2	2		T3	13
all_values[7]	86860	1			T1	11		T2	2		T3	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351336

1

T1

24

T2

16

T3

35

auto[1]

343544

1

T1

64

T3

69

T4

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648177

1

T1

76

T2

13

T3

90

auto[1]

46703

1

T1

12

T2

3

T3

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24428	1			T3	3		T4	12		T5	5
all_values[0]	auto[0]	auto[1]	19575	1			T1	4		T2	2		T4	2
all_values[0]	auto[1]	auto[0]	25681	1			T4	1		T5	15		T8	3
all_values[0]	auto[1]	auto[1]	17176	1			T1	7		T3	10		T4	3
all_values[1]	auto[0]	auto[0]	41981	1			T1	5		T2	2		T4	13
all_values[1]	auto[0]	auto[1]	1666	1			T9	1		T26	4		T52	5
all_values[1]	auto[1]	auto[0]	41714	1			T1	6		T3	13		T4	5
all_values[1]	auto[1]	auto[1]	1499	1			T5	14		T12	2		T26	1
all_values[2]	auto[0]	auto[0]	37191	1			T1	5		T2	1		T3	7
all_values[2]	auto[0]	auto[1]	2323	1			T1	1		T2	1		T3	4
all_values[2]	auto[1]	auto[0]	45213	1			T1	5		T3	2		T4	12
all_values[2]	auto[1]	auto[1]	2133	1			T5	4		T6	1		T8	6
all_values[3]	auto[0]	auto[0]	44703	1			T1	1		T2	2		T3	11
all_values[3]	auto[0]	auto[1]	251	1			T15	4		T17	7		T16	1
all_values[3]	auto[1]	auto[0]	41668	1			T1	10		T3	2		T4	1
all_values[3]	auto[1]	auto[1]	238	1			T13	3		T15	5		T17	6
all_values[4]	auto[0]	auto[0]	44240	1			T1	1		T2	2		T4	2
all_values[4]	auto[0]	auto[1]	345	1			T13	6		T15	28		T17	9
all_values[4]	auto[1]	auto[0]	41875	1			T1	10		T3	13		T4	16
all_values[4]	auto[1]	auto[1]	400	1			T15	8		T17	4		T23	5
all_values[5]	auto[0]	auto[0]	45880	1			T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	126	1			T15	2		T17	6		T100	1
all_values[5]	auto[1]	auto[0]	40701	1			T1	10		T3	11		T4	3
all_values[5]	auto[1]	auto[1]	153	1			T15	5		T17	10		T100	3
all_values[6]	auto[0]	auto[0]	40733	1			T2	2		T3	3		T4	13
all_values[6]	auto[0]	auto[1]	135	1			T15	2		T17	6		T100	1
all_values[6]	auto[1]	auto[0]	45872	1			T1	11		T3	10		T4	5
all_values[6]	auto[1]	auto[1]	120	1			T15	1		T17	8		T35	2
all_values[7]	auto[0]	auto[0]	47463	1			T1	6		T2	2		T3	5
all_values[7]	auto[0]	auto[1]	296	1			T17	7		T100	16		T35	2
all_values[7]	auto[1]	auto[0]	38834	1			T1	5		T3	8		T4	14
all_values[7]	auto[1]	auto[1]	267	1			T15	6		T17	6		T100	1