Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1878	1			T1	1		T4	2		T5	1
auto[BaudRate115200]	1597	1			T3	4		T4	1		T5	3
auto[BaudRate230400]	1575	1			T1	1		T4	1		T5	2
auto[BaudRate128Kbps]	1534	1			T3	2		T4	3		T5	1
auto[BaudRate256Kbps]	1735	1			T1	2		T5	2		T8	1
auto[BaudRate1Mbps]	1475	1			T2	2		T3	1		T5	1
auto[BaudRate1p5Mbps]	992	1			T1	1		T6	3		T8	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1254	1			T1	5		T19	2		T45	8
freqs[25]	932	1			T4	7		T264	9		T360	24
freqs[48]	326	1			T9	10		T64	7		T138	10
freqs[50]	579	1			T47	6		T18	9		T268	9
freqs[100]	1065	1			T8	6		T12	9		T121	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	219	1			T1	1		T215	1		T62	9
auto[BaudRate9600]	freqs[25]	137	1			T4	2		T264	2		T326	1
auto[BaudRate9600]	freqs[48]	54	1			T64	2		T138	4		T140	1
auto[BaudRate9600]	freqs[50]	121	1			T47	1		T18	9		T268	2
auto[BaudRate9600]	freqs[100]	167	1			T8	1		T121	2		T28	1
auto[BaudRate115200]	freqs[24]	178	1			T45	1		T215	2		T62	15
auto[BaudRate115200]	freqs[25]	147	1			T4	1		T264	1		T360	6
auto[BaudRate115200]	freqs[48]	35	1			T64	1		T82	1		T123	1
auto[BaudRate115200]	freqs[50]	81	1			T47	1		T35	10		T339	1
auto[BaudRate115200]	freqs[100]	134	1			T8	1		T12	3		T42	1
auto[BaudRate230400]	freqs[24]	205	1			T1	1		T45	1		T288	1
auto[BaudRate230400]	freqs[25]	136	1			T4	1		T264	1		T360	6
auto[BaudRate230400]	freqs[48]	48	1			T9	3		T64	1		T82	1
auto[BaudRate230400]	freqs[50]	81	1			T268	1		T333	1		T35	13
auto[BaudRate230400]	freqs[100]	173	1			T8	1		T121	1		T42	1
auto[BaudRate128Kbps]	freqs[24]	158	1			T45	1		T288	1		T215	1
auto[BaudRate128Kbps]	freqs[25]	141	1			T4	3		T264	2		T360	3
auto[BaudRate128Kbps]	freqs[48]	49	1			T9	1		T138	3		T140	1
auto[BaudRate128Kbps]	freqs[50]	65	1			T268	2		T35	6		T206	2
auto[BaudRate128Kbps]	freqs[100]	144	1			T8	1		T12	2		T121	2
auto[BaudRate256Kbps]	freqs[24]	185	1			T1	2		T19	1		T45	1
auto[BaudRate256Kbps]	freqs[25]	139	1			T264	1		T360	3		T127	6
auto[BaudRate256Kbps]	freqs[48]	55	1			T9	3		T64	2		T138	1
auto[BaudRate256Kbps]	freqs[50]	73	1			T47	1		T268	1		T333	2
auto[BaudRate256Kbps]	freqs[100]	153	1			T8	1		T12	2		T121	1
auto[BaudRate1Mbps]	freqs[24]	203	1			T19	1		T45	4		T215	1
auto[BaudRate1Mbps]	freqs[25]	171	1			T264	2		T360	3		T122	2
auto[BaudRate1Mbps]	freqs[48]	40	1			T9	1		T64	1		T138	1
auto[BaudRate1Mbps]	freqs[50]	77	1			T47	3		T268	1		T333	1
auto[BaudRate1Mbps]	freqs[100]	153	1			T12	1		T55	4		T130	1
auto[BaudRate1p5Mbps]	freqs[25]	61	1			T360	3		T122	2		T127	3
auto[BaudRate1p5Mbps]	freqs[48]	45	1			T9	2		T138	1		T140	3
auto[BaudRate1p5Mbps]	freqs[50]	81	1			T268	2		T35	5		T206	1
auto[BaudRate1p5Mbps]	freqs[100]	141	1			T8	1		T12	1		T55	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded