Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	23336497	1			T1	87		T3	78		T4	31
all_levels[1]	161392	1			T3	5		T5	2		T8	1
all_levels[2]	2148	1			T3	6		T52	2		T22	1
all_levels[3]	959	1			T3	7		T6	2		T26	1
all_levels[4]	604	1			T3	2		T121	1		T47	3
all_levels[5]	469	1			T3	3		T9	2		T43	1
all_levels[6]	390	1			T3	1		T4	1		T26	2
all_levels[7]	286	1			T4	1		T6	1		T27	1
all_levels[8]	254	1			T6	1		T9	1		T26	2
all_levels[9]	213	1			T5	1		T26	1		T53	1
all_levels[10]	171	1			T129	1		T58	4		T130	1
all_levels[11]	177	1			T26	1		T48	1		T14	1
all_levels[12]	139	1			T12	3		T27	1		T52	1
all_levels[13]	156	1			T49	1		T131	1		T58	1
all_levels[14]	111	1			T14	1		T132	2		T131	1
all_levels[15]	107	1			T12	1		T47	1		T131	4
all_levels[16]	94	1			T26	2		T14	1		T133	1
all_levels[17]	83	1			T4	2		T121	2		T14	1
all_levels[18]	95	1			T49	4		T14	2		T132	2
all_levels[19]	69	1			T12	1		T121	4		T44	1
all_levels[20]	58	1			T131	1		T15	1		T134	2
all_levels[21]	49	1			T12	1		T14	1		T135	1
all_levels[22]	56	1			T26	1		T14	1		T131	1
all_levels[23]	46	1			T26	1		T53	1		T15	1
all_levels[24]	59	1			T121	1		T15	1		T36	2
all_levels[25]	40	1			T132	1		T15	1		T17	1
all_levels[26]	61	1			T4	1		T8	1		T26	1
all_levels[27]	36	1			T4	2		T26	1		T15	1
all_levels[28]	32	1			T15	1		T136	1		T137	1
all_levels[29]	40	1			T26	1		T15	1		T100	1
all_levels[30]	52	1			T15	1		T138	1		T139	1
all_levels[31]	30	1			T26	1		T132	1		T15	1
all_levels[32]	23	1			T122	2		T140	1		T141	1
all_levels[33]	21	1			T52	2		T142	1		T143	1
all_levels[34]	12	1			T15	1		T138	1		T144	1
all_levels[35]	23	1			T81	4		T145	1		T146	1
all_levels[36]	19	1			T36	1		T147	1		T148	1
all_levels[37]	21	1			T121	1		T52	1		T36	1
all_levels[38]	22	1			T149	1		T128	1		T143	1
all_levels[39]	17	1			T133	1		T150	1		T151	1
all_levels[40]	17	1			T152	1		T142	1		T153	1
all_levels[41]	16	1			T17	1		T151	1		T154	1
all_levels[42]	12	1			T16	2		T151	1		T153	1
all_levels[43]	20	1			T27	1		T133	1		T155	1
all_levels[44]	14	1			T36	1		T156	1		T157	1
all_levels[45]	6	1			T158	1		T159	1		T160	1
all_levels[46]	9	1			T157	1		T161	1		T162	1
all_levels[47]	13	1			T15	1		T163	1		T164	2
all_levels[48]	3	1			T14	1		T156	1		T165	1
all_levels[49]	14	1			T142	2		T166	1		T167	2
all_levels[50]	11	1			T152	1		T156	1		T150	1
all_levels[51]	8	1			T27	1		T128	1		T41	1
all_levels[52]	8	1			T128	1		T164	1		T168	1
all_levels[53]	8	1			T35	1		T164	1		T169	2
all_levels[54]	9	1			T170	1		T159	2		T171	1
all_levels[55]	6	1			T172	1		T173	1		T174	1
all_levels[56]	8	1			T157	1		T175	1		T176	1
all_levels[57]	9	1			T177	1		T158	1		T178	1
all_levels[58]	8	1			T44	1		T56	1		T179	1
all_levels[59]	12	1			T152	1		T150	1		T180	1
all_levels[60]	3	1			T181	1		T182	1		T183	1
all_levels[61]	4	1			T66	1		T184	1		T185	1
all_levels[62]	3	1			T37	1		T186	2		-	-
all_levels[63]	11	1			T15	1		T17	1		T187	1
all_levels[64]	105	1			T14	4		T15	2		T133	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23501520

1

T1

87

T3

102

T4

33

auto[1]

3948

1

T4

5

T5

9

T6

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[55] , all_levels[56]]	[auto[1]]	--	--	2
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61] , all_levels[62]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	23333011	1			T1	87		T3	78		T4	28
all_levels[0]	auto[1]	3486	1			T4	3		T5	8		T6	5
all_levels[1]	auto[0]	161326	1			T3	5		T5	1		T8	1
all_levels[1]	auto[1]	66	1			T5	1		T53	1		T188	4
all_levels[2]	auto[0]	2112	1			T3	6		T52	1		T22	1
all_levels[2]	auto[1]	36	1			T52	1		T43	2		T45	1
all_levels[3]	auto[0]	936	1			T3	7		T6	2		T26	1
all_levels[3]	auto[1]	23	1			T189	1		T190	3		T191	3
all_levels[4]	auto[0]	594	1			T3	2		T121	1		T47	3
all_levels[4]	auto[1]	10	1			T148	2		T192	1		T193	1
all_levels[5]	auto[0]	454	1			T3	3		T9	2		T43	1
all_levels[5]	auto[1]	15	1			T132	1		T15	1		T130	1
all_levels[6]	auto[0]	374	1			T3	1		T4	1		T26	2
all_levels[6]	auto[1]	16	1			T194	2		T172	1		T195	1
all_levels[7]	auto[0]	270	1			T4	1		T6	1		T27	1
all_levels[7]	auto[1]	16	1			T81	1		T187	1		T196	1
all_levels[8]	auto[0]	240	1			T6	1		T9	1		T26	2
all_levels[8]	auto[1]	14	1			T152	1		T78	5		T165	1
all_levels[9]	auto[0]	206	1			T5	1		T26	1		T53	1
all_levels[9]	auto[1]	7	1			T197	1		T198	1		T199	1
all_levels[10]	auto[0]	160	1			T129	1		T58	4		T130	1
all_levels[10]	auto[1]	11	1			T200	1		T137	1		T201	2
all_levels[11]	auto[0]	170	1			T26	1		T48	1		T14	1
all_levels[11]	auto[1]	7	1			T202	1		T203	1		T204	3
all_levels[12]	auto[0]	126	1			T12	1		T27	1		T52	1
all_levels[12]	auto[1]	13	1			T12	2		T17	3		T205	1
all_levels[13]	auto[0]	140	1			T49	1		T131	1		T58	1
all_levels[13]	auto[1]	16	1			T206	1		T207	1		T146	1
all_levels[14]	auto[0]	101	1			T14	1		T132	2		T131	1
all_levels[14]	auto[1]	10	1			T130	3		T208	1		T209	1
all_levels[15]	auto[0]	102	1			T12	1		T47	1		T131	2
all_levels[15]	auto[1]	5	1			T131	2		T210	1		T211	1
all_levels[16]	auto[0]	86	1			T26	2		T14	1		T133	1
all_levels[16]	auto[1]	8	1			T212	1		T213	1		T214	1
all_levels[17]	auto[0]	68	1			T4	1		T121	1		T14	1
all_levels[17]	auto[1]	15	1			T4	1		T121	1		T142	1
all_levels[18]	auto[0]	71	1			T49	1		T14	2		T132	2
all_levels[18]	auto[1]	24	1			T49	3		T215	2		T216	2
all_levels[19]	auto[0]	62	1			T12	1		T121	1		T44	1
all_levels[19]	auto[1]	7	1			T121	3		T187	1		T217	3
all_levels[20]	auto[0]	57	1			T131	1		T15	1		T134	2
all_levels[20]	auto[1]	1	1			T218	1		-	-		-	-
all_levels[21]	auto[0]	42	1			T12	1		T14	1		T135	1
all_levels[21]	auto[1]	7	1			T82	1		T41	1		T219	1
all_levels[22]	auto[0]	52	1			T26	1		T14	1		T131	1
all_levels[22]	auto[1]	4	1			T166	1		T220	2		T221	1
all_levels[23]	auto[0]	41	1			T26	1		T53	1		T15	1
all_levels[23]	auto[1]	5	1			T190	2		T169	1		T222	1
all_levels[24]	auto[0]	48	1			T121	1		T15	1		T36	1
all_levels[24]	auto[1]	11	1			T36	1		T223	4		T224	1
all_levels[25]	auto[0]	37	1			T132	1		T15	1		T17	1
all_levels[25]	auto[1]	3	1			T225	2		T226	1		-	-
all_levels[26]	auto[0]	54	1			T4	1		T8	1		T26	1
all_levels[26]	auto[1]	7	1			T227	1		T228	1		T229	1
all_levels[27]	auto[0]	32	1			T4	1		T26	1		T15	1
all_levels[27]	auto[1]	4	1			T4	1		T230	1		T231	2
all_levels[28]	auto[0]	25	1			T15	1		T136	1		T137	1
all_levels[28]	auto[1]	7	1			T232	1		T233	1		T234	2
all_levels[29]	auto[0]	34	1			T26	1		T15	1		T100	1
all_levels[29]	auto[1]	6	1			T41	2		T159	2		T235	1
all_levels[30]	auto[0]	44	1			T15	1		T138	1		T139	1
all_levels[30]	auto[1]	8	1			T165	4		T200	1		T236	2
all_levels[31]	auto[0]	27	1			T26	1		T132	1		T15	1
all_levels[31]	auto[1]	3	1			T237	2		T238	1		-	-
all_levels[32]	auto[0]	20	1			T122	1		T140	1		T141	1
all_levels[32]	auto[1]	3	1			T122	1		T239	1		T240	1
all_levels[33]	auto[0]	16	1			T52	1		T142	1		T143	1
all_levels[33]	auto[1]	5	1			T52	1		T241	1		T167	1
all_levels[34]	auto[0]	10	1			T15	1		T138	1		T144	1
all_levels[34]	auto[1]	2	1			T242	2		-	-		-	-
all_levels[35]	auto[0]	16	1			T81	1		T145	1		T146	1
all_levels[35]	auto[1]	7	1			T81	3		T243	1		T244	2
all_levels[36]	auto[0]	16	1			T36	1		T147	1		T148	1
all_levels[36]	auto[1]	3	1			T244	1		T245	2		-	-
all_levels[37]	auto[0]	19	1			T121	1		T52	1		T36	1
all_levels[37]	auto[1]	2	1			T246	2		-	-		-	-
all_levels[38]	auto[0]	18	1			T149	1		T128	1		T143	1
all_levels[38]	auto[1]	4	1			T225	1		T247	3		-	-
all_levels[39]	auto[0]	16	1			T133	1		T150	1		T151	1
all_levels[39]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[40]	auto[0]	16	1			T152	1		T142	1		T153	1
all_levels[40]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[41]	auto[0]	14	1			T17	1		T151	1		T154	1
all_levels[41]	auto[1]	2	1			T250	1		T251	1		-	-
all_levels[42]	auto[0]	11	1			T16	1		T151	1		T153	1
all_levels[42]	auto[1]	1	1			T16	1		-	-		-	-
all_levels[43]	auto[0]	14	1			T27	1		T133	1		T155	1
all_levels[43]	auto[1]	6	1			T252	1		T253	5		-	-
all_levels[44]	auto[0]	14	1			T36	1		T156	1		T157	1
all_levels[45]	auto[0]	5	1			T158	1		T159	1		T160	1
all_levels[45]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[46]	auto[0]	8	1			T157	1		T161	1		T162	1
all_levels[46]	auto[1]	1	1			T255	1		-	-		-	-
all_levels[47]	auto[0]	11	1			T15	1		T163	1		T164	1
all_levels[47]	auto[1]	2	1			T164	1		T256	1		-	-
all_levels[48]	auto[0]	3	1			T14	1		T156	1		T165	1
all_levels[49]	auto[0]	11	1			T142	1		T166	1		T167	2
all_levels[49]	auto[1]	3	1			T142	1		T257	1		T258	1
all_levels[50]	auto[0]	9	1			T152	1		T156	1		T150	1
all_levels[50]	auto[1]	2	1			T259	2		-	-		-	-
all_levels[51]	auto[0]	8	1			T27	1		T128	1		T41	1
all_levels[52]	auto[0]	8	1			T128	1		T164	1		T168	1
all_levels[53]	auto[0]	7	1			T35	1		T164	1		T169	1
all_levels[53]	auto[1]	1	1			T169	1		-	-		-	-
all_levels[54]	auto[0]	8	1			T170	1		T159	1		T171	1
all_levels[54]	auto[1]	1	1			T159	1		-	-		-	-
all_levels[55]	auto[0]	6	1			T172	1		T173	1		T174	1
all_levels[56]	auto[0]	8	1			T157	1		T175	1		T176	1
all_levels[57]	auto[0]	8	1			T177	1		T158	1		T178	1
all_levels[57]	auto[1]	1	1			T260	1		-	-		-	-
all_levels[58]	auto[0]	8	1			T44	1		T56	1		T179	1
all_levels[59]	auto[0]	8	1			T152	1		T150	1		T180	1
all_levels[59]	auto[1]	4	1			T261	4		-	-		-	-
all_levels[60]	auto[0]	3	1			T181	1		T182	1		T183	1
all_levels[61]	auto[0]	4	1			T66	1		T184	1		T185	1
all_levels[62]	auto[0]	3	1			T37	1		T186	2		-	-
all_levels[63]	auto[0]	10	1			T15	1		T17	1		T187	1
all_levels[63]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[64]	auto[0]	82	1			T14	4		T15	2		T133	1
all_levels[64]	auto[1]	23	1			T139	4		T165	1		T262	2