Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	86860	1			T1	11		T2	2		T3	13
all_pins[1]	86860	1			T1	11		T2	2		T3	13
all_pins[2]	86860	1			T1	11		T2	2		T3	13
all_pins[3]	86860	1			T1	11		T2	2		T3	13
all_pins[4]	86860	1			T1	11		T2	2		T3	13
all_pins[5]	86860	1			T1	11		T2	2		T3	13
all_pins[6]	86860	1			T1	11		T2	2		T3	13
all_pins[7]	86860	1			T1	11		T2	2		T3	13

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	672238	1			T1	81		T2	16		T3	93
values[0x1]	22642	1			T1	7		T3	11		T4	4
transitions[0x0=>0x1]	21779	1			T1	7		T3	11		T4	4
transitions[0x1=>0x0]	21355	1			T1	6		T3	10		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	69643	1			T1	4		T2	2		T3	3
all_pins[0]	values[0x1]	17217	1			T1	7		T3	10		T4	3
all_pins[0]	transitions[0x0=>0x1]	16788	1			T1	7		T3	10		T4	3
all_pins[0]	transitions[0x1=>0x0]	1065	1			T5	14		T12	2		T26	1
all_pins[1]	values[0x0]	85366	1			T1	11		T2	2		T3	13
all_pins[1]	values[0x1]	1494	1			T5	14		T12	2		T26	1
all_pins[1]	transitions[0x0=>0x1]	1396	1			T5	14		T12	1		T121	2
all_pins[1]	transitions[0x1=>0x0]	2068	1			T5	4		T6	1		T8	6
all_pins[2]	values[0x0]	84694	1			T1	11		T2	2		T3	13
all_pins[2]	values[0x1]	2166	1			T5	4		T6	1		T8	6
all_pins[2]	transitions[0x0=>0x1]	2111	1			T5	4		T6	1		T8	6
all_pins[2]	transitions[0x1=>0x0]	183	1			T13	3		T15	4		T17	5
all_pins[3]	values[0x0]	86622	1			T1	11		T2	2		T3	13
all_pins[3]	values[0x1]	238	1			T13	3		T15	5		T17	6
all_pins[3]	transitions[0x0=>0x1]	190	1			T13	3		T15	5		T17	5
all_pins[3]	transitions[0x1=>0x0]	352	1			T15	8		T17	3		T23	5
all_pins[4]	values[0x0]	86460	1			T1	11		T2	2		T3	13
all_pins[4]	values[0x1]	400	1			T15	8		T17	4		T23	5
all_pins[4]	transitions[0x0=>0x1]	345	1			T15	7		T17	3		T23	5
all_pins[4]	transitions[0x1=>0x0]	139	1			T13	1		T15	5		T17	10
all_pins[5]	values[0x0]	86666	1			T1	11		T2	2		T3	13
all_pins[5]	values[0x1]	194	1			T13	1		T15	6		T17	11
all_pins[5]	transitions[0x0=>0x1]	157	1			T13	1		T15	5		T17	9
all_pins[5]	transitions[0x1=>0x0]	629	1			T3	1		T4	1		T5	2
all_pins[6]	values[0x0]	86194	1			T1	11		T2	2		T3	12
all_pins[6]	values[0x1]	666	1			T3	1		T4	1		T5	2
all_pins[6]	transitions[0x0=>0x1]	638	1			T3	1		T4	1		T5	2
all_pins[6]	transitions[0x1=>0x0]	239	1			T15	6		T17	3		T100	1
all_pins[7]	values[0x0]	86593	1			T1	11		T2	2		T3	13
all_pins[7]	values[0x1]	267	1			T15	6		T17	6		T100	1
all_pins[7]	transitions[0x0=>0x1]	154	1			T15	5		T17	3		T35	3
all_pins[7]	transitions[0x1=>0x0]	16680	1			T1	6		T3	9		T4	2