Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6768431	1			T1	70		T3	4		T4	2
all_levels[1]	1361098	1			T1	1		T3	4		T4	22
all_levels[2]	513409	1			T1	2		T3	6		T6	3
all_levels[3]	205185	1			T1	2		T3	2		T4	5
all_levels[4]	215319	1			T1	2		T3	1		T6	1
all_levels[5]	190979	1			T1	2		T3	1		T8	7
all_levels[6]	198669	1			T3	1		T4	2		T8	1
all_levels[7]	179782	1			T3	4		T8	4		T25	3224
all_levels[8]	270606	1			T1	1		T8	2		T9	2
all_levels[9]	260155	1			T5	3		T8	1		T12	3
all_levels[10]	269728	1			T4	1		T6	1		T8	3
all_levels[11]	252481	1			T1	2		T6	3		T8	1
all_levels[12]	180384	1			T6	2		T8	2		T9	2
all_levels[13]	155193	1			T1	1		T3	23		T6	3
all_levels[14]	155865	1			T1	1		T6	1		T25	3242
all_levels[15]	217412	1			T1	2		T6	1		T9	1
all_levels[16]	208092	1			T3	4		T6	1		T8	2
all_levels[17]	360027	1			T1	2		T6	3		T9	1
all_levels[18]	165741	1			T6	2		T8	1		T9	1
all_levels[19]	163120	1			T6	1		T9	1		T25	3223
all_levels[20]	147192	1			T3	18		T6	2		T9	3
all_levels[21]	147278	1			T6	1		T9	1		T25	3240
all_levels[22]	211090	1			T25	3238		T24	3846		T51	4815
all_levels[23]	200945	1			T8	3		T9	1		T25	3227
all_levels[24]	180849	1			T8	1		T9	1		T12	5
all_levels[25]	153510	1			T6	1		T25	3208		T24	3866
all_levels[26]	450546	1			T9	4		T25	3238		T24	3824
all_levels[27]	146584	1			T6	2		T9	2		T25	3242
all_levels[28]	135278	1			T25	3241		T24	3855		T51	4792
all_levels[29]	128607	1			T25	3237		T24	3868		T51	4820
all_levels[30]	147414	1			T9	3		T25	3236		T24	17492
all_levels[31]	473948	1			T4	1		T25	5876		T24	10323
all_levels[32]	8690264	1			T3	35		T4	6		T5	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23501520

1

T1

87

T3

102

T4

33

auto[1]

3661

1

T1

1

T3

1

T4

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6766451	1			T1	69		T3	4		T4	1
all_levels[0]	auto[1]	1980	1			T1	1		T4	1		T5	6
all_levels[1]	auto[0]	1360864	1			T1	1		T3	4		T4	21
all_levels[1]	auto[1]	234	1			T4	1		T52	1		T53	1
all_levels[2]	auto[0]	513343	1			T1	2		T3	6		T6	3
all_levels[2]	auto[1]	66	1			T27	1		T100	34		T333	1
all_levels[3]	auto[0]	205103	1			T1	2		T3	2		T4	4
all_levels[3]	auto[1]	82	1			T4	1		T121	2		T215	1
all_levels[4]	auto[0]	215303	1			T1	2		T3	1		T6	1
all_levels[4]	auto[1]	16	1			T207	1		T197	2		T241	1
all_levels[5]	auto[0]	190961	1			T1	2		T3	1		T8	7
all_levels[5]	auto[1]	18	1			T16	1		T81	3		T361	2
all_levels[6]	auto[0]	198636	1			T3	1		T4	2		T8	1
all_levels[6]	auto[1]	33	1			T12	2		T36	1		T207	1
all_levels[7]	auto[0]	179626	1			T3	4		T8	4		T25	3224
all_levels[7]	auto[1]	156	1			T23	16		T341	1		T41	1
all_levels[8]	auto[0]	270579	1			T1	1		T8	2		T9	2
all_levels[8]	auto[1]	27	1			T130	3		T263	1		T100	1
all_levels[9]	auto[0]	260130	1			T5	2		T8	1		T12	3
all_levels[9]	auto[1]	25	1			T5	1		T345	2		T127	1
all_levels[10]	auto[0]	269705	1			T4	1		T6	1		T8	3
all_levels[10]	auto[1]	23	1			T45	3		T279	1		T333	1
all_levels[11]	auto[0]	252457	1			T1	2		T6	3		T8	1
all_levels[11]	auto[1]	24	1			T282	1		T287	1		T77	1
all_levels[12]	auto[0]	180353	1			T6	2		T8	2		T9	2
all_levels[12]	auto[1]	31	1			T48	1		T49	2		T329	2
all_levels[13]	auto[0]	155163	1			T1	1		T3	23		T6	3
all_levels[13]	auto[1]	30	1			T121	1		T49	1		T130	1
all_levels[14]	auto[0]	155838	1			T1	1		T6	1		T25	3242
all_levels[14]	auto[1]	27	1			T263	3		T122	2		T362	1
all_levels[15]	auto[0]	217332	1			T1	2		T6	1		T9	1
all_levels[15]	auto[1]	80	1			T15	18		T17	4		T293	1
all_levels[16]	auto[0]	208075	1			T3	4		T6	1		T8	2
all_levels[16]	auto[1]	17	1			T16	1		T134	1		T189	2
all_levels[17]	auto[0]	360006	1			T1	2		T6	3		T9	1
all_levels[17]	auto[1]	21	1			T15	1		T165	1		T273	1
all_levels[18]	auto[0]	165716	1			T6	2		T8	1		T9	1
all_levels[18]	auto[1]	25	1			T269	1		T332	1		T172	1
all_levels[19]	auto[0]	163103	1			T6	1		T9	1		T25	3223
all_levels[19]	auto[1]	17	1			T363	1		T196	1		T113	1
all_levels[20]	auto[0]	147166	1			T3	18		T6	2		T9	3
all_levels[20]	auto[1]	26	1			T36	1		T81	1		T309	4
all_levels[21]	auto[0]	147266	1			T6	1		T9	1		T25	3240
all_levels[21]	auto[1]	12	1			T138	1		T152	4		T364	1
all_levels[22]	auto[0]	211065	1			T25	3238		T24	3846		T51	4815
all_levels[22]	auto[1]	25	1			T64	1		T200	2		T227	3
all_levels[23]	auto[0]	200923	1			T8	3		T9	1		T25	3227
all_levels[23]	auto[1]	22	1			T82	1		T365	1		T366	1
all_levels[24]	auto[0]	180826	1			T8	1		T9	1		T12	3
all_levels[24]	auto[1]	23	1			T12	2		T57	1		T205	1
all_levels[25]	auto[0]	153488	1			T6	1		T25	3208		T24	3866
all_levels[25]	auto[1]	22	1			T262	1		T355	2		T341	1
all_levels[26]	auto[0]	450535	1			T9	4		T25	3238		T24	3824
all_levels[26]	auto[1]	11	1			T317	1		T140	1		T212	1
all_levels[27]	auto[0]	146579	1			T6	2		T9	2		T25	3242
all_levels[27]	auto[1]	5	1			T47	1		T361	1		T367	1
all_levels[28]	auto[0]	135261	1			T25	3241		T24	3855		T51	4792
all_levels[28]	auto[1]	17	1			T14	1		T132	1		T227	2
all_levels[29]	auto[0]	128590	1			T25	3237		T24	3868		T51	4820
all_levels[29]	auto[1]	17	1			T42	1		T321	2		T368	1
all_levels[30]	auto[0]	147403	1			T9	3		T25	3236		T24	17492
all_levels[30]	auto[1]	11	1			T369	1		T370	2		T371	2
all_levels[31]	auto[0]	473922	1			T4	1		T25	5876		T24	10323
all_levels[31]	auto[1]	26	1			T64	1		T78	3		T372	1
all_levels[32]	auto[0]	8689752	1			T3	34		T4	3		T5	1
all_levels[32]	auto[1]	512	1			T3	1		T4	3		T5	1