Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	563	1			T15	7		T17	21		T100	4
all_values[1]	563	1			T15	7		T17	21		T100	4
all_values[2]	563	1			T15	7		T17	21		T100	4
all_values[3]	563	1			T15	7		T17	21		T100	4
all_values[4]	563	1			T15	7		T17	21		T100	4
all_values[5]	563	1			T15	7		T17	21		T100	4
all_values[6]	563	1			T15	7		T17	21		T100	4
all_values[7]	563	1			T15	7		T17	21		T100	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2458

1

T15

37

T17

79

T100

20

auto[1]

2046

1

T15

19

T17

89

T100

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1610

1

T15

16

T17

55

T100

13

auto[1]

2894

1

T15

40

T17

113

T100

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2618

1

T15

31

T17

91

T100

20

auto[1]

1886

1

T15

25

T17

77

T100

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	177	1			T15	3		T17	6		T100	3
all_values[0]	auto[0]	auto[1]	auto[1]	143	1			T15	1		T17	6		T127	1
all_values[0]	auto[1]	auto[0]	auto[1]	145	1			T15	2		T17	5		T35	4
all_values[0]	auto[1]	auto[1]	auto[1]	98	1			T15	1		T17	4		T100	1
all_values[1]	auto[0]	auto[0]	auto[0]	175	1			T15	3		T17	5		T100	3
all_values[1]	auto[0]	auto[1]	auto[0]	155	1			T15	1		T17	3		T35	1
all_values[1]	auto[1]	auto[0]	auto[1]	131	1			T15	2		T17	5		T100	1
all_values[1]	auto[1]	auto[1]	auto[1]	102	1			T15	1		T17	8		T35	2
all_values[2]	auto[0]	auto[0]	auto[0]	119	1			T15	2		T17	1		T100	1
all_values[2]	auto[0]	auto[0]	auto[1]	49	1			T15	2		T17	1		T35	2
all_values[2]	auto[0]	auto[1]	auto[0]	106	1			T17	6		T127	2		T128	1
all_values[2]	auto[0]	auto[1]	auto[1]	51	1			T17	2		T100	1		T35	1
all_values[2]	auto[1]	auto[0]	auto[1]	128	1			T15	1		T17	8		T100	1
all_values[2]	auto[1]	auto[1]	auto[1]	110	1			T15	2		T17	3		T100	1
all_values[3]	auto[0]	auto[0]	auto[0]	118	1			T15	1		T17	2		T100	1
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T15	1		T17	2		T35	1
all_values[3]	auto[0]	auto[1]	auto[0]	82	1			T15	2		T17	4		T100	1
all_values[3]	auto[0]	auto[1]	auto[1]	54	1			T15	1		T17	3		T100	1
all_values[3]	auto[1]	auto[0]	auto[1]	132	1			T15	1		T17	5		T35	2
all_values[3]	auto[1]	auto[1]	auto[1]	106	1			T15	1		T17	5		T100	1
all_values[4]	auto[0]	auto[0]	auto[0]	117	1			T15	3		T17	5		T100	1
all_values[4]	auto[0]	auto[0]	auto[1]	52	1			T15	1		T17	1		T127	2
all_values[4]	auto[0]	auto[1]	auto[0]	85	1			T17	7		T35	1		T118	2
all_values[4]	auto[0]	auto[1]	auto[1]	58	1			T17	2		T100	1		T35	2
all_values[4]	auto[1]	auto[0]	auto[1]	135	1			T15	3		T17	4		T35	3
all_values[4]	auto[1]	auto[1]	auto[1]	116	1			T17	2		T100	2		T35	1
all_values[5]	auto[0]	auto[0]	auto[0]	103	1			T17	2		T35	2		T127	3
all_values[5]	auto[0]	auto[0]	auto[1]	55	1			T15	1		T17	1		T111	1
all_values[5]	auto[0]	auto[1]	auto[0]	99	1			T17	2		T35	1		T128	3
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T15	3		T17	5		T100	1
all_values[5]	auto[1]	auto[0]	auto[1]	130	1			T15	2		T17	4		T100	2
all_values[5]	auto[1]	auto[1]	auto[1]	106	1			T15	1		T17	7		T100	1
all_values[6]	auto[0]	auto[0]	auto[0]	125	1			T15	3		T17	1		T100	3
all_values[6]	auto[0]	auto[0]	auto[1]	57	1			T15	1		T17	2		T35	1
all_values[6]	auto[0]	auto[1]	auto[0]	110	1			T17	4		T35	1		T127	1
all_values[6]	auto[0]	auto[1]	auto[1]	45	1			T17	2		T35	1		T118	1
all_values[6]	auto[1]	auto[0]	auto[1]	127	1			T15	2		T17	7		T100	1
all_values[6]	auto[1]	auto[1]	auto[1]	99	1			T15	1		T17	5		T35	1
all_values[7]	auto[0]	auto[0]	auto[0]	131	1			T15	1		T17	10		T100	2
all_values[7]	auto[0]	auto[0]	auto[1]	63	1			T17	1		T35	1		T127	1
all_values[7]	auto[0]	auto[1]	auto[0]	85	1			T17	3		T100	1		T35	1
all_values[7]	auto[0]	auto[1]	auto[1]	63	1			T15	1		T17	2		T35	1
all_values[7]	auto[1]	auto[0]	auto[1]	118	1			T15	2		T17	1		T100	1
all_values[7]	auto[1]	auto[1]	auto[1]	103	1			T15	3		T17	4		T35	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal