Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99712	1			T1	2		T2	45		T3	12
all_values[1]	99712	1			T1	2		T2	45		T3	12
all_values[2]	99712	1			T1	2		T2	45		T3	12
all_values[3]	99712	1			T1	2		T2	45		T3	12
all_values[4]	99712	1			T1	2		T2	45		T3	12
all_values[5]	99712	1			T1	2		T2	45		T3	12
all_values[6]	99712	1			T1	2		T2	45		T3	12
all_values[7]	99712	1			T1	2		T2	45		T3	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

401643

1

T1

16

T2

138

T3

32

auto[1]

396053

1

T2

222

T3

64

T4

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

744961

1

T1

13

T2

313

T3

83

auto[1]

52735

1

T1

3

T2

47

T3

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27927	1			T2	13		T5	112		T11	11
all_values[0]	auto[0]	auto[1]	19269	1			T1	2		T2	5		T3	3
all_values[0]	auto[1]	auto[0]	29154	1			T2	2		T3	3		T5	18
all_values[0]	auto[1]	auto[1]	23362	1			T2	25		T3	6		T4	3
all_values[1]	auto[0]	auto[0]	46221	1			T1	2		T2	21		T3	4
all_values[1]	auto[0]	auto[1]	1464	1			T2	7		T8	1		T154	7
all_values[1]	auto[1]	auto[0]	50339	1			T2	17		T3	8		T4	3
all_values[1]	auto[1]	auto[1]	1688	1			T152	9		T57	8		T155	16
all_values[2]	auto[0]	auto[0]	49824	1			T1	1		T2	21		T3	2
all_values[2]	auto[0]	auto[1]	2405	1			T1	1		T2	4		T3	1
all_values[2]	auto[1]	auto[0]	45254	1			T2	14		T3	6		T5	139
all_values[2]	auto[1]	auto[1]	2229	1			T2	6		T3	3		T5	5
all_values[3]	auto[0]	auto[0]	50023	1			T1	2		T2	11		T3	5
all_values[3]	auto[0]	auto[1]	262	1			T13	1		T46	1		T164	2
all_values[3]	auto[1]	auto[0]	49201	1			T2	34		T3	7		T4	3
all_values[3]	auto[1]	auto[1]	226	1			T8	1		T12	1		T163	2
all_values[4]	auto[0]	auto[0]	51266	1			T1	2		T2	15		T3	5
all_values[4]	auto[0]	auto[1]	445	1			T16	1		T275	2		T276	2
all_values[4]	auto[1]	auto[0]	47624	1			T2	30		T3	7		T5	92
all_values[4]	auto[1]	auto[1]	377	1			T28	1		T155	1		T16	3
all_values[5]	auto[0]	auto[0]	48912	1			T1	2		T2	28		T3	4
all_values[5]	auto[0]	auto[1]	110	1			T16	1		T17	4		T101	4
all_values[5]	auto[1]	auto[0]	50553	1			T2	17		T3	8		T4	3
all_values[5]	auto[1]	auto[1]	137	1			T16	3		T17	3		T31	2
all_values[6]	auto[0]	auto[0]	53597	1			T1	2		T2	10		T3	6
all_values[6]	auto[0]	auto[1]	144	1			T16	2		T17	2		T101	4
all_values[6]	auto[1]	auto[0]	45850	1			T2	35		T3	6		T5	71
all_values[6]	auto[1]	auto[1]	121	1			T16	1		T17	1		T101	4
all_values[7]	auto[0]	auto[0]	49533	1			T1	2		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	241	1			T19	2		T20	2		T29	1
all_values[7]	auto[1]	auto[0]	49683	1			T2	42		T3	10		T4	3
all_values[7]	auto[1]	auto[1]	255	1			T19	2		T57	2		T16	2