Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2013

1

T1

1

T2

1

T3

1

auto[UartRx]

2013

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3874	1			T1	2		T2	2		T3	2
values[1]	21	1			T30	1		T40	1		T43	1
values[2]	12	1			T21	1		T40	1		T45	1
values[3]	13	1			T40	1		T41	1		T122	1
values[4]	15	1			T39	1		T42	3		T44	1
values[5]	15	1			T31	2		T42	1		T43	1
values[6]	14	1			T31	1		T40	1		T43	1
values[7]	13	1			T39	1		T42	2		T43	1
values[8]	10	1			T21	2		T30	1		T39	1
values[9]	13	1			T31	2		T45	1		T195	1
values[10]	17	1			T30	1		T39	2		T43	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	1975	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	8	1			T40	1		T43	1		T349	1
auto[UartTx]	values[2]	4	1			T126	1		T127	1		T350	1
auto[UartTx]	values[3]	3	1			T62	1		T125	1		T351	1
auto[UartTx]	values[4]	5	1			T39	1		T44	1		T352	1
auto[UartTx]	values[5]	2	1			T42	1		T353	1		-	-
auto[UartTx]	values[6]	1	1			T43	1		-	-		-	-
auto[UartTx]	values[7]	4	1			T42	1		T195	1		T354	1
auto[UartTx]	values[8]	2	1			T42	1		T69	1		-	-
auto[UartTx]	values[9]	3	1			T31	1		T258	1		T355	1
auto[UartTx]	values[10]	5	1			T30	1		T258	1		T125	1
auto[UartRx]	values[0]	1899	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	13	1			T30	1		T195	1		T349	1
auto[UartRx]	values[2]	8	1			T21	1		T40	1		T45	1
auto[UartRx]	values[3]	10	1			T40	1		T41	1		T122	1
auto[UartRx]	values[4]	10	1			T42	3		T59	1		T62	1
auto[UartRx]	values[5]	13	1			T31	2		T43	1		T356	1
auto[UartRx]	values[6]	13	1			T31	1		T40	1		T44	1
auto[UartRx]	values[7]	9	1			T39	1		T42	1		T43	1
auto[UartRx]	values[8]	8	1			T21	2		T30	1		T39	1
auto[UartRx]	values[9]	10	1			T31	1		T45	1		T195	1
auto[UartRx]	values[10]	12	1			T39	2		T43	1		T195	1