Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1900	1			T2	1		T3	3		T4	2
auto[BaudRate115200]	1510	1			T1	1		T2	1		T3	1
auto[BaudRate230400]	1585	1			T3	2		T4	1		T7	2
auto[BaudRate128Kbps]	1539	1			T3	1		T4	2		T7	2
auto[BaudRate256Kbps]	1677	1			T2	1		T3	2		T4	1
auto[BaudRate1Mbps]	1452	1			T2	2		T3	1		T4	1
auto[BaudRate1p5Mbps]	983	1			T1	1		T5	1		T100	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1287	1			T8	10		T9	6		T32	2
freqs[25]	809	1			T19	10		T150	9		T27	9
freqs[48]	427	1			T11	5		T282	7		T297	12
freqs[50]	335	1			T6	2		T121	6		T50	7
freqs[100]	945	1			T5	7		T29	10		T55	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	253	1			T8	1		T9	1		T57	1
auto[BaudRate9600]	freqs[25]	123	1			T19	1		T150	2		T27	9
auto[BaudRate9600]	freqs[48]	67	1			T282	1		T46	2		T209	3
auto[BaudRate9600]	freqs[50]	44	1			T121	1		T146	1		T229	1
auto[BaudRate9600]	freqs[100]	167	1			T29	2		T357	18		T305	2
auto[BaudRate115200]	freqs[24]	181	1			T8	3		T9	2		T32	2
auto[BaudRate115200]	freqs[25]	102	1			T19	1		T150	1		T155	14
auto[BaudRate115200]	freqs[48]	54	1			T282	2		T297	2		T209	1
auto[BaudRate115200]	freqs[50]	51	1			T6	1		T121	1		T50	1
auto[BaudRate115200]	freqs[100]	120	1			T29	1		T21	3		T298	1
auto[BaudRate230400]	freqs[24]	193	1			T8	1		T9	1		T57	1
auto[BaudRate230400]	freqs[25]	152	1			T19	3		T150	1		T155	14
auto[BaudRate230400]	freqs[48]	42	1			T297	2		T46	1		T344	1
auto[BaudRate230400]	freqs[50]	47	1			T121	1		T50	2		T146	3
auto[BaudRate230400]	freqs[100]	116	1			T29	2		T21	2		T48	1
auto[BaudRate128Kbps]	freqs[24]	195	1			T8	3		T9	2		T57	4
auto[BaudRate128Kbps]	freqs[25]	128	1			T150	2		T58	1		T155	8
auto[BaudRate128Kbps]	freqs[48]	50	1			T11	4		T297	2		T46	2
auto[BaudRate128Kbps]	freqs[50]	46	1			T121	1		T50	2		T229	1
auto[BaudRate128Kbps]	freqs[100]	134	1			T29	1		T55	1		T117	1
auto[BaudRate256Kbps]	freqs[24]	166	1			T8	1		T56	2		T279	1
auto[BaudRate256Kbps]	freqs[25]	122	1			T19	2		T150	2		T155	8
auto[BaudRate256Kbps]	freqs[48]	79	1			T282	1		T297	5		T46	2
auto[BaudRate256Kbps]	freqs[50]	52	1			T50	1		T229	2		T130	1
auto[BaudRate256Kbps]	freqs[100]	141	1			T5	2		T29	1		T117	1
auto[BaudRate1Mbps]	freqs[24]	201	1			T8	1		T56	3		T279	5
auto[BaudRate1Mbps]	freqs[25]	121	1			T19	1		T150	1		T155	5
auto[BaudRate1Mbps]	freqs[48]	74	1			T11	1		T282	1		T297	1
auto[BaudRate1Mbps]	freqs[50]	45	1			T6	1		T121	1		T50	1
auto[BaudRate1Mbps]	freqs[100]	150	1			T5	4		T29	2		T55	1
auto[BaudRate1p5Mbps]	freqs[25]	61	1			T19	2		T155	7		T169	2
auto[BaudRate1p5Mbps]	freqs[48]	61	1			T282	2		T46	2		T307	1
auto[BaudRate1p5Mbps]	freqs[50]	50	1			T121	1		T146	2		T229	1
auto[BaudRate1p5Mbps]	freqs[100]	117	1			T5	1		T29	1		T21	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded