Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29323428	1			T2	52		T3	43		T4	14
all_levels[1]	165339	1			T4	1		T5	1202		T7	2
all_levels[2]	2123	1			T100	1		T12	1		T20	1
all_levels[3]	851	1			T162	3		T20	4		T13	1
all_levels[4]	623	1			T2	1		T3	2		T8	3
all_levels[5]	475	1			T162	1		T20	3		T154	3
all_levels[6]	374	1			T11	1		T29	2		T150	1
all_levels[7]	284	1			T2	2		T7	1		T162	1
all_levels[8]	228	1			T11	1		T20	2		T152	1
all_levels[9]	204	1			T2	1		T13	1		T54	1
all_levels[10]	213	1			T7	1		T20	2		T13	1
all_levels[11]	172	1			T162	2		T20	1		T29	3
all_levels[12]	142	1			T162	1		T20	1		T29	1
all_levels[13]	135	1			T162	2		T19	2		T20	1
all_levels[14]	140	1			T8	1		T162	1		T20	1
all_levels[15]	127	1			T2	1		T7	1		T29	1
all_levels[16]	107	1			T8	2		T19	1		T20	1
all_levels[17]	105	1			T7	1		T163	1		T48	2
all_levels[18]	98	1			T2	1		T7	1		T13	1
all_levels[19]	57	1			T7	1		T100	1		T162	1
all_levels[20]	69	1			T2	2		T100	2		T19	1
all_levels[21]	71	1			T8	3		T164	1		T155	1
all_levels[22]	93	1			T2	1		T19	1		T150	1
all_levels[23]	57	1			T162	2		T20	1		T165	1
all_levels[24]	52	1			T48	1		T164	1		T153	1
all_levels[25]	50	1			T8	1		T20	2		T165	1
all_levels[26]	45	1			T7	2		T166	1		T167	2
all_levels[27]	42	1			T2	1		T20	1		T120	1
all_levels[28]	50	1			T150	1		T168	1		T155	1
all_levels[29]	40	1			T7	1		T168	2		T50	1
all_levels[30]	32	1			T8	1		T169	1		T170	1
all_levels[31]	29	1			T163	2		T48	1		T171	1
all_levels[32]	32	1			T46	1		T164	1		T172	1
all_levels[33]	25	1			T173	1		T174	1		T175	1
all_levels[34]	19	1			T20	1		T171	1		T176	1
all_levels[35]	11	1			T177	1		T178	1		T179	1
all_levels[36]	19	1			T20	1		T163	1		T42	1
all_levels[37]	23	1			T2	1		T171	1		T180	1
all_levels[38]	5	1			T171	1		T181	1		T182	2
all_levels[39]	12	1			T166	1		T183	1		T184	1
all_levels[40]	12	1			T57	1		T164	1		T153	1
all_levels[41]	15	1			T170	1		T185	1		T177	1
all_levels[42]	19	1			T52	1		T186	2		T176	4
all_levels[43]	17	1			T54	1		T170	1		T187	2
all_levels[44]	14	1			T173	1		T188	2		T189	1
all_levels[45]	9	1			T155	1		T170	1		T190	3
all_levels[46]	14	1			T57	1		T191	1		T192	1
all_levels[47]	10	1			T16	1		T131	1		T193	1
all_levels[48]	9	1			T57	1		T174	1		T194	1
all_levels[49]	13	1			T150	1		T50	1		T164	2
all_levels[50]	14	1			T165	1		T52	1		T171	1
all_levels[51]	14	1			T191	1		T183	1		T180	1
all_levels[52]	9	1			T7	1		T181	1		T41	1
all_levels[53]	8	1			T195	1		T196	1		T197	1
all_levels[54]	8	1			T13	1		T198	1		T199	1
all_levels[55]	12	1			T54	1		T150	1		T120	1
all_levels[56]	10	1			T52	1		T192	1		T200	1
all_levels[57]	9	1			T131	1		T201	1		T202	3
all_levels[58]	7	1			T163	1		T191	1		T203	1
all_levels[59]	7	1			T19	1		T131	1		T204	2
all_levels[60]	2	1			T205	1		T125	1		-	-
all_levels[61]	9	1			T155	1		T206	1		T41	1
all_levels[62]	7	1			T150	1		T207	1		T208	1
all_levels[63]	10	1			T13	1		T191	1		T200	1
all_levels[64]	87	1			T13	1		T150	1		T163	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29492159

1

T2

63

T3

35

T4

10

auto[1]

4187

1

T3

10

T4

5

T7

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[45] , all_levels[46] , all_levels[47]]	[auto[1]]	--	--	3
[all_levels[52] , all_levels[53] , all_levels[54]]	[auto[1]]	--	--	3
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[60]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29319722	1			T2	52		T3	34		T4	9
all_levels[0]	auto[1]	3706	1			T3	9		T4	5		T7	4
all_levels[1]	auto[0]	165254	1			T4	1		T5	1202		T7	1
all_levels[1]	auto[1]	85	1			T7	1		T100	1		T168	1
all_levels[2]	auto[0]	2095	1			T100	1		T12	1		T20	1
all_levels[2]	auto[1]	28	1			T209	2		T183	1		T181	2
all_levels[3]	auto[0]	835	1			T162	1		T20	4		T13	1
all_levels[3]	auto[1]	16	1			T162	2		T164	1		T208	1
all_levels[4]	auto[0]	600	1			T2	1		T3	1		T8	1
all_levels[4]	auto[1]	23	1			T3	1		T8	2		T210	1
all_levels[5]	auto[0]	448	1			T162	1		T20	3		T154	3
all_levels[5]	auto[1]	27	1			T164	1		T172	1		T211	2
all_levels[6]	auto[0]	362	1			T11	1		T29	2		T150	1
all_levels[6]	auto[1]	12	1			T152	1		T212	1		T213	1
all_levels[7]	auto[0]	274	1			T2	2		T7	1		T162	1
all_levels[7]	auto[1]	10	1			T214	1		T208	1		T181	2
all_levels[8]	auto[0]	214	1			T11	1		T20	2		T152	1
all_levels[8]	auto[1]	14	1			T215	2		T216	1		T217	1
all_levels[9]	auto[0]	194	1			T2	1		T13	1		T54	1
all_levels[9]	auto[1]	10	1			T174	1		T185	1		T218	3
all_levels[10]	auto[0]	197	1			T7	1		T20	2		T13	1
all_levels[10]	auto[1]	16	1			T183	3		T174	1		T219	1
all_levels[11]	auto[0]	160	1			T162	2		T20	1		T29	3
all_levels[11]	auto[1]	12	1			T165	1		T220	1		T197	2
all_levels[12]	auto[0]	135	1			T162	1		T20	1		T29	1
all_levels[12]	auto[1]	7	1			T221	2		T222	1		T223	2
all_levels[13]	auto[0]	124	1			T162	2		T19	2		T20	1
all_levels[13]	auto[1]	11	1			T165	1		T170	1		T224	1
all_levels[14]	auto[0]	129	1			T8	1		T162	1		T20	1
all_levels[14]	auto[1]	11	1			T225	1		T170	1		T226	2
all_levels[15]	auto[0]	117	1			T2	1		T7	1		T29	1
all_levels[15]	auto[1]	10	1			T153	1		T227	1		T228	1
all_levels[16]	auto[0]	97	1			T8	2		T19	1		T20	1
all_levels[16]	auto[1]	10	1			T229	4		T219	1		T177	1
all_levels[17]	auto[0]	91	1			T7	1		T163	1		T48	2
all_levels[17]	auto[1]	14	1			T230	3		T231	2		T232	2
all_levels[18]	auto[0]	82	1			T2	1		T7	1		T13	1
all_levels[18]	auto[1]	16	1			T233	2		T234	2		T59	2
all_levels[19]	auto[0]	49	1			T7	1		T100	1		T162	1
all_levels[19]	auto[1]	8	1			T212	2		T211	2		T194	2
all_levels[20]	auto[0]	64	1			T2	2		T100	1		T19	1
all_levels[20]	auto[1]	5	1			T100	1		T235	1		T185	1
all_levels[21]	auto[0]	63	1			T8	1		T164	1		T155	1
all_levels[21]	auto[1]	8	1			T8	2		T227	2		T236	1
all_levels[22]	auto[0]	71	1			T2	1		T19	1		T150	1
all_levels[22]	auto[1]	22	1			T50	1		T237	1		T238	3
all_levels[23]	auto[0]	50	1			T162	1		T20	1		T165	1
all_levels[23]	auto[1]	7	1			T162	1		T153	1		T171	1
all_levels[24]	auto[0]	49	1			T48	1		T164	1		T153	1
all_levels[24]	auto[1]	3	1			T239	1		T240	1		T241	1
all_levels[25]	auto[0]	49	1			T8	1		T20	2		T165	1
all_levels[25]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[26]	auto[0]	41	1			T7	1		T166	1		T167	2
all_levels[26]	auto[1]	4	1			T7	1		T243	2		T244	1
all_levels[27]	auto[0]	34	1			T2	1		T20	1		T120	1
all_levels[27]	auto[1]	8	1			T245	1		T246	1		T196	1
all_levels[28]	auto[0]	41	1			T150	1		T168	1		T155	1
all_levels[28]	auto[1]	9	1			T247	3		T248	2		T249	1
all_levels[29]	auto[0]	35	1			T7	1		T168	1		T50	1
all_levels[29]	auto[1]	5	1			T168	1		T242	2		T250	2
all_levels[30]	auto[0]	29	1			T8	1		T169	1		T170	1
all_levels[30]	auto[1]	3	1			T251	2		T252	1		-	-
all_levels[31]	auto[0]	26	1			T163	1		T48	1		T171	1
all_levels[31]	auto[1]	3	1			T163	1		T253	1		T254	1
all_levels[32]	auto[0]	26	1			T46	1		T164	1		T172	1
all_levels[32]	auto[1]	6	1			T255	3		T256	1		T257	2
all_levels[33]	auto[0]	18	1			T173	1		T174	1		T175	1
all_levels[33]	auto[1]	7	1			T177	3		T123	2		T248	1
all_levels[34]	auto[0]	17	1			T20	1		T171	1		T176	1
all_levels[34]	auto[1]	2	1			T258	1		T259	1		-	-
all_levels[35]	auto[0]	11	1			T177	1		T178	1		T179	1
all_levels[36]	auto[0]	18	1			T20	1		T163	1		T42	1
all_levels[36]	auto[1]	1	1			T260	1		-	-		-	-
all_levels[37]	auto[0]	23	1			T2	1		T171	1		T180	1
all_levels[38]	auto[0]	4	1			T171	1		T181	1		T182	1
all_levels[38]	auto[1]	1	1			T182	1		-	-		-	-
all_levels[39]	auto[0]	12	1			T166	1		T183	1		T184	1
all_levels[40]	auto[0]	11	1			T57	1		T164	1		T153	1
all_levels[40]	auto[1]	1	1			T261	1		-	-		-	-
all_levels[41]	auto[0]	15	1			T170	1		T185	1		T177	1
all_levels[42]	auto[0]	14	1			T52	1		T186	1		T176	1
all_levels[42]	auto[1]	5	1			T186	1		T176	3		T262	1
all_levels[43]	auto[0]	15	1			T54	1		T170	1		T187	1
all_levels[43]	auto[1]	2	1			T187	1		T263	1		-	-
all_levels[44]	auto[0]	12	1			T173	1		T188	2		T189	1
all_levels[44]	auto[1]	2	1			T264	2		-	-		-	-
all_levels[45]	auto[0]	9	1			T155	1		T170	1		T190	3
all_levels[46]	auto[0]	14	1			T57	1		T191	1		T192	1
all_levels[47]	auto[0]	10	1			T16	1		T131	1		T193	1
all_levels[48]	auto[0]	8	1			T57	1		T174	1		T194	1
all_levels[48]	auto[1]	1	1			T265	1		-	-		-	-
all_levels[49]	auto[0]	9	1			T150	1		T50	1		T164	1
all_levels[49]	auto[1]	4	1			T164	1		T187	1		T266	1
all_levels[50]	auto[0]	12	1			T165	1		T52	1		T171	1
all_levels[50]	auto[1]	2	1			T259	2		-	-		-	-
all_levels[51]	auto[0]	11	1			T191	1		T183	1		T180	1
all_levels[51]	auto[1]	3	1			T41	1		T267	2		-	-
all_levels[52]	auto[0]	9	1			T7	1		T181	1		T41	1
all_levels[53]	auto[0]	8	1			T195	1		T196	1		T197	1
all_levels[54]	auto[0]	8	1			T13	1		T198	1		T199	1
all_levels[55]	auto[0]	11	1			T54	1		T150	1		T120	1
all_levels[55]	auto[1]	1	1			T268	1		-	-		-	-
all_levels[56]	auto[0]	10	1			T52	1		T192	1		T200	1
all_levels[57]	auto[0]	7	1			T131	1		T201	1		T202	1
all_levels[57]	auto[1]	2	1			T202	2		-	-		-	-
all_levels[58]	auto[0]	7	1			T163	1		T191	1		T203	1
all_levels[59]	auto[0]	6	1			T19	1		T131	1		T204	1
all_levels[59]	auto[1]	1	1			T204	1		-	-		-	-
all_levels[60]	auto[0]	2	1			T205	1		T125	1		-	-
all_levels[61]	auto[0]	8	1			T155	1		T206	1		T41	1
all_levels[61]	auto[1]	1	1			T269	1		-	-		-	-
all_levels[62]	auto[0]	6	1			T150	1		T207	1		T208	1
all_levels[62]	auto[1]	1	1			T270	1		-	-		-	-
all_levels[63]	auto[0]	7	1			T13	1		T191	1		T200	1
all_levels[63]	auto[1]	3	1			T271	2		T272	1		-	-
all_levels[64]	auto[0]	70	1			T13	1		T150	1		T163	1
all_levels[64]	auto[1]	17	1			T153	1		T208	1		T273	2