Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99712	1			T1	2		T2	45		T3	12
all_pins[1]	99712	1			T1	2		T2	45		T3	12
all_pins[2]	99712	1			T1	2		T2	45		T3	12
all_pins[3]	99712	1			T1	2		T2	45		T3	12
all_pins[4]	99712	1			T1	2		T2	45		T3	12
all_pins[5]	99712	1			T1	2		T2	45		T3	12
all_pins[6]	99712	1			T1	2		T2	45		T3	12
all_pins[7]	99712	1			T1	2		T2	45		T3	12

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	768442	1			T1	16		T2	328		T3	87
values[0x1]	29254	1			T2	32		T3	9		T4	3
transitions[0x0=>0x1]	28377	1			T2	32		T3	9		T4	3
transitions[0x1=>0x0]	27966	1			T2	32		T3	8		T4	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	76273	1			T1	2		T2	20		T3	6
all_pins[0]	values[0x1]	23439	1			T2	25		T3	6		T4	3
all_pins[0]	transitions[0x0=>0x1]	23017	1			T2	25		T3	6		T4	3
all_pins[0]	transitions[0x1=>0x0]	1269	1			T152	3		T57	8		T155	15
all_pins[1]	values[0x0]	98021	1			T1	2		T2	45		T3	12
all_pins[1]	values[0x1]	1691	1			T152	9		T57	8		T155	16
all_pins[1]	transitions[0x0=>0x1]	1569	1			T152	3		T57	8		T155	12
all_pins[1]	transitions[0x1=>0x0]	2181	1			T2	6		T3	3		T5	5
all_pins[2]	values[0x0]	97409	1			T1	2		T2	39		T3	9
all_pins[2]	values[0x1]	2303	1			T2	6		T3	3		T5	5
all_pins[2]	transitions[0x0=>0x1]	2250	1			T2	6		T3	3		T5	5
all_pins[2]	transitions[0x1=>0x0]	173	1			T8	1		T16	1		T275	1
all_pins[3]	values[0x0]	99486	1			T1	2		T2	45		T3	12
all_pins[3]	values[0x1]	226	1			T8	1		T12	1		T163	2
all_pins[3]	transitions[0x0=>0x1]	200	1			T8	1		T12	1		T163	2
all_pins[3]	transitions[0x1=>0x0]	351	1			T28	1		T155	1		T16	2
all_pins[4]	values[0x0]	99335	1			T1	2		T2	45		T3	12
all_pins[4]	values[0x1]	377	1			T28	1		T155	1		T16	3
all_pins[4]	transitions[0x0=>0x1]	327	1			T28	1		T155	1		T16	2
all_pins[4]	transitions[0x1=>0x0]	149	1			T16	2		T17	2		T23	1
all_pins[5]	values[0x0]	99513	1			T1	2		T2	45		T3	12
all_pins[5]	values[0x1]	199	1			T16	3		T17	3		T18	1
all_pins[5]	transitions[0x0=>0x1]	156	1			T16	2		T17	3		T18	1
all_pins[5]	transitions[0x1=>0x0]	721	1			T2	1		T8	1		T29	2
all_pins[6]	values[0x0]	98948	1			T1	2		T2	44		T3	12
all_pins[6]	values[0x1]	764	1			T2	1		T8	1		T29	2
all_pins[6]	transitions[0x0=>0x1]	726	1			T2	1		T8	1		T29	2
all_pins[6]	transitions[0x1=>0x0]	217	1			T19	2		T57	2		T16	2
all_pins[7]	values[0x0]	99457	1			T1	2		T2	45		T3	12
all_pins[7]	values[0x1]	255	1			T19	2		T57	2		T16	2
all_pins[7]	transitions[0x0=>0x1]	132	1			T19	1		T57	2		T17	1
all_pins[7]	transitions[0x1=>0x0]	22905	1			T2	25		T3	5		T4	2