Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8109539	1			T2	14		T3	26		T4	5
all_levels[1]	2649587	1			T2	1		T3	3		T5	115
all_levels[2]	241967	1			T4	1		T5	118		T9	2
all_levels[3]	249073	1			T2	1		T5	114		T9	1
all_levels[4]	296242	1			T2	3		T5	112		T149	8
all_levels[5]	202518	1			T2	2		T5	116		T11	2
all_levels[6]	273646	1			T5	105		T7	3		T149	3
all_levels[7]	198808	1			T2	9		T5	110		T162	1
all_levels[8]	431345	1			T2	15		T5	118		T19	2
all_levels[9]	351094	1			T2	3		T5	110		T100	3
all_levels[10]	195682	1			T5	117		T8	1		T20	1
all_levels[11]	284200	1			T5	112		T162	4		T294	1006
all_levels[12]	246707	1			T2	1		T5	122		T11	1
all_levels[13]	200653	1			T3	2		T5	106		T9	1
all_levels[14]	195597	1			T2	1		T5	120		T9	1
all_levels[15]	191800	1			T2	1		T3	9		T5	114
all_levels[16]	199727	1			T2	2		T4	4		T5	119
all_levels[17]	530203	1			T5	121		T8	2		T100	2
all_levels[18]	178453	1			T5	119		T7	3		T12	7
all_levels[19]	222045	1			T2	2		T5	122		T11	2
all_levels[20]	171547	1			T5	119		T9	2		T149	3
all_levels[21]	649246	1			T5	128		T100	1		T162	2
all_levels[22]	319074	1			T5	110		T294	961		T54	8
all_levels[23]	350283	1			T5	118		T19	5		T294	476
all_levels[24]	200204	1			T2	8		T5	117		T11	1
all_levels[25]	162850	1			T5	116		T162	1		T294	480
all_levels[26]	203878	1			T3	2		T5	114		T294	479
all_levels[27]	222682	1			T4	1		T5	114		T294	477
all_levels[28]	171468	1			T5	107		T294	479		T54	1
all_levels[29]	169421	1			T5	112		T19	2		T20	32
all_levels[30]	277056	1			T5	108		T19	3		T20	1
all_levels[31]	613054	1			T5	3270		T11	3		T19	1
all_levels[32]	10536466	1			T4	4		T5	112875		T9	7

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29492159

1

T2

63

T3

35

T4

10

auto[1]

3956

1

T3

7

T4

5

T7

8

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8107535	1			T2	14		T3	22		T4	2
all_levels[0]	auto[1]	2004	1			T3	4		T4	3		T7	5
all_levels[1]	auto[0]	2649300	1			T2	1		T3	1		T5	115
all_levels[1]	auto[1]	287	1			T3	2		T7	1		T8	2
all_levels[2]	auto[0]	241930	1			T4	1		T5	118		T9	2
all_levels[2]	auto[1]	37	1			T210	1		T209	2		T229	1
all_levels[3]	auto[0]	248911	1			T2	1		T5	114		T9	1
all_levels[3]	auto[1]	162	1			T28	2		T186	1		T275	6
all_levels[4]	auto[0]	296217	1			T2	3		T5	112		T149	8
all_levels[4]	auto[1]	25	1			T170	1		T171	1		T358	1
all_levels[5]	auto[0]	202499	1			T2	2		T5	116		T11	2
all_levels[5]	auto[1]	19	1			T359	2		T233	2		T203	2
all_levels[6]	auto[0]	273628	1			T5	105		T7	2		T149	3
all_levels[6]	auto[1]	18	1			T7	1		T165	1		T216	3
all_levels[7]	auto[0]	198559	1			T2	9		T5	110		T162	1
all_levels[7]	auto[1]	249	1			T210	2		T121	1		T28	12
all_levels[8]	auto[0]	431320	1			T2	15		T5	118		T19	2
all_levels[8]	auto[1]	25	1			T209	2		T176	1		T40	1
all_levels[9]	auto[0]	351061	1			T2	3		T5	110		T100	2
all_levels[9]	auto[1]	33	1			T100	1		T215	1		T168	1
all_levels[10]	auto[0]	195660	1			T5	117		T8	1		T20	1
all_levels[10]	auto[1]	22	1			T215	2		T164	1		T323	1
all_levels[11]	auto[0]	284166	1			T5	112		T162	2		T294	1006
all_levels[11]	auto[1]	34	1			T162	2		T50	1		T237	1
all_levels[12]	auto[0]	246670	1			T2	1		T5	122		T11	1
all_levels[12]	auto[1]	37	1			T210	2		T209	2		T309	1
all_levels[13]	auto[0]	200619	1			T3	2		T5	106		T9	1
all_levels[13]	auto[1]	34	1			T282	1		T339	2		T307	1
all_levels[14]	auto[0]	195575	1			T2	1		T5	120		T9	1
all_levels[14]	auto[1]	22	1			T346	1		T298	1		T336	1
all_levels[15]	auto[0]	191661	1			T2	1		T3	9		T5	114
all_levels[15]	auto[1]	139	1			T153	1		T146	2		T208	2
all_levels[16]	auto[0]	199685	1			T2	2		T4	2		T5	119
all_levels[16]	auto[1]	42	1			T4	2		T172	1		T214	2
all_levels[17]	auto[0]	530173	1			T5	121		T8	1		T100	2
all_levels[17]	auto[1]	30	1			T8	1		T172	1		T360	1
all_levels[18]	auto[0]	178427	1			T5	119		T7	2		T12	2
all_levels[18]	auto[1]	26	1			T7	1		T12	5		T163	1
all_levels[19]	auto[0]	222013	1			T2	2		T5	122		T11	2
all_levels[19]	auto[1]	32	1			T155	1		T209	1		T146	1
all_levels[20]	auto[0]	171525	1			T5	119		T9	2		T149	2
all_levels[20]	auto[1]	22	1			T149	1		T210	1		T172	1
all_levels[21]	auto[0]	649230	1			T5	128		T100	1		T162	1
all_levels[21]	auto[1]	16	1			T162	1		T165	2		T262	1
all_levels[22]	auto[0]	319048	1			T5	110		T294	961		T54	8
all_levels[22]	auto[1]	26	1			T208	2		T361	1		T327	1
all_levels[23]	auto[0]	350258	1			T5	118		T19	5		T294	476
all_levels[23]	auto[1]	25	1			T16	1		T362	2		T235	1
all_levels[24]	auto[0]	200187	1			T2	8		T5	117		T11	1
all_levels[24]	auto[1]	17	1			T165	1		T49	3		T169	1
all_levels[25]	auto[0]	162843	1			T5	116		T162	1		T294	480
all_levels[25]	auto[1]	7	1			T363	1		T253	1		T364	1
all_levels[26]	auto[0]	203861	1			T3	1		T5	114		T294	479
all_levels[26]	auto[1]	17	1			T3	1		T214	1		T365	1
all_levels[27]	auto[0]	222671	1			T4	1		T5	114		T294	477
all_levels[27]	auto[1]	11	1			T185	3		T366	1		T367	1
all_levels[28]	auto[0]	171459	1			T5	107		T294	479		T54	1
all_levels[28]	auto[1]	9	1			T368	1		T369	1		T370	2
all_levels[29]	auto[0]	169407	1			T5	112		T19	2		T20	32
all_levels[29]	auto[1]	14	1			T362	1		T40	1		T181	1
all_levels[30]	auto[0]	277044	1			T5	108		T19	3		T20	1
all_levels[30]	auto[1]	12	1			T16	2		T325	1		T371	1
all_levels[31]	auto[0]	613041	1			T5	3270		T11	3		T19	1
all_levels[31]	auto[1]	13	1			T116	2		T52	1		T212	1
all_levels[32]	auto[0]	10535976	1			T4	4		T5	112875		T9	5
all_levels[32]	auto[1]	490	1			T9	2		T100	7		T20	1