Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	504	1			T16	7		T17	7		T31	4
all_values[1]	504	1			T16	7		T17	7		T31	4
all_values[2]	504	1			T16	7		T17	7		T31	4
all_values[3]	504	1			T16	7		T17	7		T31	4
all_values[4]	504	1			T16	7		T17	7		T31	4
all_values[5]	504	1			T16	7		T17	7		T31	4
all_values[6]	504	1			T16	7		T17	7		T31	4
all_values[7]	504	1			T16	7		T17	7		T31	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2122

1

T16

28

T17

29

T31

15

auto[1]

1910

1

T16

28

T17

27

T31

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1449

1

T16

22

T17

11

T31

15

auto[1]

2583

1

T16

34

T17

45

T31

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2383

1

T16

34

T17

32

T31

19

auto[1]

1649

1

T16

22

T17

24

T31

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	167	1			T16	2		T17	4		T31	2
all_values[0]	auto[0]	auto[1]	auto[1]	140	1			T16	3		T17	2		T101	2
all_values[0]	auto[1]	auto[0]	auto[1]	97	1			T16	1		T31	2		T40	3
all_values[0]	auto[1]	auto[1]	auto[1]	100	1			T16	1		T17	1		T101	6
all_values[1]	auto[0]	auto[0]	auto[0]	149	1			T16	3		T17	2		T31	1
all_values[1]	auto[0]	auto[1]	auto[0]	147	1			T16	2		T17	2		T101	4
all_values[1]	auto[1]	auto[0]	auto[1]	111	1			T16	1		T17	3		T31	1
all_values[1]	auto[1]	auto[1]	auto[1]	97	1			T16	1		T31	2		T40	1
all_values[2]	auto[0]	auto[0]	auto[0]	111	1			T16	3		T101	4		T40	3
all_values[2]	auto[0]	auto[0]	auto[1]	54	1			T17	1		T40	1		T158	1
all_values[2]	auto[0]	auto[1]	auto[0]	88	1			T16	3		T17	1		T31	1
all_values[2]	auto[0]	auto[1]	auto[1]	51	1			T17	1		T31	1		T101	1
all_values[2]	auto[1]	auto[0]	auto[1]	102	1			T17	3		T101	1		T40	3
all_values[2]	auto[1]	auto[1]	auto[1]	98	1			T16	1		T17	1		T31	2
all_values[3]	auto[0]	auto[0]	auto[0]	99	1			T101	3		T40	1		T274	2
all_values[3]	auto[0]	auto[0]	auto[1]	59	1			T16	2		T17	2		T40	2
all_values[3]	auto[0]	auto[1]	auto[0]	77	1			T16	1		T31	4		T101	4
all_values[3]	auto[0]	auto[1]	auto[1]	52	1			T17	2		T45	1		T220	1
all_values[3]	auto[1]	auto[0]	auto[1]	117	1			T16	4		T17	1		T101	1
all_values[3]	auto[1]	auto[1]	auto[1]	100	1			T17	2		T101	3		T40	1
all_values[4]	auto[0]	auto[0]	auto[0]	116	1			T16	2		T101	5		T40	1
all_values[4]	auto[0]	auto[0]	auto[1]	47	1			T101	2		T41	1		T158	3
all_values[4]	auto[0]	auto[1]	auto[0]	88	1			T31	2		T40	1		T45	1
all_values[4]	auto[0]	auto[1]	auto[1]	54	1			T16	2		T17	3		T101	1
all_values[4]	auto[1]	auto[0]	auto[1]	112	1			T16	2		T17	1		T31	1
all_values[4]	auto[1]	auto[1]	auto[1]	87	1			T16	1		T17	3		T31	1
all_values[5]	auto[0]	auto[0]	auto[0]	112	1			T31	1		T101	5		T40	3
all_values[5]	auto[0]	auto[0]	auto[1]	47	1			T17	2		T101	1		T274	1
all_values[5]	auto[0]	auto[1]	auto[0]	90	1			T16	2		T101	2		T40	2
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T16	1		T17	1		T31	1
all_values[5]	auto[1]	auto[0]	auto[1]	102	1			T16	1		T17	3		T31	2
all_values[5]	auto[1]	auto[1]	auto[1]	95	1			T16	3		T17	1		T40	1
all_values[6]	auto[0]	auto[0]	auto[0]	89	1			T16	2		T17	2		T31	1
all_values[6]	auto[0]	auto[0]	auto[1]	60	1			T17	1		T101	1		T40	2
all_values[6]	auto[0]	auto[1]	auto[0]	87	1			T17	1		T31	1		T101	1
all_values[6]	auto[0]	auto[1]	auto[1]	52	1			T16	2		T101	2		T40	1
all_values[6]	auto[1]	auto[0]	auto[1]	111	1			T16	2		T31	2		T101	3
all_values[6]	auto[1]	auto[1]	auto[1]	105	1			T16	1		T17	3		T101	3
all_values[7]	auto[0]	auto[0]	auto[0]	98	1			T16	2		T17	2		T31	2
all_values[7]	auto[0]	auto[0]	auto[1]	44	1			T17	1		T40	1		T158	2
all_values[7]	auto[0]	auto[1]	auto[0]	98	1			T16	2		T17	1		T31	2
all_values[7]	auto[0]	auto[1]	auto[1]	49	1			T17	1		T40	1		T41	1
all_values[7]	auto[1]	auto[0]	auto[1]	118	1			T16	1		T17	1		T101	1
all_values[7]	auto[1]	auto[1]	auto[1]	97	1			T16	2		T17	1		T101	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal